1# ARM core configuration options
2
3# Copyright (c) 2015 Wind River Systems, Inc.
4# SPDX-License-Identifier: Apache-2.0
5
6config CPU_CORTEX_M
7	bool
8	select CPU_CORTEX
9	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
10	select HAS_CMSIS_CORE
11	select HAS_FLASH_LOAD_OFFSET
12	select ARCH_HAS_SINGLE_THREAD_SUPPORT
13	select ARCH_HAS_THREAD_ABORT
14	select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
15	select ARCH_HAS_STACK_PROTECTION if (ARM_MPU && !ARMV6_M_ARMV8_M_BASELINE) || CPU_CORTEX_M_HAS_SPLIM
16	select ARCH_HAS_USERSPACE if ARM_MPU
17	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
18	select ARCH_HAS_RAMFUNC_SUPPORT
19	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
20	select SWAP_NONATOMIC
21	select ARCH_HAS_EXTRA_EXCEPTION_INFO
22	select ARCH_HAS_TIMING_FUNCTIONS if CPU_CORTEX_M_HAS_DWT
23	select ARCH_SUPPORTS_ARCH_HW_INIT
24	select ARCH_HAS_SUSPEND_TO_RAM
25	select ARCH_HAS_CODE_DATA_RELOCATION
26	select ARCH_SUPPORTS_ROM_START
27	imply XIP
28	help
29	  This option signifies the use of a CPU of the Cortex-M family.
30
31config CPU_AARCH32_CORTEX_R
32	bool
33	select CPU_CORTEX
34	select HAS_CMSIS_CORE
35	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
36	select HAS_FLASH_LOAD_OFFSET
37	select ARCH_HAS_USERSPACE if ARM_MPU
38	select ARCH_HAS_EXTRA_EXCEPTION_INFO
39	select ARCH_HAS_CODE_DATA_RELOCATION
40	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
41	select ARCH_SUPPORTS_ROM_START
42	help
43	  This option signifies the use of a CPU of the Cortex-R family.
44
45config ARM_ZIMAGE_HEADER
46	bool "zImage Header"
47	depends on CPU_AARCH32_CORTEX_R || CPU_AARCH32_CORTEX_A || CPU_CORTEX_M_HAS_VTOR
48	help
49	  This option adds a zImage Header.
50
51config CPU_AARCH32_CORTEX_A
52	bool
53	select CPU_CORTEX
54	select CPU_HAS_MMU
55	select HAS_CMSIS_CORE
56	select HAS_FLASH_LOAD_OFFSET
57	select ARCH_HAS_EXTRA_EXCEPTION_INFO
58	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
59	help
60	  This option signifies the use of a CPU of the Cortex-A family.
61
62config ISA_THUMB2
63	bool
64	help
65	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
66
67	  Thumb-2 technology is the instruction set underlying the ARM Cortex
68	  architecture which provides enhanced levels of performance, energy
69	  efficiency, and code density for a wide range of embedded
70	  applications.
71
72	  Thumb-2 technology builds on the success of Thumb, the innovative
73	  high code density instruction set for ARM microprocessor cores, to
74	  increase the power of the ARM microprocessor core available to
75	  developers of low cost, high performance systems.
76
77	  The technology is backwards compatible with existing ARM and Thumb
78	  solutions, while significantly extending the features available to
79	  the Thumb instructions set. This allows more of the application to
80	  benefit from the best in class code density of Thumb.
81
82	  For performance optimized code Thumb-2 technology uses 31 percent
83	  less memory to reduce system cost, while providing up to 38 percent
84	  higher performance than existing high density code, which can be used
85	  to prolong battery-life or to enrich the product feature set. Thumb-2
86	  technology is featured in the  processor, and in all ARMv7
87	  architecture-based processors.
88
89config ISA_ARM
90	bool
91	help
92	  From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
93
94	  A32 instructions, known as Arm instructions in pre-Armv8 architectures,
95	  are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
96	  are supported by both A-profile and R-profile architectures.
97
98	  A32 was traditionally used in applications requiring the highest
99	  performance, or for handling hardware exceptions such as interrupts and
100	  processor start-up. Much of its functionality was subsumed into T32 with
101	  the introduction of Thumb-2 technology.
102
103config ASSEMBLER_ISA_THUMB2
104	bool
105	default y if ISA_THUMB2 && !ISA_ARM
106	depends on !ISA_ARM
107	help
108	  This helper symbol specifies the default target instruction set for
109	  the assembler.
110
111	  When only the Thumb-2 ISA is supported (i.e. on Cortex-M cores), the
112	  assembler must use the Thumb-2 instruction set.
113
114	  When both the Thumb-2 and ARM ISAs are supported (i.e. on Cortex-A
115	  and Cortex-R cores), the assembler must use the ARM instruction set
116	  because the architecture assembly code makes use of the ARM
117	  instructions.
118
119config COMPILER_ISA_THUMB2
120	bool "Compile C/C++ functions using Thumb-2 instruction set"
121	depends on ISA_THUMB2
122	default y
123	help
124	  This option configures the compiler to compile all C/C++ functions
125	  using the Thumb-2 instruction set.
126
127	  N.B. The scope of this symbol is not necessarily limited to the C and
128	       C++ languages; in fact, this symbol refers to all forms of
129	       "compiled" code.
130
131	       When an additional natively-compiled language support is added
132	       in the future, this symbol shall also specify the Thumb-2
133	       instruction set for that language.
134
135config NUM_IRQS
136	int
137
138config STACK_ALIGN_DOUBLE_WORD
139	bool "Align stacks on double-words (8 octets)"
140	default y
141	help
142	  This is needed to conform to AAPCS, the procedure call standard for
143	  the ARM. It wastes stack space. The option also enforces alignment
144	  of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
145	  Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
146	  on exception entry is enabled by default and it is not configurable.
147
148config RUNTIME_NMI
149	bool "Attach an NMI handler at runtime"
150	select REBOOT
151	help
152	  The kernel provides a simple NMI handler that simply hangs in a tight
153	  loop if triggered. This fills the requirement that there must be an
154	  NMI handler installed when the CPU boots. If a custom handler is
155	  needed, enable this option and attach it via z_arm_nmi_set_handler().
156
157config PLATFORM_SPECIFIC_INIT
158	bool "Platform (SOC) specific startup hook"
159	help
160	  The platform specific initialization code (z_arm_platform_init) is
161	  executed at the beginning of the startup code (__start).
162
163config FAULT_DUMP
164	int "Fault dump level"
165	default 2
166	range 0 2
167	help
168	  Different levels for display information when a fault occurs.
169
170	  2: The default. Display specific and verbose information. Consumes
171		the most memory (long strings).
172
173	  1: Display general and short information. Consumes less memory
174		(short strings).
175
176	  0: Off.
177
178config BUILTIN_STACK_GUARD
179	bool "Thread Stack Guards based on built-in ARM stack limit checking"
180	depends on CPU_CORTEX_M_HAS_SPLIM
181	select THREAD_STACK_INFO
182	help
183	  Enable Thread/Interrupt Stack Guards via built-in Stack Pointer
184	  limit checking. The functionality must be supported by HW.
185
186config ARM_STACK_PROTECTION
187	bool
188	default y if HW_STACK_PROTECTION
189	imply BUILTIN_STACK_GUARD if CPU_CORTEX_M_HAS_SPLIM
190	select MPU_STACK_GUARD if (!BUILTIN_STACK_GUARD && ARM_MPU)
191	help
192	  This option enables either:
193	  - The built-in Stack Pointer limit checking, or
194	  - the MPU-based stack guard
195	  to cause a system fatal error
196	  if the bounds of the current process stack are overflowed.
197	  The two stack guard options are mutually exclusive. The
198	  selection of the built-in Stack Pointer limit checking is
199	  prioritized over the MPU-based stack guard. The developer
200	  still has the option to manually select the MPU-based
201	  stack guard, if this is desired.
202
203config ARM_SECURE_FIRMWARE
204	bool
205	depends on ARMV8_M_SE
206	default y if TRUSTED_EXECUTION_SECURE
207	help
208	  This option indicates that we are building a Zephyr image that
209	  is intended to execute in Secure state. The option is only
210	  applicable to ARMv8-M MCUs that implement the Security Extension.
211
212	  This option enables Zephyr to include code that executes in
213	  Secure state, as well as to exclude code that is designed to
214	  execute only in Non-secure state.
215
216	  Code executing in Secure state has access to both the Secure
217	  and Non-Secure resources of the Cortex-M MCU.
218
219	  Code executing in Non-Secure state may trigger Secure Faults,
220	  if Secure MCU resources are accessed from the Non-Secure state.
221	  Secure Faults may only be handled by code executing in Secure
222	  state.
223
224config ARM_NONSECURE_FIRMWARE
225	bool
226	depends on !ARM_SECURE_FIRMWARE
227	depends on ARMV8_M_SE
228	default y if TRUSTED_EXECUTION_NONSECURE
229	help
230	  This option indicates that we are building a Zephyr image that
231	  is intended to execute in Non-Secure state. Execution of this
232	  image is triggered by Secure firmware that executes in Secure
233	  state. The option is only applicable to ARMv8-M MCUs that
234	  implement the Security Extension.
235
236	  This option enables Zephyr to include code that executes in
237	  Non-Secure state only, as well as to exclude code that is
238	  designed to execute only in Secure state.
239
240	  Code executing in Non-Secure state has no access to Secure
241	  resources of the Cortex-M MCU, and, therefore, it shall avoid
242	  accessing them.
243
244config ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS
245	bool "Allow secure function calls to be preempted"
246	depends on ARM_NONSECURE_FIRMWARE
247	help
248	  When enabled, this option indicates that preemptible Zephyr
249	  threads performing secure function calls, are allowed to be
250	  preempted. When disabled, the option indicates that such
251	  threads many not be context-switched-out while doing a Secure
252	  function call.
253
254config ARM_STORE_EXC_RETURN
255	bool
256	default y if CPU_CORTEX_M && (FPU_SHARING || ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS)
257	help
258	  Store the EXC_RETURN value when switching threads.
259	  This is needed when switching between threads that differ in either
260	  FPU usage or security domain.
261
262choice
263	prompt "Floating point ABI"
264	default FP_HARDABI
265	depends on FPU
266
267config FP_HARDABI
268	bool "Floating point Hard ABI"
269	# TF-M build system does not build the NS app and libraries correctly with Hard ABI.
270	# This limitation should be removed in the next TF-M synchronization.
271	depends on !TFM_BUILD_NS
272	depends on !(BUILD_WITH_TFM && !TFM_IPC)
273	help
274	  This option selects the Floating point ABI in which hardware floating
275	  point instructions are generated and uses FPU-specific calling
276	  conventions.
277
278	  Note: When building with TF-M enabled only the IPC mode is supported.
279
280config FP_SOFTABI
281	bool "Floating point Soft ABI"
282	help
283	  This option selects the Floating point ABI in which hardware floating
284	  point instructions are generated but soft-float calling conventions.
285
286endchoice
287
288config FP16
289	bool "Half-precision floating point support"
290	default y
291	help
292	  This option enables the half-precision (16-bit) floating point support
293	  via the `__fp16` (both IEEE and ARM alternative formats) and the
294	  `_Float16` (defined by ISO/IEC TS 18661-3:2015) types.
295
296choice
297	prompt "FP16 format"
298	default FP16_IEEE
299	depends on FP16
300
301config FP16_IEEE
302	bool "FP16 IEEE format"
303	help
304	  This option selects the IEEE 754-2008 format for FP16.  This format can
305	  represent normalized values in the range of 2^(-14) to 65504.  There are
306	  11 bits of significand precision, approximately 3 decimal digits.
307
308config FP16_ALT
309	bool "FP16 ARM alternative format"
310	help
311	  This option selects the ARM alternative format for FP16.  This
312	  representation is similar to the IEEE 754-2008 format, but does not
313	  support infinites or NaNs. Instead, the range of exponents is extended,
314	  so that this format can represent normalized values in the range of
315	  2^(-14) to 131008.
316
317	  Please note that Clang doesn't support the ARM alternative format.
318
319endchoice
320
321rsource "cortex_m/Kconfig"
322rsource "cortex_a_r/Kconfig"
323
324rsource "mpu/Kconfig"
325rsource "mmu/Kconfig"
326