1# Copyright 2024 NXP 2# SPDX-License-Identifier: Apache-2.0 3 4config SOC_MIMX8MM6_A53 5 select ARM64 6 select CPU_CORTEX_A53 7 select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS 8 select HAS_MCUX if CLOCK_CONTROL 9 select HAS_MCUX_IGPIO 10 select HAS_MCUX_CCM if CLOCK_CONTROL 11 select HAS_MCUX_IOMUXC if PINCTRL 12 select HAS_MCUX_RDC 13 select HAS_MCUX_CACHE 14 select SOC_PREP_HOOK 15 16config SOC_MIMX8MM6_M4 17 select ARM 18 select CPU_CORTEX_M4 19 select CPU_HAS_FPU 20 select CPU_HAS_ARM_MPU 21 select HAS_MCUX 22 select HAS_MCUX_CCM 23 select HAS_MCUX_RDC 24 select HAS_MCUX_IGPIO 25 select HAS_MCUX_IOMUXC 26 select SOC_EARLY_INIT_HOOK 27 28config SOC_MIMX8ML8_A53 29 select ARM64 30 select CPU_CORTEX_A53 31 select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS 32 select HAS_MCUX if CLOCK_CONTROL 33 select HAS_MCUX_CCM if CLOCK_CONTROL 34 select HAS_MCUX_IGPIO 35 select HAS_MCUX_IOMUXC if PINCTRL 36 select HAS_MCUX_RDC 37 select HAS_MCUX_CACHE 38 select SOC_PREP_HOOK 39 40config SOC_MIMX8MN6_A53 41 select ARM64 42 select CPU_CORTEX_A53 43 select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS 44 select HAS_MCUX if CLOCK_CONTROL 45 select HAS_MCUX_IGPIO 46 select HAS_MCUX_CCM if CLOCK_CONTROL 47 select HAS_MCUX_IOMUXC if PINCTRL 48 select HAS_MCUX_RDC 49 select HAS_MCUX_CACHE 50 select SOC_PREP_HOOK 51 52config SOC_MIMX8ML8_ADSP 53 select XTENSA 54 select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") 55 select XTENSA_RESET_VECTOR 56 select XTENSA_USE_CORE_CRT1 57 select ATOMIC_OPERATIONS_BUILTIN 58 select GEN_ISR_TABLES 59 select XTENSA_SMALL_VECTOR_TABLE_ENTRY 60 select HAS_MCUX if CLOCK_CONTROL 61 select HAS_MCUX_CCM if CLOCK_CONTROL 62 select HAS_MCUX_IOMUXC if PINCTRL 63 select PINCTRL_IMX if HAS_MCUX_IOMUXC 64 select CPU_HAS_DCACHE 65 66config SOC_MIMX8ML8_M7 67 select ARM 68 select CPU_CORTEX_M7 69 select CPU_HAS_FPU 70 select CPU_HAS_ICACHE 71 select CPU_HAS_DCACHE 72 select INIT_VIDEO_PLL 73 select HAS_MCUX 74 select HAS_MCUX_CCM 75 select HAS_MCUX_RDC 76 select CPU_HAS_ARM_MPU 77 select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS 78 select ARM_MPU 79 select HAS_MCUX_IGPIO 80 select HAS_MCUX_IOMUXC 81 select SOC_EARLY_INIT_HOOK 82 83config SOC_MIMX8MQ6_M4 84 select ARM 85 select CPU_CORTEX_M4 86 select CPU_HAS_FPU 87 select CPU_HAS_ARM_MPU 88 select HAS_MCUX 89 select HAS_MCUX_CCM 90 select HAS_MCUX_RDC 91 select HAS_MCUX_IOMUXC 92 93config MCUX_CORE_SUFFIX 94 default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53 95 default "_dsp" if SOC_MIMX8ML8_ADSP 96 97if SOC_MIMX8ML8_M7 98 99choice CODE_LOCATION 100 prompt "Code location selection" 101 102config CODE_ITCM 103 bool "Link code into internal instruction tightly coupled memory (ITCM)" 104 105config CODE_DDR 106 bool "Link code into DDR memory" 107 108endchoice 109 110config INIT_VIDEO_PLL 111 bool "Initialize Video PLL" 112 113endif # SOC_MIMX8ML8_M7 114
