1# STM32 MCU clock control driver config 2 3# Copyright (c) 2017 Linaro 4# Copyright (c) 2017 RnDity Sp. z o.o. 5# SPDX-License-Identifier: Apache-2.0 6 7menuconfig CLOCK_CONTROL_STM32_CUBE 8 bool "STM32 Reset & Clock Control" 9 depends on SOC_FAMILY_STM32 10 select USE_STM32_LL_UTILS 11 select USE_STM32_LL_RCC if SOC_SERIES_STM32MP1X 12 help 13 Enable driver for Reset & Clock Control subsystem found 14 in STM32 family of MCUs 15 16if CLOCK_CONTROL_STM32_CUBE 17 18config CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY 19 int "Clock Control Device Priority" 20 default 1 21 help 22 This option controls the priority of clock control 23 device initialization. Higher priority ensures that the device 24 is initialized earlier in the startup cycle. If unsure, leave 25 at default value 1 26 27DT_STM32_HSE_CLOCK := $(dt_nodelabel_path,clk_hse) 28DT_STM32_HSE_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_HSE_CLOCK),clock-frequency) 29 30config CLOCK_STM32_HSE_CLOCK 31 int "HSE clock value" 32 default "$(DT_STM32_HSE_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,clk_hse)" 33 default 8000000 34 help 35 Value of external high-speed clock (HSE). This symbol could be optionally 36 configured using device tree by setting "clock-frequency" value of clk_hse 37 node. For instance: 38 &clk_hse{ 39 status = "okay"; 40 clock-frequency = <DT_FREQ_M(25)>; 41 }; 42 Note: Device tree configuration is overridden when current symbol is set: 43 CONFIG_CLOCK_STM32_HSE_CLOCK=32000000 44 45config CLOCK_CONTROL_STM32_HAS_DTS 46 bool 47 default y if "$(dt_node_has_prop,rcc,clocks)" || "$(dt_node_has_prop,rcc,d1cpre)" 48 help 49 This symbol is added to prevent default use of CLOCK_CONTROL_STM32_* symbols 50 when board make use of device tree to configure clocks. 51 52if !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X 53 54choice CLOCK_STM32_SYSCLK_SRC 55 prompt "STM32 System Clock Source" 56 57config CLOCK_STM32_SYSCLK_SRC_HSE 58 bool "HSE" 59 help 60 Use HSE as source of SYSCLK 61 62config CLOCK_STM32_SYSCLK_SRC_HSI 63 bool "HSI" 64 help 65 Use HSI as source of SYSCLK 66 67config CLOCK_STM32_SYSCLK_SRC_MSI 68 bool "MSI" 69 depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX 70 help 71 Use MSI as source of SYSCLK 72 73config CLOCK_STM32_SYSCLK_SRC_PLL 74 bool "PLL" 75 help 76 Use PLL as source of SYSCLK 77 78config CLOCK_STM32_SYSCLK_SRC_CSI 79 bool "CSI" 80 depends on SOC_SERIES_STM32H7X 81 help 82 Use CSI as source of SYSCLK 83 84endchoice #CLOCK_STM32_SYSCLK_SRC 85 86config CLOCK_STM32_HSE_BYPASS 87 bool "HSE bypass" 88 depends on CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE 89 help 90 Enable this option to bypass external high-speed clock (HSE). 91 92config CLOCK_STM32_MSI_RANGE 93 int "MSI frequency range" 94 depends on CLOCK_STM32_SYSCLK_SRC_MSI || CLOCK_STM32_PLL_SRC_MSI 95 default 8 96 help 97 Frequency range of MSI when MSI range is provided in RCC_CR register 98 Range 0: 100kHz 99 Range 1: 200kHz 100 Range 2 around 400 kHz 101 Range 3 around 800 kHz 102 Range 4: 1 MHz 103 Range 5: 2 MHz 104 Range 6: 4 MHz (reset value) 105 Range 7: 8 MHz 106 Range 8: 16 MHz 107 Range 9: 24 MHz 108 Range 10: 32 MHz 109 Range 11: 48 MHz 110 111choice 112 prompt "STM32 PLL Clock Source" 113 default CLOCK_STM32_PLL_SRC_HSI 114 depends on CLOCK_STM32_SYSCLK_SRC_PLL 115 116config CLOCK_STM32_PLL_SRC_MSI 117 bool "MSI" 118 depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX 119 help 120 Use MSI as source of PLL 121 122config CLOCK_STM32_PLL_SRC_HSI 123 bool "HSI" 124 help 125 Use HSI as source of PLL 126 127config CLOCK_STM32_PLL_SRC_HSE 128 bool "HSE" 129 help 130 Use HSE as source of PLL 131 132config CLOCK_STM32_PLL_SRC_PLL2 133 bool "PLL2" 134 depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE 135 help 136 Use PLL2 as source of main PLL. This is equivalent of defining 137 PLL2 as source PREDIV1SCR. If not selected, default source is HSE. 138 139config CLOCK_STM32_PLL_SRC_CSI 140 bool "CSI" 141 depends on SOC_SERIES_STM32H7X 142 help 143 Use CSI 4MHz as source of the main PLL. 144 145endchoice 146 147 148# Source series specific files for PLL settings 149 150source "drivers/clock_control/Kconfig.stm32f0_f3" 151source "drivers/clock_control/Kconfig.stm32f1" 152source "drivers/clock_control/Kconfig.stm32f2_f4_f7" 153source "drivers/clock_control/Kconfig.stm32h7" 154source "drivers/clock_control/Kconfig.stm32l0_l1" 155source "drivers/clock_control/Kconfig.stm32l4_l5_wb_wl" 156source "drivers/clock_control/Kconfig.stm32g0" 157source "drivers/clock_control/Kconfig.stm32g4" 158 159# Bus clocks configuration options 160 161if !SOC_SERIES_STM32H7X 162 163config CLOCK_STM32_AHB_PRESCALER 164 int "AHB prescaler" 165 default 1 166 range 1 512 167 depends on !SOC_SERIES_STM32WBX && !SOC_SERIES_STM32WLX 168 help 169 AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 170 256, 512. 171 172config CLOCK_STM32_APB1_PRESCALER 173 int "APB1 prescaler" 174 default 1 175 range 1 16 176 help 177 APB1 Low speed clock (PCLK1) prescaler, allowed values: 178 1, 2, 4, 8, 16 179 180config CLOCK_STM32_APB2_PRESCALER 181 int "APB2 prescaler" 182 default 1 183 range 1 16 184 depends on !SOC_SERIES_STM32F0X && !SOC_SERIES_STM32G0X 185 help 186 APB2 High speed clock (PCLK2) prescaler, allowed values: 187 1, 2, 4, 8, 16 188 189config CLOCK_STM32_CPU1_PRESCALER 190 int "CPU1 HCLK prescaler" 191 default 1 192 range 1 512 193 depends on SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX 194 help 195 CPU1 HCLK prescaler, allowed values: 1, 2, 3, 4, 5, 6, 8, 10, 16, 32, 196 64, 128, 256, 512. 197 198config CLOCK_STM32_CPU2_PRESCALER 199 int "CPU2 HCLK prescaler" 200 default 1 201 range 1 512 202 depends on SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX 203 help 204 CPU2 HCLK prescaler, allowed values: 1, 2, 3, 4, 5, 6, 8, 10, 16, 32, 205 64, 128, 256, 512. 206 207config CLOCK_STM32_AHB3_PRESCALER 208 int "AHB3 HCLK prescaler" 209 default 1 210 range 1 512 211 depends on SOC_SERIES_STM32WLX 212 help 213 HCLK4 prescaler, allowed values: 1, 2, 3, 4, 5, 6, 8, 10, 16, 32, 214 64, 128, 256, 512. 215 216config CLOCK_STM32_AHB4_PRESCALER 217 int "AHB4 HCLK prescaler" 218 default 1 219 range 1 512 220 depends on SOC_SERIES_STM32WBX 221 help 222 HCLK4 prescaler, allowed values: 1, 2, 3, 4, 5, 6, 8, 10, 16, 32, 223 64, 128, 256, 512. 224 225endif # !SOC_SERIES_STM32H7X && !SOC_SERIES_STM32MP1X 226 227endif # CLOCK_CONTROL_STM32_HAS_DTS 228 229# Micro-controller Clock output configuration options 230 231choice 232 prompt "STM32 MCO1 Clock Source" 233 default CLOCK_STM32_MCO1_SRC_NOCLOCK 234 235config CLOCK_STM32_MCO1_SRC_NOCLOCK 236 bool "NOCLOCK" 237 help 238 MCO1 output disabled, no clock on MCO1 239 240config CLOCK_STM32_MCO1_SRC_LSE 241 bool "LSE" 242 depends on SOC_SERIES_STM32F4X 243 help 244 Use LSE as source of MCO1 245 246config CLOCK_STM32_MCO1_SRC_HSE 247 bool "HSE" 248 depends on SOC_SERIES_STM32F4X 249 help 250 Use HSE as source of MCO1 251 252config CLOCK_STM32_MCO1_SRC_HSI 253 bool "HSI" 254 depends on SOC_SERIES_STM32F4X 255 help 256 Use HSI as source of MCO1 257 258config CLOCK_STM32_MCO1_SRC_PLLCLK 259 bool "PLLCLK" 260 depends on SOC_SERIES_STM32F4X 261 help 262 Use PLLCLK as source of MCO1 263 264endchoice 265 266config CLOCK_STM32_MCO1_DIV 267 int "MCO1 prescaler" 268 depends on !CLOCK_STM32_MCO1_SRC_NOCLOCK 269 default 1 270 range 1 5 271 help 272 allowed values: 1, 2, 3, 4, 5 273 274choice 275 prompt "STM32 MCO2 Clock Source" 276 default CLOCK_STM32_MCO2_SRC_NOCLOCK 277 278config CLOCK_STM32_MCO2_SRC_NOCLOCK 279 bool "NOCLOCK" 280 help 281 MCO2 output disabled, no clock on MCO2 282 283config CLOCK_STM32_MCO2_SRC_SYSCLK 284 bool "SYSCLK" 285 depends on SOC_SERIES_STM32F4X 286 help 287 Use SYSCLK as source of MCO2 288 289config CLOCK_STM32_MCO2_SRC_PLLI2S 290 bool "PLLI2S" 291 depends on SOC_SERIES_STM32F4X 292 help 293 Use PLLI2S as source of MCO2 294 295config CLOCK_STM32_MCO2_SRC_HSE 296 bool "HSE" 297 depends on SOC_SERIES_STM32F4X 298 help 299 Use HSE as source of MCO2 300 301config CLOCK_STM32_MCO2_SRC_PLLCLK 302 bool "PLLCLK" 303 depends on SOC_SERIES_STM32F4X 304 help 305 Use PLLCLK as source of MCO2 306 307endchoice 308 309config CLOCK_STM32_MCO2_DIV 310 int "MCO2 prescaler" 311 depends on !CLOCK_STM32_MCO2_SRC_NOCLOCK 312 default 1 313 range 1 5 314 help 315 allowed values: 1, 2, 3, 4, 5 316 317endif # CLOCK_CONTROL_STM32_CUBE 318
