1# General architecture configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# Copyright (c) 2015 Intel Corporation 5# Copyright (c) 2016 Cadence Design Systems, Inc. 6# SPDX-License-Identifier: Apache-2.0 7 8# Include these first so that any properties (e.g. defaults) below can be 9# overridden (by defining symbols in multiple locations) 10 11source "$(ARCH_DIR)/Kconfig.$(HWM_SCHEME)" 12 13# ToDo: Generate a Kconfig.arch for loading of additional arch in HWMv2. 14osource "$(KCONFIG_BINARY_DIR)/Kconfig.arch" 15 16# Architecture symbols 17# 18# Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that, 19# by SOC_*. 20 21config ARC 22 bool 23 select ARCH_IS_SET 24 imply XIP 25 select ARCH_HAS_THREAD_LOCAL_STORAGE 26 select ARCH_SUPPORTS_ROM_START 27 select ARCH_HAS_DIRECTED_IPIS 28 help 29 ARC architecture 30 31config ARM 32 bool 33 select ARCH_IS_SET 34 select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M 35 select ARCH_SUPPORTS_COREDUMP_THREADS if CPU_CORTEX_M 36 # FIXME: current state of the code for all ARM requires this, but 37 # is really only necessary for Cortex-M with ARM MPU! 38 select GEN_PRIV_STACKS 39 select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M || CPU_AARCH32_CORTEX_A 40 select BARRIER_OPERATIONS_ARCH 41 help 42 ARM architecture 43 44config ARM64 45 bool 46 select ARCH_IS_SET 47 select 64BIT 48 select ARCH_SUPPORTS_COREDUMP 49 select HAS_ARM_SMCCC 50 select ARCH_HAS_THREAD_LOCAL_STORAGE 51 select USE_SWITCH 52 select USE_SWITCH_SUPPORTED 53 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 54 select BARRIER_OPERATIONS_ARCH 55 select ARCH_HAS_DIRECTED_IPIS 56 help 57 ARM64 (AArch64) architecture 58 59config MIPS 60 bool 61 select ARCH_IS_SET 62 select ATOMIC_OPERATIONS_C 63 help 64 MIPS architecture 65 66config SPARC 67 bool 68 select ARCH_IS_SET 69 select USE_SWITCH 70 select USE_SWITCH_SUPPORTED 71 select BIG_ENDIAN 72 select ATOMIC_OPERATIONS_BUILTIN if SPARC_CASA 73 select ATOMIC_OPERATIONS_C if !SPARC_CASA 74 select ARCH_HAS_THREAD_LOCAL_STORAGE 75 select ARCH_HAS_EXTRA_EXCEPTION_INFO 76 help 77 SPARC architecture 78 79config X86 80 bool 81 select ARCH_IS_SET 82 select ATOMIC_OPERATIONS_BUILTIN 83 select ARCH_SUPPORTS_COREDUMP 84 select ARCH_SUPPORTS_ROM_START if !X86_64 85 select CPU_HAS_MMU 86 select ARCH_MEM_DOMAIN_DATA if USERSPACE && !X86_COMMON_PAGE_TABLE 87 select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE 88 select ARCH_HAS_GDBSTUB if !X86_64 89 select ARCH_HAS_TIMING_FUNCTIONS 90 select ARCH_HAS_THREAD_LOCAL_STORAGE 91 select ARCH_HAS_DEMAND_PAGING if !X86_64 92 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 93 select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \ 94 && !BOARD_HAS_TIMING_FUNCTIONS \ 95 && !SOC_HAS_TIMING_FUNCTIONS 96 select ARCH_HAS_STACK_CANARIES_TLS 97 select ARCH_SUPPORTS_MEM_MAPPED_STACKS if X86_MMU && !DEMAND_PAGING 98 help 99 x86 architecture 100 101config NIOS2 102 bool 103 select ARCH_IS_SET 104 select ATOMIC_OPERATIONS_C 105 imply XIP 106 select ARCH_HAS_TIMING_FUNCTIONS 107 help 108 Nios II Gen 2 architecture 109 110config RISCV 111 bool 112 select ARCH_IS_SET 113 select ARCH_SUPPORTS_COREDUMP 114 select ARCH_SUPPORTS_ROM_START if !SOC_FAMILY_ESPRESSIF_ESP32 115 select ARCH_HAS_CODE_DATA_RELOCATION 116 select ARCH_HAS_THREAD_LOCAL_STORAGE 117 select ARCH_HAS_STACKWALK 118 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 119 select USE_SWITCH_SUPPORTED 120 select USE_SWITCH 121 select SCHED_IPI_SUPPORTED if SMP 122 select ARCH_HAS_DIRECTED_IPIS 123 select BARRIER_OPERATIONS_BUILTIN 124 imply XIP 125 help 126 RISCV architecture 127 128config XTENSA 129 bool 130 select ARCH_IS_SET 131 select USE_SWITCH 132 select USE_SWITCH_SUPPORTED 133 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 134 select ARCH_HAS_CODE_DATA_RELOCATION 135 select ARCH_HAS_TIMING_FUNCTIONS 136 select ARCH_MEM_DOMAIN_DATA if USERSPACE 137 select ARCH_HAS_DIRECTED_IPIS 138 select THREAD_STACK_INFO 139 help 140 Xtensa architecture 141 142config ARCH_POSIX 143 bool 144 select ARCH_IS_SET 145 select ATOMIC_OPERATIONS_BUILTIN 146 select ARCH_HAS_CUSTOM_SWAP_TO_MAIN 147 select ARCH_HAS_CUSTOM_BUSY_WAIT 148 select ARCH_HAS_THREAD_ABORT 149 select NATIVE_BUILD 150 select HAS_COVERAGE_SUPPORT 151 select BARRIER_OPERATIONS_BUILTIN 152 # POSIX arch based targets get their memory cleared on entry by the host OS 153 select SKIP_BSS_CLEAR 154 # Override the C standard used for compilation to C 2011 155 # This is due to some tests using _Static_assert which is a 2011 feature, but 156 # otherwise relying on compilers supporting it also when set to C99. 157 # This was in general ok, but with some host compilers and C library versions 158 # it led to problems. So we override it to 2011 for the native targets. 159 select REQUIRES_STD_C11 160 help 161 POSIX (native) architecture 162 163config ARCH_IS_SET 164 bool 165 help 166 Helper symbol to detect SoCs forgetting to select one of the arch 167 symbols above. See the top-level CMakeLists.txt. 168 169menu "General Architecture Options" 170 171source "arch/common/Kconfig" 172 173module = ARCH 174module-str = arch 175source "subsys/logging/Kconfig.template.log_config" 176 177config BIG_ENDIAN 178 bool 179 help 180 This option tells the build system that the target system is big-endian. 181 Little-endian architecture is the default and should leave this option 182 unselected. This option is selected by arch/$ARCH/Kconfig, 183 soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid 184 modifying it. The option is used to select linker script OUTPUT_FORMAT 185 and command line option for gen_isr_tables.py. 186 187config LITTLE_ENDIAN 188 # Hidden Kconfig option representing the default little-endian architecture 189 # This is just the opposite of BIG_ENDIAN and is used for non-negative 190 # conditional compilation 191 bool 192 depends on !BIG_ENDIAN 193 default y 194 195config 64BIT 196 bool 197 help 198 This option tells the build system that the target system is 199 using a 64-bit address space, meaning that pointer and long types 200 are 64 bits wide. This option is selected by arch/$ARCH/Kconfig, 201 soc/**/Kconfig, or boards/**/Kconfig and the user should generally 202 avoid modifying it. 203 204# Workaround for not being able to have commas in macro arguments 205DT_CHOSEN_Z_SRAM := zephyr,sram 206 207config SRAM_SIZE 208 int "SRAM Size in kB" 209 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K) 210 help 211 The SRAM size in kB. The default value comes from /chosen/zephyr,sram in 212 devicetree. The user should generally avoid changing it via menuconfig or 213 in configuration files. 214 215config SRAM_BASE_ADDRESS 216 hex "SRAM Base Address" 217 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)) 218 help 219 The SRAM base address. The default value comes from 220 /chosen/zephyr,sram in devicetree. The user should generally avoid 221 changing it via menuconfig or in configuration files. 222 223if ARC || ARM || ARM64 || NIOS2 || X86 || RISCV 224 225# Workaround for not being able to have commas in macro arguments 226DT_CHOSEN_Z_FLASH := zephyr,flash 227 228config FLASH_SIZE 229 int "Flash Size in kB" 230 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && (ARM ||ARM64)) || !ARM 231 default 0 if !XIP 232 help 233 This option specifies the size of the flash in kB. It is normally set by 234 the board's defconfig file and the user should generally avoid modifying 235 it via the menu configuration. 236 237config FLASH_BASE_ADDRESS 238 hex "Flash Base Address" 239 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && (ARM || ARM64)) || !ARM 240 default 0 if !XIP 241 help 242 This option specifies the base address of the flash on the board. It is 243 normally set by the board's defconfig file and the user should generally 244 avoid modifying it via the menu configuration. 245 246endif # ARM || ARM64 || ARC || NIOS2 || X86 || RISCV 247 248if ARCH_HAS_TRUSTED_EXECUTION 249 250config TRUSTED_EXECUTION_SECURE 251 bool "Trusted Execution: Secure firmware image" 252 help 253 Select this option to enable building a Secure firmware 254 image for a platform that supports Trusted Execution. A 255 Secure firmware image will execute in Secure state. It may 256 allow the CPU to execute in Non-Secure (Normal) state. 257 Therefore, a Secure firmware image shall be able to 258 configure security attributions of CPU resources (memory 259 areas, peripherals, interrupts, etc.) as well as to handle 260 faults, related to security violations. It may optionally 261 allow certain functions to be called from the Non-Secure 262 (Normal) domain. 263 264config TRUSTED_EXECUTION_NONSECURE 265 depends on !TRUSTED_EXECUTION_SECURE 266 bool "Trusted Execution: Non-Secure firmware image" 267 help 268 Select this option to enable building a Non-Secure 269 firmware image for a platform that supports Trusted 270 Execution. A Non-Secure firmware image will execute 271 in Non-Secure (Normal) state. Therefore, it shall not 272 access CPU resources (memory areas, peripherals, 273 interrupts etc.) belonging to the Secure domain. 274 275endif # ARCH_HAS_TRUSTED_EXECUTION 276 277config HW_STACK_PROTECTION 278 bool "Hardware Stack Protection" 279 depends on ARCH_HAS_STACK_PROTECTION 280 help 281 Select this option to enable hardware-based platform features to 282 catch stack overflows when the system is running in privileged 283 mode. If CONFIG_USERSPACE is not enabled, the system is always 284 running in privileged mode. 285 286 Note that this does not necessarily prevent corruption and assertions 287 about the overall system state when a fault is triggered cannot be 288 made. 289 290config USERSPACE 291 bool "User mode threads" 292 depends on ARCH_HAS_USERSPACE 293 depends on RUNTIME_ERROR_CHECKS 294 depends on SRAM_REGION_PERMISSIONS 295 select THREAD_STACK_INFO 296 select LINKER_USE_NO_RELAX 297 help 298 When enabled, threads may be created or dropped down to user mode, 299 which has significantly restricted permissions and must interact 300 with the kernel via system calls. See Zephyr documentation for more 301 details about this feature. 302 303 If a user thread overflows its stack, this will be caught and the 304 kernel itself will be shielded from harm. Enabling this option 305 may or may not catch stack overflows when the system is in 306 privileged mode or handling a system call; to ensure these are always 307 caught, enable CONFIG_HW_STACK_PROTECTION. 308 309config PRIVILEGED_STACK_SIZE 310 int "Size of privileged stack" 311 default 2048 if EMUL 312 default 1024 313 depends on ARCH_HAS_USERSPACE 314 help 315 This option sets the privileged stack region size that will be used 316 in addition to the user mode thread stack. During normal execution, 317 this region will be inaccessible from user mode. During system calls, 318 this region will be utilized by the system call. This value must be 319 a multiple of the minimum stack alignment. 320 321config KOBJECT_TEXT_AREA 322 int "Size of kobject text area" 323 default 512 if COVERAGE_GCOV 324 default 512 if NO_OPTIMIZATIONS 325 default 512 if STACK_CANARIES && RISCV 326 default 256 327 depends on ARCH_HAS_USERSPACE 328 help 329 Size of kernel object text area. Used in linker script. 330 331config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT 332 int "Reserve extra kobject data area (in percentage)" 333 default 100 334 depends on ARCH_HAS_USERSPACE 335 help 336 Multiplication factor used to calculate the size of placeholder to 337 reserve space for kobject metadata hash table. The hash table is 338 generated via gperf is highly dependent on the absolute addresses of 339 kobjects which might change between prebuilts. To reserve enough 340 space for the hash table during final linking passes to keep 341 kobjects in same place, the size of reserved space is calculated 342 from the first prebuilt plus additional space calculated with 343 this percentage (of the kobject data area in first prebuilt). 344 345config KOBJECT_RODATA_AREA_EXTRA_BYTES 346 int "Reserve extra bytes for kobject rodata area" 347 default 16 348 depends on ARCH_HAS_USERSPACE 349 help 350 Reserve a few more bytes for the RODATA region for kobject metadata. 351 This is to account for the uncertainty of tables generated by gperf. 352 353config GEN_PRIV_STACKS 354 bool 355 help 356 Selected if the architecture requires that privilege elevation stacks 357 be allocated in a separate memory area. This is typical of arches 358 whose MPUs require regions to be power-of-two aligned/sized. 359 360 FIXME: This should be removed and replaced with checks against 361 CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT, but both ARM and ARC 362 changes will be necessary for this. 363 364config STACK_GROWS_UP 365 bool "Stack grows towards higher memory addresses" 366 help 367 Select this option if the architecture has upward growing thread 368 stacks. This is not common. 369 370config NO_UNUSED_STACK_INSPECTION 371 bool 372 help 373 Selected if the architecture will generate a fault if unused stack 374 memory is examined, which is the region between the current stack 375 pointer and the deepest available address in the current stack 376 region. 377 378config MAX_THREAD_BYTES 379 int "Bytes to use when tracking object thread permissions" 380 default 2 381 depends on USERSPACE 382 help 383 Every kernel object will have an associated bitfield to store 384 thread permissions for that object. This controls the size of the 385 bitfield (in bytes) and imposes a limit on how many threads can 386 be created in the system. 387 388config DYNAMIC_OBJECTS 389 bool "Allow kernel objects to be allocated at runtime" 390 depends on USERSPACE 391 help 392 Enabling this option allows for kernel objects to be requested from 393 the calling thread's resource pool, at a slight cost in performance 394 due to the supplemental run-time tables required to validate such 395 objects. 396 397 Objects allocated in this way can be freed with a supervisor-only 398 API call, or when the number of references to that object drops to 399 zero. 400 401config NOCACHE_MEMORY 402 bool "Support for uncached memory" 403 depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT 404 help 405 Add a "nocache" read-write memory section that is configured to 406 not be cached. This memory section can be used to perform DMA 407 transfers when cache coherence issues are not optimal or can not 408 be solved using cache maintenance operations. 409 410config FRAME_POINTER 411 bool "Compile the kernel with frame pointers" 412 select OVERRIDE_FRAME_POINTER_DEFAULT 413 help 414 Select Y here to gain precise stack traces at the expense of slightly 415 increased size and decreased speed. 416 417config ARCH_STACKWALK_MAX_FRAMES 418 int "Max depth for stack walk function" 419 default 8 420 depends on ARCH_HAS_STACKWALK 421 help 422 Depending on implementation, this can place a hard limit on the depths of the stack 423 for the stack walk function to examine. 424 425menu "Interrupt Configuration" 426 427config ISR_TABLES_LOCAL_DECLARATION_SUPPORTED 428 bool 429 default y 430 # Userspace is currently not supported 431 depends on !USERSPACE 432 # List of currently supported architectures 433 depends on ARM || ARM64 434 # List of currently supported toolchains 435 depends on "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" || "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "gnuarmemb" 436 437config ISR_TABLES_LOCAL_DECLARATION 438 bool "ISR tables created locally and placed by linker [EXPERIMENTAL]" 439 depends on ISR_TABLES_LOCAL_DECLARATION_SUPPORTED 440 select EXPERIMENTAL 441 help 442 Enable new scheme of interrupt tables generation. 443 This is totally different generator that would create tables entries locally 444 where the IRQ_CONNECT macro is called and then use the linker script to position it 445 in the right place in memory. 446 The most important advantage of such approach is that the generated interrupt tables 447 are LTO compatible. 448 The drawback is that the support on the architecture port is required. 449 450config DYNAMIC_INTERRUPTS 451 bool "Installation of IRQs at runtime" 452 help 453 Enable installation of interrupts at runtime, which will move some 454 interrupt-related data structures to RAM instead of ROM, and 455 on some architectures increase code size. 456 457config SHARED_INTERRUPTS 458 bool "Set this to enable support for shared interrupts" 459 depends on GEN_SW_ISR_TABLE 460 select EXPERIMENTAL 461 help 462 Set this to enable support for shared interrupts. Use this with 463 caution as enabling this will increase the image size by a 464 non-negligible amount. 465 466config SHARED_IRQ_MAX_NUM_CLIENTS 467 int "Maximum number of clients allowed per shared interrupt" 468 default 2 469 depends on SHARED_INTERRUPTS 470 help 471 This option controls the maximum number of clients allowed 472 per shared interrupt. Set this according to your needs. 473 474config GEN_ISR_TABLES 475 bool "Use generated IRQ tables" 476 help 477 This option controls whether a platform uses the gen_isr_tables 478 script to generate its interrupt tables. This mechanism will create 479 an appropriate hardware vector table and/or software IRQ table. 480 481config GEN_IRQ_VECTOR_TABLE 482 bool "Generate an interrupt vector table" 483 default y 484 depends on GEN_ISR_TABLES 485 help 486 This option controls whether a platform using gen_isr_tables 487 needs an interrupt vector table created. Only disable this if the 488 platform does not use a vector table at all, or requires the vector 489 table to be in a format that is not an array of function pointers 490 indexed by IRQ line. In the latter case, the vector table must be 491 supplied by the application or architecture code. 492 493config ARCH_IRQ_VECTOR_TABLE_ALIGN 494 int "Alignment size of the interrupt vector table" 495 default 4 496 depends on GEN_IRQ_VECTOR_TABLE 497 help 498 This option controls alignment size of generated 499 _irq_vector_table. Some architecture needs an IRQ vector table 500 to be aligned to architecture specific size. The default 501 size is 0 for no alignment. 502 503choice IRQ_VECTOR_TABLE_TYPE 504 prompt "IRQ vector table type" 505 depends on GEN_IRQ_VECTOR_TABLE 506 default IRQ_VECTOR_TABLE_JUMP_BY_CODE if (RISCV && !RISCV_HAS_CLIC) 507 default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS 508 509config IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS 510 bool "Jump by address" 511 help 512 The IRQ vector table contains the address of the interrupt handler. 513 514config IRQ_VECTOR_TABLE_JUMP_BY_CODE 515 bool "Jump by code" 516 help 517 The IRQ vector table contains the opcode of a jump instruction to the 518 interrupt handler address. 519 520endchoice 521 522config GEN_SW_ISR_TABLE 523 bool "Generate a software ISR table" 524 default y 525 depends on GEN_ISR_TABLES 526 help 527 This option controls whether a platform using gen_isr_tables 528 needs a software ISR table table created. This is an array of struct 529 _isr_table_entry containing the interrupt service routine and supplied 530 parameter. 531 532config ARCH_SW_ISR_TABLE_ALIGN 533 int "Alignment size of a software ISR table" 534 default 64 if RISCV_HAS_CLIC 535 default 4 536 depends on GEN_SW_ISR_TABLE 537 help 538 This option controls alignment size of generated 539 _sw_isr_table. Some architecture needs a software ISR table 540 to be aligned to architecture specific size. The default 541 size is 4. 542 543config GEN_IRQ_START_VECTOR 544 int 545 default 0 546 depends on GEN_ISR_TABLES 547 help 548 On some architectures, part of the vector table may be reserved for 549 system exceptions and is declared separately from the tables 550 created by gen_isr_tables.py. When creating these tables, this value 551 will be subtracted from CONFIG_NUM_IRQS to properly size them. 552 This is a hidden option which needs to be set per architecture and 553 left alone. 554 555config IRQ_OFFLOAD 556 bool "IRQ offload" 557 depends on TEST 558 help 559 Enable irq_offload() API which allows functions to be synchronously 560 run in interrupt context. Only useful for test cases that need 561 to validate the correctness of kernel objects in IRQ context. 562 563config IRQ_OFFLOAD_NESTED 564 bool "irq_offload() supports nested IRQs" 565 depends on IRQ_OFFLOAD 566 help 567 When set by the arch layer, indicates that irq_offload() may 568 legally be called in interrupt context to cause a 569 synchronous nested interrupt on the current CPU. Not all 570 hardware is capable. 571 572config EXCEPTION_DEBUG 573 bool "Unhandled exception debugging" 574 default y 575 depends on PRINTK || LOG 576 help 577 Install handlers for various CPU exception/trap vectors to 578 make debugging them easier, at a small expense in code size. 579 This prints out the specific exception vector and any associated 580 error codes. 581 582config EXTRA_EXCEPTION_INFO 583 bool "Collect extra exception info" 584 depends on ARCH_HAS_EXTRA_EXCEPTION_INFO 585 help 586 This option enables the collection of extra information, such as 587 register state, when a fault occurs. This information can be useful 588 to collect for post-mortem analysis and debug of issues. 589 590config SIMPLIFIED_EXCEPTION_CODES 591 bool "Convert arch specific exception codes to K_ERR_CPU_EXCEPTION" 592 default y if ZTEST 593 help 594 The same piece of faulty code (NULL dereference, etc) can result in 595 a multitude of potential exception codes at the CPU level, depending 596 upon whether addresses exist, an MPU is configured, the particular 597 implementation of the CPU or any number of other reasons. Enabling 598 this option collapses all the architecture specific exception codes 599 down to the generic K_ERR_CPU_EXCEPTION, which makes testing code 600 much more portable. 601 602endmenu # Interrupt configuration 603 604config INIT_ARCH_HW_AT_BOOT 605 bool "Initialize internal architecture state at boot" 606 depends on ARCH_SUPPORTS_ARCH_HW_INIT 607 help 608 This option instructs Zephyr to force the initialization 609 of the internal architectural state (for example ARCH-level 610 HW registers and system control blocks) during boot to 611 the reset values as specified by the corresponding 612 architecture manual. The option is useful when the Zephyr 613 firmware image is chain-loaded, for example, by a debugger 614 or a bootloader, and we need to guarantee that the internal 615 states of the architecture core blocks are restored to the 616 reset values (as specified by the architecture). 617 618 Note: the functionality is architecture-specific. For the 619 implementation details refer to each architecture where 620 this feature is supported. 621 622endmenu 623 624# 625# Architecture Capabilities 626# 627 628config ARCH_HAS_SINGLE_THREAD_SUPPORT 629 bool 630 631config ARCH_HAS_TIMING_FUNCTIONS 632 bool 633 634config ARCH_HAS_TRUSTED_EXECUTION 635 bool 636 637config ARCH_HAS_STACK_PROTECTION 638 bool 639 640config ARCH_HAS_USERSPACE 641 bool 642 643config ARCH_HAS_EXECUTABLE_PAGE_BIT 644 bool 645 646config ARCH_HAS_NOCACHE_MEMORY_SUPPORT 647 bool 648 649config ARCH_HAS_RAMFUNC_SUPPORT 650 bool 651 652config ARCH_HAS_NESTED_EXCEPTION_DETECTION 653 bool 654 655config ARCH_SUPPORTS_COREDUMP 656 bool 657 658config ARCH_SUPPORTS_COREDUMP_THREADS 659 bool 660 661config ARCH_SUPPORTS_ARCH_HW_INIT 662 bool 663 664config ARCH_SUPPORTS_ROM_START 665 bool 666 667config ARCH_HAS_EXTRA_EXCEPTION_INFO 668 bool 669 670config ARCH_HAS_GDBSTUB 671 bool 672 673config ARCH_HAS_STACKWALK 674 bool 675 help 676 This is selected when the architecture implemented the arch_stack_walk() API. 677 678config ARCH_HAS_COHERENCE 679 bool 680 help 681 When selected, the architecture supports the 682 arch_mem_coherent() API and can link into incoherent/cached 683 memory using the ".cached" linker section. 684 685config ARCH_HAS_THREAD_LOCAL_STORAGE 686 bool 687 688config ARCH_HAS_SUSPEND_TO_RAM 689 bool 690 help 691 When selected, the architecture supports suspend-to-RAM (S2RAM). 692 693config ARCH_HAS_STACK_CANARIES_TLS 694 bool 695 696config ARCH_SUPPORTS_MEM_MAPPED_STACKS 697 bool 698 help 699 Select when the architecture supports memory mapped stacks. 700 701# 702# Other architecture related options 703# 704 705config ARCH_HAS_THREAD_ABORT 706 bool 707 708config ARCH_HAS_CODE_DATA_RELOCATION 709 bool 710 help 711 When selected, the architecture/SoC implements support for 712 CODE_DATA_RELOCATION in its linker scripts. 713 714# 715# Hidden CPU family configs 716# 717 718config CPU_HAS_TEE 719 bool 720 help 721 This option is enabled when the CPU has support for Trusted 722 Execution Environment (e.g. when it has a security attribution 723 unit). 724 725config CPU_HAS_DCLS 726 bool 727 help 728 This option is enabled when the processor hardware has support for 729 Dual-redundant Core Lock-step (DCLS) topology. 730 731config CPU_HAS_FPU 732 bool 733 help 734 This option is enabled when the CPU has hardware floating point 735 unit. 736 737config CPU_HAS_DSP 738 bool 739 help 740 This option is enabled when the CPU has hardware DSP unit. 741 742config CPU_HAS_FPU_DOUBLE_PRECISION 743 bool 744 select CPU_HAS_FPU 745 help 746 When enabled, this indicates that the CPU has a double floating point 747 precision unit. 748 749config CPU_HAS_MPU 750 bool 751 help 752 This option is enabled when the CPU has a Memory Protection Unit (MPU). 753 754config CPU_HAS_MMU 755 bool 756 help 757 This hidden option is selected when the CPU has a Memory Management Unit 758 (MMU). 759 760config ARCH_HAS_DEMAND_PAGING 761 bool 762 help 763 This hidden configuration should be selected by the architecture if 764 demand paging is supported. 765 766config ARCH_HAS_RESERVED_PAGE_FRAMES 767 bool 768 help 769 This hidden configuration should be selected by the architecture if 770 certain RAM page frames need to be marked as reserved and never used for 771 memory mappings. The architecture will need to implement 772 arch_reserved_pages_update(). 773 774config ARCH_HAS_DIRECTED_IPIS 775 bool 776 help 777 This hidden configuration should be selected by the architecture if 778 it has an implementation for arch_sched_directed_ipi() which allows 779 for IPIs to be directed to specific CPUs. 780 781config CPU_HAS_DCACHE 782 bool 783 help 784 This hidden configuration should be selected when the CPU has a d-cache. 785 786config CPU_CACHE_INCOHERENT 787 bool 788 help 789 This hidden configuration should be selected when the CPU has 790 incoherent cache. This applies to intra-CPU multiprocessing 791 incoherence and makes only sense when MP_NUM_CPUS > 1. 792 793config CPU_HAS_ICACHE 794 bool 795 help 796 This hidden configuration should be selected when the CPU has an i-cache. 797 798config ARCH_MAPS_ALL_RAM 799 bool 800 help 801 This hidden option is selected by the architecture to inform the kernel 802 that all RAM is mapped at boot, and not just the bounds of the Zephyr image. 803 If RAM starts at 0x0, the first page must remain un-mapped to catch NULL 804 pointer dereferences. With this enabled, the kernel will not assume that 805 virtual memory addresses past the kernel image are available for mappings, 806 but instead takes into account an entire RAM mapping instead. 807 808 This is typically set by architectures which need direct access to all memory. 809 It is the architecture's responsibility to mark reserved memory regions 810 as such in arch_reserved_pages_update(). 811 812 Although the kernel will not disturb this RAM mapping by re-mapping the associated 813 virtual addresses elsewhere, this is limited to only management of the 814 virtual address space. The kernel's page frame ontology will not consider 815 this mapping at all; non-kernel pages will be considered free (unless marked 816 as reserved) and K_MEM_PAGE_FRAME_MAPPED will not be set. 817 818config DCLS 819 bool "Processor is configured in DCLS mode" 820 depends on CPU_HAS_DCLS 821 default y 822 help 823 This option is enabled when the processor hardware is configured in 824 Dual-redundant Core Lock-step (DCLS) topology. For the processor that 825 supports DCLS, but is configured in split-lock mode (by default or 826 changed at flash time), this option should be disabled. 827 828menuconfig MPU 829 bool "MPU features" 830 depends on CPU_HAS_MPU 831 help 832 This option, when enabled, indicates to the core kernel that an MPU 833 is enabled. 834 835if MPU 836module = MPU 837module-str = mpu 838source "subsys/logging/Kconfig.template.log_config" 839 840config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT 841 bool 842 help 843 This option is enabled when the MPU requires a power of two alignment 844 and size for MPU regions. 845 846config MPU_REQUIRES_NON_OVERLAPPING_REGIONS 847 bool 848 help 849 This option is enabled when the MPU requires the active (i.e. enabled) 850 MPU regions to be non-overlapping with each other. 851 852config MPU_GAP_FILLING 853 bool "Force MPU to be filling in background memory regions" 854 depends on MPU_REQUIRES_NON_OVERLAPPING_REGIONS 855 default y if !USERSPACE 856 help 857 This Kconfig option instructs the MPU driver to enforce 858 a full kernel SRAM partitioning, when it programs the 859 dynamic MPU regions (user thread stack, PRIV stack guard 860 and application memory domains) during context-switch. We 861 allow this to be a configurable option, in order to be able 862 to switch the option off and have an increased number of MPU 863 regions available for application memory domain programming. 864 865 Notes: 866 An increased number of MPU regions should only be required, 867 when building with USERSPACE support. As a result, when we 868 build without USERSPACE support, gap filling should always 869 be required. 870 871 When the option is switched off, access to memory areas not 872 covered by explicit MPU regions is restricted to privileged 873 code on an ARCH-specific basis. Refer to ARCH-specific 874 documentation for more information on how this option is 875 used. 876 877endif # MPU 878 879config SRAM_REGION_PERMISSIONS 880 bool "Assign appropriate permissions to kernel areas in SRAM" 881 depends on MMU || MPU 882 default y 883 help 884 This option indicates that memory protection hardware 885 is present, enabled, and regions have been configured at boot for memory 886 ranges within the kernel image. 887 888 If this option is turned on, certain areas of the kernel image will 889 have the following access policies applied for all threads, including 890 supervisor threads: 891 892 1) All program text will be have read-only, execute memory permission 893 2) All read-only data will have read-only permission, and execution 894 disabled if the hardware supports it. 895 3) All other RAM addresses will have read-write permission, and 896 execution disabled if the hardware supports it. 897 898 Options such as USERSPACE or HW_STACK_PROTECTION may additionally 899 impose additional policies on the memory map, which may be global 900 or local to the current running thread. 901 902 This option may consume additional memory to satisfy memory protection 903 hardware alignment constraints. 904 905 If this option is disabled, the entire kernel will have default memory 906 access permissions set, typically read/write/execute. It may be desirable 907 to turn this off on MMU systems which are using the MMU for demand 908 paging, do not need memory protection, and would rather not use up 909 RAM for the alignment between regions. 910 911config CODE_DATA_RELOCATION 912 bool "Support code/data section relocation" 913 depends on ARCH_HAS_CODE_DATA_RELOCATION 914 help 915 Enable support for relocating .text, data and .bss sections from specified 916 files and placing them in a chosen memory region. Files to relocate and 917 the target regions should be specified in CMakeLists.txt using 918 zephyr_code_relocate(). 919 920menu "DSP Options" 921 922config DSP_SHARING 923 bool "DSP register sharing" 924 depends on CPU_HAS_DSP 925 help 926 This option enables preservation of the hardware DSP registers 927 across context switches to allow multiple threads to perform concurrent 928 DSP operations. 929endmenu 930 931menu "Floating Point Options" 932 933config FPU 934 bool "Floating point unit (FPU)" 935 depends on CPU_HAS_FPU 936 help 937 This option enables the hardware Floating Point Unit (FPU), in order to 938 support using the floating point registers and instructions. 939 940 When this option is enabled, by default, threads may use the floating 941 point registers only in an exclusive manner, and this usually means that 942 only one thread may perform floating point operations. 943 944 If it is necessary for multiple threads to perform concurrent floating 945 point operations, the "FPU register sharing" option must be enabled to 946 preserve the floating point registers across context switches. 947 948 Note that this option cannot be selected for the platforms that do not 949 include a hardware floating point unit; the floating point support for 950 those platforms is dependent on the availability of the toolchain- 951 provided software floating point library. 952 953config FPU_SHARING 954 bool "FPU register sharing" 955 depends on FPU && MULTITHREADING 956 help 957 This option enables preservation of the hardware floating point registers 958 across context switches to allow multiple threads to perform concurrent 959 floating point operations. 960 961 Note that some compiler configurations may activate a floating point 962 context by generating FP instructions for any thread, and that 963 context must be preserved when switching such threads in and out. 964 The developers can still disable the FP sharing mode in their 965 application projects, and switch to Unshared FP registers mode, 966 if it is guaranteed that the image code does not generate FP 967 instructions outside the single thread context that is allowed 968 to do so. 969 970endmenu 971 972menu "Cache Options" 973 974config DCACHE 975 bool "Data cache (d-cache) support" 976 depends on CPU_HAS_DCACHE 977 default y 978 help 979 This option enables the support for the data cache (d-cache). 980 981config ICACHE 982 bool "Instruction cache (i-cache) support" 983 depends on CPU_HAS_ICACHE 984 default y 985 help 986 This option enables the support for the instruction cache (i-cache). 987 988config CACHE_DOUBLEMAP 989 bool "Cache double-mapping support" 990 depends on CPU_CACHE_INCOHERENT 991 default y 992 help 993 Double-mapping behavior where a pointer can be cheaply converted to 994 point to the same cached/uncached memory at different locations. 995 996 This applies to intra-CPU multiprocessing incoherence and makes only 997 sense when MP_NUM_CPUS > 1. 998 999config CACHE_MANAGEMENT 1000 bool "Cache management features" 1001 depends on DCACHE || ICACHE 1002 help 1003 This option enables the cache management functions backed by arch or 1004 driver code. 1005 1006config DCACHE_LINE_SIZE_DETECT 1007 bool "Detect d-cache line size at runtime" 1008 depends on CACHE_MANAGEMENT && DCACHE 1009 help 1010 This option enables querying some architecture-specific hardware for 1011 finding the d-cache line size at the expense of taking more memory and 1012 code and a slightly increased boot time. 1013 1014 If the CPU's d-cache line size is known in advance, disable this option and 1015 manually enter the value for DCACHE_LINE_SIZE or set it in the DT 1016 using the 'd-cache-line-size' property. 1017 1018config DCACHE_LINE_SIZE 1019 int "d-cache line size" 1020 depends on CACHE_MANAGEMENT && DCACHE && !DCACHE_LINE_SIZE_DETECT 1021 default 0 1022 help 1023 Size in bytes of a CPU d-cache line. If this is set to 0 the value is 1024 obtained from the 'd-cache-line-size' DT property instead if present. 1025 1026 1027 Detect automatically at runtime by selecting DCACHE_LINE_SIZE_DETECT. 1028 1029config ICACHE_LINE_SIZE_DETECT 1030 bool "Detect i-cache line size at runtime" 1031 depends on CACHE_MANAGEMENT && ICACHE 1032 help 1033 This option enables querying some architecture-specific hardware for 1034 finding the i-cache line size at the expense of taking more memory and 1035 code and a slightly increased boot time. 1036 1037 If the CPU's i-cache line size is known in advance, disable this option and 1038 manually enter the value for ICACHE_LINE_SIZE or set it in the DT 1039 using the 'i-cache-line-size' property. 1040 1041config ICACHE_LINE_SIZE 1042 int "i-cache line size" 1043 depends on CACHE_MANAGEMENT && ICACHE && !ICACHE_LINE_SIZE_DETECT 1044 default 0 1045 help 1046 Size in bytes of a CPU i-cache line. If this is set to 0 the value is 1047 obtained from the 'i-cache-line-size' DT property instead if present. 1048 1049 Detect automatically at runtime by selecting ICACHE_LINE_SIZE_DETECT. 1050 1051choice CACHE_TYPE 1052 prompt "Cache type" 1053 depends on CACHE_MANAGEMENT 1054 default ARCH_CACHE 1055 1056config ARCH_CACHE 1057 bool "Integrated cache controller" 1058 help 1059 Integrated on-core cache controller 1060 1061config EXTERNAL_CACHE 1062 bool "External cache controller" 1063 help 1064 External cache controller 1065 1066endchoice 1067 1068endmenu 1069 1070config ARCH 1071 string 1072 help 1073 System architecture string. 1074 1075config TOOLCHAIN_HAS_BUILTIN_FFS 1076 bool 1077 default y if !(64BIT && RISCV) 1078 help 1079 Hidden option to signal that toolchain has __builtin_ffs*(). 1080 1081config ARCH_CPU_IDLE_CUSTOM 1082 bool "Custom arch_cpu_idle implementation" 1083 default n 1084 help 1085 This options allows applications to override the default arch idle implementation with 1086 a custom one. 1087
