1# ARM core configuration options
2
3# Copyright (c) 2015 Wind River Systems, Inc.
4# SPDX-License-Identifier: Apache-2.0
5
6config CPU_CORTEX_M
7	bool
8	select CPU_CORTEX
9	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
10	select HAS_CMSIS_CORE
11	select HAS_FLASH_LOAD_OFFSET
12	select ARCH_HAS_SINGLE_THREAD_SUPPORT
13	select ARCH_HAS_THREAD_ABORT
14	select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
15	select ARCH_HAS_STACK_PROTECTION if (ARM_MPU && !ARMV6_M_ARMV8_M_BASELINE) || CPU_CORTEX_M_HAS_SPLIM
16	select ARCH_HAS_USERSPACE if ARM_MPU
17	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_CORTEX_M7
18	select ARCH_HAS_RAMFUNC_SUPPORT
19	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
20	select SWAP_NONATOMIC
21	select ARCH_HAS_EXTRA_EXCEPTION_INFO
22	select ARCH_HAS_TIMING_FUNCTIONS if CPU_CORTEX_M_HAS_DWT
23	select ARCH_SUPPORTS_ARCH_HW_INIT
24	imply XIP
25	help
26	  This option signifies the use of a CPU of the Cortex-M family.
27
28config CPU_CORTEX_R
29	bool
30	select CPU_CORTEX
31	select HAS_CMSIS_CORE
32	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
33	select HAS_FLASH_LOAD_OFFSET
34	select ARCH_HAS_USERSPACE if ARM_MPU
35	select ARCH_HAS_EXTRA_EXCEPTION_INFO
36	help
37	  This option signifies the use of a CPU of the Cortex-R family.
38
39config ISA_THUMB2
40	bool
41	help
42	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
43
44	  Thumb-2 technology is the instruction set underlying the ARM Cortex
45	  architecture which provides enhanced levels of performance, energy
46	  efficiency, and code density for a wide range of embedded
47	  applications.
48
49	  Thumb-2 technology builds on the success of Thumb, the innovative
50	  high code density instruction set for ARM microprocessor cores, to
51	  increase the power of the ARM microprocessor core available to
52	  developers of low cost, high performance systems.
53
54	  The technology is backwards compatible with existing ARM and Thumb
55	  solutions, while significantly extending the features available to
56	  the Thumb instructions set. This allows more of the application to
57	  benefit from the best in class code density of Thumb.
58
59	  For performance optimized code Thumb-2 technology uses 31 percent
60	  less memory to reduce system cost, while providing up to 38 percent
61	  higher performance than existing high density code, which can be used
62	  to prolong battery-life or to enrich the product feature set. Thumb-2
63	  technology is featured in the  processor, and in all ARMv7
64	  architecture-based processors.
65
66config ISA_ARM
67	bool
68	help
69	  From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
70
71	  A32 instructions, known as Arm instructions in pre-Armv8 architectures,
72	  are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
73	  are supported by both A-profile and R-profile architectures.
74
75	  A32 was traditionally used in applications requiring the highest
76	  performance, or for handling hardware exceptions such as interrupts and
77	  processor start-up. Much of its functionality was subsumed into T32 with
78	  the introduction of Thumb-2 technology.
79
80config ASSEMBLER_ISA_THUMB2
81	bool
82	default y if ISA_THUMB2 && !ISA_ARM
83	depends on !ISA_ARM
84	help
85	  This helper symbol specifies the default target instruction set for
86	  the assembler.
87
88	  When only the Thumb-2 ISA is supported (i.e. on Cortex-M cores), the
89	  assembler must use the Thumb-2 instruction set.
90
91	  When both the Thumb-2 and ARM ISAs are supported (i.e. on Cortex-A
92	  and Cortex-R cores), the assembler must use the ARM instruction set
93	  because the architecture assembly code makes use of the ARM
94	  instructions.
95
96config COMPILER_ISA_THUMB2
97	bool "Compile C/C++ functions using Thumb-2 instruction set"
98	depends on ISA_THUMB2
99	default y
100	help
101	  This option configures the compiler to compile all C/C++ functions
102	  using the Thumb-2 instruction set.
103
104	  N.B. The scope of this symbol is not necessarily limited to the C and
105	       C++ languages; in fact, this symbol refers to all forms of
106	       "compiled" code.
107
108	       When an additional natively-compiled language support is added
109	       in the future, this symbol shall also specify the Thumb-2
110	       instruction set for that language.
111
112config NUM_IRQS
113	int
114
115config STACK_ALIGN_DOUBLE_WORD
116	bool "Align stacks on double-words (8 octets)"
117	default y
118	help
119	  This is needed to conform to AAPCS, the procedure call standard for
120	  the ARM. It wastes stack space. The option also enforces alignment
121	  of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
122	  Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
123	  on exception entry is enabled by default and it is not configurable.
124
125config RUNTIME_NMI
126	bool "Attach an NMI handler at runtime"
127	select REBOOT
128	help
129	  The kernel provides a simple NMI handler that simply hangs in a tight
130	  loop if triggered. This fills the requirement that there must be an
131	  NMI handler installed when the CPU boots. If a custom handler is
132	  needed, enable this option and attach it via _NmiHandlerSet().
133
134config PLATFORM_SPECIFIC_INIT
135	bool "Enable platform (SOC) specific startup hook"
136	help
137	  The platform specific initialization code (z_arm_platform_init) is
138	  executed at the beginning of the startup code (__start).
139
140config FAULT_DUMP
141	int "Fault dump level"
142	default 2
143	range 0 2
144	help
145	  Different levels for display information when a fault occurs.
146
147	  2: The default. Display specific and verbose information. Consumes
148		the most memory (long strings).
149
150	  1: Display general and short information. Consumes less memory
151		(short strings).
152
153	  0: Off.
154
155config BUILTIN_STACK_GUARD
156	bool "Thread Stack Guards based on built-in ARM stack limit checking"
157	depends on CPU_CORTEX_M_HAS_SPLIM
158	select THREAD_STACK_INFO
159	help
160	  Enable Thread/Interrupt Stack Guards via built-in Stack Pointer
161	  limit checking. The functionality must be supported by HW.
162
163config ARM_STACK_PROTECTION
164	bool
165	default y if HW_STACK_PROTECTION
166	imply BUILTIN_STACK_GUARD if CPU_CORTEX_M_HAS_SPLIM
167	select MPU_STACK_GUARD if (!BUILTIN_STACK_GUARD && ARM_MPU)
168	help
169	  This option enables either:
170	  - The built-in Stack Pointer limit checking, or
171	  - the MPU-based stack guard
172	  to cause a system fatal error
173	  if the bounds of the current process stack are overflowed.
174	  The two stack guard options are mutually exclusive. The
175	  selection of the built-in Stack Pointer limit checking is
176	  prioritized over the MPU-based stack guard. The developer
177	  still has the option to manually select the MPU-based
178	  stack guard, if this is desired.
179
180config ARM_SECURE_FIRMWARE
181	bool
182	depends on ARMV8_M_SE
183	default y if TRUSTED_EXECUTION_SECURE
184	help
185	  This option indicates that we are building a Zephyr image that
186	  is intended to execute in Secure state. The option is only
187	  applicable to ARMv8-M MCUs that implement the Security Extension.
188
189	  This option enables Zephyr to include code that executes in
190	  Secure state, as well as to exclude code that is designed to
191	  execute only in Non-secure state.
192
193	  Code executing in Secure state has access to both the Secure
194	  and Non-Secure resources of the Cortex-M MCU.
195
196	  Code executing in Non-Secure state may trigger Secure Faults,
197	  if Secure MCU resources are accessed from the Non-Secure state.
198	  Secure Faults may only be handled by code executing in Secure
199	  state.
200
201config ARM_NONSECURE_FIRMWARE
202	bool
203	depends on !ARM_SECURE_FIRMWARE
204	depends on ARMV8_M_SE
205	default y if TRUSTED_EXECUTION_NONSECURE
206	help
207	  This option indicates that we are building a Zephyr image that
208	  is intended to execute in Non-Secure state. Execution of this
209	  image is triggered by Secure firmware that executes in Secure
210	  state. The option is only applicable to ARMv8-M MCUs that
211	  implement the Security Extension.
212
213	  This option enables Zephyr to include code that executes in
214	  Non-Secure state only, as well as to exclude code that is
215	  designed to execute only in Secure state.
216
217	  Code executing in Non-Secure state has no access to Secure
218	  resources of the Cortex-M MCU, and, therefore, it shall avoid
219	  accessing them.
220
221config ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS
222	bool "Allow secure function calls to be preempted"
223	depends on ARM_NONSECURE_FIRMWARE
224	help
225	  When enabled, this option indicates that preemptible Zephyr
226	  threads performing secure function calls, are allowed to be
227	  preempted. When disabled, the option indicates that such
228	  threads many not be context-switched-out while doing a Secure
229	  function call.
230
231config ARM_STORE_EXC_RETURN
232	bool
233	default y if FPU_SHARING || ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS
234	help
235	  Store the EXC_RETURN value when switching threads.
236	  This is needed when switching between threads that differ in either
237	  FPU usage or security domain.
238
239choice
240	prompt "Floating point ABI"
241	default FP_HARDABI
242	depends on FPU
243
244config FP_HARDABI
245	bool "Floating point Hard ABI"
246	depends on !BUILD_WITH_TFM
247	help
248	  This option selects the Floating point ABI in which hardware floating
249	  point instructions are generated and uses FPU-specific calling
250	  conventions.
251	  Note: the option is disabled for Zephyr builds with TF-M, as TF-M
252	  does not currently support building with Hard ABI, hence linking
253	  Zephyr with TF-M libraries would not be possible.
254
255config FP_SOFTABI
256	bool "Floating point Soft ABI"
257	help
258	  This option selects the Floating point ABI in which hardware floating
259	  point instructions are generated but soft-float calling conventions.
260
261endchoice
262
263config FP16
264	bool "Half-precision floating point support"
265	default y
266	help
267	  This option enables the half-precision (16-bit) floating point support
268	  via the `__fp16` (both IEEE and ARM alternative formats) and the
269	  `_Float16` (IEEE format only) types.
270
271choice
272	prompt "FP16 format"
273	default FP16_IEEE
274	depends on FP16
275
276config FP16_IEEE
277	bool "FP16 IEEE format"
278	help
279	  This option selects the IEEE 754-2008 format for FP16.  This format can
280	  represent normalized values in the range of 2^(-14) to 65504.  There are
281	  11 bits of significand precision, approximately 3 decimal digits.
282
283config FP16_ALT
284	bool "FP16 ARM alternative format"
285	help
286	  This option selects the ARM alternative format for FP16.  This
287	  representation is similar to the IEEE 754-2008 format, but does not
288	  support infinites or NaNs. Instead, the range of exponents is extended,
289	  so that this format can represent normalized values in the range of
290	  2^(-14) to 131008.
291
292endchoice
293
294rsource "cortex_m/Kconfig"
295rsource "cortex_a_r/Kconfig"
296
297rsource "mpu/Kconfig"
298