1# ARM core configuration options
2
3# Copyright (c) 2015 Wind River Systems, Inc.
4# SPDX-License-Identifier: Apache-2.0
5
6config CPU_CORTEX_M
7	bool
8	select CPU_CORTEX
9	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
10	select HAS_CMSIS_CORE
11	select HAS_FLASH_LOAD_OFFSET
12	select ARCH_HAS_SINGLE_THREAD_SUPPORT
13	select ARCH_HAS_THREAD_ABORT
14	select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
15	select ARCH_HAS_STACK_PROTECTION if (ARM_MPU && !ARMV6_M_ARMV8_M_BASELINE) || CPU_CORTEX_M_HAS_SPLIM
16	select ARCH_HAS_USERSPACE if ARM_MPU
17	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
18	select ARCH_HAS_RAMFUNC_SUPPORT
19	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
20	select SWAP_NONATOMIC
21	select ARCH_HAS_EXTRA_EXCEPTION_INFO
22	select ARCH_HAS_TIMING_FUNCTIONS if CPU_CORTEX_M_HAS_DWT
23	select ARCH_SUPPORTS_ARCH_HW_INIT
24	select ARCH_HAS_SUSPEND_TO_RAM
25	select ARCH_HAS_CODE_DATA_RELOCATION
26	select ARCH_SUPPORTS_ROM_START
27	imply XIP
28	help
29	  This option signifies the use of a CPU of the Cortex-M family.
30
31config CPU_AARCH32_CORTEX_R
32	bool
33	select CPU_CORTEX
34	select HAS_CMSIS_CORE
35	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
36	select HAS_FLASH_LOAD_OFFSET
37	select ARCH_HAS_USERSPACE if ARM_MPU && !USE_SWITCH
38	select ARCH_HAS_EXTRA_EXCEPTION_INFO if !USE_SWITCH
39	select ARCH_HAS_CODE_DATA_RELOCATION
40	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
41	select ARCH_SUPPORTS_ROM_START
42	select USE_SWITCH_SUPPORTED
43	help
44	  This option signifies the use of a CPU of the Cortex-R family.
45
46config ARM_ZIMAGE_HEADER
47	bool "zImage Header"
48	depends on CPU_AARCH32_CORTEX_R || CPU_AARCH32_CORTEX_A || CPU_CORTEX_M_HAS_VTOR
49	help
50	  This option adds a zImage Header.
51
52config CPU_AARCH32_CORTEX_A
53	bool
54	select CPU_CORTEX
55	select CPU_HAS_MMU
56	select HAS_CMSIS_CORE
57	select HAS_FLASH_LOAD_OFFSET
58	select ARCH_HAS_EXTRA_EXCEPTION_INFO if !USE_SWITCH
59	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
60	select USE_SWITCH_SUPPORTED
61	# GDBSTUB has not yet been tested on Cortex M or R SoCs
62	select ARCH_HAS_GDBSTUB
63	# GDB on ARM needs the extra registers
64	select EXTRA_EXCEPTION_INFO if GDBSTUB
65	help
66	  This option signifies the use of a CPU of the Cortex-A family.
67
68config GDBSTUB_BUF_SZ
69	# GDB for ARM expects up to 18 4-byte plus 8 12-byte
70	# registers - 336 HEX letters
71	default 350 if GDBSTUB
72
73config ISA_THUMB2
74	bool
75	help
76	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
77
78	  Thumb-2 technology is the instruction set underlying the ARM Cortex
79	  architecture which provides enhanced levels of performance, energy
80	  efficiency, and code density for a wide range of embedded
81	  applications.
82
83	  Thumb-2 technology builds on the success of Thumb, the innovative
84	  high code density instruction set for ARM microprocessor cores, to
85	  increase the power of the ARM microprocessor core available to
86	  developers of low cost, high performance systems.
87
88	  The technology is backwards compatible with existing ARM and Thumb
89	  solutions, while significantly extending the features available to
90	  the Thumb instructions set. This allows more of the application to
91	  benefit from the best in class code density of Thumb.
92
93	  For performance optimized code Thumb-2 technology uses 31 percent
94	  less memory to reduce system cost, while providing up to 38 percent
95	  higher performance than existing high density code, which can be used
96	  to prolong battery-life or to enrich the product feature set. Thumb-2
97	  technology is featured in the  processor, and in all ARMv7
98	  architecture-based processors.
99
100config ISA_ARM
101	bool
102	help
103	  From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
104
105	  A32 instructions, known as Arm instructions in pre-Armv8 architectures,
106	  are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
107	  are supported by both A-profile and R-profile architectures.
108
109	  A32 was traditionally used in applications requiring the highest
110	  performance, or for handling hardware exceptions such as interrupts and
111	  processor start-up. Much of its functionality was subsumed into T32 with
112	  the introduction of Thumb-2 technology.
113
114config ASSEMBLER_ISA_THUMB2
115	bool
116	default y if ISA_THUMB2 && !ISA_ARM
117	depends on !ISA_ARM
118	help
119	  This helper symbol specifies the default target instruction set for
120	  the assembler.
121
122	  When only the Thumb-2 ISA is supported (i.e. on Cortex-M cores), the
123	  assembler must use the Thumb-2 instruction set.
124
125	  When both the Thumb-2 and ARM ISAs are supported (i.e. on Cortex-A
126	  and Cortex-R cores), the assembler must use the ARM instruction set
127	  because the architecture assembly code makes use of the ARM
128	  instructions.
129
130config COMPILER_ISA_THUMB2
131	bool "Compile C/C++ functions using Thumb-2 instruction set"
132	depends on ISA_THUMB2
133	default y
134	help
135	  This option configures the compiler to compile all C/C++ functions
136	  using the Thumb-2 instruction set.
137
138	  N.B. The scope of this symbol is not necessarily limited to the C and
139	       C++ languages; in fact, this symbol refers to all forms of
140	       "compiled" code.
141
142	       When an additional natively-compiled language support is added
143	       in the future, this symbol shall also specify the Thumb-2
144	       instruction set for that language.
145
146config NUM_IRQS
147	int
148
149config STACK_ALIGN_DOUBLE_WORD
150	bool "Align stacks on double-words (8 octets)"
151	default y
152	help
153	  This is needed to conform to AAPCS, the procedure call standard for
154	  the ARM. It wastes stack space. The option also enforces alignment
155	  of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
156	  Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
157	  on exception entry is enabled by default and it is not configurable.
158
159config RUNTIME_NMI
160	bool "Attach an NMI handler at runtime"
161	select REBOOT
162	help
163	  The kernel provides a simple NMI handler that simply hangs in a tight
164	  loop if triggered. This fills the requirement that there must be an
165	  NMI handler installed when the CPU boots. If a custom handler is
166	  needed, enable this option and attach it via z_arm_nmi_set_handler().
167
168config PLATFORM_SPECIFIC_INIT
169	bool "Platform (SOC) specific startup hook"
170	help
171	  The platform specific initialization code (z_arm_platform_init) is
172	  executed at the beginning of the startup code (__start).
173
174config FAULT_DUMP
175	int "Fault dump level"
176	default 2
177	range 0 2
178	help
179	  Different levels for display information when a fault occurs.
180
181	  2: The default. Display specific and verbose information. Consumes
182		the most memory (long strings).
183
184	  1: Display general and short information. Consumes less memory
185		(short strings).
186
187	  0: Off.
188
189config BUILTIN_STACK_GUARD
190	bool "Thread Stack Guards based on built-in ARM stack limit checking"
191	depends on CPU_CORTEX_M_HAS_SPLIM
192	select THREAD_STACK_INFO
193	help
194	  Enable Thread/Interrupt Stack Guards via built-in Stack Pointer
195	  limit checking. The functionality must be supported by HW.
196
197config ARM_STACK_PROTECTION
198	bool
199	default y if HW_STACK_PROTECTION
200	imply BUILTIN_STACK_GUARD if CPU_CORTEX_M_HAS_SPLIM
201	select MPU_STACK_GUARD if (!BUILTIN_STACK_GUARD && ARM_MPU)
202	help
203	  This option enables either:
204	  - The built-in Stack Pointer limit checking, or
205	  - the MPU-based stack guard
206	  to cause a system fatal error
207	  if the bounds of the current process stack are overflowed.
208	  The two stack guard options are mutually exclusive. The
209	  selection of the built-in Stack Pointer limit checking is
210	  prioritized over the MPU-based stack guard. The developer
211	  still has the option to manually select the MPU-based
212	  stack guard, if this is desired.
213
214config ARM_SECURE_FIRMWARE
215	bool
216	depends on ARMV8_M_SE
217	default y if TRUSTED_EXECUTION_SECURE
218	help
219	  This option indicates that we are building a Zephyr image that
220	  is intended to execute in Secure state. The option is only
221	  applicable to ARMv8-M MCUs that implement the Security Extension.
222
223	  This option enables Zephyr to include code that executes in
224	  Secure state, as well as to exclude code that is designed to
225	  execute only in Non-secure state.
226
227	  Code executing in Secure state has access to both the Secure
228	  and Non-Secure resources of the Cortex-M MCU.
229
230	  Code executing in Non-Secure state may trigger Secure Faults,
231	  if Secure MCU resources are accessed from the Non-Secure state.
232	  Secure Faults may only be handled by code executing in Secure
233	  state.
234
235config ARM_NONSECURE_FIRMWARE
236	bool
237	depends on !ARM_SECURE_FIRMWARE
238	depends on ARMV8_M_SE
239	default y if TRUSTED_EXECUTION_NONSECURE
240	help
241	  This option indicates that we are building a Zephyr image that
242	  is intended to execute in Non-Secure state. Execution of this
243	  image is triggered by Secure firmware that executes in Secure
244	  state. The option is only applicable to ARMv8-M MCUs that
245	  implement the Security Extension.
246
247	  This option enables Zephyr to include code that executes in
248	  Non-Secure state only, as well as to exclude code that is
249	  designed to execute only in Secure state.
250
251	  Code executing in Non-Secure state has no access to Secure
252	  resources of the Cortex-M MCU, and, therefore, it shall avoid
253	  accessing them.
254
255config ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS
256	bool "Allow secure function calls to be preempted"
257	depends on ARM_NONSECURE_FIRMWARE
258	help
259	  When enabled, this option indicates that preemptible Zephyr
260	  threads performing secure function calls, are allowed to be
261	  preempted. When disabled, the option indicates that such
262	  threads many not be context-switched-out while doing a Secure
263	  function call.
264
265config ARM_STORE_EXC_RETURN
266	bool
267	default y if CPU_CORTEX_M && (FPU_SHARING || ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS)
268	help
269	  Store the EXC_RETURN value when switching threads.
270	  This is needed when switching between threads that differ in either
271	  FPU usage or security domain.
272
273choice
274	prompt "Floating point ABI"
275	default FP_HARDABI
276	depends on FPU
277
278config FP_HARDABI
279	bool "Floating point Hard ABI"
280	help
281	  This option selects the Floating point ABI in which hardware floating
282	  point instructions are generated and uses FPU-specific calling
283	  conventions.
284
285config FP_SOFTABI
286	bool "Floating point Soft ABI"
287	help
288	  This option selects the Floating point ABI in which hardware floating
289	  point instructions are generated but soft-float calling conventions.
290
291endchoice
292
293config FP16
294	bool "Half-precision floating point support"
295	default y
296	help
297	  This option enables the half-precision (16-bit) floating point support
298	  via the `__fp16` (both IEEE and ARM alternative formats) and the
299	  `_Float16` (defined by ISO/IEC TS 18661-3:2015) types.
300
301choice
302	prompt "FP16 format"
303	default FP16_IEEE
304	depends on FP16
305
306config FP16_IEEE
307	bool "FP16 IEEE format"
308	help
309	  This option selects the IEEE 754-2008 format for FP16.  This format can
310	  represent normalized values in the range of 2^(-14) to 65504.  There are
311	  11 bits of significand precision, approximately 3 decimal digits.
312
313config FP16_ALT
314	bool "FP16 ARM alternative format"
315	help
316	  This option selects the ARM alternative format for FP16.  This
317	  representation is similar to the IEEE 754-2008 format, but does not
318	  support infinites or NaNs. Instead, the range of exponents is extended,
319	  so that this format can represent normalized values in the range of
320	  2^(-14) to 131008.
321
322	  Please note that Clang doesn't support the ARM alternative format.
323
324endchoice
325
326rsource "cortex_m/Kconfig"
327rsource "cortex_a_r/Kconfig"
328
329rsource "mpu/Kconfig"
330rsource "mmu/Kconfig"
331