1# ARM Cortex-M platform configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6# NOTE: We have the specific core implementations first and outside of the 7# if CPU_CORTEX_M block so that SoCs can select which core they are using 8# without having to select all the options related to that core. Everything 9# else is captured inside the if CPU_CORTEX_M block so they are not exposed 10# if one select a different ARM Cortex Family (Cortex-A or Cortex-R) 11 12config CPU_CORTEX_M0 13 bool 14 select CPU_CORTEX_M 15 select ARMV6_M_ARMV8_M_BASELINE 16 help 17 This option signifies the use of a Cortex-M0 CPU 18 19config CPU_CORTEX_M0PLUS 20 bool 21 select CPU_CORTEX_M 22 select ARMV6_M_ARMV8_M_BASELINE 23 help 24 This option signifies the use of a Cortex-M0+ CPU 25 26config CPU_CORTEX_M1 27 bool 28 select CPU_CORTEX_M 29 select ARMV6_M_ARMV8_M_BASELINE 30 help 31 This option signifies the use of a Cortex-M1 CPU 32 33config CPU_CORTEX_M3 34 bool 35 select CPU_CORTEX_M 36 select ARMV7_M_ARMV8_M_MAINLINE 37 help 38 This option signifies the use of a Cortex-M3 CPU 39 40config CPU_CORTEX_M4 41 bool 42 select CPU_CORTEX_M 43 select ARMV7_M_ARMV8_M_MAINLINE 44 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 45 help 46 This option signifies the use of a Cortex-M4 CPU 47 48config CPU_CORTEX_M23 49 bool 50 select CPU_CORTEX_M 51 select ARMV8_M_BASELINE 52 select ARMV8_M_SE if CPU_HAS_TEE 53 help 54 This option signifies the use of a Cortex-M23 CPU 55 56config CPU_CORTEX_M33 57 bool 58 select CPU_CORTEX_M 59 select ARMV8_M_MAINLINE 60 select ARMV8_M_SE if CPU_HAS_TEE 61 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 62 help 63 This option signifies the use of a Cortex-M33 CPU 64 65config CPU_CORTEX_M55 66 bool 67 select CPU_CORTEX_M 68 select ARMV8_1_M_MAINLINE 69 select ARMV8_M_SE if CPU_HAS_TEE 70 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 71 select CPU_HAS_DCACHE 72 select CPU_HAS_ICACHE 73 help 74 This option signifies the use of a Cortex-M55 CPU 75 76config CPU_CORTEX_M7 77 bool 78 select CPU_CORTEX_M 79 select ARMV7_M_ARMV8_M_MAINLINE 80 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 81 help 82 This option signifies the use of a Cortex-M7 CPU 83 84if CPU_CORTEX_M 85 86config CPU_CORTEX_M_HAS_SYSTICK 87 bool 88 help 89 This option is enabled when the CPU implements the SysTick timer. 90 91config DCACHE_LINE_SIZE 92 default 32 93 94config ICACHE_LINE_SIZE 95 default 32 96 97config CPU_CORTEX_M_HAS_DWT 98 bool 99 depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS && !CPU_CORTEX_M1 100 help 101 This option signifies that the CPU implements the Data Watchpoint and 102 Trace (DWT) unit specified by the ARMv7-M and above. 103 104 While ARMv6-M does define a "DWT" unit, this is significantly different 105 from the DWT specified by the ARMv7-M and above in terms of both feature 106 set and register mappings. 107 108config CPU_CORTEX_M_HAS_BASEPRI 109 bool 110 depends on ARMV7_M_ARMV8_M_MAINLINE 111 help 112 This option signifies the CPU has the BASEPRI register. 113 114 The BASEPRI register defines the minimum priority for 115 exception processing. When BASEPRI is set to a nonzero 116 value, it prevents the activation of all exceptions with 117 the same or lower priority level as the BASEPRI value. 118 Always present in CPUs that implement the ARMv7-M or 119 ARM8-M Mainline architectures. 120 121config CPU_CORTEX_M_HAS_VTOR 122 bool 123 depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M1 124 help 125 This option signifies the CPU has the VTOR register. 126 The VTOR indicates the offset of the vector table base 127 address from memory address 0x00000000. Always present 128 in CPUs implementing the ARMv7-M or ARMv8-M architectures. 129 Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline 130 architectures (except for Cortex-M0/M1, where it is never 131 implemented). 132 133config CPU_CORTEX_M_HAS_SPLIM 134 bool 135 depends on ARMV8_M_MAINLINE || (ARMV8_M_SE && !ARM_NONSECURE_FIRMWARE) 136 help 137 This option signifies the CPU has the MSPLIM, PSPLIM registers. 138 139 The stack pointer limit registers, MSPLIM, PSPLIM, limit the 140 extend to which the Main and Process Stack Pointers, respectively, 141 can descend. MSPLIM, PSPLIM are always present in ARMv8-M 142 MCUs that implement the ARMv8-M Main Extension (Mainline). 143 144 In an ARMv8-M Mainline implementation with the Security Extension 145 the MSPLIM, PSPLIM registers have additional Secure instances. 146 In an ARMv8-M Baseline implementation with the Security Extension 147 the MSPLIM, PSPLIM registers have only Secure instances. 148 149config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 150 bool 151 depends on ARMV7_M_ARMV8_M_MAINLINE 152 help 153 This option signifies the CPU may trigger system faults 154 (other than HardFault) with configurable priority, and, 155 therefore, it needs to reserve a priority level for them. 156 157config CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP 158 bool 159 depends on ARMV6_M_ARMV8_M_BASELINE 160 help 161 This option signifies the Cortex-M0 has some mechanisms that can map 162 the vector table to SRAM 163 164config CPU_CORTEX_M_HAS_CMSE 165 bool 166 depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE 167 help 168 This option signifies the Cortex-M CPU has the CMSE intrinsics. 169 170config ARMV6_M_ARMV8_M_BASELINE 171 bool 172 select ATOMIC_OPERATIONS_C if !ARMV8_M_BASELINE 173 select ISA_THUMB2 174 help 175 This option signifies the use of an ARMv6-M processor 176 implementation, or the use of an ARMv8-M processor 177 supporting the Baseline implementation. 178 179 Notes: 180 - A Processing Element (PE) without the Main Extension 181 is also referred to as a Baseline Implementation. A 182 Baseline implementation has a subset of the instructions, 183 registers, and features, of a Mainline implementation. 184 - ARMv6-M compatibility is provided by all ARMv8-M 185 implementations. 186 187config ARMV8_M_BASELINE 188 bool 189 select ARMV6_M_ARMV8_M_BASELINE 190 select CPU_CORTEX_M_HAS_CMSE 191 help 192 This option signifies the use of an ARMv8-M processor 193 implementation. 194 195 ARMv8-M Baseline includes additional features 196 not present in the ARMv6-M architecture. 197 198config ARMV7_M_ARMV8_M_MAINLINE 199 bool 200 select ATOMIC_OPERATIONS_BUILTIN 201 select ISA_THUMB2 202 select CPU_CORTEX_M_HAS_BASEPRI 203 select CPU_CORTEX_M_HAS_VTOR 204 select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 205 select CPU_CORTEX_M_HAS_SYSTICK 206 help 207 This option signifies the use of an ARMv7-M processor 208 implementation, or the use of a backwards-compatible 209 ARMv8-M processor implementation supporting the Main 210 Extension. 211 212 Notes: 213 - A Processing Element (PE) with the Main Extension is also 214 referred to as a Mainline Implementation. 215 - ARMv7-M compatibility requires the Main Extension. 216 217 From https://developer.arm.com/products/architecture/m-profile: 218 The Main Extension provides backwards compatibility 219 with ARMv7-M. 220 221config ARMV8_M_MAINLINE 222 bool 223 select ARMV7_M_ARMV8_M_MAINLINE 224 select CPU_CORTEX_M_HAS_SPLIM 225 select CPU_CORTEX_M_HAS_CMSE 226 help 227 This option signifies the use of an ARMv8-M processor 228 implementation, supporting the Main Extension. 229 230 ARMv8-M Main Extension includes additional features 231 not present in the ARMv7-M architecture. 232 233config ARMV8_1_M_MAINLINE 234 bool 235 select ARMV8_M_MAINLINE 236 help 237 This option signifies the use of an ARMv8.1-M processor 238 implementation, supporting the Main Extension. 239 240 ARMv8.1-M Main Extension includes additional features 241 not present in the ARMv8-M architecture. 242 243config ARMV8_M_SE 244 bool 245 depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE 246 select CPU_CORTEX_M_HAS_SPLIM if !ARM_NONSECURE_FIRMWARE 247 help 248 This option signifies the use of an ARMv8-M processor 249 implementation (Baseline or Mainline) supporting the 250 Security Extensions. 251 252config ARMV7_M_ARMV8_M_FP 253 bool 254 depends on ARMV7_M_ARMV8_M_MAINLINE && !CPU_CORTEX_M3 255 imply FPU_SHARING 256 help 257 This option signifies the use of an ARMv7-M processor 258 implementation, or the use of an ARMv8-M processor 259 implementation supporting the Floating-Point Extension. 260 261config ARMV8_M_DSP 262 bool 263 depends on ARMV8_M_MAINLINE 264 help 265 This option signifies the use of an ARMv8-M processor 266 implementation supporting the DSP Extension. 267 268config ARMV8_1_M_MVEI 269 bool 270 depends on ARMV8_1_M_MAINLINE 271 depends on ARMV8_M_DSP 272 help 273 This option signifies the use of an ARMv8.1-M processor implementation 274 supporting the M-Profile Vector Extension (MVE) integer instruction set. 275 276config ARMV8_1_M_MVEF 277 bool 278 depends on ARMV8_1_M_MVEI 279 help 280 This option signifies the use of an ARMv8.1-M processor implementation 281 supporting the M-Profile Vector Extension (MVE) floating-point 282 instruction set. 283 284config ARMV8_1_M_PMU 285 bool 286 help 287 This option is enabled when the CPU implements ARMv8-M Performance 288 Monitoring Unit (PMU). 289 290config ARMV8_M_PMU_EVENTCNT 291 int "Number of event counters in the Performance Monitoring Unit" 292 depends on ARMV8_1_M_PMU 293 range 2 8 294 help 295 The number of event counters implemented. 296 297menu "ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33/M55 options" 298 depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE 299 300config GEN_ISR_TABLES 301 default y 302 303config ZERO_LATENCY_IRQS 304 bool "Zero-latency interrupts" 305 depends on CPU_CORTEX_M_HAS_BASEPRI 306 help 307 The kernel may reserve some of the highest interrupts priorities in 308 the system for its own use. These interrupts will not be masked 309 by interrupt locking. 310 When connecting interrupts the kernel will offset all interrupts 311 to lower priority than those reserved by the kernel. 312 Zero-latency interrupt can be used to set up an interrupt at the 313 highest interrupt priority which will not be blocked by interrupt 314 locking. 315 Since Zero-latency ISRs will run in the same priority or possibly at 316 higher priority than the rest of the kernel they cannot use any 317 kernel functionality. 318 319config ZERO_LATENCY_LEVELS 320 int "Number of interrupt priority levels reserved for zero latency" 321 depends on ZERO_LATENCY_IRQS 322 range 1 255 323 help 324 The amount of interrupt priority levels reserved for zero latency 325 interrupts. Increase this value to reserve more than one priority 326 level for zero latency interrupts. 327 328config DYNAMIC_DIRECT_INTERRUPTS 329 bool "Support for dynamic direct interrupts" 330 depends on DYNAMIC_INTERRUPTS 331 help 332 Direct interrupts are designed for performance-critical interrupt 333 handling and do not go through all of the common interrupt handling 334 code. This option enables the installation of interrupt service 335 routines for direct interrupts at runtime. 336 Note: this requires enabling support for dynamic interrupts in the 337 kernel. 338 339config SW_VECTOR_RELAY 340 bool "Software Vector Relay" 341 help 342 When building a bootloader firmware this option adds a 343 vector table relay handler and a vector relay table, to 344 relay interrupts based on a vector table pointer. 345 This is only required but not limited to Cortex-M Baseline CPUs 346 with no hardware vector table relocation mechanisms (e.g. VTOR). 347 348config SW_VECTOR_RELAY_CLIENT 349 bool "Software Vector Relay (client)" 350 default y if BOOTLOADER_MCUBOOT && !CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP 351 depends on !CPU_CORTEX_M_HAS_VTOR 352 help 353 Another image has enabled SW_VECTOR_RELAY, and will be forwarding 354 exceptions and HW interrupts to this image. Enable this option to make 355 sure the vector table pointer in RAM is set properly by the image upon 356 initialization. 357 358config CORTEX_M_DWT 359 bool "Data Watchpoint and Trace (DWT)" 360 depends on CPU_CORTEX_M_HAS_DWT 361 default y if TIMING_FUNCTIONS 362 help 363 Enable and use the Data Watchpoint and Trace (DWT) unit for 364 timing functions. 365 366config CORTEX_M_DEBUG_MONITOR_HOOK 367 bool "Debug monitor interrupt for debugging" 368 depends on !ARMV6_M_ARMV8_M_BASELINE 369 help 370 Enable this option to configure debug monitor exception to low priority 371 for debugging purposes. 372 373# enabled, which may increase ESF stacking requirements for 374# threads. 375config TEST_EXTRA_STACK_SIZE 376 default 512 if TEST_ARM_CORTEX_M && FPU_SHARING 377 378config TRAP_UNALIGNED_ACCESS 379 bool "Unaligned access trap" 380 depends on !ARMV6_M_ARMV8_M_BASELINE 381 help 382 If enabled, the CPU generates a UsageFault exception when executing a 383 halfword or word access. 384 385endmenu 386 387# Implement the null pointer detection using either the Data Watchpoint and 388# Trace Unit and the Debug Monitor Exception, or the Memory Protection Unit. 389 390choice NULL_POINTER_EXCEPTION_DETECTION 391 bool "Null-pointer exception" 392 # Disable this until https://github.com/zephyrproject-rtos/zephyr/issues/32984 is fixed 393 # default NULL_POINTER_EXCEPTION_DETECTION_DWT if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && CPU_CORTEX_M_HAS_DWT 394 default NULL_POINTER_EXCEPTION_DETECTION_MPU if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && ARM_MPU && !CPU_CORTEX_M_HAS_DWT 395 default NULL_POINTER_EXCEPTION_DETECTION_NONE 396 help 397 There are 2 implementations available, one based 398 on DWT and the other based on MPU. Use this choice 399 symbol to select one of the options. By default the 400 feature is disabled. In the test suite the feature 401 is enabled and the DWT-based solution is preferred. 402 403config NULL_POINTER_EXCEPTION_DETECTION_NONE 404 bool "No null pointer exception detection" 405 help 406 Null pointer exception detection feature is not 407 enabled. 408 409config NULL_POINTER_EXCEPTION_DETECTION_DWT 410 bool "Use DWT for null pointer exception detection" 411 depends on CPU_CORTEX_M_HAS_DWT 412 depends on !TRUSTED_EXECUTION_NONSECURE 413 select CORTEX_M_DWT 414 select CORTEX_M_NULL_POINTER_EXCEPTION 415 help 416 Null pointer dereference detection implemented 417 using the DWT unit functionality. 418 Notes: 419 - Not enabled for Non-Secure FW images, where 420 null-pointer dereferencing is likely caught as 421 a SecureFault. 422 - Requires DWT functionality in the Cortex-M SoC 423 implementation (1 comparator for ARMv7-M, 2 comparators 424 for ARMv8-M). 425 - Requires the Cortex-M core be in normal mode. 426 427config NULL_POINTER_EXCEPTION_DETECTION_MPU 428 bool "Use MPU for null pointer exception detection" 429 depends on !TRUSTED_EXECUTION_NONSECURE 430 depends on ARM_MPU 431 select CORTEX_M_NULL_POINTER_EXCEPTION 432 help 433 Null pointer dereference detection implemented 434 using MPU functionality. 435 Notes: 436 - Mutually exclusive to the DWT-based solution 437 - Not enabled for Non-Secure FW images, where 438 null-pointer dereferencing is likely caught as 439 a SecureFault. 440 - Requires MPU functionality to be present and 441 enabled. The implementation consumes 1 MPU region. 442 - In ARMv8-M, explicit null-pointer dereference 443 detection with MPU requires, additionally, that 444 the area: [0x0, 445 CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) 446 is not unmapped (covered by an MPU region already). 447 If it is unmapped null-pointer dereferencing may 448 still be indirectly detected (e.g. via a precise 449 Bus access fault), but this is not guaranteed. A 450 build-time message warns the user of this scenario. 451 452endchoice 453 454config CORTEX_M_NULL_POINTER_EXCEPTION 455 bool 456 help 457 Enable and use the null pointer exception option. 458 This is a debug feature in Cortex-M, allowing for 459 detecting null pointer dereferencing (raising a 460 CPU fault). Supporting the feature results in an 461 increased code footprint, determined by option 462 CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE. 463 464 Note: this hidden option is selected by the choice 465 symbols corresponding to the DWT-based or to the 466 MPU-based solution. 467 468if CORTEX_M_NULL_POINTER_EXCEPTION 469 470config CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE 471 hex "Size of paged unmapped to implement null pointer detection" 472 default 0x400 473 help 474 Size of the page reserved for detecting null pointer 475 dereferencing. Must be a power of two. A large value 476 offers enhanced detection performance to the cost of 477 wasting a large flash area that code may not use. 478 479endif # CORTEX_M_NULL_POINTER_EXCEPTION 480 481rsource "tz/Kconfig" 482 483endif # CPU_CORTEX_M 484
