1# ARM64 core configuration options 2 3# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com> 4# SPDX-License-Identifier: Apache-2.0 5 6config CPU_CORTEX_A 7 bool 8 select CPU_CORTEX 9 select HAS_FLASH_LOAD_OFFSET 10 select SCHED_IPI_SUPPORTED if SMP 11 select CPU_HAS_FPU 12 select ARCH_HAS_SINGLE_THREAD_SUPPORT 13 select CPU_HAS_DCACHE 14 select CPU_HAS_ICACHE 15 imply FPU 16 imply FPU_SHARING 17 help 18 This option signifies the use of a CPU of the Cortex-A family. 19 20config CPU_AARCH64_CORTEX_R 21 bool 22 select CPU_CORTEX 23 select HAS_FLASH_LOAD_OFFSET 24 select CPU_HAS_DCACHE 25 select CPU_HAS_ICACHE 26 select ARCH_HAS_STACK_PROTECTION 27 select CPU_HAS_FPU 28 imply FPU 29 imply FPU_SHARING 30 help 31 This option signifies the use of a CPU of the Cortex-R 64-bit family. 32 33config CPU_CORTEX_A53 34 bool 35 select CPU_CORTEX_A 36 select ARMV8_A 37 help 38 This option signifies the use of a Cortex-A53 CPU 39 40config CPU_CORTEX_A55 41 bool 42 select CPU_CORTEX_A 43 select ARMV8_A 44 help 45 This option signifies the use of a Cortex-A55 CPU 46 47config CPU_CORTEX_A57 48 bool 49 select CPU_CORTEX_A 50 select ARMV8_A 51 help 52 This option signifies the use of a Cortex-A57 CPU 53 54config CPU_CORTEX_A72 55 bool 56 select CPU_CORTEX_A 57 select ARMV8_A 58 help 59 This option signifies the use of a Cortex-A72 CPU 60 61config CPU_CORTEX_A76 62 bool 63 select CPU_CORTEX_A 64 select ARMV8_A 65 help 66 This option signifies the use of a Cortex-A76 CPU 67 68config CPU_CORTEX_A76_A55 69 bool 70 select CPU_CORTEX_A 71 select ARMV8_A 72 help 73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster 74 75config CPU_CORTEX_R82 76 bool 77 select CPU_AARCH64_CORTEX_R 78 select ARMV8_R 79 help 80 This option signifies the use of a Cortex-R82 CPU 81 82config HAS_ARM_SMCCC 83 bool 84 help 85 Include support for the Secure Monitor Call (SMC) and Hypervisor 86 Call (HVC) instructions on Armv7 and above architectures. 87 88config NUM_IRQS 89 int 90 91config MAIN_STACK_SIZE 92 default 4096 93 94config IDLE_STACK_SIZE 95 default 4096 96 97config ISR_STACK_SIZE 98 default 4096 99 100config TEST_EXTRA_STACK_SIZE 101 default 2048 102 103config SYSTEM_WORKQUEUE_STACK_SIZE 104 default 4096 105 106config CMSIS_THREAD_MAX_STACK_SIZE 107 default 4096 108 109config CMSIS_V2_THREAD_MAX_STACK_SIZE 110 default 4096 111 112config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE 113 default 4096 114 115config IPM_CONSOLE_STACK_SIZE 116 default 2048 117 118config AARCH64_IMAGE_HEADER 119 bool "Add image header" 120 default y if ARM_MMU || ARM_MPU 121 help 122 This option enables standard ARM64 boot image header used by Linux 123 and understood by loaders such as u-boot on Xen xl tool. 124 125config PRIVILEGED_STACK_SIZE 126 default 4096 127 128config KOBJECT_TEXT_AREA 129 default 512 if TEST 130 131config WAIT_AT_RESET_VECTOR 132 bool "Wait at reset vector" 133 default n 134 help 135 Spin at reset vector waiting for debugger to attach and resume 136 execution 137 138config ARM64_SAFE_EXCEPTION_STACK 139 bool "To enable the safe exception stack" 140 help 141 The safe exception stack is used for checking whether the kernel stack 142 overflows during the exception happens from EL1. This stack is not 143 used for user stack overflow checking, because kernel stack support 144 the checking work. 145 146config ARM64_EXCEPTION_STACK_TRACE 147 bool 148 default y 149 depends on FRAME_POINTER 150 help 151 Internal config to enable runtime stack traces on fatal exceptions. 152 153config ARCH_HAS_STACKWALK 154 bool 155 default y 156 depends on FRAME_POINTER 157 help 158 Internal config to indicate that the arch_stack_walk() API is implemented 159 and it can be enabled. 160 161config ARM64_SAFE_EXCEPTION_STACK_SIZE 162 int "The stack size of the safe exception stack" 163 default 4096 164 depends on ARM64_SAFE_EXCEPTION_STACK 165 help 166 The stack size of the safe exception stack. The safe exception stack 167 requires to be enough to do the stack overflow check. 168 169config ARM64_FALLBACK_ON_RESERVED_CORES 170 bool "To enable fallback on reserved cores" 171 help 172 Give the ability to define more cores in the device tree than required 173 via CONFIG_MP_MAX_NUM_CPUS. The extra cores in the device tree 174 become reserved. If there is an issue powering on a core during boot 175 then that core will be skipped and the next core in the device tree 176 will be used. 177 178config ARM64_STACK_PROTECTION 179 bool 180 default y if HW_STACK_PROTECTION 181 depends on ARM_MPU 182 select THREAD_STACK_INFO 183 select ARM64_SAFE_EXCEPTION_STACK 184 help 185 This option leverages the MMU or MPU to cause a system fatal error if 186 the bounds of the current process stack are overflowed. This is done 187 by preceding all stack areas with a fixed guard region. 188 189if CPU_CORTEX_A 190 191config ARMV8_A_NS 192 bool "ARMv8-A Normal World (Non-Secure world of Trustzone)" 193 help 194 This option signifies that Zephyr is entered in TrustZone 195 Non-Secure state 196 197config ARMV8_A 198 bool 199 select ATOMIC_OPERATIONS_BUILTIN 200 select CPU_HAS_MMU 201 select ARCH_HAS_USERSPACE if ARM_MMU 202 select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MMU 203 help 204 This option signifies the use of an ARMv8-A processor 205 implementation. 206 207 From https://developer.arm.com/products/architecture/cpu-architecture/a-profile: 208 The Armv8-A architecture introduces the ability to use 64-bit and 209 32-bit Execution states, known as AArch64 and AArch32 respectively. 210 The AArch64 Execution state supports the A64 instruction set, holds 211 addresses in 64-bit registers and allows instructions in the base 212 instruction set to use 64-bit registers for their processing. The AArch32 213 Execution state is a 32-bit Execution state that preserves backwards 214 compatibility with the Armv7-A architecture and enhances that profile 215 so that it can support some features included in the AArch64 state. 216 It supports the T32 and A32 instruction sets. 217 218rsource "xen/Kconfig" 219 220endif # CPU_CORTEX_A 221 222if CPU_AARCH64_CORTEX_R 223 224config ARMV8_R 225 bool 226 select ATOMIC_OPERATIONS_BUILTIN 227 select SCHED_IPI_SUPPORTED if SMP 228 select ARCH_HAS_USERSPACE if ARM_MPU 229 help 230 This option signifies the use of an ARMv8-R processor 231 implementation. 232 233 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile: 234 The Armv8-R architecture targets at the Real-time profile. It introduces 235 virtualization at the highest security level while retaining the 236 Protected Memory System Architecture (PMSA) based on a Memory Protection 237 Unit (MPU). It supports the A32 and T32 instruction sets. 238 239rsource "cortex_r/Kconfig" 240 241endif # CPU_AARCH64_CORTEX_R 242 243if CPU_CORTEX_A || CPU_AARCH64_CORTEX_R 244 245config GEN_ISR_TABLES 246 default y 247 248config GEN_IRQ_VECTOR_TABLE 249 default n 250 251config ARM_MMU 252 bool "ARM MMU Support" 253 default n if CPU_AARCH64_CORTEX_R 254 default y 255 select MMU 256 select SRAM_REGION_PERMISSIONS 257 select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE 258 select ARCH_MEM_DOMAIN_DATA if USERSPACE 259 help 260 Memory Management Unit support. 261 262config XIP 263 select AARCH64_IMAGE_HEADER 264 265config ARM64_SET_VMPIDR_EL2 266 bool "Set VMPIDR_EL2 at EL2 stage" 267 help 268 VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. 269 This is the value returned by EL1 reads of MPIDR_EL1. 270 This register may already be set by bootloader at the EL2 stage, if 271 not, Zephyr should set it. 272 273if ARM_MMU 274 275config MMU_PAGE_SIZE 276 default 0x1000 277 278choice ARM64_VA_BITS 279 prompt "Virtual address space size" 280 default ARM64_VA_BITS_32 281 help 282 Allows choosing one of multiple possible virtual address 283 space sizes. The level of translation table is determined by 284 a combination of page size and virtual address space size. 285 286config ARM64_VA_BITS_32 287 bool "32-bit" 288 289config ARM64_VA_BITS_36 290 bool "36-bit" 291 292config ARM64_VA_BITS_40 293 bool "40-bit" 294 295config ARM64_VA_BITS_42 296 bool "42-bit" 297 298config ARM64_VA_BITS_48 299 bool "48-bit" 300endchoice 301 302config ARM64_VA_BITS 303 int 304 default 32 if ARM64_VA_BITS_32 305 default 36 if ARM64_VA_BITS_36 306 default 40 if ARM64_VA_BITS_40 307 default 42 if ARM64_VA_BITS_42 308 default 48 if ARM64_VA_BITS_48 309 310choice ARM64_PA_BITS 311 prompt "Physical address space size" 312 default ARM64_PA_BITS_32 313 help 314 Choose the maximum physical address range that the kernel will 315 support. 316 317config ARM64_PA_BITS_32 318 bool "32-bit" 319 320config ARM64_PA_BITS_36 321 bool "36-bit" 322 323config ARM64_PA_BITS_40 324 bool "40-bit" 325 326config ARM64_PA_BITS_42 327 bool "42-bit" 328 329config ARM64_PA_BITS_48 330 bool "48-bit" 331endchoice 332 333config ARM64_PA_BITS 334 int 335 default 32 if ARM64_PA_BITS_32 336 default 36 if ARM64_PA_BITS_36 337 default 40 if ARM64_PA_BITS_40 338 default 42 if ARM64_PA_BITS_42 339 default 48 if ARM64_PA_BITS_48 340 341config MAX_XLAT_TABLES 342 int "Maximum numbers of translation tables" 343 default 20 if USERSPACE && (ARM64_VA_BITS >= 40) 344 default 16 if USERSPACE 345 default 12 if (ARM64_VA_BITS >= 40) 346 default 8 347 help 348 This option specifies the maximum numbers of translation tables. 349 Based on this, translation tables are allocated at compile time and 350 used at runtime as needed. If the runtime need exceeds preallocated 351 numbers of translation tables, it will result in assert. Number of 352 translation tables required is decided based on how many discrete 353 memory regions (both normal and device memory) are present on given 354 platform and how much granularity is required while assigning 355 attributes to these memory regions. 356 357endif # ARM_MMU 358 359endif # CPU_CORTEX_A || CPU_AARCH64_CORTEX_R 360
