1# ARM64 core configuration options 2 3# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com> 4# SPDX-License-Identifier: Apache-2.0 5 6config CPU_CORTEX_A 7 bool 8 select CPU_CORTEX 9 select HAS_FLASH_LOAD_OFFSET 10 select SCHED_IPI_SUPPORTED if SMP 11 select CPU_HAS_FPU 12 select ARCH_HAS_SINGLE_THREAD_SUPPORT 13 select CPU_HAS_DCACHE 14 select CPU_HAS_ICACHE 15 imply FPU 16 imply FPU_SHARING 17 help 18 This option signifies the use of a CPU of the Cortex-A family. 19 20config CPU_AARCH64_CORTEX_R 21 bool 22 select CPU_CORTEX 23 select HAS_FLASH_LOAD_OFFSET 24 select CPU_HAS_DCACHE 25 select CPU_HAS_ICACHE 26 select ARCH_HAS_STACK_PROTECTION 27 select CPU_HAS_FPU 28 imply FPU 29 imply FPU_SHARING 30 help 31 This option signifies the use of a CPU of the Cortex-R 64-bit family. 32 33config CPU_CORTEX_A53 34 bool 35 select CPU_CORTEX_A 36 select ARMV8_A 37 help 38 This option signifies the use of a Cortex-A53 CPU 39 40config CPU_CORTEX_A55 41 bool 42 select CPU_CORTEX_A 43 select ARMV8_A 44 help 45 This option signifies the use of a Cortex-A55 CPU 46 47config CPU_CORTEX_A57 48 bool 49 select CPU_CORTEX_A 50 select ARMV8_A 51 help 52 This option signifies the use of a Cortex-A57 CPU 53 54config CPU_CORTEX_A72 55 bool 56 select CPU_CORTEX_A 57 select ARMV8_A 58 help 59 This option signifies the use of a Cortex-A72 CPU 60 61config CPU_CORTEX_A76 62 bool 63 select CPU_CORTEX_A 64 select ARMV8_A 65 help 66 This option signifies the use of a Cortex-A76 CPU 67 68config CPU_CORTEX_A76_A55 69 bool 70 select CPU_CORTEX_A 71 select ARMV8_A 72 help 73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster 74 75config CPU_CORTEX_R82 76 bool 77 select CPU_AARCH64_CORTEX_R 78 select ARMV8_R 79 help 80 This option signifies the use of a Cortex-R82 CPU 81 82config HAS_ARM_SMCCC 83 bool 84 help 85 Include support for the Secure Monitor Call (SMC) and Hypervisor 86 Call (HVC) instructions on Armv7 and above architectures. 87 88config NUM_IRQS 89 int 90 91config MAIN_STACK_SIZE 92 default 4096 93 94config IDLE_STACK_SIZE 95 default 4096 96 97config ISR_STACK_SIZE 98 default 4096 99 100config TEST_EXTRA_STACK_SIZE 101 default 2048 102 103config SYSTEM_WORKQUEUE_STACK_SIZE 104 default 4096 105 106config CMSIS_THREAD_MAX_STACK_SIZE 107 default 4096 108 109config CMSIS_V2_THREAD_MAX_STACK_SIZE 110 default 4096 111 112config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE 113 default 4096 114 115config IPM_CONSOLE_STACK_SIZE 116 default 2048 117 118config AARCH64_IMAGE_HEADER 119 bool "Add image header" 120 default y if ARM_MMU || ARM_MPU 121 help 122 This option enables standard ARM64 boot image header used by Linux 123 and understood by loaders such as u-boot on Xen xl tool. 124 125config PRIVILEGED_STACK_SIZE 126 default 4096 127 128config KOBJECT_TEXT_AREA 129 default 512 if TEST 130 131config WAIT_AT_RESET_VECTOR 132 bool "Wait at reset vector" 133 default n 134 help 135 Spin at reset vector waiting for debugger to attach and resume 136 execution 137 138config ARM64_SAFE_EXCEPTION_STACK 139 bool "To enable the safe exception stack" 140 help 141 The safe exception stack is used for checking whether the kernel stack 142 overflows during the exception happens from EL1. This stack is not 143 used for user stack overflow checking, because kernel stack support 144 the checking work. 145 146config ARM64_ENABLE_FRAME_POINTER 147 bool 148 depends on OVERRIDE_FRAME_POINTER_DEFAULT && !OMIT_FRAME_POINTER 149 depends on !FRAME_POINTER 150 select DEPRECATED 151 help 152 Deprecated. Use CONFIG_FRAME_POINTER instead. 153 Hidden option to simplify access to OVERRIDE_FRAME_POINTER_DEFAULT 154 and OMIT_FRAME_POINTER. It is automatically enabled when the frame 155 pointer unwinding is enabled. 156 157config ARM64_EXCEPTION_STACK_TRACE 158 bool 159 default y 160 depends on FRAME_POINTER 161 help 162 Internal config to enable runtime stack traces on fatal exceptions. 163 164config ARCH_HAS_STACKWALK 165 bool 166 default y 167 depends on FRAME_POINTER 168 help 169 Internal config to indicate that the arch_stack_walk() API is implemented 170 and it can be enabled. 171 172config ARM64_SAFE_EXCEPTION_STACK_SIZE 173 int "The stack size of the safe exception stack" 174 default 4096 175 depends on ARM64_SAFE_EXCEPTION_STACK 176 help 177 The stack size of the safe exception stack. The safe exception stack 178 requires to be enough to do the stack overflow check. 179 180config ARM64_FALLBACK_ON_RESERVED_CORES 181 bool "To enable fallback on reserved cores" 182 help 183 Give the ability to define more cores in the device tree than required 184 via CONFIG_MP_MAX_NUM_CPUS. The extra cores in the device tree 185 become reserved. If there is an issue powering on a core during boot 186 then that core will be skipped and the next core in the device tree 187 will be used. 188 189config ARM64_STACK_PROTECTION 190 bool 191 default y if HW_STACK_PROTECTION 192 depends on ARM_MPU 193 select THREAD_STACK_INFO 194 select ARM64_SAFE_EXCEPTION_STACK 195 help 196 This option leverages the MMU or MPU to cause a system fatal error if 197 the bounds of the current process stack are overflowed. This is done 198 by preceding all stack areas with a fixed guard region. 199 200if CPU_CORTEX_A 201 202config ARMV8_A_NS 203 bool "ARMv8-A Normal World (Non-Secure world of Trustzone)" 204 help 205 This option signifies that Zephyr is entered in TrustZone 206 Non-Secure state 207 208config ARMV8_A 209 bool 210 select ATOMIC_OPERATIONS_BUILTIN 211 select CPU_HAS_MMU 212 select ARCH_HAS_USERSPACE if ARM_MMU 213 select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MMU 214 help 215 This option signifies the use of an ARMv8-A processor 216 implementation. 217 218 From https://developer.arm.com/products/architecture/cpu-architecture/a-profile: 219 The Armv8-A architecture introduces the ability to use 64-bit and 220 32-bit Execution states, known as AArch64 and AArch32 respectively. 221 The AArch64 Execution state supports the A64 instruction set, holds 222 addresses in 64-bit registers and allows instructions in the base 223 instruction set to use 64-bit registers for their processing. The AArch32 224 Execution state is a 32-bit Execution state that preserves backwards 225 compatibility with the Armv7-A architecture and enhances that profile 226 so that it can support some features included in the AArch64 state. 227 It supports the T32 and A32 instruction sets. 228 229rsource "xen/Kconfig" 230 231endif # CPU_CORTEX_A 232 233if CPU_AARCH64_CORTEX_R 234 235config ARMV8_R 236 bool 237 select ATOMIC_OPERATIONS_BUILTIN 238 select SCHED_IPI_SUPPORTED if SMP 239 select ARCH_HAS_USERSPACE if ARM_MPU 240 help 241 This option signifies the use of an ARMv8-R processor 242 implementation. 243 244 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile: 245 The Armv8-R architecture targets at the Real-time profile. It introduces 246 virtualization at the highest security level while retaining the 247 Protected Memory System Architecture (PMSA) based on a Memory Protection 248 Unit (MPU). It supports the A32 and T32 instruction sets. 249 250rsource "cortex_r/Kconfig" 251 252endif # CPU_AARCH64_CORTEX_R 253 254if CPU_CORTEX_A || CPU_AARCH64_CORTEX_R 255 256config GEN_ISR_TABLES 257 default y 258 259config GEN_IRQ_VECTOR_TABLE 260 default n 261 262config ARM_MMU 263 bool "ARM MMU Support" 264 default n if CPU_AARCH64_CORTEX_R 265 default y 266 select MMU 267 select SRAM_REGION_PERMISSIONS 268 select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE 269 select ARCH_MEM_DOMAIN_DATA if USERSPACE 270 help 271 Memory Management Unit support. 272 273config XIP 274 select AARCH64_IMAGE_HEADER 275 276config ARM64_SET_VMPIDR_EL2 277 bool "Set VMPIDR_EL2 at EL2 stage" 278 help 279 VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. 280 This is the value returned by EL1 reads of MPIDR_EL1. 281 This register may already be set by bootloader at the EL2 stage, if 282 not, Zephyr should set it. 283 284if ARM_MMU 285 286config MMU_PAGE_SIZE 287 default 0x1000 288 289choice ARM64_VA_BITS 290 prompt "Virtual address space size" 291 default ARM64_VA_BITS_32 292 help 293 Allows choosing one of multiple possible virtual address 294 space sizes. The level of translation table is determined by 295 a combination of page size and virtual address space size. 296 297config ARM64_VA_BITS_32 298 bool "32-bit" 299 300config ARM64_VA_BITS_36 301 bool "36-bit" 302 303config ARM64_VA_BITS_40 304 bool "40-bit" 305 306config ARM64_VA_BITS_42 307 bool "42-bit" 308 309config ARM64_VA_BITS_48 310 bool "48-bit" 311endchoice 312 313config ARM64_VA_BITS 314 int 315 default 32 if ARM64_VA_BITS_32 316 default 36 if ARM64_VA_BITS_36 317 default 40 if ARM64_VA_BITS_40 318 default 42 if ARM64_VA_BITS_42 319 default 48 if ARM64_VA_BITS_48 320 321choice ARM64_PA_BITS 322 prompt "Physical address space size" 323 default ARM64_PA_BITS_32 324 help 325 Choose the maximum physical address range that the kernel will 326 support. 327 328config ARM64_PA_BITS_32 329 bool "32-bit" 330 331config ARM64_PA_BITS_36 332 bool "36-bit" 333 334config ARM64_PA_BITS_40 335 bool "40-bit" 336 337config ARM64_PA_BITS_42 338 bool "42-bit" 339 340config ARM64_PA_BITS_48 341 bool "48-bit" 342endchoice 343 344config ARM64_PA_BITS 345 int 346 default 32 if ARM64_PA_BITS_32 347 default 36 if ARM64_PA_BITS_36 348 default 40 if ARM64_PA_BITS_40 349 default 42 if ARM64_PA_BITS_42 350 default 48 if ARM64_PA_BITS_48 351 352config MAX_XLAT_TABLES 353 int "Maximum numbers of translation tables" 354 default 20 if USERSPACE && (ARM64_VA_BITS >= 40) 355 default 16 if USERSPACE 356 default 12 if (ARM64_VA_BITS >= 40) 357 default 8 358 help 359 This option specifies the maximum numbers of translation tables. 360 Based on this, translation tables are allocated at compile time and 361 used at runtime as needed. If the runtime need exceeds preallocated 362 numbers of translation tables, it will result in assert. Number of 363 translation tables required is decided based on how many discrete 364 memory regions (both normal and device memory) are present on given 365 platform and how much granularity is required while assigning 366 attributes to these memory regions. 367 368endif # ARM_MMU 369 370endif # CPU_CORTEX_A || CPU_AARCH64_CORTEX_R 371
