1# ARM64 core configuration options 2 3# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com> 4# SPDX-License-Identifier: Apache-2.0 5 6config CPU_CORTEX_A 7 bool 8 select CPU_CORTEX 9 select HAS_FLASH_LOAD_OFFSET 10 select SCHED_IPI_SUPPORTED if SMP 11 select CPU_HAS_FPU 12 select ARCH_HAS_SINGLE_THREAD_SUPPORT 13 select CPU_HAS_DCACHE 14 select CPU_HAS_ICACHE 15 imply FPU 16 imply FPU_SHARING 17 help 18 This option signifies the use of a CPU of the Cortex-A family. 19 20config CPU_AARCH64_CORTEX_R 21 bool 22 select CPU_CORTEX 23 select HAS_FLASH_LOAD_OFFSET 24 select CPU_HAS_DCACHE 25 select CPU_HAS_ICACHE 26 select ARCH_HAS_STACK_PROTECTION 27 select CPU_HAS_FPU 28 imply FPU 29 imply FPU_SHARING 30 help 31 This option signifies the use of a CPU of the Cortex-R 64-bit family. 32 33config CPU_CORTEX_A53 34 bool 35 select CPU_CORTEX_A 36 select ARMV8_A 37 help 38 This option signifies the use of a Cortex-A53 CPU 39 40config CPU_CORTEX_A55 41 bool 42 select CPU_CORTEX_A 43 select ARMV8_A 44 help 45 This option signifies the use of a Cortex-A55 CPU 46 47config CPU_CORTEX_A57 48 bool 49 select CPU_CORTEX_A 50 select ARMV8_A 51 help 52 This option signifies the use of a Cortex-A57 CPU 53 54config CPU_CORTEX_A72 55 bool 56 select CPU_CORTEX_A 57 select ARMV8_A 58 help 59 This option signifies the use of a Cortex-A72 CPU 60 61config CPU_CORTEX_A76 62 bool 63 select CPU_CORTEX_A 64 select ARMV8_A 65 help 66 This option signifies the use of a Cortex-A76 CPU 67 68config CPU_CORTEX_A76_A55 69 bool 70 select CPU_CORTEX_A 71 select ARMV8_A 72 help 73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster 74 75config CPU_CORTEX_R82 76 bool 77 select CPU_AARCH64_CORTEX_R 78 select ARMV8_R 79 help 80 This option signifies the use of a Cortex-R82 CPU 81 82config HAS_ARM_SMCCC 83 bool 84 help 85 Include support for the Secure Monitor Call (SMC) and Hypervisor 86 Call (HVC) instructions on Armv7 and above architectures. 87 88config NUM_IRQS 89 int 90 91config MAIN_STACK_SIZE 92 default 4096 93 94config IDLE_STACK_SIZE 95 default 4096 96 97config ISR_STACK_SIZE 98 default 4096 99 100config TEST_EXTRA_STACK_SIZE 101 default 2048 102 103config SYSTEM_WORKQUEUE_STACK_SIZE 104 default 4096 105 106config CMSIS_THREAD_MAX_STACK_SIZE 107 default 4096 108 109config CMSIS_V2_THREAD_MAX_STACK_SIZE 110 default 4096 111 112config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE 113 default 4096 114 115config IPM_CONSOLE_STACK_SIZE 116 default 2048 117 118config AARCH64_IMAGE_HEADER 119 bool "Add image header" 120 default y if ARM_MMU || ARM_MPU 121 help 122 This option enables standard ARM64 boot image header used by Linux 123 and understood by loaders such as u-boot on Xen xl tool. 124 125config PRIVILEGED_STACK_SIZE 126 default 4096 127 128config KOBJECT_TEXT_AREA 129 default 512 if TEST 130 131config WAIT_AT_RESET_VECTOR 132 bool "Wait at reset vector" 133 default n 134 help 135 Spin at reset vector waiting for debugger to attach and resume 136 execution 137 138config ARM64_SAFE_EXCEPTION_STACK 139 bool "To enable the safe exception stack" 140 help 141 The safe exception stack is used for checking whether the kernel stack 142 overflows during the exception happens from EL1. This stack is not 143 used for user stack overflow checking, because kernel stack support 144 the checking work. 145 146config ARM64_ENABLE_FRAME_POINTER 147 bool 148 default y 149 depends on OVERRIDE_FRAME_POINTER_DEFAULT && !OMIT_FRAME_POINTER 150 help 151 Hidden option to simplify access to OVERRIDE_FRAME_POINTER_DEFAULT 152 and OMIT_FRAME_POINTER. It is automatically enabled when the frame 153 pointer unwinding is enabled. 154 155config ARM64_SAFE_EXCEPTION_STACK_SIZE 156 int "The stack size of the safe exception stack" 157 default 4096 158 depends on ARM64_SAFE_EXCEPTION_STACK 159 help 160 The stack size of the safe exception stack. The safe exception stack 161 requires to be enough to do the stack overflow check. 162 163config ARM64_FALLBACK_ON_RESERVED_CORES 164 bool "To enable fallback on reserved cores" 165 help 166 Give the ability to define more cores in the device tree than required 167 via CONFIG_MP_MAX_NUM_CPUS. The extra cores in the device tree 168 become reserved. If there is an issue powering on a core during boot 169 then that core will be skipped and the next core in the device tree 170 will be used. 171 172config ARM64_STACK_PROTECTION 173 bool 174 default y if HW_STACK_PROTECTION 175 depends on ARM_MPU 176 select THREAD_STACK_INFO 177 select ARM64_SAFE_EXCEPTION_STACK 178 help 179 This option leverages the MMU or MPU to cause a system fatal error if 180 the bounds of the current process stack are overflowed. This is done 181 by preceding all stack areas with a fixed guard region. 182 183if CPU_CORTEX_A 184 185config ARMV8_A_NS 186 bool "ARMv8-A Normal World (Non-Secure world of Trustzone)" 187 help 188 This option signifies that Zephyr is entered in TrustZone 189 Non-Secure state 190 191config ARMV8_A 192 bool 193 select ATOMIC_OPERATIONS_BUILTIN 194 select CPU_HAS_MMU 195 select ARCH_HAS_USERSPACE if ARM_MMU 196 select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MMU 197 help 198 This option signifies the use of an ARMv8-A processor 199 implementation. 200 201 From https://developer.arm.com/products/architecture/cpu-architecture/a-profile: 202 The Armv8-A architecture introduces the ability to use 64-bit and 203 32-bit Execution states, known as AArch64 and AArch32 respectively. 204 The AArch64 Execution state supports the A64 instruction set, holds 205 addresses in 64-bit registers and allows instructions in the base 206 instruction set to use 64-bit registers for their processing. The AArch32 207 Execution state is a 32-bit Execution state that preserves backwards 208 compatibility with the Armv7-A architecture and enhances that profile 209 so that it can support some features included in the AArch64 state. 210 It supports the T32 and A32 instruction sets. 211 212rsource "xen/Kconfig" 213 214endif # CPU_CORTEX_A 215 216if CPU_AARCH64_CORTEX_R 217 218config ARMV8_R 219 bool 220 select ATOMIC_OPERATIONS_BUILTIN 221 select SCHED_IPI_SUPPORTED if SMP 222 select ARCH_HAS_USERSPACE if ARM_MPU 223 help 224 This option signifies the use of an ARMv8-R processor 225 implementation. 226 227 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile: 228 The Armv8-R architecture targets at the Real-time profile. It introduces 229 virtualization at the highest security level while retaining the 230 Protected Memory System Architecture (PMSA) based on a Memory Protection 231 Unit (MPU). It supports the A32 and T32 instruction sets. 232 233rsource "cortex_r/Kconfig" 234 235endif # CPU_AARCH64_CORTEX_R 236 237if CPU_CORTEX_A || CPU_AARCH64_CORTEX_R 238 239config GEN_ISR_TABLES 240 default y 241 242config GEN_IRQ_VECTOR_TABLE 243 default n 244 245config ARM_MMU 246 bool "ARM MMU Support" 247 default n if CPU_AARCH64_CORTEX_R 248 default y 249 select MMU 250 select SRAM_REGION_PERMISSIONS 251 select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE 252 select ARCH_MEM_DOMAIN_DATA if USERSPACE 253 help 254 Memory Management Unit support. 255 256config EXCEPTION_DEBUG 257 bool "Unhandled exception debugging information" 258 default y 259 depends on LOG 260 help 261 Print human-readable information about exception vectors, cause codes, 262 and parameters, at a cost of code/data size for the human-readable 263 strings. 264 265config XIP 266 select AARCH64_IMAGE_HEADER 267 268config ARM64_SET_VMPIDR_EL2 269 bool "Set VMPIDR_EL2 at EL2 stage" 270 help 271 VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. 272 This is the value returned by EL1 reads of MPIDR_EL1. 273 This register may already be set by bootloader at the EL2 stage, if 274 not, Zephyr should set it. 275 276if ARM_MMU 277 278config MMU_PAGE_SIZE 279 default 0x1000 280 281choice ARM64_VA_BITS 282 prompt "Virtual address space size" 283 default ARM64_VA_BITS_32 284 help 285 Allows choosing one of multiple possible virtual address 286 space sizes. The level of translation table is determined by 287 a combination of page size and virtual address space size. 288 289config ARM64_VA_BITS_32 290 bool "32-bit" 291 292config ARM64_VA_BITS_36 293 bool "36-bit" 294 295config ARM64_VA_BITS_40 296 bool "40-bit" 297 298config ARM64_VA_BITS_42 299 bool "42-bit" 300 301config ARM64_VA_BITS_48 302 bool "48-bit" 303endchoice 304 305config ARM64_VA_BITS 306 int 307 default 32 if ARM64_VA_BITS_32 308 default 36 if ARM64_VA_BITS_36 309 default 40 if ARM64_VA_BITS_40 310 default 42 if ARM64_VA_BITS_42 311 default 48 if ARM64_VA_BITS_48 312 313choice ARM64_PA_BITS 314 prompt "Physical address space size" 315 default ARM64_PA_BITS_32 316 help 317 Choose the maximum physical address range that the kernel will 318 support. 319 320config ARM64_PA_BITS_32 321 bool "32-bit" 322 323config ARM64_PA_BITS_36 324 bool "36-bit" 325 326config ARM64_PA_BITS_40 327 bool "40-bit" 328 329config ARM64_PA_BITS_42 330 bool "42-bit" 331 332config ARM64_PA_BITS_48 333 bool "48-bit" 334endchoice 335 336config ARM64_PA_BITS 337 int 338 default 32 if ARM64_PA_BITS_32 339 default 36 if ARM64_PA_BITS_36 340 default 40 if ARM64_PA_BITS_40 341 default 42 if ARM64_PA_BITS_42 342 default 48 if ARM64_PA_BITS_48 343 344config MAX_XLAT_TABLES 345 int "Maximum numbers of translation tables" 346 default 20 if USERSPACE && (ARM64_VA_BITS >= 40) 347 default 16 if USERSPACE 348 default 12 if (ARM64_VA_BITS >= 40) 349 default 8 350 help 351 This option specifies the maximum numbers of translation tables. 352 Based on this, translation tables are allocated at compile time and 353 used at runtime as needed. If the runtime need exceeds preallocated 354 numbers of translation tables, it will result in assert. Number of 355 translation tables required is decided based on how many discrete 356 memory regions (both normal and device memory) are present on given 357 platform and how much granularity is required while assigning 358 attributes to these memory regions. 359 360endif # ARM_MMU 361 362endif # CPU_CORTEX_A || CPU_AARCH64_CORTEX_R 363
