1# Copyright (c) 2014-2015 Wind River Systems, Inc.
2# Copyright (c) 2016 Cadence Design Systems, Inc.
3# Copyright (c) 2019 Intel Corp.
4# SPDX-License-Identifier: Apache-2.0
5
6menuconfig APIC_TIMER
7	bool "New local APIC timer"
8	depends on X86
9	depends on LOAPIC
10	select TICKLESS_CAPABLE
11	select SYSTEM_CLOCK_LOCK_FREE_COUNT
12	help
13	  Use the x86 local APIC in one-shot mode as the system time
14	  source.  NOTE: this probably isn't what you want except on
15	  older or idiosyncratic hardware (or environments like qemu
16	  without complete APIC emulation).  Modern hardware will work
17	  better with CONFIG_APIC_TSC_DEADLINE_TIMER.
18
19if APIC_TIMER
20
21config APIC_TIMER_IRQ
22	int "Local APIC timer IRQ"
23	default 24
24	help
25	  This option specifies the IRQ used by the local APIC timer.
26	  Note: this MUST be set to the index immediately after the
27	  last IO-APIC IRQ (the timer is the first entry in the APIC
28	  local vector table).  This footgun is not intended to be
29	  user-configurable and almost certainly should be managed via
30	  a different mechanism.
31
32config APIC_TIMER_TSC
33	bool "Use invariant TSC for sys_clock_cycle_get_32()"
34	select TIMER_HAS_64BIT_CYCLE_COUNTER
35	help
36	  If your CPU supports invariant TSC, and you know the ratio of the
37	  TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC
38	  timer frequency), then enable this for a much faster and more
39	  accurate sys_clock_cycle_get_32().
40
41if APIC_TIMER_TSC
42
43config APIC_TIMER_TSC_N
44	int "TSC to local APIC timer frequency multiplier (N)"
45	default 1
46
47config APIC_TIMER_TSC_M
48	int "TSC to local APIC timer frequency divisor (M)"
49	default 1
50
51endif # APIC_TIMER_TSC
52
53endif # APIC_TIMER
54
55config APIC_TSC_DEADLINE_TIMER
56	bool "Even newer APIC timer using TSC deadline mode"
57	depends on X86
58	select LOAPIC
59	select TICKLESS_CAPABLE
60	select TIMER_HAS_64BIT_CYCLE_COUNTER
61	help
62	  Extremely simple timer driver based the local APIC TSC
63	  deadline capability.  The use of a free-running 64 bit
64	  counter with comparator eliminates almost all edge cases
65	  from the handling, and the near-instruction-cycle resolution
66	  permits effectively unlimited precision where needed (the
67	  limit becomes the CPU time taken to execute the timing
68	  logic). SMP-safe and very fast, this should be the obvious
69	  choice for any x86 device with invariant TSC and TSC
70	  deadline capability.
71
72config APIC_TIMER_IRQ_PRIORITY
73	int "Local APIC timer interrupt priority"
74	depends on APIC_TIMER || APIC_TSC_DEADLINE_TIMER
75	default 4
76	help
77	  This option specifies the interrupt priority used by the
78	  local APIC timer.
79