1 /**
2   ******************************************************************************
3   * @file    stm32h503xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32H503xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2023 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 #ifndef STM32H503xx_H
26 #define STM32H503xx_H
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 /** @addtogroup ST
33   * @{
34   */
35 
36 
37 /** @addtogroup STM32H503xx
38   * @{
39   */
40 
41 
42 /** @addtogroup Configuration_of_CMSIS
43   * @{
44   */
45 
46 
47 /* =========================================================================================================================== */
48 /* ================                                Interrupt Number Definition                                ================ */
49 /* =========================================================================================================================== */
50 
51 typedef enum
52 {
53 /* =======================================  ARM Cortex-M33 Specific Interrupt Numbers  ======================================= */
54   Reset_IRQn                = -15,    /*!< -15 Reset Vector, invoked on Power up and warm reset              */
55   NonMaskableInt_IRQn       = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted        */
56   HardFault_IRQn            = -13,    /*!< -13 Hard Fault, all classes of Fault                              */
57   MemoryManagement_IRQn     = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation
58                                                and No Match                                                  */
59   BusFault_IRQn             = -11,    /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
60                                                related Fault                                                 */
61   UsageFault_IRQn           = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
62   SVCall_IRQn               =  -5,    /*!< -5  System Service Call via SVC instruction                       */
63   DebugMonitor_IRQn         =  -4,    /*!< -4  Debug Monitor                                                 */
64   PendSV_IRQn               =  -2,    /*!< -2  Pendable request for system service                           */
65   SysTick_IRQn              =  -1,    /*!< -1  System Tick Timer                                             */
66 
67 /* ===========================================  STM32H503xx Specific Interrupt Numbers  ====================================== */
68   WWDG_IRQn                 = 0,      /*!< Window WatchDog interrupt                                         */
69   PVD_AVD_IRQn              = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */
70   RTC_IRQn                  = 2,      /*!< RTC non-secure interrupt                                          */
71   TAMP_IRQn                 = 4,      /*!< Tamper global interrupt                                           */
72   RAMCFG_IRQn               = 5,      /*!< RAMCFG global interrupt                                           */
73   FLASH_IRQn                = 6,      /*!< FLASH non-secure global interrupt                                 */
74   RCC_IRQn                  = 9,      /*!< RCC non secure global interrupt                                   */
75   EXTI0_IRQn                = 11,     /*!< EXTI Line0 interrupt                                              */
76   EXTI1_IRQn                = 12,     /*!< EXTI Line1 interrupt                                              */
77   EXTI2_IRQn                = 13,     /*!< EXTI Line2 interrupt                                              */
78   EXTI3_IRQn                = 14,     /*!< EXTI Line3 interrupt                                              */
79   EXTI4_IRQn                = 15,     /*!< EXTI Line4 interrupt                                              */
80   EXTI5_IRQn                = 16,     /*!< EXTI Line5 interrupt                                              */
81   EXTI6_IRQn                = 17,     /*!< EXTI Line6 interrupt                                              */
82   EXTI7_IRQn                = 18,     /*!< EXTI Line7 interrupt                                              */
83   EXTI8_IRQn                = 19,     /*!< EXTI Line8 interrupt                                              */
84   EXTI9_IRQn                = 20,     /*!< EXTI Line9 interrupt                                              */
85   EXTI10_IRQn               = 21,     /*!< EXTI Line10 interrupt                                             */
86   EXTI11_IRQn               = 22,     /*!< EXTI Line11 interrupt                                             */
87   EXTI12_IRQn               = 23,     /*!< EXTI Line12 interrupt                                             */
88   EXTI13_IRQn               = 24,     /*!< EXTI Line13 interrupt                                             */
89   EXTI14_IRQn               = 25,     /*!< EXTI Line14 interrupt                                             */
90   EXTI15_IRQn               = 26,     /*!< EXTI Line15 interrupt                                             */
91   GPDMA1_Channel0_IRQn      = 27,     /*!< GPDMA1 Channel 0 global interrupt                                 */
92   GPDMA1_Channel1_IRQn      = 28,     /*!< GPDMA1 Channel 1 global interrupt                                 */
93   GPDMA1_Channel2_IRQn      = 29,     /*!< GPDMA1 Channel 2 global interrupt                                 */
94   GPDMA1_Channel3_IRQn      = 30,     /*!< GPDMA1 Channel 3 global interrupt                                 */
95   GPDMA1_Channel4_IRQn      = 31,     /*!< GPDMA1 Channel 4 global interrupt                                 */
96   GPDMA1_Channel5_IRQn      = 32,     /*!< GPDMA1 Channel 5 global interrupt                                 */
97   GPDMA1_Channel6_IRQn      = 33,     /*!< GPDMA1 Channel 6 global interrupt                                 */
98   GPDMA1_Channel7_IRQn      = 34,     /*!< GPDMA1 Channel 7 global interrupt                                 */
99   IWDG_IRQn                 = 35,     /*!< IWDG global interrupt                                             */
100   ADC1_IRQn                 = 37,     /*!< ADC1 global interrupt                                             */
101   DAC1_IRQn                 = 38,     /*!< DAC1 global interrupt                                             */
102   FDCAN1_IT0_IRQn           = 39,     /*!< FDCAN1 interrupt 0                                                */
103   FDCAN1_IT1_IRQn           = 40,     /*!< FDCAN1 interrupt 1                                                */
104   TIM1_BRK_IRQn             = 41,     /*!< TIM1 Break interrupt                                              */
105   TIM1_UP_IRQn              = 42,     /*!< TIM1 Update interrupt                                             */
106   TIM1_TRG_COM_IRQn         = 43,     /*!< TIM1 Trigger and Commutation interrupt                            */
107   TIM1_CC_IRQn              = 44,     /*!< TIM1 Capture Compare interrupt                                    */
108   TIM2_IRQn                 = 45,     /*!< TIM2 global interrupt                                             */
109   TIM3_IRQn                 = 46,     /*!< TIM3 global interrupt                                             */
110   TIM6_IRQn                 = 49,     /*!< TIM6 global interrupt                                             */
111   TIM7_IRQn                 = 50,     /*!< TIM7 global interrupt                                             */
112   I2C1_EV_IRQn              = 51,     /*!< I2C1 Event interrupt                                              */
113   I2C1_ER_IRQn              = 52,     /*!< I2C1 Error interrupt                                              */
114   I2C2_EV_IRQn              = 53,     /*!< I2C2 Event interrupt                                              */
115   I2C2_ER_IRQn              = 54,     /*!< I2C2 Error interrupt                                              */
116   SPI1_IRQn                 = 55,     /*!< SPI1 global interrupt                                             */
117   SPI2_IRQn                 = 56,     /*!< SPI2 global interrupt                                             */
118   SPI3_IRQn                 = 57,     /*!< SPI3 global interrupt                                             */
119   USART1_IRQn               = 58,     /*!< USART1 global interrupt                                           */
120   USART2_IRQn               = 59,     /*!< USART2 global interrupt                                           */
121   USART3_IRQn               = 60,     /*!< USART3 global interrupt                                           */
122   LPUART1_IRQn              = 63,     /*!< LPUART1 global interrupt                                          */
123   LPTIM1_IRQn               = 64,     /*!< LPTIM1 global interrupt                                           */
124   LPTIM2_IRQn               = 70,     /*!< LPTIM2 global interrupt                                           */
125   USB_DRD_FS_IRQn           = 74,     /*!< USB FS global interrupt                                           */
126   CRS_IRQn                  = 75,     /*!< CRS global interrupt                                              */
127   GPDMA2_Channel0_IRQn      = 90,     /*!< GPDMA2 Channel 0 global interrupt                                 */
128   GPDMA2_Channel1_IRQn      = 91,     /*!< GPDMA2 Channel 1 global interrupt                                 */
129   GPDMA2_Channel2_IRQn      = 92,     /*!< GPDMA2 Channel 2 global interrupt                                 */
130   GPDMA2_Channel3_IRQn      = 93,     /*!< GPDMA2 Channel 3 global interrupt                                 */
131   GPDMA2_Channel4_IRQn      = 94,     /*!< GPDMA2 Channel 4 global interrupt                                 */
132   GPDMA2_Channel5_IRQn      = 95,     /*!< GPDMA2 Channel 5 global interrupt                                 */
133   GPDMA2_Channel6_IRQn      = 96,     /*!< GPDMA2 Channel 6 global interrupt                                 */
134   GPDMA2_Channel7_IRQn      = 97,     /*!< GPDMA2 Channel 7 global interrupt                                 */
135   FPU_IRQn                  = 103,    /*!< FPU global interrupt                                              */
136   ICACHE_IRQn               = 104,    /*!< Instruction cache global interrupt                                */
137   DTS_IRQn                  = 113,    /*!< DTS global interrupt                                              */
138   RNG_IRQn                  = 114,    /*!< RNG global interrupt                                              */
139   HASH_IRQn                 = 117,    /*!< HASH global interrupt                                             */
140   I3C1_EV_IRQn              = 123,    /*!< I3C1 event interrupt                                              */
141   I3C1_ER_IRQn              = 124,    /*!< I3C1 error interrupt                                              */
142   I3C2_EV_IRQn              = 131,    /*!< I3C2 Event interrupt                                              */
143   I3C2_ER_IRQn              = 132,    /*!< I3C2 Error interrupt                                              */
144   COMP1_IRQn                = 133,    /*!< COMP global interrupt                                             */
145 } IRQn_Type;
146 
147 
148 
149 /* =========================================================================================================================== */
150 /* ================                           Processor and Core Peripheral Section                           ================ */
151 /* =========================================================================================================================== */
152 
153 /* -------  Start of section using anonymous unions and disabling warnings  ------- */
154 #if   defined (__CC_ARM)
155   #pragma push
156   #pragma anon_unions
157 #elif defined (__ICCARM__)
158   #pragma language=extended
159 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
160   #pragma clang diagnostic push
161   #pragma clang diagnostic ignored "-Wc11-extensions"
162   #pragma clang diagnostic ignored "-Wreserved-id-macro"
163 #elif defined (__GNUC__)
164   /* anonymous unions are enabled by default */
165 #elif defined (__TMS470__)
166   /* anonymous unions are enabled by default */
167 #elif defined (__TASKING__)
168   #pragma warning 586
169 #elif defined (__CSMC__)
170   /* anonymous unions are enabled by default */
171 #else
172   #warning Not supported compiler type
173 #endif
174 
175 
176 /* --------  Configuration of the Cortex-M33 Processor and Core Peripherals  ------ */
177 #define __CM33_REV                0x0000U   /* Core revision r0p1 */
178 #define __SAUREGION_PRESENT       0U        /* SAU regions present */
179 #define __MPU_PRESENT             1U        /* MPU present */
180 #define __VTOR_PRESENT            1U        /* VTOR present */
181 #define __NVIC_PRIO_BITS          4U        /* Number of Bits used for Priority Levels */
182 #define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
183 #define __FPU_PRESENT             1U        /* FPU present */
184 #define __DSP_PRESENT             1U        /* DSP extension present */
185 
186 /** @} */ /* End of group Configuration_of_CMSIS */
187 
188 
189 #include "core_cm33.h"                       /*!< ARM Cortex-M33 processor and core peripherals */
190 #include "system_stm32h5xx.h"                /*!< STM32H5xx System */
191 
192 
193 /* =========================================================================================================================== */
194 /* ================                            Device Specific Peripheral Section                             ================ */
195 /* =========================================================================================================================== */
196 
197 
198 /** @addtogroup STM32H5xx_peripherals
199   * @{
200   */
201 
202 /**
203   * @brief CRC calculation unit
204   */
205 typedef struct
206 {
207   __IO uint32_t DR;             /*!< CRC Data register,                           Address offset: 0x00 */
208   __IO uint32_t IDR;            /*!< CRC Independent data register,               Address offset: 0x04 */
209   __IO uint32_t CR;             /*!< CRC Control register,                        Address offset: 0x08 */
210        uint32_t RESERVED2;      /*!< Reserved,                                                    0x0C */
211   __IO uint32_t INIT;           /*!< Initial CRC value register,                  Address offset: 0x10 */
212   __IO uint32_t POL;            /*!< CRC polynomial register,                     Address offset: 0x14 */
213        uint32_t RESERVED3[246]; /*!< Reserved,                                                         */
214   __IO uint32_t HWCFGR;         /*!< CRC IP HWCFGR register,                     Address offset: 0x3F0 */
215   __IO uint32_t VERR;           /*!< CRC IP version register,                    Address offset: 0x3F4 */
216   __IO uint32_t PIDR;           /*!< CRC IP type identification register,        Address offset: 0x3F8 */
217   __IO uint32_t SIDR;           /*!< CRC IP map Size ID register,                Address offset: 0x3FC */
218 } CRC_TypeDef;
219 
220 /**
221   * @brief Inter-integrated Circuit Interface
222   */
223 typedef struct
224 {
225   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
226   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
227   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
228   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
229   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
230   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
231   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
232   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
233   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
234   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
235   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
236 } I2C_TypeDef;
237 
238 /**
239   * @brief Improved Inter-integrated Circuit Interface
240   */
241 typedef struct
242 {
243   __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
244   __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
245   uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
246   __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
247   __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
248   __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
249   __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
250   __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
251   __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
252   uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
253   __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
254   __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
255   uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
256   __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
257   uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
258   __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
259   __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
260   __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
261   uint32_t RESERVED5;           /*!< Reserved,                                  Address offset: 0x5C      */
262   __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
263   __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
264   uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
265   __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
266   __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
267   uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
268   __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
269   __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
270   __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
271   uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
272   __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
273   __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
274   __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
275   __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
276   __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
277   __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
278 } I3C_TypeDef;
279 
280 /**
281   * @brief DAC
282   */
283 typedef struct
284 {
285   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
286   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
287   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
288   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
289   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
290   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
291   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
292   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
293   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
294   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
295   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
296   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
297   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
298   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
299   __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
300   __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
301   __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
302   __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
303   __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
304   __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
305   __IO uint32_t RESERVED[1];
306   __IO uint32_t AUTOCR;      /*!< DAC Autonomous mode register,                         Address offset: 0x54 */
307 } DAC_TypeDef;
308 
309 /**
310   * @brief Clock Recovery System
311   */
312 typedef struct
313 {
314 __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
315 __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
316 __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
317 __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
318 } CRS_TypeDef;
319 
320 
321 /**
322   * @brief HASH
323   */
324 typedef struct
325 {
326   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
327   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
328   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
329   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
330   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
331   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
332        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
333   __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
334 } HASH_TypeDef;
335 
336 /**
337   * @brief HASH_DIGEST
338   */
339 typedef struct
340 {
341   __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
342 } HASH_DIGEST_TypeDef;
343 
344 /**
345   * @brief RNG
346   */
347 typedef struct
348 {
349   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
350   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
351   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
352   __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
353 } RNG_TypeDef;
354 
355 /**
356   * @brief Debug MCU
357   */
358 typedef struct
359 {
360   __IO uint32_t IDCODE;       /*!< MCU device ID code,                 Address offset: 0x00  */
361   __IO uint32_t CR;           /*!< Debug MCU configuration register,   Address offset: 0x04  */
362   __IO uint32_t APB1FZR1;     /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08  */
363   __IO uint32_t APB1FZR2;     /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C  */
364   __IO uint32_t APB2FZR;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10  */
365   __IO uint32_t APB3FZR;      /*!< Debug MCU APB3 freeze register,     Address offset: 0x14  */
366        uint32_t RESERVED1[2]; /*!< Reserved,                                    0x18 - 0x1C  */
367   __IO uint32_t AHB1FZR;      /*!< Debug MCU AHB1 freeze register,     Address offset: 0x20  */
368        uint32_t RESERVED2[54]; /*!< Reserved,                                   0x24 - 0xF8  */
369   __IO uint32_t SR;           /*!< Debug MCU SR register,              Address offset: 0xFC  */
370   __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register,      Address offset: 0x100 */
371   __IO uint32_t DBG_AUTH_DEV;  /*!< Debug DBG_AUTH_DEV register,       Address offset: 0x104 */
372   __IO uint32_t DBG_AUTH_ACK;  /*!< Debug DBG_AUTH_ACK register,       Address offset: 0x108 */
373        uint32_t RESERVED3[945]; /*!< Reserved,                                 0x10C - 0xFCC */
374   __IO uint32_t PIDR4;       /*!< Debug MCU Peripheral ID register 4,  Address offset: 0xFD0 */
375   __IO uint32_t PIDR5;       /*!< Debug MCU Peripheral ID register 5,  Address offset: 0xFD4 */
376   __IO uint32_t PIDR6;       /*!< Debug MCU Peripheral ID register 6,  Address offset: 0xFD8 */
377   __IO uint32_t PIDR7;       /*!< Debug MCU Peripheral ID register 7,  Address offset: 0xFDC */
378   __IO uint32_t PIDR0;       /*!< Debug MCU Peripheral ID register 0,  Address offset: 0xFE0 */
379   __IO uint32_t PIDR1;       /*!< Debug MCU Peripheral ID register 1,  Address offset: 0xFE4 */
380   __IO uint32_t PIDR2;       /*!< Debug MCU Peripheral ID register 2,  Address offset: 0xFE8 */
381   __IO uint32_t PIDR3;       /*!< Debug MCU Peripheral ID register 3,  Address offset: 0xFEC */
382   __IO uint32_t CIDR0;       /*!< Debug MCU Component ID register 0,   Address offset: 0xFF0 */
383   __IO uint32_t CIDR1;       /*!< Debug MCU Component ID register 1,   Address offset: 0xFF4 */
384   __IO uint32_t CIDR2;       /*!< Debug MCU Component ID register 2,   Address offset: 0xFF8 */
385   __IO uint32_t CIDR3;       /*!< Debug MCU Component ID register 3,   Address offset: 0xFFC */
386 } DBGMCU_TypeDef;
387 
388 
389 /**
390   * @brief DMA Controller
391   */
392 typedef struct
393 {
394        uint32_t RESERVED0;   /*!< Reserved                                         Address offset: 0x00  */
395   __IO uint32_t PRIVCFGR;    /*!< DMA privileged configuration register,           Address offset: 0x04  */
396        uint32_t RESERVED1;   /*!< Reserved                                         Address offset: 0x08  */
397   __IO uint32_t MISR;        /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
398        uint32_t RESERVED2;   /*!< Reserved                                         Address offset: 0x08  */
399 } DMA_TypeDef;
400 
401 typedef struct
402 {
403   __IO uint32_t CLBAR;        /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
404        uint32_t RESERVED1[2]; /*!< Reserved 1,                                      Address offset: 0x54 -- 0x58      */
405   __IO uint32_t CFCR;         /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
406   __IO uint32_t CSR;          /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
407   __IO uint32_t CCR;          /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
408        uint32_t RESERVED2[10];/*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C      */
409   __IO uint32_t CTR1;         /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
410   __IO uint32_t CTR2;         /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
411   __IO uint32_t CBR1;         /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
412   __IO uint32_t CSAR;         /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
413   __IO uint32_t CDAR;         /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
414   __IO uint32_t CTR3;         /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
415   __IO uint32_t CBR2;         /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
416        uint32_t RESERVED3[8]; /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8      */
417   __IO uint32_t CLLR;         /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
418 } DMA_Channel_TypeDef;
419 
420 
421 /**
422   * @brief Asynch Interrupt/Event Controller (EXTI)
423   */
424 typedef struct
425 {
426   __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
427   __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
428   __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
429   __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
430   __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
431        uint32_t RESERVED1;      /*!< Reserved 1,                                      Address offset:   0x14 */
432   __IO uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
433        uint32_t RESERVED2;      /*!< Reserved 2,                                      Address offset:   0x1C */
434   __IO uint32_t RTSR2;          /*!< EXTI Rising Trigger Selection Register 2,        Address offset:   0x20 */
435   __IO uint32_t FTSR2;          /*!< EXTI Falling Trigger Selection Register 2,       Address offset:   0x24 */
436   __IO uint32_t SWIER2;         /*!< EXTI Software Interrupt event Register 2,        Address offset:   0x28 */
437   __IO uint32_t RPR2;           /*!< EXTI Rising Pending Register 2,                  Address offset:   0x2C */
438   __IO uint32_t FPR2;           /*!< EXTI Falling Pending Register 2,                 Address offset:   0x30 */
439        uint32_t RESERVED3;      /*!< Reserved 3,                                      Address offset:   0x34 */
440   __IO uint32_t PRIVCFGR2;      /*!< EXTI Privilege Configuration Register 2,         Address offset:   0x38 */
441        uint32_t RESERVED4[9];   /*!< Reserved 4,                                                 0x3C-- 0x5C */
442   __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
443        uint32_t RESERVED5[4];   /*!< Reserved 5,                                                0x70 -- 0x7C */
444   __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
445   __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
446        uint32_t RESERVED6[2];   /*!< Reserved 6,                                                0x88 -- 0x8C */
447   __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
448   __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
449 } EXTI_TypeDef;
450 
451 /**
452   * @brief FLASH Registers
453   */
454 typedef struct
455 {
456   __IO uint32_t ACR;             /*!< FLASH access control register,                                     Address offset: 0x00 */
457   __IO uint32_t NSKEYR;          /*!< FLASH non-secure key register,                                     Address offset: 0x04 */
458        uint32_t RESERVED1;       /*!< Reserved1,                                                         Address offset: 0x08 */
459   __IO uint32_t OPTKEYR;         /*!< FLASH option key register,                                         Address offset: 0x0C */
460        uint32_t RESERVED2[2];    /*!< Reserved2,                                                         Address offset: 0x10-0x14 */
461   __IO uint32_t OPSR;            /*!< FLASH OPSR register,                                               Address offset: 0x18 */
462   __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                                     Address offset: 0x1C */
463   __IO uint32_t NSSR;            /*!< FLASH non-secure status register,                                  Address offset: 0x20 */
464        uint32_t RESERVED3;       /*!< Reserved3,                                                         Address offset: 0x24 */
465   __IO uint32_t NSCR;            /*!< FLASH non-secure control register,                                 Address offset: 0x28 */
466        uint32_t RESERVED4;       /*!< Reserved4,                                                         Address offset: 0x2C */
467   __IO uint32_t NSCCR;           /*!< FLASH non-secure clear control register,                           Address offset: 0x30 */
468        uint32_t RESERVED5[2];    /*!< Reserved5,                                                         Address offset: 0x34-0x38 */
469   __IO uint32_t PRIVCFGR;        /*!< FLASH privilege configuration register,                            Address offset: 0x3C */
470        uint32_t RESERVED6[2];    /*!< Reserved6,                                                         Address offset: 0x40-0x44 */
471   __IO uint32_t HDPEXTR;         /*!< FLASH HDP extension register,                                      Address offset: 0x48 */
472        uint32_t RESERVED7;       /*!< Reserved7,                                                         Address offset: 0x4C */
473   __IO uint32_t OPTSR_CUR;       /*!< FLASH option status current register,                              Address offset: 0x50 */
474   __IO uint32_t OPTSR_PRG;       /*!< FLASH option status to program register,                           Address offset: 0x54 */
475        uint32_t RESERVED8[2];    /*!< Reserved8,                                                         Address offset: 0x58-0x5C */
476   __IO uint32_t NSEPOCHR_CUR;    /*!< FLASH non-secure epoch current register,                           Address offset: 0x60 */
477   __IO uint32_t NSEPOCHR_PRG;    /*!< FLASH non-secure epoch to program register,                        Address offset: 0x64 */
478        uint32_t RESERVED9[2];    /*!< Reserved9,                                                         Address offset: 0x68-0x6C */
479   __IO uint32_t OPTSR2_CUR;      /*!< FLASH option status current register 2,                            Address offset: 0x70 */
480   __IO uint32_t OPTSR2_PRG;      /*!< FLASH option status to program register 2,                         Address offset: 0x74 */
481        uint32_t RESERVED10[2];   /*!< Reserved10,                                                        Address offset: 0x78-0x7C */
482   __IO uint32_t NSBOOTR_CUR;     /*!< FLASH non-secure unique boot entry current register,               Address offset: 0x80 */
483   __IO uint32_t NSBOOTR_PRG;     /*!< FLASH non-secure unique boot entry to program register,            Address offset: 0x84 */
484       uint32_t RESERVED11[2];    /*!< Reserved11,                                                        Address offset: 0x88-0x8C */
485   __IO uint32_t OTPBLR_CUR;      /*!< FLASH OTP block lock current register,                             Address offset: 0x90 */
486   __IO uint32_t OTPBLR_PRG;      /*!< FLASH OTP block Lock to program register,                          Address offset: 0x94 */
487       uint32_t RESERVED12[10];    /*!< Reserved12,                                                        Address offset: 0x98-0xBC */
488   __IO uint32_t PRIVBB1R1;       /*!< FLASH privilege block-based bank 1 register 1,                     Address offset: 0xC0 */
489       uint32_t RESERVED13[9];    /*!< Reserved13,                                                        Address offset: 0xC4-0xE4 */
490   __IO uint32_t WRP1R_CUR;       /*!< FLASH write sector group protection current register for bank1,    Address offset: 0xE8 */
491   __IO uint32_t WRP1R_PRG;       /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */
492       uint32_t RESERVED14[2];    /*!< Reserved14,                                                        Address offset: 0xF0-0xF4 */
493   __IO uint32_t HDP1R_CUR;       /*!< FLASH HDP configuration current register for bank1,                Address offset: 0xF8 */
494   __IO uint32_t HDP1R_PRG;       /*!< FLASH HDP configuration to program register for bank1,             Address offset: 0xFC */
495   __IO uint32_t ECCCORR;         /*!< FLASH ECC correction register,                                     Address offset: 0x100 */
496   __IO uint32_t ECCDETR;         /*!< FLASH ECC detection register,                                      Address offset: 0x104 */
497   __IO uint32_t ECCDR;           /*!< FLASH ECC data register,                                           Address offset: 0x108 */
498       uint32_t RESERVED15[45];   /*!< Reserved15,                                                        Address offset: 0x10C-0x1BC */
499   __IO uint32_t PRIVBB2R1;       /*!< FLASH privilege block-based bank 2 register 1,                     Address offset: 0x1C0 */
500       uint32_t RESERVED16[9];    /*!< Reserved16,                                                        Address offset: 0x1C4-0x1E4 */
501   __IO uint32_t WRP2R_CUR;       /*!< FLASH write sector group protection current register for bank2,    Address offset: 0x1E8 */
502   __IO uint32_t WRP2R_PRG;       /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */
503       uint32_t RESERVED17[2];    /*!< Reserved17,                                                        Address offset: 0x1F0-0x1F4 */
504   __IO uint32_t HDP2R_CUR;       /*!< FLASH HDP configuration current register for bank2,                Address offset: 0x1F8 */
505   __IO uint32_t HDP2R_PRG;       /*!< FLASH HDP configuration to program register for bank2,             Address offset: 0x1FC */
506 } FLASH_TypeDef;
507 
508 /**
509   * @brief General Purpose I/O
510   */
511 typedef struct
512 {
513   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
514   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
515   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
516   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
517   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
518   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
519   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
520   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
521   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
522   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
523   __IO uint32_t HSLVR;       /*!< GPIO high-speed low voltage register,  Address offset: 0x2C      */
524   __IO uint32_t SECCFGR;     /*!< GPIO secure configuration register,    Address offset: 0x30      */
525 } GPIO_TypeDef;
526 
527 /**
528   * @brief Global TrustZone Controller
529   */
530 typedef struct
531 {
532        uint32_t RESERVED1[8];   /*!< Reserved1,                                                            Address offset: 0x00-0x1C */
533   __IO uint32_t PRIVCFGR1;      /*!< TZSC privilege configuration register 1,                              Address offset: 0x20      */
534   __IO uint32_t PRIVCFGR2;      /*!< TZSC privilege configuration register 2,                              Address offset: 0x24      */
535   __IO uint32_t PRIVCFGR3;      /*!< TZSC privilege configuration register 3,                              Address offset: 0x28      */
536        uint32_t RESERVED3[17];  /*!< Reserved3,                                                            Address offset: 0x2C-0x6C */
537   __IO uint32_t MPCWM4ACFGR;    /*!< TZSC memory 4 sub-region A watermark configuration register,          Address offset: 0x70      */
538   __IO uint32_t MPCWM4AR;       /*!< TZSC memory 4 sub-region A watermark register,                        Address offset: 0x74      */
539 } GTZC_TZSC_TypeDef;
540 
541 typedef struct
542 {
543   uint32_t RESERVED1[128];      /*!< Reserved1,                                Address offset: 0x000-0x1FC */
544   __IO uint32_t PRIVCFGR[32];   /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
545 } GTZC_MPCBB_TypeDef;
546 
547 /**
548   * @brief Instruction Cache
549   */
550 typedef struct
551 {
552   __IO uint32_t CR;             /*!< ICACHE control register,                Address offset: 0x00 */
553   __IO uint32_t SR;             /*!< ICACHE status register,                 Address offset: 0x04 */
554   __IO uint32_t IER;            /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
555   __IO uint32_t FCR;            /*!< ICACHE Flag clear register,             Address offset: 0x0C */
556   __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,            Address offset: 0x10 */
557   __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,           Address offset: 0x14 */
558 } ICACHE_TypeDef;
559 
560 /**
561   * @brief TIM
562   */
563 typedef struct
564 {
565   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
566   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
567   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
568   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
569   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
570   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
571   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
572   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
573   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
574   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
575   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
576   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
577   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
578   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
579   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
580   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
581   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
582   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
583   __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
584   __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
585   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
586   __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
587   __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
588   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
589   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
590   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
591   __IO uint32_t OR1 ;        /*!< TIM option register,                      Address offset: 0x68 */
592        uint32_t RESERVED0[220];/*!< Reserved,                               Address offset: 0x6C */
593   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
594   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
595 } TIM_TypeDef;
596 
597 /**
598   * @brief LPTIMER
599   */
600 typedef struct
601 {
602   __IO uint32_t ISR;            /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
603   __IO uint32_t ICR;            /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
604   __IO uint32_t DIER;           /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
605   __IO uint32_t CFGR;           /*!< LPTIM Configuration register,           Address offset: 0x0C */
606   __IO uint32_t CR;             /*!< LPTIM Control register,                 Address offset: 0x10 */
607   __IO uint32_t CCR1;           /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
608   __IO uint32_t ARR;            /*!< LPTIM Autoreload register,              Address offset: 0x18 */
609   __IO uint32_t CNT;            /*!< LPTIM Counter register,                 Address offset: 0x1C */
610   __IO uint32_t RESERVED0;      /*!< Reserved,                               Address offset: 0x20 */
611   __IO uint32_t CFGR2;          /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
612   __IO uint32_t RCR;            /*!< LPTIM Repetition register,              Address offset: 0x28 */
613   __IO uint32_t CCMR1;          /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
614   __IO uint32_t RESERVED1;      /*!< Reserved,                               Address offset: 0x30 */
615   __IO uint32_t CCR2;           /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
616 } LPTIM_TypeDef;
617 
618 /**
619   * @brief Comparator
620   */
621 typedef struct
622 {
623   __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
624   __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,      Address offset: 0x04 */
625 } COMPOPT_TypeDef;
626 
627 typedef struct
628 {
629   __IO uint32_t SR;         /*!< Comparator status register,                   Address offset: 0x00 */
630   __IO uint32_t ICFR;       /*!< Comparator interrupt clear flag register,     Address offset: 0x04 */
631   __IO uint32_t RESERVED1;  /*!< Reserved,                                     Address offset: 0x08 */
632   __IO uint32_t CFGR1;      /*!< Comparator configuration register 1  ,        Address offset: 0x0C */
633   __IO uint32_t CFGR2;      /*!< Comparator configuration register 2 ,         Address offset: 0x10 */
634 } COMP_TypeDef;
635 
636 typedef struct
637 {
638   __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
639 } COMP_Common_TypeDef;
640 
641 /**
642   * @brief Operational Amplifier (OPAMP)
643   */
644 
645 typedef struct
646 {
647   __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */
648   __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */
649   __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
650 } OPAMP_TypeDef;
651 
652 
653 
654 /**
655   * @brief Power Control
656   */
657 typedef struct
658 {
659   __IO uint32_t PMCR;         /*!< Power mode control register ,          Address offset: 0x00      */
660   __IO uint32_t PMSR;         /*!< Power mode status register ,           Address offset: 0x04      */
661        uint32_t RESERVED1[2]; /*!< Reserved,                              Address offset: 0x08-0x0C */
662   __IO uint32_t VOSCR;        /*!< Voltage scaling control register ,     Address offset: 0x10      */
663   __IO uint32_t VOSSR;        /*!< Voltage sacling status register ,      Address offset: 0x14      */
664        uint32_t RESERVED2[2]; /*!< Reserved,                              Address offset: 0x18-0x1C */
665   __IO uint32_t BDCR;         /*!< BacKup domain control register ,       Address offset: 0x20      */
666   __IO uint32_t DBPCR;        /*!< DBP control register,                  Address offset: 0x24      */
667   __IO uint32_t BDSR;         /*!< BacKup domain status register,         Address offset: 0x28      */
668        uint32_t RESERVED3;    /*!< Reserved,                              Address offset: 0x38      */
669   __IO uint32_t SCCR;         /*!< Supply configuration control register, Address offset: 0x30      */
670   __IO uint32_t VMCR;         /*!< Voltage Monitor Control Register,      Address offset: 0x34      */
671        uint32_t RESERVED4;    /*!< Reserved,                              Address offset: 0x38      */
672   __IO uint32_t VMSR;         /*!< Status Register Voltage Monitoring,    Address offset: 0x3C      */
673   __IO uint32_t WUSCR;        /*!< WakeUP status clear register,          Address offset: 0x40      */
674   __IO uint32_t WUSR;         /*!< WakeUP status Register,                Address offset: 0x44      */
675   __IO uint32_t WUCR;         /*!< WakeUP configuration register,         Address offset: 0x48      */
676        uint32_t RESERVED5;    /*!< Reserved,                              Address offset: 0x4C      */
677   __IO uint32_t IORETR;       /*!< IO RETention Register,                 Address offset: 0x50      */
678        uint32_t RESERVED6[43];/*!< Reserved,                              Address offset: 0x54-0xFC */
679        uint32_t RESERVED7;    /*!< Reserved,                              Address offset: 0x100     */
680   __IO uint32_t PRIVCFGR;     /*!< Privilege configuration register,     Address offset: 0x104      */
681 }PWR_TypeDef;
682 
683 /**
684   * @brief SRAMs configuration controller
685   */
686 typedef struct
687 {
688   __IO uint32_t CR;       /*!< Control Register,                  Address offset: 0x00 */
689   __IO uint32_t IER;      /*!< Interrupt Enable Register,         Address offset: 0x04 */
690   __IO uint32_t ISR;      /*!< Interrupt Status Register,         Address offset: 0x08 */
691   __IO uint32_t SEAR;     /*!< ECC Single Error Address Register, Address offset: 0x0C */
692   __IO uint32_t DEAR;     /*!< ECC Double Error Address Register, Address offset: 0x10 */
693   __IO uint32_t ICR;      /*!< Interrupt Clear Register,          Address offset: 0x14 */
694   __IO uint32_t WPR1;     /*!< SRAM Write Protection Register 1,  Address offset: 0x18 */
695   __IO uint32_t WPR2;     /*!< SRAM Write Protection Register 2,  Address offset: 0x1C */
696   uint32_t      RESERVED; /*!< Reserved,                          Address offset: 0x20 */
697   __IO uint32_t ECCKEY;   /*!< SRAM ECC Key Register,             Address offset: 0x24 */
698   __IO uint32_t ERKEYR;   /*!< SRAM Erase Key Register,           Address offset: 0x28 */
699 }RAMCFG_TypeDef;
700 
701 /**
702   * @brief Reset and Clock Control
703   */
704 typedef struct
705 {
706   __IO uint32_t CR;            /*!< RCC clock control register                                               Address offset: 0x00 */
707   uint32_t      RESERVED1[3];  /*!< Reserved,                                                                Address offset: 0x04 */
708   __IO uint32_t HSICFGR;       /*!< RCC HSI Clock Calibration Register,                                      Address offset: 0x10 */
709   __IO uint32_t CRRCR;         /*!< RCC Clock Recovery RC Register,                                          Address offset: 0x14 */
710   __IO uint32_t CSICFGR;       /*!< RCC CSI Clock Calibration Register,                                      Address offset: 0x18 */
711   __IO uint32_t CFGR1;         /*!< RCC clock configuration register 1                                       Address offset: 0x1C */
712   __IO uint32_t CFGR2;         /*!< RCC clock configuration register 2                                       Address offset: 0x20 */
713   uint32_t      RESERVED2;     /*!< Reserved,                                                                Address offset: 0x24 */
714   __IO uint32_t PLL1CFGR;      /*!< RCC PLL1 Configuration Register                                          Address offset: 0x28 */
715   __IO uint32_t PLL2CFGR;      /*!< RCC PLL2 Configuration Register                                          Address offset: 0x2C */
716   uint32_t      RESERVED3;     /*!< Reserved,                                                                Address offset: 0x30 */
717   __IO uint32_t PLL1DIVR;      /*!< RCC PLL1 Dividers Configuration Register                                 Address offset: 0x34 */
718   __IO uint32_t PLL1FRACR;     /*!< RCC PLL1 Fractional Divider Configuration Register                       Address offset: 0x38 */
719   __IO uint32_t PLL2DIVR;      /*!< RCC PLL2 Dividers Configuration Register                                 Address offset: 0x3C */
720   __IO uint32_t PLL2FRACR;     /*!< RCC PLL2 Fractional Divider Configuration Register                       Address offset: 0x40 */
721   uint32_t      RESERVED4[2];  /*!< Reserved,                                                                Address offset: 0x44 */
722   uint32_t      RESERVED5;     /*!< Reserved                                                                 Address offset: 0x4C */
723   __IO uint32_t CIER;          /*!< RCC Clock Interrupt Enable Register                                      Address offset: 0x50 */
724   __IO uint32_t CIFR;          /*!< RCC Clock Interrupt Flag Register                                        Address offset: 0x54 */
725   __IO uint32_t CICR;          /*!< RCC Clock Interrupt Clear Register                                       Address offset: 0x58 */
726   uint32_t      RESERVED6;     /*!< Reserved                                                                 Address offset: 0x5C */
727   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 Peripherals Reset Register                                      Address offset: 0x60 */
728   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 Peripherals Reset Register                                      Address offset: 0x64 */
729   uint32_t      RESERVED7;     /*!< Reserved                                                                 Address offset: 0x68 */
730   uint32_t      RESERVED8;     /*!< Reserved,                                                                Address offset: 0x6C */
731   uint32_t      RESERVED9;     /*!< Reserved                                                                 Address offset: 0x70 */
732   __IO uint32_t APB1LRSTR;     /*!< RCC APB1 Peripherals reset Low Word register                             Address offset: 0x74 */
733   __IO uint32_t APB1HRSTR;     /*!< RCC APB1 Peripherals reset High Word register                            Address offset: 0x78 */
734   __IO uint32_t APB2RSTR;      /*!< RCC APB2 Peripherals Reset Register                                      Address offset: 0x7C */
735   __IO uint32_t APB3RSTR;      /*!< RCC APB3 Peripherals Reset Register                                      Address offset: 0x80 */
736   uint32_t      RESERVED10;    /*!< Reserved                                                                 Address offset: 0x84 */
737   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 Peripherals Clock Enable Register                               Address offset: 0x88 */
738   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 Peripherals Clock Enable Register                               Address offset: 0x8C */
739   uint32_t      RESERVED11;    /*!< Reserved                                                                 Address offset: 0x90 */
740   uint32_t      RESERVED12;    /*!< Reserved,                                                                Address offset: 0x94 */
741   uint32_t      RESERVED13;    /*!< Reserved                                                                 Address offset: 0x98 */
742   __IO uint32_t APB1LENR;      /*!< RCC APB1 Peripherals clock Enable Low Word register                      Address offset: 0x9C */
743   __IO uint32_t APB1HENR;      /*!< RCC APB1 Peripherals clock Enable High Word register                     Address offset: 0xA0 */
744   __IO uint32_t APB2ENR;       /*!< RCC APB2 Peripherals Clock Enable Register                               Address offset: 0xA4 */
745   __IO uint32_t APB3ENR;       /*!< RCC APB3 Peripherals Clock Enable Register                               Address offset: 0xA8 */
746   uint32_t      RESERVED14;    /*!< Reserved                                                                 Address offset: 0xAC */
747   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 Peripheral sleep clock Register                                 Address offset: 0xB0 */
748   __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 Peripheral sleep clock Register                                 Address offset: 0xB4 */
749   uint32_t      RESERVED15;    /*!< Reserved                                                                 Address offset: 0xB8 */
750   uint32_t      RESERVED16;    /*!< Reserved,                                                                Address offset: 0xBC */
751   uint32_t      RESERVED17;    /*!< Reserved                                                                 Address offset: 0xC0 */
752   __IO uint32_t APB1LLPENR;    /*!< RCC APB1 Peripherals sleep clock Low Word Register                       Address offset: 0xC4 */
753   __IO uint32_t APB1HLPENR;    /*!< RCC APB1 Peripherals sleep clock High Word Register                      Address offset: 0xC8 */
754   __IO uint32_t APB2LPENR;     /*!< RCC APB2 Peripherals sleep clock Register                                Address offset: 0xCC */
755   __IO uint32_t APB3LPENR;     /*!< RCC APB3 Peripherals Clock Low Power Enable Register                     Address offset: 0xD0 */
756   uint32_t      RESERVED18;    /*!< Reserved                                                                 Address offset: 0xD4 */
757   __IO uint32_t CCIPR1;        /*!< RCC IPs Clocks Configuration Register 1                                  Address offset: 0xD8 */
758   __IO uint32_t CCIPR2;        /*!< RCC IPs Clocks Configuration Register 2                                  Address offset: 0xDC */
759   __IO uint32_t CCIPR3;        /*!< RCC IPs Clocks Configuration Register 3                                  Address offset: 0xE0 */
760   __IO uint32_t CCIPR4;        /*!< RCC IPs Clocks Configuration Register 4                                  Address offset: 0xE4 */
761   __IO uint32_t CCIPR5;        /*!< RCC IPs Clocks Configuration Register 5                                  Address offset: 0xE8 */
762   uint32_t      RESERVED19;    /*!< Reserved,                                                                Address offset: 0xEC */
763   __IO uint32_t BDCR;          /*!< RCC VSW Backup Domain & V33 Domain Control Register                      Address offset: 0xF0 */
764   __IO uint32_t RSR;           /*!< RCC Reset status Register                                                Address offset: 0xF4 */
765   uint32_t      RESERVED20[6]; /*!< Reserved                                                                 Address offset: 0xF8 */
766   uint32_t      RESERVED21;    /*!< Reserved,                                                                Address offset: 0x110 */
767   __IO uint32_t PRIVCFGR;      /*!< RCC Privilege configuration register                                     Address offset: 0x114 */
768 } RCC_TypeDef;
769 
770 
771 /*
772 * @brief RTC Specific device feature definitions
773 */
774 #define RTC_BKP_NB         32U
775 #define RTC_TAMP_NB        2U
776 
777 /**
778   * @brief Real-Time Clock
779   */
780 typedef struct
781 {
782   __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
783   __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
784   __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
785   __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
786   __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
787   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
788   __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
789   __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
790        uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x20 */
791   __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
792   __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
793   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
794   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
795   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
796   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
797        uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
798   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
799   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
800   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
801   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
802   __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
803   __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
804        uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x58 */
805   __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
806   __IO uint32_t OR;          /*!< RTC option register,                            Address offset: 0x60 */
807        uint32_t RESERVED3[3];/*!< Reserved,                                       Address offset: 0x64 */
808   __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
809   __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
810 } RTC_TypeDef;
811 
812 /**
813   * @brief Tamper and backup registers
814   */
815 typedef struct
816 {
817   __IO uint32_t CR1;         /*!< TAMP control register 1,                  Address offset: 0x00 */
818   __IO uint32_t CR2;         /*!< TAMP control register 2,                  Address offset: 0x04 */
819   __IO uint32_t CR3;         /*!< TAMP control register 3,                  Address offset: 0x08 */
820   __IO uint32_t FLTCR;       /*!< TAMP filter control register,             Address offset: 0x0C */
821   __IO uint32_t ATCR1;       /*!< TAMP filter control register 1            Address offset: 0x10 */
822   __IO uint32_t ATSEEDR;     /*!< TAMP active tamper seed register,         Address offset: 0x14 */
823   __IO uint32_t ATOR;        /*!< TAMP active tamper output register,       Address offset: 0x18 */
824   __IO uint32_t ATCR2;       /*!< TAMP filter control register 2,           Address offset: 0x1C */
825   __IO uint32_t SECCFGR;     /*!< TAMP secure mode control register,        Address offset: 0x20 */
826   __IO uint32_t PRIVCFGR;    /*!< TAMP privilege mode control register,     Address offset: 0x24 */
827        uint32_t RESERVED0;   /*!< Reserved,                                 Address offset: 0x28 */
828   __IO uint32_t IER;         /*!< TAMP interrupt enable register,           Address offset: 0x2C */
829   __IO uint32_t SR;          /*!< TAMP status register,                     Address offset: 0x30 */
830   __IO uint32_t MISR;        /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
831        uint32_t RESERVED1;   /*!< Reserved,                                 Address offset: 0x38 */
832   __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
833   __IO uint32_t COUNT1R;     /*!< TAMP monotonic counter register,          Address offset: 0x40 */
834        uint32_t RESERVED2[3];/*!< Reserved,                                 Address offset: 0x44 -- 0x4C */
835   __IO uint32_t OR;          /*!< TAMP option register,                     Address offset: 0x50 */
836   __IO uint32_t ERCFGR;      /*!< TAMP erase configuration register,        Address offset: 0x54 */
837        uint32_t RESERVED3[42];/*!< Reserved,                                Address offset: 0x58 -- 0xFC */
838   __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
839   __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
840   __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
841   __IO uint32_t BKP3R;       /*!< TAMP backup register 3,                   Address offset: 0x10C */
842   __IO uint32_t BKP4R;       /*!< TAMP backup register 4,                   Address offset: 0x110 */
843   __IO uint32_t BKP5R;       /*!< TAMP backup register 5,                   Address offset: 0x114 */
844   __IO uint32_t BKP6R;       /*!< TAMP backup register 6,                   Address offset: 0x118 */
845   __IO uint32_t BKP7R;       /*!< TAMP backup register 7,                   Address offset: 0x11C */
846   __IO uint32_t BKP8R;       /*!< TAMP backup register 8,                   Address offset: 0x120 */
847   __IO uint32_t BKP9R;       /*!< TAMP backup register 9,                   Address offset: 0x124 */
848   __IO uint32_t BKP10R;      /*!< TAMP backup register 10,                  Address offset: 0x128 */
849   __IO uint32_t BKP11R;      /*!< TAMP backup register 11,                  Address offset: 0x12C */
850   __IO uint32_t BKP12R;      /*!< TAMP backup register 12,                  Address offset: 0x130 */
851   __IO uint32_t BKP13R;      /*!< TAMP backup register 13,                  Address offset: 0x134 */
852   __IO uint32_t BKP14R;      /*!< TAMP backup register 14,                  Address offset: 0x138 */
853   __IO uint32_t BKP15R;      /*!< TAMP backup register 15,                  Address offset: 0x13C */
854   __IO uint32_t BKP16R;      /*!< TAMP backup register 16,                  Address offset: 0x140 */
855   __IO uint32_t BKP17R;      /*!< TAMP backup register 17,                  Address offset: 0x144 */
856   __IO uint32_t BKP18R;      /*!< TAMP backup register 18,                  Address offset: 0x148 */
857   __IO uint32_t BKP19R;      /*!< TAMP backup register 19,                  Address offset: 0x14C */
858   __IO uint32_t BKP20R;      /*!< TAMP backup register 20,                  Address offset: 0x150 */
859   __IO uint32_t BKP21R;      /*!< TAMP backup register 21,                  Address offset: 0x154 */
860   __IO uint32_t BKP22R;      /*!< TAMP backup register 22,                  Address offset: 0x158 */
861   __IO uint32_t BKP23R;      /*!< TAMP backup register 23,                  Address offset: 0x15C */
862   __IO uint32_t BKP24R;      /*!< TAMP backup register 24,                  Address offset: 0x160 */
863   __IO uint32_t BKP25R;      /*!< TAMP backup register 25,                  Address offset: 0x164 */
864   __IO uint32_t BKP26R;      /*!< TAMP backup register 26,                  Address offset: 0x168 */
865   __IO uint32_t BKP27R;      /*!< TAMP backup register 27,                  Address offset: 0x16C */
866   __IO uint32_t BKP28R;      /*!< TAMP backup register 28,                  Address offset: 0x170 */
867   __IO uint32_t BKP29R;      /*!< TAMP backup register 29,                  Address offset: 0x174 */
868   __IO uint32_t BKP30R;      /*!< TAMP backup register 30,                  Address offset: 0x178 */
869   __IO uint32_t BKP31R;      /*!< TAMP backup register 31,                  Address offset: 0x17C */
870 } TAMP_TypeDef;
871 
872 /**
873   * @brief Universal Synchronous Asynchronous Receiver Transmitter
874   */
875 typedef struct
876 {
877   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
878   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
879   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
880   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
881   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
882   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14  */
883   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
884   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
885   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
886   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
887   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
888   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
889 } USART_TypeDef;
890 
891 /**
892   * @brief System configuration, Boot and Security
893   */
894 typedef struct
895 {
896        uint32_t RESERVED1[4];   /*!< RESERVED1,                                       Address offset: 0x00 - 0x0C */
897   __IO uint32_t HDPLCR;         /*!< SBS HDPL Control Register,                       Address offset: 0x10 */
898   __IO uint32_t HDPLSR;         /*!< SBS HDPL Status Register,                        Address offset: 0x14 */
899   __IO uint32_t RESERVED2[2];   /*!< RESERVED2,                                       Address offset: 0x18 - 0x1C */
900   __IO uint32_t DBGCR;          /*!< SBS Debug Control Register,                      Address offset: 0x20 */
901   __IO uint32_t DBGLOCKR;       /*!< SBS Debug Lock Register,                         Address offset: 0x24 */
902        uint32_t RESERVED3[3];   /*!< RESERVED3,                                       Address offset: 0x28 - 0x30 */
903        uint32_t RESERVED4[36];   /*!< RESERVED4,                                      Address offset: 0x34 - 0xC0 */
904        uint32_t RESERVED6[15];  /*!< RESERVED6,                                       Address offset: 0xC4 - 0xFC */
905   __IO uint32_t PMCR;           /*!< SBS Product Mode & Config Register,              Address offset: 0x100 */
906   __IO uint32_t FPUIMR;         /*!< SBS FPU Interrupt Mask Register,                 Address offset: 0x104 */
907   __IO uint32_t MESR;           /*!< SBS Memory Erase Status Register,                Address offset: 0x108 */
908        uint32_t RESERVED7;      /*!< RESERVED7,                                       Address offset: 0x10C */
909   __IO uint32_t CCCSR;          /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */
910   __IO uint32_t CCVALR;         /*!< SBS Compensation Cell Value Register,            Address offset: 0x114 */
911   __IO uint32_t CCSWCR;         /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */
912   __IO uint32_t RESERVED8;      /*!< RESERVED8,                                       Address offset: 0x11C */
913   __IO uint32_t CFGR2;          /*!< SBS Class B Register,                            Address offset: 0x120 */
914        uint32_t RESERVED9[8];   /*!< RESERVED9,                                       Address offset: 0x124 - 0x140 */
915   __IO uint32_t CNSLCKR;        /*!< SBS CPU Non-secure Lock Register,                Address offset: 0x144 */
916        uint32_t RESERVED10;     /*!< RESERVED10,                                      Address offset: 0x148 */
917   __IO uint32_t ECCNMIR;        /*!< SBS FLITF ECC NMI MASK Register,                 Address offset: 0x14C */
918 } SBS_TypeDef;
919 
920 
921 /**
922   * @brief Universal Serial Bus Full Speed Dual Role Device
923   */
924 typedef struct
925 {
926   __IO uint32_t CHEP0R;          /*!< USB Channel/Endpoint 0 register,      Address offset: 0x00 */
927   __IO uint32_t CHEP1R;          /*!< USB Channel/Endpoint 1 register,      Address offset: 0x04 */
928   __IO uint32_t CHEP2R;          /*!< USB Channel/Endpoint 2 register,      Address offset: 0x08 */
929   __IO uint32_t CHEP3R;          /*!< USB Channel/Endpoint 3 register,      Address offset: 0x0C */
930   __IO uint32_t CHEP4R;          /*!< USB Channel/Endpoint 4 register,      Address offset: 0x10 */
931   __IO uint32_t CHEP5R;          /*!< USB Channel/Endpoint 5 register,      Address offset: 0x14 */
932   __IO uint32_t CHEP6R;          /*!< USB Channel/Endpoint 6 register,      Address offset: 0x18 */
933   __IO uint32_t CHEP7R;          /*!< USB Channel/Endpoint 7 register,      Address offset: 0x1C */
934   __IO uint32_t RESERVED0[8];    /*!< Reserved,                                                  */
935   __IO uint32_t CNTR;            /*!< Control register,                     Address offset: 0x40 */
936   __IO uint32_t ISTR;            /*!< Interrupt status register,            Address offset: 0x44 */
937   __IO uint32_t FNR;             /*!< Frame number register,                Address offset: 0x48 */
938   __IO uint32_t DADDR;           /*!< Device address register,              Address offset: 0x4C */
939   __IO uint32_t RESERVED1;       /*!< Reserved */
940   __IO uint32_t LPMCSR;          /*!< LPM Control and Status register,      Address offset: 0x54 */
941   __IO uint32_t BCDR;            /*!< Battery Charging detector register,   Address offset: 0x58 */
942 } USB_DRD_TypeDef;
943 
944 /**
945   * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table
946   */
947 typedef struct
948 {
949   __IO uint32_t TXBD;             /*!<Transmission buffer address*/
950   __IO uint32_t RXBD;             /*!<Reception buffer address */
951 } USB_DRD_PMABuffDescTypeDef;
952 
953 /**
954   * @brief FD Controller Area Network
955   */
956 typedef struct
957 {
958   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
959   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
960        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
961   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
962   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
963   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
964   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
965   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
966   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
967   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
968   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
969   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
970        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
971   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
972   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
973   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
974        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
975   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
976   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
977   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
978   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
979        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
980   __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
981   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
982   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
983        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
984   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
985   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
986   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
987   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
988        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
989   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
990   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
991   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
992   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
993   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
994   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
995   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
996   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
997   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
998   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
999   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
1000 } FDCAN_GlobalTypeDef;
1001 
1002 /**
1003   * @brief FD Controller Area Network Configuration
1004   */
1005 typedef struct
1006 {
1007   __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
1008        uint32_t RESERVED1[128];/*!< Reserved,                                               0x100 + 0x004 - 0x100 + 0x200 */
1009   __IO uint32_t OPTR;         /*!< FDCAN option register,                                   Address offset: 0x100 + 0x204 */
1010        uint32_t RESERVED2[58];/*!< Reserved,                                                0x100 + 0x208 - 0x100 + 0x2EC */
1011   __IO uint32_t HWCFG;        /*!< FDCAN hardware configuration register,                   Address offset: 0x100 + 0x2F0 */
1012   __IO uint32_t VERR;         /*!< FDCAN IP version register,                               Address offset: 0x100 + 0x2F4 */
1013   __IO uint32_t IPIDR;        /*!< FDCAN IP ID register,                                    Address offset: 0x100 + 0x2F8 */
1014   __IO uint32_t SIDR;         /*!< FDCAN size ID register,                                  Address offset: 0x100 + 0x2FC */
1015 } FDCAN_Config_TypeDef;
1016 
1017 
1018 /**
1019   * @brief ADC
1020   */
1021 typedef struct
1022 {
1023   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
1024   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
1025   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
1026   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
1027   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
1028   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
1029   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
1030        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
1031   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
1032   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
1033   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
1034        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
1035   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
1036   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
1037   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
1038   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
1039   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
1040        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
1041        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
1042   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
1043        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
1044   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
1045   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
1046   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
1047   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
1048        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
1049   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
1050   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
1051   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
1052   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
1053        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
1054   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
1055   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
1056        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
1057        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
1058   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
1059   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
1060        uint32_t RESERVED10[4];/*!< Reserved,                                             0x0B8 - 0x0C4 */
1061   __IO uint32_t OR;           /*!< ADC option register,                           Address offset: 0xC8 */
1062 } ADC_TypeDef;
1063 
1064 typedef struct
1065 {
1066   uint32_t      RESERVED1[2]; /*!< Reserved,                              Address offset: 0x300 + 0x00 */
1067   __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
1068 } ADC_Common_TypeDef;
1069 
1070 
1071 /**
1072   * @brief IWDG
1073   */
1074 typedef struct
1075 {
1076   __IO uint32_t KR;            /*!< IWDG Key register,          Address offset: 0x00 */
1077   __IO uint32_t PR;            /*!< IWDG Prescaler register,    Address offset: 0x04 */
1078   __IO uint32_t RLR;           /*!< IWDG Reload register,       Address offset: 0x08 */
1079   __IO uint32_t SR;            /*!< IWDG Status register,       Address offset: 0x0C */
1080   __IO uint32_t WINR;          /*!< IWDG Window register,       Address offset: 0x10 */
1081   __IO uint32_t EWCR;          /*!< IWDG Early Wakeup register, Address offset: 0x14 */
1082 } IWDG_TypeDef;
1083 
1084 /**
1085   * @brief SPI
1086   */
1087 typedef struct
1088 {
1089   __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
1090   __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
1091   __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
1092   __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
1093   __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
1094   __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
1095   __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
1096   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
1097   __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
1098   uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
1099   __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
1100   uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
1101   __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
1102   __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
1103   __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
1104   __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
1105   __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
1106 } SPI_TypeDef;
1107 
1108 /**
1109   * @brief DTS
1110   */
1111 typedef struct
1112 {
1113   __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */
1114   uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */
1115   __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */
1116   uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */
1117   __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */
1118   __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */
1119   uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */
1120   __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */
1121   __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */
1122   __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */
1123   __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */
1124   __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */
1125 }
1126 DTS_TypeDef;
1127 
1128 /**
1129   * @brief WWDG
1130   */
1131 typedef struct
1132 {
1133   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
1134   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
1135   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
1136 } WWDG_TypeDef;
1137 
1138 /*@}*/ /* end of group STM32H503xx_Peripherals */
1139 
1140 
1141 /* --------  End of section using anonymous unions and disabling warnings  -------- */
1142 #if   defined (__CC_ARM)
1143   #pragma pop
1144 #elif defined (__ICCARM__)
1145   /* leave anonymous unions enabled */
1146 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
1147   #pragma clang diagnostic pop
1148 #elif defined (__GNUC__)
1149   /* anonymous unions are enabled by default */
1150 #elif defined (__TMS470__)
1151   /* anonymous unions are enabled by default */
1152 #elif defined (__TASKING__)
1153   #pragma warning restore
1154 #elif defined (__CSMC__)
1155   /* anonymous unions are enabled by default */
1156 #else
1157   #warning Not supported compiler type
1158 #endif
1159 
1160 
1161 /* =========================================================================================================================== */
1162 /* ================                          Device Specific Peripheral Address Map                           ================ */
1163 /* =========================================================================================================================== */
1164 
1165 
1166 /** @addtogroup STM32H5xx_Peripheral_peripheralAddr
1167   * @{
1168   */
1169 
1170 /* Internal SRAMs size */
1171 
1172 #define SRAM1_SIZE               (0x4000UL)    /*!< SRAM1=16k  */
1173 #define SRAM2_SIZE               (0x4000UL)    /*!< SRAM2=16k  */
1174 #define BKPSRAM_SIZE             (0x0800UL)    /*!< BKPSRAM=2k */
1175 
1176 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
1177 #define FLASH_BASE_NS            (0x08000000UL) /*!< FLASH (up to 128 KB) non-secure base address       */
1178 #define SRAM1_BASE_NS            (0x20000000UL) /*!< SRAM1 (16 KB) non-secure base address              */
1179 #define SRAM2_BASE_NS            (0x20004000UL) /*!< SRAM2 (16 KB) non-secure base address              */
1180 #define PERIPH_BASE_NS           (0x40000000UL) /*!< Peripheral non-secure base address                 */
1181 
1182 /* Peripheral memory map - Non secure */
1183 #define APB1PERIPH_BASE_NS       PERIPH_BASE_NS
1184 #define APB2PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x00010000UL)
1185 #define AHB1PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x00020000UL)
1186 #define AHB2PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x02020000UL)
1187 #define APB3PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x04000000UL)
1188 #define AHB3PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x04020000UL)
1189 
1190 /*!< APB1 Non secure peripherals */
1191 #define TIM2_BASE_NS             (APB1PERIPH_BASE_NS + 0x0000UL)
1192 #define TIM3_BASE_NS             (APB1PERIPH_BASE_NS + 0x0400UL)
1193 #define TIM6_BASE_NS             (APB1PERIPH_BASE_NS + 0x1000UL)
1194 #define TIM7_BASE_NS             (APB1PERIPH_BASE_NS + 0x1400UL)
1195 #define WWDG_BASE_NS             (APB1PERIPH_BASE_NS + 0x2C00UL)
1196 #define IWDG_BASE_NS             (APB1PERIPH_BASE_NS + 0x3000UL)
1197 #define OPAMP1_BASE_NS           (APB1PERIPH_BASE_NS + 0x3400UL)
1198 #define SPI2_BASE_NS             (APB1PERIPH_BASE_NS + 0x3800UL)
1199 #define SPI3_BASE_NS             (APB1PERIPH_BASE_NS + 0x3C00UL)
1200 #define COMP1_BASE_NS            (APB1PERIPH_BASE_NS + 0x4000UL)
1201 #define USART2_BASE_NS           (APB1PERIPH_BASE_NS + 0x4400UL)
1202 #define USART3_BASE_NS           (APB1PERIPH_BASE_NS + 0x4800UL)
1203 #define I2C1_BASE_NS             (APB1PERIPH_BASE_NS + 0x5400UL)
1204 #define I2C2_BASE_NS             (APB1PERIPH_BASE_NS + 0x5800UL)
1205 #define I3C1_BASE_NS             (APB1PERIPH_BASE_NS + 0x5C00UL)
1206 #define CRS_BASE_NS              (APB1PERIPH_BASE_NS + 0x6000UL)
1207 #define DTS_BASE_NS              (APB1PERIPH_BASE_NS + 0x8C00UL)
1208 #define LPTIM2_BASE_NS           (APB1PERIPH_BASE_NS + 0x9400UL)
1209 #define FDCAN1_BASE_NS           (APB1PERIPH_BASE_NS + 0xA400UL)
1210 #define FDCAN_CONFIG_BASE_NS     (APB1PERIPH_BASE_NS + 0xA500UL)
1211 #define SRAMCAN_BASE_NS          (APB1PERIPH_BASE_NS + 0xAC00UL)
1212 
1213 /*!< APB2 Non secure peripherals */
1214 #define TIM1_BASE_NS             (APB2PERIPH_BASE_NS + 0x2C00UL)
1215 #define SPI1_BASE_NS             (APB2PERIPH_BASE_NS + 0x3000UL)
1216 #define USART1_BASE_NS           (APB2PERIPH_BASE_NS + 0x3800UL)
1217 #define USB_DRD_BASE_NS          (APB2PERIPH_BASE_NS + 0x6000UL)
1218 #define USB_DRD_PMAADDR_NS       (APB2PERIPH_BASE_NS + 0x6400UL)
1219 
1220 /*!< AHB1 Non secure peripherals */
1221 #define GPDMA1_BASE_NS           AHB1PERIPH_BASE_NS
1222 #define GPDMA2_BASE_NS           (AHB1PERIPH_BASE_NS + 0x01000UL)
1223 #define FLASH_R_BASE_NS          (AHB1PERIPH_BASE_NS + 0x02000UL)
1224 #define CRC_BASE_NS              (AHB1PERIPH_BASE_NS + 0x03000UL)
1225 #define RAMCFG_BASE_NS           (AHB1PERIPH_BASE_NS + 0x06000UL)
1226 #define ICACHE_BASE_NS           (AHB1PERIPH_BASE_NS + 0x10400UL)
1227 #define GTZC_TZSC1_BASE_NS       (AHB1PERIPH_BASE_NS + 0x12400UL)
1228 #define GTZC_MPCBB1_BASE_NS      (AHB1PERIPH_BASE_NS + 0x12C00UL)
1229 #define GTZC_MPCBB2_BASE_NS      (AHB1PERIPH_BASE_NS + 0x13000UL)
1230 #define BKPSRAM_BASE_NS          (AHB1PERIPH_BASE_NS + 0x16400UL)
1231 
1232 #define GPDMA1_Channel0_BASE_NS   (GPDMA1_BASE_NS + 0x0050UL)
1233 #define GPDMA1_Channel1_BASE_NS   (GPDMA1_BASE_NS + 0x00D0UL)
1234 #define GPDMA1_Channel2_BASE_NS   (GPDMA1_BASE_NS + 0x0150UL)
1235 #define GPDMA1_Channel3_BASE_NS   (GPDMA1_BASE_NS + 0x01D0UL)
1236 #define GPDMA1_Channel4_BASE_NS   (GPDMA1_BASE_NS + 0x0250UL)
1237 #define GPDMA1_Channel5_BASE_NS   (GPDMA1_BASE_NS + 0x02D0UL)
1238 #define GPDMA1_Channel6_BASE_NS   (GPDMA1_BASE_NS + 0x0350UL)
1239 #define GPDMA1_Channel7_BASE_NS   (GPDMA1_BASE_NS + 0x03D0UL)
1240 #define GPDMA2_Channel0_BASE_NS   (GPDMA2_BASE_NS + 0x0050UL)
1241 #define GPDMA2_Channel1_BASE_NS   (GPDMA2_BASE_NS + 0x00D0UL)
1242 #define GPDMA2_Channel2_BASE_NS   (GPDMA2_BASE_NS + 0x0150UL)
1243 #define GPDMA2_Channel3_BASE_NS   (GPDMA2_BASE_NS + 0x01D0UL)
1244 #define GPDMA2_Channel4_BASE_NS   (GPDMA2_BASE_NS + 0x0250UL)
1245 #define GPDMA2_Channel5_BASE_NS   (GPDMA2_BASE_NS + 0x02D0UL)
1246 #define GPDMA2_Channel6_BASE_NS   (GPDMA2_BASE_NS + 0x0350UL)
1247 #define GPDMA2_Channel7_BASE_NS   (GPDMA2_BASE_NS + 0x03D0UL)
1248 
1249 #define RAMCFG_SRAM1_BASE_NS     (RAMCFG_BASE_NS)
1250 #define RAMCFG_SRAM2_BASE_NS     (RAMCFG_BASE_NS + 0x0040UL)
1251 #define RAMCFG_BKPRAM_BASE_NS    (RAMCFG_BASE_NS + 0x0100UL)
1252 
1253 /*!< AHB2 Non secure peripherals */
1254 #define GPIOA_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00000UL)
1255 #define GPIOB_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00400UL)
1256 #define GPIOC_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00800UL)
1257 #define GPIOD_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00C00UL)
1258 #define GPIOH_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01C00UL)
1259 #define ADC1_BASE_NS             (AHB2PERIPH_BASE_NS + 0x08000UL)
1260 #define ADC12_COMMON_BASE_NS     (AHB2PERIPH_BASE_NS + 0x08300UL)
1261 #define DAC1_BASE_NS             (AHB2PERIPH_BASE_NS + 0x08400UL)
1262 #define HASH_BASE_NS             (AHB2PERIPH_BASE_NS + 0xA0400UL)
1263 #define HASH_DIGEST_BASE_NS      (AHB2PERIPH_BASE_NS + 0xA0710UL)
1264 #define RNG_BASE_NS              (AHB2PERIPH_BASE_NS + 0xA0800UL)
1265 
1266 /*!< APB3 Non secure peripherals */
1267 #define SBS_BASE_NS              (APB3PERIPH_BASE_NS + 0x0400UL)
1268 #define LPUART1_BASE_NS          (APB3PERIPH_BASE_NS + 0x2400UL)
1269 #define I3C2_BASE_NS             (APB3PERIPH_BASE_NS + 0x3000UL)
1270 #define LPTIM1_BASE_NS           (APB3PERIPH_BASE_NS + 0x4400UL)
1271 #define RTC_BASE_NS              (APB3PERIPH_BASE_NS + 0x7800UL)
1272 #define TAMP_BASE_NS             (APB3PERIPH_BASE_NS + 0x7C00UL)
1273 
1274 /*!< AHB3 Non secure peripherals */
1275 #define PWR_BASE_NS              (AHB3PERIPH_BASE_NS + 0x0800UL)
1276 #define RCC_BASE_NS              (AHB3PERIPH_BASE_NS + 0x0C00UL)
1277 #define EXTI_BASE_NS             (AHB3PERIPH_BASE_NS + 0x2000UL)
1278 #define DEBUG_BASE_NS            (AHB3PERIPH_BASE_NS + 0x4000UL)
1279 
1280 /* Debug MCU registers base address */
1281 #define DBGMCU_BASE             (0x44024000UL)
1282 #define PACKAGE_BASE            (0x08FFF80EUL) /*!< Package data register base address     */
1283 #define UID_BASE                (0x08FFF800UL) /*!< Unique device ID register base address */
1284 #define FLASHSIZE_BASE          (0x08FFF80CUL) /*!< Flash size data register base address  */
1285 
1286 /* Internal Flash OTP Area */
1287 #define FLASH_OTP_BASE          (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */
1288 #define FLASH_OTP_SIZE          (0x800U)       /*!< 2048 bytes OTP (one-time programmable)         */
1289 
1290 /* Flash system Area */
1291 #define FLASH_SYSTEM_BASE_NS    (0x0BF80000UL) /*!< FLASH System non-secure base address  */
1292 #define FLASH_SYSTEM_SIZE       (0x8000U)      /*!< 32 Kbytes system Flash */
1293 
1294 
1295 /*!< Non Secure Service Library */
1296 /************ RSSLIB SAU system Flash region definition constants *************/
1297 #define NSSLIB_SYS_FLASH_NS_PFUNC_START   (0xBF8FE6CUL)
1298 #define NSSLIB_SYS_FLASH_NS_PFUNC_END     (0xBF8FE74UL)
1299 
1300 /************ RSSLIB function return constants ********************************/
1301 #define NSSLIB_ERROR   (0xF5F5F5F5UL)
1302 #define NSSLIB_SUCCESS (0xEAEAEAEAUL)
1303 
1304 /*!< RSSLIB  pointer function structure address definition */
1305 #define NSSLIB_PFUNC_BASE (0xBF8FE6CUL)
1306 #define NSSLIB_PFUNC      ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE)
1307 
1308 /**
1309   * @brief  Prototype of RSSLIB Jump to HDP level2 Function
1310   * @detail This function increments HDP level up to HDP level 2
1311   *         Then it enables the MPU region corresponding the MPU index
1312   *         provided as input parameter. The Vector Table shall be located
1313   *         within this MPU region.
1314   *         Then it jumps to the reset handler present within the
1315   *         Vector table. The function does not return on successful execution.
1316   * @param  pointer on the vector table containing the reset handler the function
1317   *         jumps to.
1318   * @param  MPU region index containing the vector table
1319   *         jumps to.
1320   * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
1321   */
1322 typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);
1323 
1324 /**
1325   * @brief  Prototype of RSSLIB Jump to HDP level3 Function
1326   * @detail This function increments HDP level up to HDP level 3
1327   *         Then it enables the MPU region corresponding the MPU index
1328   *         provided as input parameter. The Vector Table shall be located
1329   *         within this MPU region.
1330   *         Then it jumps to the reset handler present within the
1331   *         Vector table. The function does not return on successful execution.
1332   * @param  pointer on the vector table containing the reset handler the function
1333   *         jumps to.
1334   * @param  MPU region index containing the vector table
1335   *         jumps to.
1336   * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
1337   */
1338 typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);
1339 
1340 /**
1341   * @brief RSSLib secure callable function pointer structure
1342   */
1343 typedef struct
1344 {
1345   __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2;
1346   __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
1347 } NSSLIB_pFunc_TypeDef;
1348 
1349 
1350 /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
1351 
1352 
1353 /* =========================================================================================================================== */
1354 /* ================                                  Peripheral declaration                                   ================ */
1355 /* =========================================================================================================================== */
1356 
1357 
1358 /** @addtogroup STM32H5xx_Peripheral_declaration
1359   * @{
1360   */
1361 
1362 /*!< APB1 Non secure peripherals */
1363 #define TIM2_NS                ((TIM_TypeDef *)TIM2_BASE_NS)
1364 #define TIM3_NS                ((TIM_TypeDef *)TIM3_BASE_NS)
1365 #define TIM6_NS                ((TIM_TypeDef *)TIM6_BASE_NS)
1366 #define TIM7_NS                ((TIM_TypeDef *)TIM7_BASE_NS)
1367 #define WWDG_NS                ((WWDG_TypeDef *)WWDG_BASE_NS)
1368 #define IWDG_NS                ((IWDG_TypeDef *)IWDG_BASE_NS)
1369 #define OPAMP1_NS              ((OPAMP_TypeDef *)OPAMP1_BASE_NS)
1370 #define SPI2_NS                ((SPI_TypeDef *)SPI2_BASE_NS)
1371 #define SPI3_NS                ((SPI_TypeDef *)SPI3_BASE_NS)
1372 #define COMP1_NS               ((COMP_TypeDef *)COMP1_BASE_NS)
1373 #define USART2_NS              ((USART_TypeDef *)USART2_BASE_NS)
1374 #define USART3_NS              ((USART_TypeDef *)USART3_BASE_NS)
1375 #define I2C1_NS                ((I2C_TypeDef *)I2C1_BASE_NS)
1376 #define I2C2_NS                ((I2C_TypeDef *)I2C2_BASE_NS)
1377 #define I3C1_NS                ((I3C_TypeDef *)I3C1_BASE_NS)
1378 #define CRS_NS                 ((CRS_TypeDef *)CRS_BASE_NS)
1379 #define DTS_NS                 ((DTS_TypeDef *)DTS_BASE_NS)
1380 #define LPTIM2_NS              ((LPTIM_TypeDef *)LPTIM2_BASE_NS)
1381 #define FDCAN1_NS              ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS)
1382 #define FDCAN_CONFIG_NS        ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS)
1383 
1384 /*!< APB2 Non secure peripherals */
1385 #define TIM1_NS                ((TIM_TypeDef *) TIM1_BASE_NS)
1386 #define SPI1_NS                ((SPI_TypeDef *) SPI1_BASE_NS)
1387 #define USART1_NS              ((USART_TypeDef *) USART1_BASE_NS)
1388 #define USB_DRD_FS_NS          ((USB_DRD_TypeDef *) USB_DRD_BASE_NS)
1389 #define USB_DRD_PMA_BUFF_NS    ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS)
1390 
1391 /*!< AHB1 Non secure peripherals */
1392 #define GPDMA1_NS              ((DMA_TypeDef *) GPDMA1_BASE_NS)
1393 #define GPDMA2_NS              ((DMA_TypeDef *) GPDMA2_BASE_NS)
1394 #define FLASH_NS               ((FLASH_TypeDef *) FLASH_R_BASE_NS)
1395 #define CRC_NS                 ((CRC_TypeDef *) CRC_BASE_NS)
1396 #define RAMCFG_SRAM1_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS)
1397 #define RAMCFG_SRAM2_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS)
1398 #define RAMCFG_BKPRAM_NS       ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS)
1399 #define ICACHE_NS              ((ICACHE_TypeDef *) ICACHE_BASE_NS)
1400 #define GTZC_TZSC1_NS          ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS)
1401 #define GTZC_MPCBB1_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS)
1402 #define GTZC_MPCBB2_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS)
1403 #define GPDMA1_Channel0_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
1404 #define GPDMA1_Channel1_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
1405 #define GPDMA1_Channel2_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
1406 #define GPDMA1_Channel3_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
1407 #define GPDMA1_Channel4_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
1408 #define GPDMA1_Channel5_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
1409 #define GPDMA1_Channel6_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
1410 #define GPDMA1_Channel7_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
1411 #define GPDMA2_Channel0_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS)
1412 #define GPDMA2_Channel1_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS)
1413 #define GPDMA2_Channel2_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS)
1414 #define GPDMA2_Channel3_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS)
1415 #define GPDMA2_Channel4_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS)
1416 #define GPDMA2_Channel5_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS)
1417 #define GPDMA2_Channel6_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS)
1418 #define GPDMA2_Channel7_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS)
1419 
1420 /*!< AHB2 Non secure peripherals */
1421 #define GPIOA_NS               ((GPIO_TypeDef *) GPIOA_BASE_NS)
1422 #define GPIOB_NS               ((GPIO_TypeDef *) GPIOB_BASE_NS)
1423 #define GPIOC_NS               ((GPIO_TypeDef *) GPIOC_BASE_NS)
1424 #define GPIOD_NS               ((GPIO_TypeDef *) GPIOD_BASE_NS)
1425 #define GPIOH_NS               ((GPIO_TypeDef *) GPIOH_BASE_NS)
1426 #define ADC1_NS                ((ADC_TypeDef *) ADC1_BASE_NS)
1427 #define ADC12_COMMON_NS        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
1428 #define DAC1_NS                ((DAC_TypeDef *) DAC1_BASE_NS)
1429 #define HASH_NS                ((HASH_TypeDef *) HASH_BASE_NS)
1430 #define HASH_DIGEST_NS         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
1431 #define RNG_NS                 ((RNG_TypeDef *) RNG_BASE_NS)
1432 
1433 
1434 /*!< APB3 Non secure peripherals */
1435 #define SBS_NS                 ((SBS_TypeDef *) SBS_BASE_NS)
1436 #define LPUART1_NS             ((USART_TypeDef *) LPUART1_BASE_NS)
1437 #define I3C2_NS                ((I3C_TypeDef *) I3C2_BASE_NS)
1438 #define LPTIM1_NS              ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
1439 #define RTC_NS                 ((RTC_TypeDef *) RTC_BASE_NS)
1440 #define TAMP_NS                ((TAMP_TypeDef *) TAMP_BASE_NS)
1441 
1442 /*!< AHB3 Non secure peripherals */
1443 #define PWR_NS                 ((PWR_TypeDef *) PWR_BASE_NS)
1444 #define RCC_NS                 ((RCC_TypeDef *) RCC_BASE_NS)
1445 #define EXTI_NS                ((EXTI_TypeDef *) EXTI_BASE_NS)
1446 
1447 
1448 #define DBGMCU                 ((DBGMCU_TypeDef *) DBGMCU_BASE)
1449 
1450 
1451 /*!< Memory base addresses for Non secure peripherals */
1452 #define FLASH_BASE                     FLASH_BASE_NS
1453 #define FLASH_SYSTEM_BASE              FLASH_SYSTEM_BASE_NS
1454 #define SRAM1_BASE                     SRAM1_BASE_NS
1455 #define SRAM2_BASE                     SRAM2_BASE_NS
1456 #define BKPSRAM_BASE                   BKPSRAM_BASE_NS
1457 
1458 #define PERIPH_BASE                    PERIPH_BASE_NS
1459 #define APB1PERIPH_BASE                APB1PERIPH_BASE_NS
1460 #define APB2PERIPH_BASE                APB2PERIPH_BASE_NS
1461 #define APB3PERIPH_BASE                APB3PERIPH_BASE_NS
1462 #define AHB1PERIPH_BASE                AHB1PERIPH_BASE_NS
1463 #define AHB2PERIPH_BASE                AHB2PERIPH_BASE_NS
1464 #define AHB3PERIPH_BASE                AHB3PERIPH_BASE_NS
1465 
1466 /*!< Instance aliases and base addresses for Non secure peripherals */
1467 #define RCC                            RCC_NS
1468 #define RCC_BASE                       RCC_BASE_NS
1469 
1470 #define DTS                            DTS_NS
1471 #define DTS_BASE                       DTS_BASE_NS
1472 
1473 #define FLASH                          FLASH_NS
1474 #define FLASH_R_BASE                   FLASH_R_BASE_NS
1475 
1476 #define GPDMA1                         GPDMA1_NS
1477 #define GPDMA1_BASE                    GPDMA1_BASE_NS
1478 
1479 #define GPDMA1_Channel0                GPDMA1_Channel0_NS
1480 #define GPDMA1_Channel0_BASE           GPDMA1_Channel0_BASE_NS
1481 
1482 #define GPDMA1_Channel1                GPDMA1_Channel1_NS
1483 #define GPDMA1_Channel1_BASE           GPDMA1_Channel1_BASE_NS
1484 
1485 #define GPDMA1_Channel2                GPDMA1_Channel2_NS
1486 #define GPDMA1_Channel2_BASE           GPDMA1_Channel2_BASE_NS
1487 
1488 #define GPDMA1_Channel3                GPDMA1_Channel3_NS
1489 #define GPDMA1_Channel3_BASE           GPDMA1_Channel3_BASE_NS
1490 
1491 #define GPDMA1_Channel4                GPDMA1_Channel4_NS
1492 #define GPDMA1_Channel4_BASE           GPDMA1_Channel4_BASE_NS
1493 
1494 #define GPDMA1_Channel5                GPDMA1_Channel5_NS
1495 #define GPDMA1_Channel5_BASE           GPDMA1_Channel5_BASE_NS
1496 
1497 #define GPDMA1_Channel6                GPDMA1_Channel6_NS
1498 #define GPDMA1_Channel6_BASE           GPDMA1_Channel6_BASE_NS
1499 
1500 #define GPDMA1_Channel7                GPDMA1_Channel7_NS
1501 #define GPDMA1_Channel7_BASE           GPDMA1_Channel7_BASE_NS
1502 
1503 #define GPDMA2                         GPDMA2_NS
1504 #define GPDMA2_BASE                    GPDMA2_BASE_NS
1505 
1506 #define GPDMA2_Channel0                GPDMA2_Channel0_NS
1507 #define GPDMA2_Channel0_BASE           GPDMA2_Channel0_BASE_NS
1508 
1509 #define GPDMA2_Channel1                GPDMA2_Channel1_NS
1510 #define GPDMA2_Channel1_BASE           GPDMA2_Channel1_BASE_NS
1511 
1512 #define GPDMA2_Channel2                GPDMA2_Channel2_NS
1513 #define GPDMA2_Channel2_BASE           GPDMA2_Channel2_BASE_NS
1514 
1515 #define GPDMA2_Channel3                GPDMA2_Channel3_NS
1516 #define GPDMA2_Channel3_BASE           GPDMA2_Channel3_BASE_NS
1517 
1518 #define GPDMA2_Channel4                GPDMA2_Channel4_NS
1519 #define GPDMA2_Channel4_BASE           GPDMA2_Channel4_BASE_NS
1520 
1521 #define GPDMA2_Channel5                GPDMA2_Channel5_NS
1522 #define GPDMA2_Channel5_BASE           GPDMA2_Channel5_BASE_NS
1523 
1524 #define GPDMA2_Channel6                GPDMA2_Channel6_NS
1525 #define GPDMA2_Channel6_BASE           GPDMA2_Channel6_BASE_NS
1526 
1527 #define GPDMA2_Channel7                GPDMA2_Channel7_NS
1528 #define GPDMA2_Channel7_BASE           GPDMA2_Channel7_BASE_NS
1529 
1530 #define GPIOA                          GPIOA_NS
1531 #define GPIOA_BASE                     GPIOA_BASE_NS
1532 
1533 #define GPIOB                          GPIOB_NS
1534 #define GPIOB_BASE                     GPIOB_BASE_NS
1535 
1536 #define GPIOC                          GPIOC_NS
1537 #define GPIOC_BASE                     GPIOC_BASE_NS
1538 
1539 #define GPIOD                          GPIOD_NS
1540 #define GPIOD_BASE                     GPIOD_BASE_NS
1541 
1542 #define GPIOH                          GPIOH_NS
1543 #define GPIOH_BASE                     GPIOH_BASE_NS
1544 
1545 #define PWR                            PWR_NS
1546 #define PWR_BASE                       PWR_BASE_NS
1547 
1548 #define RAMCFG_SRAM1                   RAMCFG_SRAM1_NS
1549 #define RAMCFG_SRAM1_BASE              RAMCFG_SRAM1_BASE_NS
1550 
1551 #define RAMCFG_SRAM2                   RAMCFG_SRAM2_NS
1552 #define RAMCFG_SRAM2_BASE              RAMCFG_SRAM2_BASE_NS
1553 
1554 #define RAMCFG_BKPRAM                  RAMCFG_BKPRAM_NS
1555 #define RAMCFG_BKPRAM_BASE             RAMCFG_BKPRAM_BASE_NS
1556 
1557 #define EXTI                           EXTI_NS
1558 #define EXTI_BASE                      EXTI_BASE_NS
1559 
1560 #define ICACHE                         ICACHE_NS
1561 #define ICACHE_BASE                    ICACHE_BASE_NS
1562 
1563 #define GTZC_TZSC1                     GTZC_TZSC1_NS
1564 #define GTZC_TZSC1_BASE                GTZC_TZSC1_BASE_NS
1565 
1566 #define GTZC_MPCBB1                    GTZC_MPCBB1_NS
1567 #define GTZC_MPCBB1_BASE               GTZC_MPCBB1_BASE_NS
1568 
1569 #define GTZC_MPCBB2                    GTZC_MPCBB2_NS
1570 #define GTZC_MPCBB2_BASE               GTZC_MPCBB2_BASE_NS
1571 
1572 #define RTC                            RTC_NS
1573 #define RTC_BASE                       RTC_BASE_NS
1574 
1575 #define TAMP                           TAMP_NS
1576 #define TAMP_BASE                      TAMP_BASE_NS
1577 
1578 #define TIM1                           TIM1_NS
1579 #define TIM1_BASE                      TIM1_BASE_NS
1580 
1581 #define TIM2                           TIM2_NS
1582 #define TIM2_BASE                      TIM2_BASE_NS
1583 
1584 #define TIM3                           TIM3_NS
1585 #define TIM3_BASE                      TIM3_BASE_NS
1586 
1587 #define TIM6                           TIM6_NS
1588 #define TIM6_BASE                      TIM6_BASE_NS
1589 
1590 #define TIM7                           TIM7_NS
1591 #define TIM7_BASE                      TIM7_BASE_NS
1592 
1593 #define WWDG                           WWDG_NS
1594 #define WWDG_BASE                      WWDG_BASE_NS
1595 
1596 #define IWDG                           IWDG_NS
1597 #define IWDG_BASE                      IWDG_BASE_NS
1598 
1599 #define OPAMP1                         OPAMP1_NS
1600 #define OPAMP1_BASE                    OPAMP1_BASE_NS
1601 
1602 #define SPI1                           SPI1_NS
1603 #define SPI1_BASE                      SPI1_BASE_NS
1604 
1605 #define SPI2                           SPI2_NS
1606 #define SPI2_BASE                      SPI2_BASE_NS
1607 
1608 #define SPI3                           SPI3_NS
1609 #define SPI3_BASE                      SPI3_BASE_NS
1610 
1611 #define COMP1                          COMP1_NS
1612 #define COMP1_BASE                     COMP1_BASE_NS
1613 
1614 #define USART1                         USART1_NS
1615 #define USART1_BASE                    USART1_BASE_NS
1616 
1617 #define USART2                         USART2_NS
1618 #define USART2_BASE                    USART2_BASE_NS
1619 
1620 #define USART3                         USART3_NS
1621 #define USART3_BASE                    USART3_BASE_NS
1622 
1623 #define I2C1                           I2C1_NS
1624 #define I2C1_BASE                      I2C1_BASE_NS
1625 
1626 #define I2C2                           I2C2_NS
1627 #define I2C2_BASE                      I2C2_BASE_NS
1628 
1629 #define I3C1                           I3C1_NS
1630 #define I3C1_BASE                      I3C1_BASE_NS
1631 
1632 #define I3C2                           I3C2_NS
1633 #define I3C2_BASE                      I3C2_BASE_NS
1634 
1635 #define CRS                            CRS_NS
1636 #define CRS_BASE                       CRS_BASE_NS
1637 
1638 #define FDCAN1                         FDCAN1_NS
1639 #define FDCAN1_BASE                    FDCAN1_BASE_NS
1640 
1641 #define FDCAN_CONFIG                   FDCAN_CONFIG_NS
1642 #define FDCAN_CONFIG_BASE              FDCAN_CONFIG_BASE_NS
1643 #define SRAMCAN_BASE                   SRAMCAN_BASE_NS
1644 
1645 #define DAC1                           DAC1_NS
1646 #define DAC1_BASE                      DAC1_BASE_NS
1647 
1648 #define LPTIM1                         LPTIM1_NS
1649 #define LPTIM1_BASE                    LPTIM1_BASE_NS
1650 
1651 #define LPTIM2                         LPTIM2_NS
1652 #define LPTIM2_BASE                    LPTIM2_BASE_NS
1653 
1654 #define LPUART1                        LPUART1_NS
1655 #define LPUART1_BASE                   LPUART1_BASE_NS
1656 
1657 #define SBS                            SBS_NS
1658 #define SBS_BASE                       SBS_BASE_NS
1659 
1660 #define USB_DRD_FS                     USB_DRD_FS_NS
1661 #define USB_DRD_FS_BASE                USB_DRD_BASE_NS
1662 #define USB_DRD_PMAADDR                USB_DRD_PMAADDR_NS
1663 #define USB_DRD_PMA_BUFF               USB_DRD_PMA_BUFF_NS
1664 
1665 #define CRC                            CRC_NS
1666 #define CRC_BASE                       CRC_BASE_NS
1667 
1668 #define ADC1                           ADC1_NS
1669 #define ADC1_BASE                      ADC1_BASE_NS
1670 
1671 #define ADC12_COMMON                   ADC12_COMMON_NS
1672 #define ADC12_COMMON_BASE              ADC12_COMMON_BASE_NS
1673 
1674 #define HASH                           HASH_NS
1675 #define HASH_BASE                      HASH_BASE_NS
1676 
1677 #define HASH_DIGEST                    HASH_DIGEST_NS
1678 #define HASH_DIGEST_BASE               HASH_DIGEST_BASE_NS
1679 
1680 #define RNG                            RNG_NS
1681 #define RNG_BASE                       RNG_BASE_NS
1682 
1683 
1684 /******************************************************************************/
1685 /*                                                                            */
1686 /*                        Analog to Digital Converter                         */
1687 /*                                                                            */
1688 /******************************************************************************/
1689 /********************  Bit definition for ADC_ISR register  *******************/
1690 #define ADC_ISR_ADRDY_Pos              (0U)
1691 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1692 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1693 #define ADC_ISR_EOSMP_Pos              (1U)
1694 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1695 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1696 #define ADC_ISR_EOC_Pos                (2U)
1697 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1698 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1699 #define ADC_ISR_EOS_Pos                (3U)
1700 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1701 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1702 #define ADC_ISR_OVR_Pos                (4U)
1703 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1704 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1705 #define ADC_ISR_JEOC_Pos               (5U)
1706 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1707 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1708 #define ADC_ISR_JEOS_Pos               (6U)
1709 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1710 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1711 #define ADC_ISR_AWD1_Pos               (7U)
1712 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1713 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1714 #define ADC_ISR_AWD2_Pos               (8U)
1715 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1716 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1717 #define ADC_ISR_AWD3_Pos               (9U)
1718 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1719 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1720 #define ADC_ISR_JQOVF_Pos              (10U)
1721 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1722 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1723 
1724 /********************  Bit definition for ADC_IER register  *******************/
1725 #define ADC_IER_ADRDYIE_Pos            (0U)
1726 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1727 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1728 #define ADC_IER_EOSMPIE_Pos            (1U)
1729 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1730 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1731 #define ADC_IER_EOCIE_Pos              (2U)
1732 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1733 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1734 #define ADC_IER_EOSIE_Pos              (3U)
1735 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1736 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1737 #define ADC_IER_OVRIE_Pos              (4U)
1738 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1739 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1740 #define ADC_IER_JEOCIE_Pos             (5U)
1741 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1742 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1743 #define ADC_IER_JEOSIE_Pos             (6U)
1744 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1745 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1746 #define ADC_IER_AWD1IE_Pos             (7U)
1747 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1748 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1749 #define ADC_IER_AWD2IE_Pos             (8U)
1750 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1751 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1752 #define ADC_IER_AWD3IE_Pos             (9U)
1753 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1754 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1755 #define ADC_IER_JQOVFIE_Pos            (10U)
1756 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1757 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1758 
1759 /********************  Bit definition for ADC_CR register  ********************/
1760 #define ADC_CR_ADEN_Pos                (0U)
1761 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1762 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1763 #define ADC_CR_ADDIS_Pos               (1U)
1764 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1765 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1766 #define ADC_CR_ADSTART_Pos             (2U)
1767 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1768 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1769 #define ADC_CR_JADSTART_Pos            (3U)
1770 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1771 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1772 #define ADC_CR_ADSTP_Pos               (4U)
1773 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1774 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1775 #define ADC_CR_JADSTP_Pos              (5U)
1776 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1777 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1778 #define ADC_CR_ADVREGEN_Pos            (28U)
1779 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1780 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1781 #define ADC_CR_DEEPPWD_Pos             (29U)
1782 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1783 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1784 #define ADC_CR_ADCALDIF_Pos            (30U)
1785 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1786 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1787 #define ADC_CR_ADCAL_Pos               (31U)
1788 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1789 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1790 
1791 /********************  Bit definition for ADC_CFGR register  ******************/
1792 #define ADC_CFGR_DMAEN_Pos             (0U)
1793 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1794 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1795 #define ADC_CFGR_DMACFG_Pos            (1U)
1796 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1797 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1798 
1799 #define ADC_CFGR_RES_Pos               (3U)
1800 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1801 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1802 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1803 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1804 
1805 #define ADC_CFGR_EXTSEL_Pos            (5U)
1806 #define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
1807 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1808 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
1809 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1810 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1811 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1812 #define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */
1813 
1814 #define ADC_CFGR_EXTEN_Pos             (10U)
1815 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1816 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1817 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1818 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1819 
1820 #define ADC_CFGR_OVRMOD_Pos            (12U)
1821 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1822 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1823 #define ADC_CFGR_CONT_Pos              (13U)
1824 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1825 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1826 #define ADC_CFGR_AUTDLY_Pos            (14U)
1827 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1828 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1829 #define ADC_CFGR_ALIGN_Pos             (15U)
1830 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
1831 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
1832 #define ADC_CFGR_DISCEN_Pos            (16U)
1833 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1834 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1835 
1836 #define ADC_CFGR_DISCNUM_Pos           (17U)
1837 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1838 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1839 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1840 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1841 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1842 
1843 #define ADC_CFGR_JDISCEN_Pos           (20U)
1844 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1845 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1846 #define ADC_CFGR_JQM_Pos               (21U)
1847 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1848 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1849 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1850 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1851 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1852 #define ADC_CFGR_AWD1EN_Pos            (23U)
1853 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1854 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1855 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1856 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1857 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1858 #define ADC_CFGR_JAUTO_Pos             (25U)
1859 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1860 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1861 
1862 #define ADC_CFGR_AWD1CH_Pos            (26U)
1863 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1864 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1865 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1866 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1867 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1868 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1869 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1870 
1871 #define ADC_CFGR_JQDIS_Pos             (31U)
1872 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1873 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1874 
1875 /********************  Bit definition for ADC_CFGR2 register  *****************/
1876 #define ADC_CFGR2_ROVSE_Pos            (0U)
1877 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1878 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1879 #define ADC_CFGR2_JOVSE_Pos            (1U)
1880 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1881 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1882 
1883 #define ADC_CFGR2_OVSR_Pos             (2U)
1884 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1885 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1886 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1887 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1888 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1889 
1890 #define ADC_CFGR2_OVSS_Pos             (5U)
1891 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1892 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1893 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1894 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1895 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1896 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1897 
1898 #define ADC_CFGR2_TROVS_Pos            (9U)
1899 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1900 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1901 #define ADC_CFGR2_ROVSM_Pos            (10U)
1902 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1903 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1904 
1905 #define ADC_CFGR2_GCOMP_Pos            (16U)
1906 #define ADC_CFGR2_GCOMP_Msk            (0x1UL << ADC_CFGR2_GCOMP_Pos)          /*!< 0x00010000 */
1907 #define ADC_CFGR2_GCOMP                ADC_CFGR2_GCOMP_Msk                     /*!< ADC Gain Compensation mode */
1908 
1909 #define ADC_CFGR2_SWTRIG_Pos           (25U)
1910 #define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
1911 #define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1912 #define ADC_CFGR2_BULB_Pos             (26U)
1913 #define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
1914 #define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
1915 #define ADC_CFGR2_SMPTRIG_Pos          (27U)
1916 #define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
1917 #define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */
1918 
1919 #define ADC_CFGR2_LFTRIG_Pos           (29U)
1920 #define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
1921 #define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC Low Frequency Trigger */
1922 
1923 /********************  Bit definition for ADC_SMPR1 register  *****************/
1924 #define ADC_SMPR1_SMP0_Pos             (0U)
1925 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1926 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1927 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1928 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1929 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1930 
1931 #define ADC_SMPR1_SMP1_Pos             (3U)
1932 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1933 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1934 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1935 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1936 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1937 
1938 #define ADC_SMPR1_SMP2_Pos             (6U)
1939 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1940 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1941 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1942 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1943 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1944 
1945 #define ADC_SMPR1_SMP3_Pos             (9U)
1946 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1947 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1948 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1949 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1950 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1951 
1952 #define ADC_SMPR1_SMP4_Pos             (12U)
1953 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1954 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1955 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1956 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1957 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1958 
1959 #define ADC_SMPR1_SMP5_Pos             (15U)
1960 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1961 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1962 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1963 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1964 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1965 
1966 #define ADC_SMPR1_SMP6_Pos             (18U)
1967 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1968 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1969 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1970 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1971 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1972 
1973 #define ADC_SMPR1_SMP7_Pos             (21U)
1974 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1975 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1976 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1977 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1978 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1979 
1980 #define ADC_SMPR1_SMP8_Pos             (24U)
1981 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1982 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1983 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1984 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1985 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1986 
1987 #define ADC_SMPR1_SMP9_Pos             (27U)
1988 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1989 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1990 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
1991 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
1992 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
1993 
1994 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
1995 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
1996 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
1997 
1998 /********************  Bit definition for ADC_SMPR2 register  *****************/
1999 #define ADC_SMPR2_SMP10_Pos            (0U)
2000 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
2001 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
2002 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
2003 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
2004 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
2005 
2006 #define ADC_SMPR2_SMP11_Pos            (3U)
2007 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
2008 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
2009 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
2010 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
2011 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
2012 
2013 #define ADC_SMPR2_SMP12_Pos            (6U)
2014 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
2015 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
2016 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
2017 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
2018 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
2019 
2020 #define ADC_SMPR2_SMP13_Pos            (9U)
2021 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
2022 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
2023 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
2024 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
2025 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
2026 
2027 #define ADC_SMPR2_SMP14_Pos            (12U)
2028 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
2029 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
2030 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
2031 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
2032 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
2033 
2034 #define ADC_SMPR2_SMP15_Pos            (15U)
2035 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
2036 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
2037 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
2038 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
2039 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
2040 
2041 #define ADC_SMPR2_SMP16_Pos            (18U)
2042 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
2043 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
2044 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
2045 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
2046 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
2047 
2048 #define ADC_SMPR2_SMP17_Pos            (21U)
2049 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
2050 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
2051 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
2052 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
2053 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
2054 
2055 #define ADC_SMPR2_SMP18_Pos            (24U)
2056 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
2057 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
2058 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
2059 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
2060 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
2061 
2062 /********************  Bit definition for ADC_TR1 register  *******************/
2063 #define ADC_TR1_LT1_Pos                (0U)
2064 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
2065 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
2066 
2067 #define ADC_TR1_AWDFILT_Pos            (12U)
2068 #define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
2069 #define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
2070 #define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
2071 #define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
2072 #define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */
2073 
2074 #define ADC_TR1_HT1_Pos                (16U)
2075 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
2076 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */
2077 
2078 /********************  Bit definition for ADC_TR2 register  *******************/
2079 #define ADC_TR2_LT2_Pos                (0U)
2080 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
2081 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
2082 
2083 #define ADC_TR2_HT2_Pos                (16U)
2084 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
2085 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
2086 
2087 /********************  Bit definition for ADC_TR3 register  *******************/
2088 #define ADC_TR3_LT3_Pos                (0U)
2089 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
2090 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
2091 
2092 #define ADC_TR3_HT3_Pos                (16U)
2093 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
2094 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
2095 
2096 /********************  Bit definition for ADC_SQR1 register  ******************/
2097 #define ADC_SQR1_L_Pos                 (0U)
2098 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
2099 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
2100 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
2101 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
2102 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
2103 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
2104 
2105 #define ADC_SQR1_SQ1_Pos               (6U)
2106 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
2107 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
2108 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
2109 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
2110 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
2111 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
2112 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
2113 
2114 #define ADC_SQR1_SQ2_Pos               (12U)
2115 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
2116 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
2117 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
2118 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
2119 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
2120 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
2121 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
2122 
2123 #define ADC_SQR1_SQ3_Pos               (18U)
2124 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
2125 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
2126 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
2127 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
2128 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
2129 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
2130 #define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
2131 
2132 #define ADC_SQR1_SQ4_Pos               (24U)
2133 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
2134 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
2135 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
2136 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
2137 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
2138 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
2139 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
2140 
2141 /********************  Bit definition for ADC_SQR2 register  ******************/
2142 #define ADC_SQR2_SQ5_Pos               (0U)
2143 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
2144 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
2145 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
2146 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
2147 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
2148 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
2149 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
2150 
2151 #define ADC_SQR2_SQ6_Pos               (6U)
2152 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
2153 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
2154 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
2155 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
2156 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
2157 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
2158 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
2159 
2160 #define ADC_SQR2_SQ7_Pos               (12U)
2161 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
2162 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
2163 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
2164 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
2165 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
2166 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
2167 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
2168 
2169 #define ADC_SQR2_SQ8_Pos               (18U)
2170 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
2171 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
2172 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
2173 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
2174 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
2175 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
2176 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
2177 
2178 #define ADC_SQR2_SQ9_Pos               (24U)
2179 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
2180 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
2181 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
2182 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
2183 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
2184 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
2185 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
2186 
2187 /********************  Bit definition for ADC_SQR3 register  ******************/
2188 #define ADC_SQR3_SQ10_Pos              (0U)
2189 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
2190 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
2191 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
2192 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
2193 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
2194 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
2195 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
2196 
2197 #define ADC_SQR3_SQ11_Pos              (6U)
2198 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
2199 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
2200 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
2201 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
2202 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
2203 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
2204 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
2205 
2206 #define ADC_SQR3_SQ12_Pos              (12U)
2207 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
2208 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
2209 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
2210 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
2211 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
2212 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
2213 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
2214 
2215 #define ADC_SQR3_SQ13_Pos              (18U)
2216 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
2217 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
2218 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
2219 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
2220 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
2221 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
2222 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
2223 
2224 #define ADC_SQR3_SQ14_Pos              (24U)
2225 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
2226 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
2227 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
2228 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
2229 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
2230 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
2231 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
2232 
2233 /********************  Bit definition for ADC_SQR4 register  ******************/
2234 #define ADC_SQR4_SQ15_Pos              (0U)
2235 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
2236 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
2237 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
2238 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
2239 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
2240 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
2241 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
2242 
2243 #define ADC_SQR4_SQ16_Pos              (6U)
2244 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
2245 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
2246 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
2247 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
2248 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
2249 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
2250 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
2251 
2252 /********************  Bit definition for ADC_DR register  ********************/
2253 #define ADC_DR_RDATA_Pos               (0U)
2254 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
2255 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
2256 
2257 /********************  Bit definition for ADC_JSQR register  ******************/
2258 #define ADC_JSQR_JL_Pos                (0U)
2259 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
2260 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
2261 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
2262 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
2263 
2264 #define ADC_JSQR_JEXTSEL_Pos           (2U)
2265 #define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
2266 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
2267 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
2268 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
2269 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
2270 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
2271 #define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
2272 
2273 #define ADC_JSQR_JEXTEN_Pos            (7U)
2274 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
2275 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
2276 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
2277 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
2278 
2279 #define ADC_JSQR_JSQ1_Pos              (9U)
2280 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
2281 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
2282 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
2283 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
2284 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
2285 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
2286 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
2287 
2288 #define ADC_JSQR_JSQ2_Pos              (15U)
2289 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
2290 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
2291 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
2292 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
2293 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
2294 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
2295 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
2296 
2297 #define ADC_JSQR_JSQ3_Pos              (21U)
2298 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
2299 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
2300 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
2301 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
2302 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
2303 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
2304 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
2305 
2306 #define ADC_JSQR_JSQ4_Pos              (27U)
2307 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
2308 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
2309 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
2310 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
2311 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
2312 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
2313 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
2314 
2315 /********************  Bit definition for ADC_OFR1 register  ******************/
2316 #define ADC_OFR1_OFFSET1_Pos           (0U)
2317 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
2318 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
2319 
2320 #define ADC_OFR1_OFFSETPOS_Pos         (24U)
2321 #define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
2322 #define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
2323 #define ADC_OFR1_SATEN_Pos             (25U)
2324 #define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
2325 #define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */
2326 
2327 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
2328 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
2329 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
2330 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
2331 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
2332 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
2333 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
2334 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
2335 
2336 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
2337 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
2338 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
2339 
2340 /********************  Bit definition for ADC_OFR2 register  ******************/
2341 #define ADC_OFR2_OFFSET2_Pos           (0U)
2342 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
2343 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
2344 
2345 #define ADC_OFR2_OFFSETPOS_Pos         (24U)
2346 #define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
2347 #define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
2348 #define ADC_OFR2_SATEN_Pos             (25U)
2349 #define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
2350 #define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */
2351 
2352 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
2353 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
2354 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
2355 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
2356 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
2357 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
2358 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
2359 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
2360 
2361 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
2362 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
2363 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
2364 
2365 /********************  Bit definition for ADC_OFR3 register  ******************/
2366 #define ADC_OFR3_OFFSET3_Pos           (0U)
2367 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
2368 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
2369 
2370 #define ADC_OFR3_OFFSETPOS_Pos         (24U)
2371 #define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
2372 #define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
2373 #define ADC_OFR3_SATEN_Pos             (25U)
2374 #define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
2375 #define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */
2376 
2377 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
2378 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
2379 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
2380 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
2381 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
2382 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
2383 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
2384 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
2385 
2386 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
2387 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
2388 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
2389 
2390 /********************  Bit definition for ADC_OFR4 register  ******************/
2391 #define ADC_OFR4_OFFSET4_Pos           (0U)
2392 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
2393 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
2394 
2395 #define ADC_OFR4_OFFSETPOS_Pos         (24U)
2396 #define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
2397 #define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
2398 #define ADC_OFR4_SATEN_Pos             (25U)
2399 #define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
2400 #define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */
2401 
2402 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
2403 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
2404 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
2405 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
2406 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
2407 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
2408 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
2409 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
2410 
2411 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
2412 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
2413 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
2414 
2415 /********************  Bit definition for ADC_JDR1 register  ******************/
2416 #define ADC_JDR1_JDATA_Pos             (0U)
2417 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
2418 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
2419 
2420 /********************  Bit definition for ADC_JDR2 register  ******************/
2421 #define ADC_JDR2_JDATA_Pos             (0U)
2422 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
2423 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
2424 
2425 /********************  Bit definition for ADC_JDR3 register  ******************/
2426 #define ADC_JDR3_JDATA_Pos             (0U)
2427 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
2428 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
2429 
2430 /********************  Bit definition for ADC_JDR4 register  ******************/
2431 #define ADC_JDR4_JDATA_Pos             (0U)
2432 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
2433 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
2434 
2435 /********************  Bit definition for ADC_AWD2CR register  ****************/
2436 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
2437 #define ADC_AWD2CR_AWD2CH_Msk          (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
2438 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
2439 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
2440 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
2441 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
2442 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
2443 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
2444 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
2445 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
2446 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
2447 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
2448 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
2449 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
2450 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
2451 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
2452 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
2453 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
2454 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
2455 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
2456 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
2457 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
2458 #define ADC_AWD2CR_AWD2CH_19           (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00080000 */
2459 
2460 /********************  Bit definition for ADC_AWD3CR register  ****************/
2461 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
2462 #define ADC_AWD3CR_AWD3CH_Msk          (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
2463 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
2464 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
2465 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
2466 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
2467 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
2468 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
2469 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
2470 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
2471 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
2472 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
2473 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
2474 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
2475 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
2476 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
2477 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
2478 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
2479 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
2480 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
2481 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
2482 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
2483 #define ADC_AWD3CR_AWD2CH_19           (0x80000UL << ADC_AWD3CR_AWD2CH_Pos)    /*!< 0x00080000 */
2484 
2485 /********************  Bit definition for ADC_DIFSEL register  ****************/
2486 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
2487 #define ADC_DIFSEL_DIFSEL_Msk          (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
2488 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
2489 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
2490 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
2491 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
2492 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
2493 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
2494 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
2495 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
2496 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
2497 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
2498 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
2499 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
2500 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
2501 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
2502 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
2503 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
2504 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
2505 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
2506 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
2507 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
2508 #define ADC_DIFSEL_DIFSEL_19           (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00080000 */
2509 
2510 /********************  Bit definition for ADC_CALFACT register  ***************/
2511 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2512 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
2513 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2514 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
2515 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
2516 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
2517 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
2518 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
2519 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
2520 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */
2521 
2522 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2523 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
2524 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2525 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
2526 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
2527 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
2528 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
2529 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
2530 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
2531 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */
2532 
2533 /********************  Bit definition for ADC_OR register  *****************/
2534 #define ADC_OR_OP0_Pos       (0U)
2535 #define ADC_OR_OP0_Msk       (0x01UL << ADC_OR_OP0_Pos)                        /*!< 0x00000001 */
2536 #define ADC_OR_OP0           ADC_OR_OP0_Msk                                    /*!< ADC Option bit 0 */
2537 #define ADC_OR_OP1_Pos       (1U)
2538 #define ADC_OR_OP1_Msk       (0x01UL << ADC_OR_OP1_Pos)                        /*!< 0x00000001 */
2539 #define ADC_OR_OP1           ADC_OR_OP1_Msk                                    /*!< ADC Option bit 1 */
2540 
2541 /*************************  ADC Common registers  *****************************/
2542 /********************  Bit definition for ADC_CSR register  *******************/
2543 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2544 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
2545 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2546 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2547 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
2548 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2549 #define ADC_CSR_EOC_MST_Pos            (2U)
2550 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
2551 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2552 #define ADC_CSR_EOS_MST_Pos            (3U)
2553 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
2554 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2555 #define ADC_CSR_OVR_MST_Pos            (4U)
2556 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
2557 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2558 #define ADC_CSR_JEOC_MST_Pos           (5U)
2559 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
2560 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2561 #define ADC_CSR_JEOS_MST_Pos           (6U)
2562 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
2563 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2564 #define ADC_CSR_AWD1_MST_Pos           (7U)
2565 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
2566 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2567 #define ADC_CSR_AWD2_MST_Pos           (8U)
2568 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
2569 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2570 #define ADC_CSR_AWD3_MST_Pos           (9U)
2571 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
2572 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2573 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2574 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
2575 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2576 
2577 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2578 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
2579 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2580 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2581 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
2582 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2583 #define ADC_CSR_EOC_SLV_Pos            (18U)
2584 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
2585 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2586 #define ADC_CSR_EOS_SLV_Pos            (19U)
2587 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
2588 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2589 #define ADC_CSR_OVR_SLV_Pos            (20U)
2590 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
2591 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2592 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2593 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
2594 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2595 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2596 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
2597 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2598 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2599 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
2600 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2601 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2602 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
2603 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2604 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2605 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
2606 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2607 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2608 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
2609 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2610 
2611 /********************  Bit definition for ADC_CCR register  *******************/
2612 #define ADC_CCR_DUAL_Pos               (0U)
2613 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
2614 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2615 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
2616 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
2617 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
2618 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
2619 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
2620 
2621 #define ADC_CCR_DELAY_Pos              (8U)
2622 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
2623 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2624 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
2625 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
2626 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
2627 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
2628 
2629 #define ADC_CCR_DMACFG_Pos             (13U)
2630 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
2631 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2632 
2633 #define ADC_CCR_MDMA_Pos               (14U)
2634 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
2635 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2636 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
2637 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
2638 
2639 #define ADC_CCR_CKMODE_Pos             (16U)
2640 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2641 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2642 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2643 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2644 
2645 #define ADC_CCR_PRESC_Pos              (18U)
2646 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2647 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2648 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2649 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2650 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2651 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2652 
2653 #define ADC_CCR_VREFEN_Pos             (22U)
2654 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2655 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2656 #define ADC_CCR_TSEN_Pos               (23U)
2657 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
2658 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
2659 #define ADC_CCR_VBATEN_Pos             (24U)
2660 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
2661 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
2662 
2663 /********************  Bit definition for ADC_CDR register  *******************/
2664 #define ADC_CDR_RDATA_MST_Pos          (0U)
2665 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
2666 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2667 
2668 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2669 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
2670 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2671 
2672 
2673 /**********************************************************************************************************************/
2674 /*                                                                                                                    */
2675 /*                                            Analog Comparators (COMP)                                               */
2676 /*                                                                                                                    */
2677 /**********************************************************************************************************************/
2678 
2679 /**********************************      Bit definition for COMP_SR register  *****************************************/
2680 #define COMP_SR_C1VAL_Pos            (0U)
2681 #define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)          /*!< 0x00000001                            */
2682 #define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
2683 
2684 #define COMP_SR_C1IF_Pos             (16U)
2685 #define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)           /*!< 0x00010000                            */
2686 #define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
2687 
2688 /**********************************     Bit definition for COMP_ICFR register *****************************************/
2689 #define COMP_ICFR_CC1IF_Pos          (16U)
2690 #define COMP_ICFR_CC1IF_Msk          (0x1UL << COMP_ICFR_CC1IF_Pos)        /*!< 0x00010000                            */
2691 #define COMP_ICFR_CC1IF              COMP_ICFR_CC1IF_Msk
2692 
2693 /**********************************      Bit definition for COMP_CFGR1 register  **************************************/
2694 #define COMP_CFGR1_EN_Pos            (0U)
2695 #define COMP_CFGR1_EN_Msk            (0x1UL << COMP_CFGR1_EN_Pos)          /*!< 0x00000001                            */
2696 #define COMP_CFGR1_EN                COMP_CFGR1_EN_Msk                     /*!< COMP1 enable bit                      */
2697 
2698 #define COMP_CFGR1_BRGEN_Pos         (1U)
2699 #define COMP_CFGR1_BRGEN_Msk         (0x1UL << COMP_CFGR1_BRGEN_Pos)       /*!< 0x00000002                            */
2700 #define COMP_CFGR1_BRGEN             COMP_CFGR1_BRGEN_Msk                  /*!< COMP1 Scaler bridge enable            */
2701 
2702 #define COMP_CFGR1_SCALEN_Pos        (2U)
2703 #define COMP_CFGR1_SCALEN_Msk        (0x1UL << COMP_CFGR1_SCALEN_Pos)      /*!< 0x00000004                            */
2704 #define COMP_CFGR1_SCALEN            COMP_CFGR1_SCALEN_Msk                 /*!< COMP1 Voltage scaler enable bit       */
2705 
2706 #define COMP_CFGR1_POLARITY_Pos      (3U)
2707 #define COMP_CFGR1_POLARITY_Msk      (0x1UL << COMP_CFGR1_POLARITY_Pos)    /*!< 0x00000008                            */
2708 #define COMP_CFGR1_POLARITY          COMP_CFGR1_POLARITY_Msk               /*!< COMP1 polarity selection bit          */
2709 
2710 #define COMP_CFGR1_ITEN_Pos          (6U)
2711 #define COMP_CFGR1_ITEN_Msk          (0x1UL << COMP_CFGR1_ITEN_Pos)        /*!< 0x00000040                            */
2712 #define COMP_CFGR1_ITEN              COMP_CFGR1_ITEN_Msk                   /*!< COMP1 interrupt enable                */
2713 
2714 #define COMP_CFGR1_HYST_Pos          (8U)
2715 #define COMP_CFGR1_HYST_Msk          (0x3UL << COMP_CFGR1_HYST_Pos)        /*!< 0x00000300                            */
2716 #define COMP_CFGR1_HYST              COMP_CFGR1_HYST_Msk                   /*!< COMP1 hysteresis selection bits       */
2717 #define COMP_CFGR1_HYST_0            (0x1UL << COMP_CFGR1_HYST_Pos)        /*!< 0x00000100                            */
2718 #define COMP_CFGR1_HYST_1            (0x2UL << COMP_CFGR1_HYST_Pos)        /*!< 0x00000200                            */
2719 
2720 #define COMP_CFGR1_PWRMODE_Pos       (12U)
2721 #define COMP_CFGR1_PWRMODE_Msk       (0x3UL << COMP_CFGR1_PWRMODE_Pos)     /*!< 0x00003000                            */
2722 #define COMP_CFGR1_PWRMODE           COMP_CFGR1_PWRMODE_Msk                /*!< COMP1 Power Mode of the comparator    */
2723 #define COMP_CFGR1_PWRMODE_0         (0x1UL << COMP_CFGR1_PWRMODE_Pos)     /*!< 0x00001000                            */
2724 #define COMP_CFGR1_PWRMODE_1         (0x2UL << COMP_CFGR1_PWRMODE_Pos)     /*!< 0x00002000                            */
2725 
2726 #define COMP_CFGR1_INMSEL_Pos        (16U)
2727 #define COMP_CFGR1_INMSEL_Msk        (0xFUL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x000F0000                            */
2728 #define COMP_CFGR1_INMSEL            COMP_CFGR1_INMSEL_Msk                 /*!< COMP1 input minus selection bit       */
2729 #define COMP_CFGR1_INMSEL_0          (0x1UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00010000                            */
2730 #define COMP_CFGR1_INMSEL_1          (0x2UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00020000                            */
2731 #define COMP_CFGR1_INMSEL_2          (0x4UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00040000                            */
2732 #define COMP_CFGR1_INMSEL_3          (0x8UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00080000                            */
2733 
2734 #define COMP_CFGR1_INPSEL1_Pos       (20U)
2735 #define COMP_CFGR1_INPSEL1_Msk       (0x1UL << COMP_CFGR1_INPSEL1_Pos)     /*!< 0x00100000                            */
2736 #define COMP_CFGR1_INPSEL1           COMP_CFGR1_INPSEL1_Msk                /*!< COMP1 input plus 1 selection bit      */
2737 
2738 #define COMP_CFGR1_INPSEL2_Pos       (22U)
2739 #define COMP_CFGR1_INPSEL2_Msk       (0x1UL << COMP_CFGR1_INPSEL2_Pos)     /*!< 0x00400000                            */
2740 #define COMP_CFGR1_INPSEL2           COMP_CFGR1_INPSEL2_Msk                /*!< COMP1 input plus 2 selection bit      */
2741 
2742 #define COMP_CFGR1_BLANKING_Pos      (24U)
2743 #define COMP_CFGR1_BLANKING_Msk      (0xFUL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x0F000000                            */
2744 #define COMP_CFGR1_BLANKING          COMP_CFGR1_BLANKING_Msk               /*!< COMP1 blanking source selection bits  */
2745 #define COMP_CFGR1_BLANKING_0        (0x1UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x01000000                            */
2746 #define COMP_CFGR1_BLANKING_1        (0x2UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x02000000                            */
2747 #define COMP_CFGR1_BLANKING_2        (0x4UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x04000000                            */
2748 #define COMP_CFGR1_BLANKING_3        (0x8UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x08000000                            */
2749 
2750 #define COMP_CFGR1_LOCK_Pos          (31U)
2751 #define COMP_CFGR1_LOCK_Msk          (0x1UL << COMP_CFGR1_LOCK_Pos)        /*!< 0x80000000                            */
2752 #define COMP_CFGR1_LOCK              COMP_CFGR1_LOCK_Msk                   /*!< COMP1 Lock Bit                        */
2753 
2754 /*********************************  Bit definition for COMP_CFGR2 register  *******************************************/
2755 #define COMP_CFGR2_INPSEL0_Pos       (4U)
2756 #define COMP_CFGR2_INPSEL0_Msk       (0x1UL << COMP_CFGR2_INPSEL0_Pos)     /*!< 0x00000010                            */
2757 #define COMP_CFGR2_INPSEL0           COMP_CFGR2_INPSEL0_Msk                /*!< COMP1 input plus 0 selection bit      */
2758 
2759 /**********************************************************************************************************************/
2760 /*                                                                                                                    */
2761 /*                                        Operational Amplifier (OPAMP)                                               */
2762 /*                                                                                                                    */
2763 /**********************************************************************************************************************/
2764 
2765 /**********************************   Bit definition for OPAMP_CSR register   *****************************************/
2766 #define OPAMP_CSR_OPAMPxEN_Pos        (0U)
2767 #define OPAMP_CSR_OPAMPxEN_Msk        (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001                               */
2768 #define OPAMP_CSR_OPAMPxEN            OPAMP_CSR_OPAMPxEN_Msk            /*!< OPAMP enable                             */
2769 
2770 #define OPAMP_CSR_FORCEVP_Pos         (1U)
2771 #define OPAMP_CSR_FORCEVP_Msk         (0x1UL << OPAMP_CSR_FORCEVP_Pos)  /*!< 0x00000002                               */
2772 #define OPAMP_CSR_FORCEVP             OPAMP_CSR_FORCEVP_Msk             /*!< Force internal reference on VP           */
2773 
2774 #define OPAMP_CSR_VPSEL_Pos           (2U)
2775 #define OPAMP_CSR_VPSEL_Msk           (0x3UL << OPAMP_CSR_VPSEL_Pos)    /*!< 0x0000000C                               */
2776 #define OPAMP_CSR_VPSEL               OPAMP_CSR_VPSEL_Msk               /*!< Non inverted input selection             */
2777 #define OPAMP_CSR_VPSEL_0             (0x1UL << OPAMP_CSR_VPSEL_Pos)    /*!< 0x00000004                               */
2778 #define OPAMP_CSR_VPSEL_1             (0x2UL << OPAMP_CSR_VPSEL_Pos)    /*!< 0x00000008                               */
2779 
2780 #define OPAMP_CSR_VMSEL_Pos           (5U)
2781 #define OPAMP_CSR_VMSEL_Msk           (0x3UL << OPAMP_CSR_VMSEL_Pos)    /*!< 0x00000060                               */
2782 #define OPAMP_CSR_VMSEL               OPAMP_CSR_VMSEL_Msk               /*!< Inverting input selection                */
2783 #define OPAMP_CSR_VMSEL_0             (0x1UL << OPAMP_CSR_VMSEL_Pos)    /*!< 0x00000020                               */
2784 #define OPAMP_CSR_VMSEL_1             (0x2UL << OPAMP_CSR_VMSEL_Pos)    /*!< 0x00000040                               */
2785 
2786 #define OPAMP_CSR_OPAHSM_Pos          (8U)
2787 #define OPAMP_CSR_OPAHSM_Msk          (0x1UL << OPAMP_CSR_OPAHSM_Pos)   /*!< 0x00000100                               */
2788 #define OPAMP_CSR_OPAHSM              OPAMP_CSR_OPAHSM_Msk              /*!< high speed mode                          */
2789 
2790 #define OPAMP_CSR_CALON_Pos           (11U)
2791 #define OPAMP_CSR_CALON_Msk           (0x1UL << OPAMP_CSR_CALON_Pos)    /*!< 0x00000800                               */
2792 #define OPAMP_CSR_CALON               OPAMP_CSR_CALON_Msk               /*!< Calibration mode enable                  */
2793 
2794 #define OPAMP_CSR_CALSEL_Pos          (12U)
2795 #define OPAMP_CSR_CALSEL_Msk          (0x3UL << OPAMP_CSR_CALSEL_Pos)   /*!< 0x00003000                               */
2796 #define OPAMP_CSR_CALSEL              OPAMP_CSR_CALSEL_Msk              /*!< Calibration selection                    */
2797 #define OPAMP_CSR_CALSEL_0            (0x1UL << OPAMP_CSR_CALSEL_Pos)   /*!< 0x00001000                               */
2798 #define OPAMP_CSR_CALSEL_1            (0x2UL << OPAMP_CSR_CALSEL_Pos)   /*!< 0x00002000                               */
2799 
2800 #define OPAMP_CSR_PGGAIN_Pos          (14U)
2801 #define OPAMP_CSR_PGGAIN_Msk          (0xFUL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x0003C000                               */
2802 #define OPAMP_CSR_PGGAIN              OPAMP_CSR_PGGAIN_Msk              /*!< Programmable amplifier gain value        */
2803 #define OPAMP_CSR_PGGAIN_0            (0x1UL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x00004000                               */
2804 #define OPAMP_CSR_PGGAIN_1            (0x2UL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x00008000                               */
2805 #define OPAMP_CSR_PGGAIN_2            (0x4UL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x00010000                               */
2806 #define OPAMP_CSR_PGGAIN_3            (0x8UL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x00020000                               */
2807 
2808 #define OPAMP_CSR_USERTRIM_Pos        (18U)
2809 #define OPAMP_CSR_USERTRIM_Msk        (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000                               */
2810 #define OPAMP_CSR_USERTRIM            OPAMP_CSR_USERTRIM_Msk            /*!< User trimming enable                     */
2811 
2812 #define OPAMP_CSR_TSTREF_Pos          (29U)
2813 #define OPAMP_CSR_TSTREF_Msk          (0x1UL << OPAMP_CSR_TSTREF_Pos)   /*!< 0x20000000                               */
2814 #define OPAMP_CSR_TSTREF              OPAMP_CSR_TSTREF_Msk              /*!< calibration reference voltage output     */
2815 
2816 #define OPAMP_CSR_CALOUT_Pos          (30U)
2817 #define OPAMP_CSR_CALOUT_Msk          (0x1UL << OPAMP_CSR_CALOUT_Pos)   /*!< 0x40000000                               */
2818 #define OPAMP_CSR_CALOUT              OPAMP_CSR_CALOUT_Msk              /*!< Calibration output                       */
2819 
2820 /**********************************   Bit definition for OPAMP_OTR register  ******************************************/
2821 #define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
2822 #define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F                        */
2823 #define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs  */
2824 
2825 #define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
2826 #define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00                        */
2827 #define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs  */
2828 
2829 /**********************************   Bit definition for OPAMP_HSOTR register   ***************************************/
2830 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
2831 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F                    */
2832 #define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk             /*!< Trim for NMOS pairs           */
2833 
2834 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
2835 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00                    */
2836 #define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk             /*!< Trim for PMOS pairs           */
2837 
2838 
2839 /******************************************************************************/
2840 /*                                                                            */
2841 /*                          CRC calculation unit                              */
2842 /*                                                                            */
2843 /******************************************************************************/
2844 /*******************  Bit definition for CRC_DR register  *********************/
2845 #define CRC_DR_DR_Pos                       (0U)
2846 #define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)         /*!< 0xFFFFFFFF */
2847 #define CRC_DR_DR                           CRC_DR_DR_Msk                           /*!< Data register bits */
2848 
2849 /*******************  Bit definition for CRC_IDR register  ********************/
2850 #define CRC_IDR_IDR_Pos                     (0U)
2851 #define CRC_IDR_IDR_Msk                     (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)       /*!< 0xFFFFFFFF */
2852 #define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                         /*!< General-purpose 32-bits data register bits */
2853 
2854 /********************  Bit definition for CRC_CR register  ********************/
2855 #define CRC_CR_RESET_Pos                    (0U)
2856 #define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)             /*!< 0x00000001 */
2857 #define CRC_CR_RESET                        CRC_CR_RESET_Msk                        /*!< RESET the CRC computation unit bit */
2858 #define CRC_CR_POLYSIZE_Pos                 (3U)
2859 #define CRC_CR_POLYSIZE_Msk                 (0x3UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000018 */
2860 #define CRC_CR_POLYSIZE                     CRC_CR_POLYSIZE_Msk                     /*!< Polynomial size bits */
2861 #define CRC_CR_POLYSIZE_0                   (0x1UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000008 */
2862 #define CRC_CR_POLYSIZE_1                   (0x2UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000010 */
2863 #define CRC_CR_REV_IN_Pos                   (5U)
2864 #define CRC_CR_REV_IN_Msk                   (0x3UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000060 */
2865 #define CRC_CR_REV_IN                       CRC_CR_REV_IN_Msk                       /*!< REV_IN Reverse Input Data bits */
2866 #define CRC_CR_REV_IN_0                     (0x1UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000020 */
2867 #define CRC_CR_REV_IN_1                     (0x2UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000040 */
2868 #define CRC_CR_REV_OUT_Pos                  (7U)
2869 #define CRC_CR_REV_OUT_Msk                  (0x1UL << CRC_CR_REV_OUT_Pos)           /*!< 0x00000080 */
2870 #define CRC_CR_REV_OUT                      CRC_CR_REV_OUT_Msk                      /*!< REV_OUT Reverse Output Data bits */
2871 
2872 /*******************  Bit definition for CRC_INIT register  *******************/
2873 #define CRC_INIT_INIT_Pos                   (0U)
2874 #define CRC_INIT_INIT_Msk                   (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)     /*!< 0xFFFFFFFF */
2875 #define CRC_INIT_INIT                       CRC_INIT_INIT_Msk                       /*!< Initial CRC value bits */
2876 
2877 /*******************  Bit definition for CRC_POL register  ********************/
2878 #define CRC_POL_POL_Pos                     (0U)
2879 #define CRC_POL_POL_Msk                     (0xFFFFFFFFUL << CRC_POL_POL_Pos)       /*!< 0xFFFFFFFF */
2880 #define CRC_POL_POL                         CRC_POL_POL_Msk                         /*!< Coefficients of the polynomial */
2881 
2882 
2883 /******************************************************************************/
2884 /*                                                                            */
2885 /*                          CRS Clock Recovery System                         */
2886 /******************************************************************************/
2887 /*******************  Bit definition for CRS_CR register  *********************/
2888 #define CRS_CR_SYNCOKIE_Pos                 (0U)
2889 #define CRS_CR_SYNCOKIE_Msk                 (0x1UL << CRS_CR_SYNCOKIE_Pos)          /*!< 0x00000001 */
2890 #define CRS_CR_SYNCOKIE                     CRS_CR_SYNCOKIE_Msk                     /*!< SYNC event OK interrupt enable */
2891 #define CRS_CR_SYNCWARNIE_Pos               (1U)
2892 #define CRS_CR_SYNCWARNIE_Msk               (0x1UL << CRS_CR_SYNCWARNIE_Pos)        /*!< 0x00000002 */
2893 #define CRS_CR_SYNCWARNIE                   CRS_CR_SYNCWARNIE_Msk                   /*!< SYNC warning interrupt enable */
2894 #define CRS_CR_ERRIE_Pos                    (2U)
2895 #define CRS_CR_ERRIE_Msk                    (0x1UL << CRS_CR_ERRIE_Pos)             /*!< 0x00000004 */
2896 #define CRS_CR_ERRIE                        CRS_CR_ERRIE_Msk                        /*!< SYNC error or trimming error interrupt enable */
2897 #define CRS_CR_ESYNCIE_Pos                  (3U)
2898 #define CRS_CR_ESYNCIE_Msk                  (0x1UL << CRS_CR_ESYNCIE_Pos)           /*!< 0x00000008 */
2899 #define CRS_CR_ESYNCIE                      CRS_CR_ESYNCIE_Msk                      /*!< Expected SYNC interrupt enable */
2900 #define CRS_CR_CEN_Pos                      (5U)
2901 #define CRS_CR_CEN_Msk                      (0x1UL << CRS_CR_CEN_Pos)               /*!< 0x00000020 */
2902 #define CRS_CR_CEN                          CRS_CR_CEN_Msk                          /*!< Frequency error counter enable */
2903 #define CRS_CR_AUTOTRIMEN_Pos               (6U)
2904 #define CRS_CR_AUTOTRIMEN_Msk               (0x1UL << CRS_CR_AUTOTRIMEN_Pos)        /*!< 0x00000040 */
2905 #define CRS_CR_AUTOTRIMEN                   CRS_CR_AUTOTRIMEN_Msk                   /*!< Automatic trimming enable */
2906 #define CRS_CR_SWSYNC_Pos                   (7U)
2907 #define CRS_CR_SWSYNC_Msk                   (0x1UL << CRS_CR_SWSYNC_Pos)            /*!< 0x00000080 */
2908 #define CRS_CR_SWSYNC                       CRS_CR_SWSYNC_Msk                       /*!< Generate software SYNC event */
2909 #define CRS_CR_TRIM_Pos                     (8U)
2910 #define CRS_CR_TRIM_Msk                     (0x3FUL << CRS_CR_TRIM_Pos)             /*!< 0x00003F00 */
2911 #define CRS_CR_TRIM                         CRS_CR_TRIM_Msk                         /*!< HSI48 oscillator smooth trimming */
2912 
2913 /*******************  Bit definition for CRS_CFGR register  *********************/
2914 #define CRS_CFGR_RELOAD_Pos                 (0U)
2915 #define CRS_CFGR_RELOAD_Msk                 (0xFFFFUL << CRS_CFGR_RELOAD_Pos)       /*!< 0x0000FFFF */
2916 #define CRS_CFGR_RELOAD                     CRS_CFGR_RELOAD_Msk                     /*!< Counter reload value */
2917 #define CRS_CFGR_FELIM_Pos                  (16U)
2918 #define CRS_CFGR_FELIM_Msk                  (0xFFUL << CRS_CFGR_FELIM_Pos)          /*!< 0x00FF0000 */
2919 #define CRS_CFGR_FELIM                      CRS_CFGR_FELIM_Msk                      /*!< Frequency error limit */
2920 #define CRS_CFGR_SYNCDIV_Pos                (24U)
2921 #define CRS_CFGR_SYNCDIV_Msk                (0x7UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x07000000 */
2922 #define CRS_CFGR_SYNCDIV                    CRS_CFGR_SYNCDIV_Msk                    /*!< SYNC divider */
2923 #define CRS_CFGR_SYNCDIV_0                  (0x1UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x01000000 */
2924 #define CRS_CFGR_SYNCDIV_1                  (0x2UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x02000000 */
2925 #define CRS_CFGR_SYNCDIV_2                  (0x4UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x04000000 */
2926 #define CRS_CFGR_SYNCSRC_Pos                (28U)
2927 #define CRS_CFGR_SYNCSRC_Msk                (0x3UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x30000000 */
2928 #define CRS_CFGR_SYNCSRC                    CRS_CFGR_SYNCSRC_Msk                    /*!< SYNC signal source selection */
2929 #define CRS_CFGR_SYNCSRC_0                  (0x1UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x10000000 */
2930 #define CRS_CFGR_SYNCSRC_1                  (0x2UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x20000000 */
2931 #define CRS_CFGR_SYNCPOL_Pos                (31U)
2932 #define CRS_CFGR_SYNCPOL_Msk                (0x1UL << CRS_CFGR_SYNCPOL_Pos)         /*!< 0x80000000 */
2933 #define CRS_CFGR_SYNCPOL                    CRS_CFGR_SYNCPOL_Msk                    /*!< SYNC polarity selection */
2934 
2935 /*******************  Bit definition for CRS_ISR register  *********************/
2936 #define CRS_ISR_SYNCOKF_Pos                 (0U)
2937 #define CRS_ISR_SYNCOKF_Msk                 (0x1UL << CRS_ISR_SYNCOKF_Pos)          /*!< 0x00000001 */
2938 #define CRS_ISR_SYNCOKF                     CRS_ISR_SYNCOKF_Msk                     /*!< SYNC event OK flag */
2939 #define CRS_ISR_SYNCWARNF_Pos               (1U)
2940 #define CRS_ISR_SYNCWARNF_Msk               (0x1UL << CRS_ISR_SYNCWARNF_Pos)        /*!< 0x00000002 */
2941 #define CRS_ISR_SYNCWARNF                   CRS_ISR_SYNCWARNF_Msk                   /*!< SYNC warning flag */
2942 #define CRS_ISR_ERRF_Pos                    (2U)
2943 #define CRS_ISR_ERRF_Msk                    (0x1UL << CRS_ISR_ERRF_Pos)             /*!< 0x00000004 */
2944 #define CRS_ISR_ERRF                        CRS_ISR_ERRF_Msk                        /*!< Error flag */
2945 #define CRS_ISR_ESYNCF_Pos                  (3U)
2946 #define CRS_ISR_ESYNCF_Msk                  (0x1UL << CRS_ISR_ESYNCF_Pos)           /*!< 0x00000008 */
2947 #define CRS_ISR_ESYNCF                      CRS_ISR_ESYNCF_Msk                      /*!< Expected SYNC flag */
2948 #define CRS_ISR_SYNCERR_Pos                 (8U)
2949 #define CRS_ISR_SYNCERR_Msk                 (0x1UL << CRS_ISR_SYNCERR_Pos)          /*!< 0x00000100 */
2950 #define CRS_ISR_SYNCERR                     CRS_ISR_SYNCERR_Msk                     /*!< SYNC error */
2951 #define CRS_ISR_SYNCMISS_Pos                (9U)
2952 #define CRS_ISR_SYNCMISS_Msk                (0x1UL << CRS_ISR_SYNCMISS_Pos)         /*!< 0x00000200 */
2953 #define CRS_ISR_SYNCMISS                    CRS_ISR_SYNCMISS_Msk                    /*!< SYNC missed */
2954 #define CRS_ISR_TRIMOVF_Pos                 (10U)
2955 #define CRS_ISR_TRIMOVF_Msk                 (0x1UL << CRS_ISR_TRIMOVF_Pos)          /*!< 0x00000400 */
2956 #define CRS_ISR_TRIMOVF                     CRS_ISR_TRIMOVF_Msk                     /*!< Trimming overflow or underflow */
2957 #define CRS_ISR_FEDIR_Pos                   (15U)
2958 #define CRS_ISR_FEDIR_Msk                   (0x1UL << CRS_ISR_FEDIR_Pos)            /*!< 0x00008000 */
2959 #define CRS_ISR_FEDIR                       CRS_ISR_FEDIR_Msk                       /*!< Frequency error direction */
2960 #define CRS_ISR_FECAP_Pos                   (16U)
2961 #define CRS_ISR_FECAP_Msk                   (0xFFFFUL << CRS_ISR_FECAP_Pos)         /*!< 0xFFFF0000 */
2962 #define CRS_ISR_FECAP                       CRS_ISR_FECAP_Msk                       /*!< Frequency error capture */
2963 
2964 /*******************  Bit definition for CRS_ICR register  *********************/
2965 #define CRS_ICR_SYNCOKC_Pos                 (0U)
2966 #define CRS_ICR_SYNCOKC_Msk                 (0x1UL << CRS_ICR_SYNCOKC_Pos)          /*!< 0x00000001 */
2967 #define CRS_ICR_SYNCOKC                     CRS_ICR_SYNCOKC_Msk                     /*!< SYNC event OK clear flag */
2968 #define CRS_ICR_SYNCWARNC_Pos               (1U)
2969 #define CRS_ICR_SYNCWARNC_Msk               (0x1UL << CRS_ICR_SYNCWARNC_Pos)        /*!< 0x00000002 */
2970 #define CRS_ICR_SYNCWARNC                   CRS_ICR_SYNCWARNC_Msk                   /*!< SYNC warning clear flag */
2971 #define CRS_ICR_ERRC_Pos                    (2U)
2972 #define CRS_ICR_ERRC_Msk                    (0x1UL << CRS_ICR_ERRC_Pos)             /*!< 0x00000004 */
2973 #define CRS_ICR_ERRC                        CRS_ICR_ERRC_Msk                        /*!< Error clear flag */
2974 #define CRS_ICR_ESYNCC_Pos                  (3U)
2975 #define CRS_ICR_ESYNCC_Msk                  (0x1UL << CRS_ICR_ESYNCC_Pos)           /*!< 0x00000008 */
2976 #define CRS_ICR_ESYNCC                      CRS_ICR_ESYNCC_Msk                      /*!< Expected SYNC clear flag */
2977 
2978 
2979 /******************************************************************************/
2980 /*                                                                            */
2981 /*                                    RNG                                     */
2982 /*                                                                            */
2983 /******************************************************************************/
2984 /********************  Bits definition for RNG_CR register  *******************/
2985 #define RNG_CR_RNGEN_Pos                    (2U)
2986 #define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
2987 #define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
2988 #define RNG_CR_IE_Pos                       (3U)
2989 #define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
2990 #define RNG_CR_IE                           RNG_CR_IE_Msk
2991 #define RNG_CR_CED_Pos                      (5U)
2992 #define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
2993 #define RNG_CR_CED                          RNG_CR_CED_Msk
2994 #define RNG_CR_ARDIS_Pos                    (7U)
2995 #define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
2996 #define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
2997 #define RNG_CR_RNG_CONFIG3_Pos              (8U)
2998 #define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
2999 #define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
3000 #define RNG_CR_NISTC_Pos                    (12U)
3001 #define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
3002 #define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
3003 #define RNG_CR_RNG_CONFIG2_Pos              (13U)
3004 #define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
3005 #define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
3006 #define RNG_CR_CLKDIV_Pos                   (16U)
3007 #define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
3008 #define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
3009 #define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
3010 #define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
3011 #define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
3012 #define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
3013 #define RNG_CR_RNG_CONFIG1_Pos              (20U)
3014 #define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
3015 #define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
3016 #define RNG_CR_CONDRST_Pos                  (30U)
3017 #define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
3018 #define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
3019 #define RNG_CR_CONFIGLOCK_Pos               (31U)
3020 #define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
3021 #define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
3022 
3023 /********************  Bits definition for RNG_SR register  *******************/
3024 #define RNG_SR_DRDY_Pos                     (0U)
3025 #define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
3026 #define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
3027 #define RNG_SR_CECS_Pos                     (1U)
3028 #define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
3029 #define RNG_SR_CECS                         RNG_SR_CECS_Msk
3030 #define RNG_SR_SECS_Pos                     (2U)
3031 #define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
3032 #define RNG_SR_SECS                         RNG_SR_SECS_Msk
3033 #define RNG_SR_CEIS_Pos                     (5U)
3034 #define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
3035 #define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
3036 #define RNG_SR_SEIS_Pos                     (6U)
3037 #define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
3038 #define RNG_SR_SEIS                         RNG_SR_SEIS_Msk
3039 
3040 
3041 /********************  Bits definition for RNG_HTCR register  *******************/
3042 #define RNG_HTCR_HTCFG_Pos                  (0U)
3043 #define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
3044 #define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
3045 
3046 /********************  RNG Nist Compliance Values  ******************************/
3047 #define RNG_CR_NIST_VALUE                   (0x00F00D00U)
3048 #define RNG_HTCR_NIST_VALUE                 (0xAAC7U)
3049 
3050 /******************************************************************************/
3051 /*                                                                            */
3052 /*                      Digital to Analog Converter                           */
3053 /*                                                                            */
3054 /******************************************************************************/
3055 #define DAC_CHANNEL2_SUPPORT                                                        /*!< DAC feature available only on specific devices: DAC channel 2 available */
3056 
3057 /********************  Bit definition for DAC_CR register  ********************/
3058 #define DAC_CR_EN1_Pos                      (0U)
3059 #define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)               /*!< 0x00000001 */
3060 #define DAC_CR_EN1                          DAC_CR_EN1_Msk                          /*!<DAC channel1 enable */
3061 #define DAC_CR_TEN1_Pos                     (1U)
3062 #define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)              /*!< 0x00000002 */
3063 #define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                         /*!<DAC channel1 Trigger enable */
3064 #define DAC_CR_TSEL1_Pos                    (2U)
3065 #define DAC_CR_TSEL1_Msk                    (0xFUL << DAC_CR_TSEL1_Pos)             /*!< 0x0000003C */
3066 #define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                        /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
3067 #define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000004 */
3068 #define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000008 */
3069 #define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000010 */
3070 #define DAC_CR_TSEL1_3                      (0x8UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000020 */
3071 #define DAC_CR_WAVE1_Pos                    (6U)
3072 #define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)             /*!< 0x000000C0 */
3073 #define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3074 #define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000040 */
3075 #define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000080 */
3076 #define DAC_CR_MAMP1_Pos                    (8U)
3077 #define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)             /*!< 0x00000F00 */
3078 #define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3079 #define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000100 */
3080 #define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000200 */
3081 #define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000400 */
3082 #define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000800 */
3083 #define DAC_CR_DMAEN1_Pos                   (12U)
3084 #define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)            /*!< 0x00001000 */
3085 #define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                       /*!<DAC channel1 DMA enable */
3086 #define DAC_CR_DMAUDRIE1_Pos                (13U)
3087 #define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)         /*!< 0x00002000 */
3088 #define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk                    /*!<DAC channel 1 DMA underrun interrupt enable  >*/
3089 #define DAC_CR_CEN1_Pos                     (14U)
3090 #define DAC_CR_CEN1_Msk                     (0x1UL << DAC_CR_CEN1_Pos)              /*!< 0x00004000 */
3091 #define DAC_CR_CEN1                         DAC_CR_CEN1_Msk                         /*!<DAC channel 1 calibration enable >*/
3092 #define DAC_CR_EN2_Pos                      (16U)
3093 #define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)               /*!< 0x00010000 */
3094 #define DAC_CR_EN2                          DAC_CR_EN2_Msk                          /*!<DAC channel2 enable */
3095 #define DAC_CR_TEN2_Pos                     (17U)
3096 #define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)              /*!< 0x00020000 */
3097 #define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                         /*!<DAC channel2 Trigger enable */
3098 #define DAC_CR_TSEL2_Pos                    (18U)
3099 #define DAC_CR_TSEL2_Msk                    (0xFUL << DAC_CR_TSEL2_Pos)             /*!< 0x003C0000 */
3100 #define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                        /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
3101 #define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)             /*!< 0x00040000 */
3102 #define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)             /*!< 0x00080000 */
3103 #define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)             /*!< 0x00100000 */
3104 #define DAC_CR_TSEL2_3                      (0x8UL << DAC_CR_TSEL2_Pos)             /*!< 0x00200000 */
3105 #define DAC_CR_WAVE2_Pos                    (22U)
3106 #define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)             /*!< 0x00C00000 */
3107 #define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3108 #define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)             /*!< 0x00400000 */
3109 #define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)             /*!< 0x00800000 */
3110 #define DAC_CR_MAMP2_Pos                    (24U)
3111 #define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)             /*!< 0x0F000000 */
3112 #define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3113 #define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)             /*!< 0x01000000 */
3114 #define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)             /*!< 0x02000000 */
3115 #define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)             /*!< 0x04000000 */
3116 #define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)             /*!< 0x08000000 */
3117 #define DAC_CR_DMAEN2_Pos                   (28U)
3118 #define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)            /*!< 0x10000000 */
3119 #define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                       /*!<DAC channel2 DMA enabled */
3120 #define DAC_CR_DMAUDRIE2_Pos                (29U)
3121 #define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)         /*!< 0x20000000 */
3122 #define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk                    /*!<DAC channel2 DMA underrun interrupt enable  >*/
3123 #define DAC_CR_CEN2_Pos                     (30U)
3124 #define DAC_CR_CEN2_Msk                     (0x1UL << DAC_CR_CEN2_Pos)              /*!< 0x40000000 */
3125 #define DAC_CR_CEN2                         DAC_CR_CEN2_Msk                         /*!<DAC channel2 calibration enable >*/
3126 
3127 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
3128 #define DAC_SWTRIGR_SWTRIG1_Pos             (0U)
3129 #define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)      /*!< 0x00000001 */
3130 #define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk                 /*!<DAC channel1 software trigger */
3131 #define DAC_SWTRIGR_SWTRIG2_Pos             (1U)
3132 #define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)      /*!< 0x00000002 */
3133 #define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk                 /*!<DAC channel2 software trigger */
3134 #define DAC_SWTRIGR_SWTRIGB1_Pos            (16U)
3135 #define DAC_SWTRIGR_SWTRIGB1_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)     /*!< 0x00010000 */
3136 #define DAC_SWTRIGR_SWTRIGB1                DAC_SWTRIGR_SWTRIGB1_Msk                /*!<DAC channel1 software trigger B */
3137 #define DAC_SWTRIGR_SWTRIGB2_Pos            (17U)
3138 #define DAC_SWTRIGR_SWTRIGB2_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)     /*!< 0x00020000 */
3139 #define DAC_SWTRIGR_SWTRIGB2                DAC_SWTRIGR_SWTRIGB2_Msk                /*!<DAC channel2 software trigger B */
3140 
3141 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
3142 #define DAC_DHR12R1_DACC1DHR_Pos            (0U)
3143 #define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000FFF */
3144 #define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
3145 #define DAC_DHR12R1_DACC1DHRB_Pos           (16U)
3146 #define DAC_DHR12R1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x0FFF0000 */
3147 #define DAC_DHR12R1_DACC1DHRB               DAC_DHR12R1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Right-aligned data B */
3148 
3149 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
3150 #define DAC_DHR12L1_DACC1DHR_Pos            (4U)
3151 #define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
3152 #define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
3153 #define DAC_DHR12L1_DACC1DHRB_Pos           (20U)
3154 #define DAC_DHR12L1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0xFFF00000 */
3155 #define DAC_DHR12L1_DACC1DHRB               DAC_DHR12L1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Left aligned data B */
3156 
3157 /******************  Bit definition for DAC_DHR8R1 register  ******************/
3158 #define DAC_DHR8R1_DACC1DHR_Pos             (0U)
3159 #define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x000000FF */
3160 #define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
3161 #define DAC_DHR8R1_DACC1DHRB_Pos            (8U)
3162 #define DAC_DHR8R1_DACC1DHRB_Msk            (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x0000FF00 */
3163 #define DAC_DHR8R1_DACC1DHRB                DAC_DHR8R1_DACC1DHRB_Msk                /*!<DAC channel1 8-bit Right aligned data B */
3164 
3165 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
3166 #define DAC_DHR12R2_DACC2DHR_Pos            (0U)
3167 #define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)   /*!< 0x00000FFF */
3168 #define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */
3169 #define DAC_DHR12R2_DACC2DHRB_Pos           (16U)
3170 #define DAC_DHR12R2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)  /*!< 0x0FFF0000 */
3171 #define DAC_DHR12R2_DACC2DHRB               DAC_DHR12R2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Right-aligned data B */
3172 
3173 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
3174 #define DAC_DHR12L2_DACC2DHR_Pos            (4U)
3175 #define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)   /*!< 0x0000FFF0 */
3176 #define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */
3177 #define DAC_DHR12L2_DACC2DHRB_Pos           (20U)
3178 #define DAC_DHR12L2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)  /*!< 0xFFF00000 */
3179 #define DAC_DHR12L2_DACC2DHRB               DAC_DHR12L2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Left aligned data B */
3180 
3181 /******************  Bit definition for DAC_DHR8R2 register  ******************/
3182 #define DAC_DHR8R2_DACC2DHR_Pos             (0U)
3183 #define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)     /*!< 0x000000FF */
3184 #define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */
3185 #define DAC_DHR8R2_DACC2DHRB_Pos            (8U)
3186 #define DAC_DHR8R2_DACC2DHRB_Msk            (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)    /*!< 0x0000FF00 */
3187 #define DAC_DHR8R2_DACC2DHRB                DAC_DHR8R2_DACC2DHRB_Msk                /*!<DAC channel2 8-bit Right aligned data B */
3188 
3189 /*****************  Bit definition for DAC_DHR12RD register  ******************/
3190 #define DAC_DHR12RD_DACC1DHR_Pos            (0U)
3191 #define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)   /*!< 0x00000FFF */
3192 #define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
3193 #define DAC_DHR12RD_DACC2DHR_Pos            (16U)
3194 #define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)   /*!< 0x0FFF0000 */
3195 #define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */
3196 
3197 /*****************  Bit definition for DAC_DHR12LD register  ******************/
3198 #define DAC_DHR12LD_DACC1DHR_Pos            (4U)
3199 #define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
3200 #define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
3201 #define DAC_DHR12LD_DACC2DHR_Pos            (20U)
3202 #define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)   /*!< 0xFFF00000 */
3203 #define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */
3204 
3205 /******************  Bit definition for DAC_DHR8RD register  ******************/
3206 #define DAC_DHR8RD_DACC1DHR_Pos             (0U)
3207 #define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)     /*!< 0x000000FF */
3208 #define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
3209 #define DAC_DHR8RD_DACC2DHR_Pos             (8U)
3210 #define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)     /*!< 0x0000FF00 */
3211 #define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */
3212 
3213 /*******************  Bit definition for DAC_DOR1 register  *******************/
3214 #define DAC_DOR1_DACC1DOR_Pos               (0U)
3215 #define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000FFF */
3216 #define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk                   /*!<DAC channel1 data output */
3217 #define DAC_DOR1_DACC1DORB_Pos              (16U)
3218 #define DAC_DOR1_DACC1DORB_Msk              (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x0FFF0000 */
3219 #define DAC_DOR1_DACC1DORB                  DAC_DOR1_DACC1DORB_Msk                  /*!<DAC channel1 data output B */
3220 
3221 /*******************  Bit definition for DAC_DOR2 register  *******************/
3222 #define DAC_DOR2_DACC2DOR_Pos               (0U)
3223 #define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)      /*!< 0x00000FFF */
3224 #define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk                   /*!<DAC channel2 data output */
3225 #define DAC_DOR2_DACC2DORB_Pos              (16U)
3226 #define DAC_DOR2_DACC2DORB_Msk              (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)     /*!< 0x0FFF0000 */
3227 #define DAC_DOR2_DACC2DORB                  DAC_DOR2_DACC2DORB_Msk                  /*!<DAC channel2 data output B */
3228 
3229 /********************  Bit definition for DAC_SR register  ********************/
3230 #define DAC_SR_DAC1RDY_Pos                  (11U)
3231 #define DAC_SR_DAC1RDY_Msk                  (0x1UL << DAC_SR_DAC1RDY_Pos)           /*!< 0x00000800 */
3232 #define DAC_SR_DAC1RDY                      DAC_SR_DAC1RDY_Msk                      /*!<DAC channel 1 ready status bit */
3233 #define DAC_SR_DORSTAT1_Pos                 (12U)
3234 #define DAC_SR_DORSTAT1_Msk                 (0x1UL << DAC_SR_DORSTAT1_Pos)          /*!< 0x00001000 */
3235 #define DAC_SR_DORSTAT1                     DAC_SR_DORSTAT1_Msk                     /*!<DAC channel 1 output register status bit */
3236 #define DAC_SR_DMAUDR1_Pos                  (13U)
3237 #define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)           /*!< 0x00002000 */
3238 #define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                      /*!<DAC channel1 DMA underrun flag */
3239 #define DAC_SR_CAL_FLAG1_Pos                (14U)
3240 #define DAC_SR_CAL_FLAG1_Msk                (0x1UL << DAC_SR_CAL_FLAG1_Pos)         /*!< 0x00004000 */
3241 #define DAC_SR_CAL_FLAG1                    DAC_SR_CAL_FLAG1_Msk                    /*!<DAC channel1 calibration offset status */
3242 #define DAC_SR_BWST1_Pos                    (15U)
3243 #define DAC_SR_BWST1_Msk                    (0x1UL << DAC_SR_BWST1_Pos)             /*!< 0x00008000 */
3244 #define DAC_SR_BWST1                        DAC_SR_BWST1_Msk                        /*!<DAC channel1 busy writing sample time flag */
3245 
3246 #define DAC_SR_DAC2RDY_Pos                  (27U)
3247 #define DAC_SR_DAC2RDY_Msk                  (0x1UL << DAC_SR_DAC2RDY_Pos)           /*!< 0x08000000 */
3248 #define DAC_SR_DAC2RDY                      DAC_SR_DAC2RDY_Msk                      /*!<DAC channel 2 ready status bit */
3249 #define DAC_SR_DORSTAT2_Pos                 (28U)
3250 #define DAC_SR_DORSTAT2_Msk                 (0x1UL << DAC_SR_DORSTAT2_Pos)          /*!< 0x10000000 */
3251 #define DAC_SR_DORSTAT2                     DAC_SR_DORSTAT2_Msk                     /*!<DAC channel 2 output register status bit */
3252 #define DAC_SR_DMAUDR2_Pos                  (29U)
3253 #define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)           /*!< 0x20000000 */
3254 #define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                      /*!<DAC channel2 DMA underrun flag */
3255 #define DAC_SR_CAL_FLAG2_Pos                (30U)
3256 #define DAC_SR_CAL_FLAG2_Msk                (0x1UL << DAC_SR_CAL_FLAG2_Pos)         /*!< 0x40000000 */
3257 #define DAC_SR_CAL_FLAG2                    DAC_SR_CAL_FLAG2_Msk                    /*!<DAC channel2 calibration offset status */
3258 #define DAC_SR_BWST2_Pos                    (31U)
3259 #define DAC_SR_BWST2_Msk                    (0x1UL << DAC_SR_BWST2_Pos)             /*!< 0x80000000 */
3260 #define DAC_SR_BWST2                        DAC_SR_BWST2_Msk                        /*!<DAC channel2 busy writing sample time flag */
3261 
3262 /*******************  Bit definition for DAC_CCR register  ********************/
3263 #define DAC_CCR_OTRIM1_Pos                  (0U)
3264 #define DAC_CCR_OTRIM1_Msk                  (0x1FUL << DAC_CCR_OTRIM1_Pos)          /*!< 0x0000001F */
3265 #define DAC_CCR_OTRIM1                      DAC_CCR_OTRIM1_Msk                      /*!<DAC channel1 offset trimming value */
3266 #define DAC_CCR_OTRIM2_Pos                  (16U)
3267 #define DAC_CCR_OTRIM2_Msk                  (0x1FUL << DAC_CCR_OTRIM2_Pos)          /*!< 0x001F0000 */
3268 #define DAC_CCR_OTRIM2                      DAC_CCR_OTRIM2_Msk                      /*!<DAC channel2 offset trimming value */
3269 
3270 /*******************  Bit definition for DAC_MCR register  *******************/
3271 #define DAC_MCR_MODE1_Pos                   (0U)
3272 #define DAC_MCR_MODE1_Msk                   (0x7UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000007 */
3273 #define DAC_MCR_MODE1                       DAC_MCR_MODE1_Msk                       /*!<MODE1[2:0] (DAC channel1 mode) */
3274 #define DAC_MCR_MODE1_0                     (0x1UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000001 */
3275 #define DAC_MCR_MODE1_1                     (0x2UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000002 */
3276 #define DAC_MCR_MODE1_2                     (0x4UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000004 */
3277 #define DAC_MCR_DMADOUBLE1_Pos              (8U)
3278 #define DAC_MCR_DMADOUBLE1_Msk              (0x1UL << DAC_MCR_DMADOUBLE1_Pos)       /*!< 0x00000100 */
3279 #define DAC_MCR_DMADOUBLE1                  DAC_MCR_DMADOUBLE1_Msk                  /*!<DAC Channel 1 DMA double data mode */
3280 #define DAC_MCR_SINFORMAT1_Pos              (9U)
3281 #define DAC_MCR_SINFORMAT1_Msk              (0x1UL << DAC_MCR_SINFORMAT1_Pos)       /*!< 0x00000200 */
3282 #define DAC_MCR_SINFORMAT1                  DAC_MCR_SINFORMAT1_Msk                  /*!<DAC Channel 1 enable signed format */
3283 #define DAC_MCR_HFSEL_Pos                   (14U)
3284 #define DAC_MCR_HFSEL_Msk                   (0x3UL << DAC_MCR_HFSEL_Pos)            /*!< 0x0000C000 */
3285 #define DAC_MCR_HFSEL                       DAC_MCR_HFSEL_Msk                       /*!<HFSEL[1:0] (High Frequency interface mode selection) */
3286 #define DAC_MCR_HFSEL_0                     (0x1UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00004000 */
3287 #define DAC_MCR_HFSEL_1                     (0x2UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00008000 */
3288 #define DAC_MCR_MODE2_Pos                   (16U)
3289 #define DAC_MCR_MODE2_Msk                   (0x7UL << DAC_MCR_MODE2_Pos)            /*!< 0x00070000 */
3290 #define DAC_MCR_MODE2                       DAC_MCR_MODE2_Msk                       /*!<MODE2[2:0] (DAC channel2 mode) */
3291 #define DAC_MCR_MODE2_0                     (0x1UL << DAC_MCR_MODE2_Pos)            /*!< 0x00010000 */
3292 #define DAC_MCR_MODE2_1                     (0x2UL << DAC_MCR_MODE2_Pos)            /*!< 0x00020000 */
3293 #define DAC_MCR_MODE2_2                     (0x4UL << DAC_MCR_MODE2_Pos)            /*!< 0x00040000 */
3294 #define DAC_MCR_DMADOUBLE2_Pos              (24U)
3295 #define DAC_MCR_DMADOUBLE2_Msk              (0x1UL << DAC_MCR_DMADOUBLE2_Pos)       /*!< 0x01000000 */
3296 #define DAC_MCR_DMADOUBLE2                  DAC_MCR_DMADOUBLE2_Msk                  /*!<DAC Channel 2 DMA double data mode */
3297 #define DAC_MCR_SINFORMAT2_Pos              (25U)
3298 #define DAC_MCR_SINFORMAT2_Msk              (0x1UL << DAC_MCR_SINFORMAT2_Pos)       /*!< 0x02000000 */
3299 #define DAC_MCR_SINFORMAT2                  DAC_MCR_SINFORMAT2_Msk                  /*!<DAC Channel 2 enable signed format */
3300 
3301 /******************  Bit definition for DAC_SHSR1 register  ******************/
3302 #define DAC_SHSR1_TSAMPLE1_Pos              (0U)
3303 #define DAC_SHSR1_TSAMPLE1_Msk              (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)     /*!< 0x000003FF */
3304 #define DAC_SHSR1_TSAMPLE1                  DAC_SHSR1_TSAMPLE1_Msk                  /*!<DAC channel1 sample time */
3305 
3306 /******************  Bit definition for DAC_SHSR2 register  ******************/
3307 #define DAC_SHSR2_TSAMPLE2_Pos              (0U)
3308 #define DAC_SHSR2_TSAMPLE2_Msk              (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)     /*!< 0x000003FF */
3309 #define DAC_SHSR2_TSAMPLE2                  DAC_SHSR2_TSAMPLE2_Msk                  /*!<DAC channel2 sample time */
3310 
3311 /******************  Bit definition for DAC_SHHR register  ******************/
3312 #define DAC_SHHR_THOLD1_Pos                 (0U)
3313 #define DAC_SHHR_THOLD1_Msk                 (0x3FFUL << DAC_SHHR_THOLD1_Pos)        /*!< 0x000003FF */
3314 #define DAC_SHHR_THOLD1                     DAC_SHHR_THOLD1_Msk                     /*!<DAC channel1 hold time */
3315 #define DAC_SHHR_THOLD2_Pos                 (16U)
3316 #define DAC_SHHR_THOLD2_Msk                 (0x3FFUL << DAC_SHHR_THOLD2_Pos)        /*!< 0x03FF0000 */
3317 #define DAC_SHHR_THOLD2                     DAC_SHHR_THOLD2_Msk                     /*!<DAC channel2 hold time */
3318 
3319 /******************  Bit definition for DAC_SHRR register  ******************/
3320 #define DAC_SHRR_TREFRESH1_Pos              (0U)
3321 #define DAC_SHRR_TREFRESH1_Msk              (0xFFUL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x000000FF */
3322 #define DAC_SHRR_TREFRESH1                  DAC_SHRR_TREFRESH1_Msk                  /*!<DAC channel1 refresh time */
3323 #define DAC_SHRR_TREFRESH2_Pos              (16U)
3324 #define DAC_SHRR_TREFRESH2_Msk              (0xFFUL << DAC_SHRR_TREFRESH2_Pos)      /*!< 0x00FF0000 */
3325 #define DAC_SHRR_TREFRESH2                  DAC_SHRR_TREFRESH2_Msk                  /*!<DAC channel2 refresh time */
3326 
3327 /******************  Bit definition for DAC_AUTOCR register  ******************/
3328 #define DAC_AUTOCR_AUTOMODE_Pos             (22U)
3329 #define DAC_AUTOCR_AUTOMODE_Msk             (0x1UL << DAC_AUTOCR_AUTOMODE_Pos)      /*!< 0x00400000 */
3330 #define DAC_AUTOCR_AUTOMODE                 DAC_AUTOCR_AUTOMODE_Msk                 /*!< AUTOCR Enable */
3331 
3332 
3333 /******************************************************************************/
3334 /*                                                                            */
3335 /*                                    HASH                                    */
3336 /*                                                                            */
3337 /******************************************************************************/
3338 /******************  Bits definition for HASH_CR register  ********************/
3339 #define HASH_CR_INIT_Pos                    (2U)
3340 #define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
3341 #define HASH_CR_INIT                        HASH_CR_INIT_Msk
3342 #define HASH_CR_DMAE_Pos                    (3U)
3343 #define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
3344 #define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
3345 #define HASH_CR_DATATYPE_Pos                (4U)
3346 #define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
3347 #define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
3348 #define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
3349 #define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
3350 #define HASH_CR_MODE_Pos                    (6U)
3351 #define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
3352 #define HASH_CR_MODE                        HASH_CR_MODE_Msk
3353 #define HASH_CR_NBW_Pos                     (8U)
3354 #define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
3355 #define HASH_CR_NBW                         HASH_CR_NBW_Msk
3356 #define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
3357 #define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
3358 #define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
3359 #define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
3360 #define HASH_CR_DINNE_Pos                   (12U)
3361 #define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
3362 #define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
3363 #define HASH_CR_MDMAT_Pos                   (13U)
3364 #define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
3365 #define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
3366 #define HASH_CR_LKEY_Pos                    (16U)
3367 #define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
3368 #define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
3369 #define HASH_CR_ALGO_Pos                    (17U)
3370 #define HASH_CR_ALGO_Msk                    (0x3UL << HASH_CR_ALGO_Pos)             /*!< 0x00060000 */
3371 #define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
3372 #define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
3373 #define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
3374 
3375 /******************  Bits definition for HASH_STR register  *******************/
3376 #define HASH_STR_NBLW_Pos                   (0U)
3377 #define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
3378 #define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
3379 #define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
3380 #define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
3381 #define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
3382 #define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
3383 #define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
3384 #define HASH_STR_DCAL_Pos                   (8U)
3385 #define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
3386 #define HASH_STR_DCAL                       HASH_STR_DCAL_Msk
3387 
3388 /******************  Bits definition for HASH_IMR register  *******************/
3389 #define HASH_IMR_DINIE_Pos                  (0U)
3390 #define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
3391 #define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
3392 #define HASH_IMR_DCIE_Pos                   (1U)
3393 #define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
3394 #define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk
3395 
3396 /******************  Bits definition for HASH_SR register  ********************/
3397 #define HASH_SR_DINIS_Pos                   (0U)
3398 #define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
3399 #define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
3400 #define HASH_SR_DCIS_Pos                    (1U)
3401 #define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
3402 #define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
3403 #define HASH_SR_DMAS_Pos                    (2U)
3404 #define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
3405 #define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
3406 #define HASH_SR_BUSY_Pos                    (3U)
3407 #define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
3408 #define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
3409 #define HASH_SR_NBWE_Pos                    (16U)
3410 #define HASH_SR_NBWE_Msk                    (0xFUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
3411 #define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
3412 #define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
3413 #define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
3414 #define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
3415 #define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
3416 #define HASH_SR_DINNE_Pos                   (15U)
3417 #define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
3418 #define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
3419 #define HASH_SR_NBWP_Pos                    (9U)
3420 #define HASH_SR_NBWP_Msk                    (0xFUL << HASH_SR_NBWP_Pos)             /*!< 0x000F0000 */
3421 #define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
3422 #define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
3423 #define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
3424 #define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
3425 #define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
3426 
3427 
3428 /******************************************************************************/
3429 /*                                                                            */
3430 /*                                 Debug MCU                                  */
3431 /*                                                                            */
3432 /******************************************************************************/
3433 /********************  Bit definition for DBGMCU_IDCODE register  *************/
3434 #define DBGMCU_IDCODE_DEV_ID_Pos            (0U)
3435 #define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)   /*!< 0x00000FFF */
3436 #define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk
3437 #define DBGMCU_IDCODE_REV_ID_Pos            (16U)
3438 #define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)  /*!< 0xFFFF0000 */
3439 #define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk
3440 
3441 /********************  Bit definition for DBGMCU_CR register  *****************/
3442 #define DBGMCU_CR_DBG_STOP_Pos              (1U)
3443 #define DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos)       /*!< 0x00000002 */
3444 #define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk
3445 #define DBGMCU_CR_DBG_STANDBY_Pos           (2U)
3446 #define DBGMCU_CR_DBG_STANDBY_Msk           (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)    /*!< 0x00000004 */
3447 #define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk
3448 #define DBGMCU_CR_TRACE_IOEN_Pos            (4U)
3449 #define DBGMCU_CR_TRACE_IOEN_Msk            (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)     /*!< 0x00000010 */
3450 #define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk
3451 #define DBGMCU_CR_TRACE_CLKEN_Pos           (5U)
3452 #define DBGMCU_CR_TRACE_CLKEN_Msk           (0x1UL << DBGMCU_CR_TRACE_CLKEN_Pos)    /*!< 0x00000020 */
3453 #define DBGMCU_CR_TRACE_CLKEN               DBGMCU_CR_TRACE_CLKEN_Msk
3454 #define DBGMCU_CR_TRACE_MODE_Pos            (6U)
3455 #define DBGMCU_CR_TRACE_MODE_Msk            (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x000000C0 */
3456 #define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk
3457 #define DBGMCU_CR_TRACE_MODE_0              (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000040 */
3458 #define DBGMCU_CR_TRACE_MODE_1              (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000080 */
3459 #define DBGMCU_CR_DCRT_Pos                  (16U)
3460 #define DBGMCU_CR_DCRT_Msk                  (0x1UL << DBGMCU_CR_DCRT_Pos)           /*!< 0x00010000 */
3461 #define DBGMCU_CR_DCRT                      DBGMCU_CR_DCRT_Msk
3462 
3463 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
3464 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos   (0U)
3465 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
3466 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP       DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
3467 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos   (1U)
3468 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)
3469 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP       DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
3470 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos   (4U)
3471 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
3472 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP       DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
3473 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos   (5U)
3474 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
3475 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP       DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
3476 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos   (11U)
3477 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
3478 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP       DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
3479 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos   (12U)
3480 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
3481 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP       DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
3482 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos   (21U)
3483 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
3484 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP       DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
3485 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos   (22U)
3486 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
3487 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP       DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
3488 #define DBGMCU_APB1FZR1_DBG_I3C1_STOP_Pos   (23U)
3489 #define DBGMCU_APB1FZR1_DBG_I3C1_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I3C1_STOP_Pos)
3490 #define DBGMCU_APB1FZR1_DBG_I3C1_STOP       DBGMCU_APB1FZR1_DBG_I3C1_STOP_Msk
3491 
3492 /********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
3493 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
3494 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
3495 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP     DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
3496 
3497 /********************  Bit definition for DBGMCU_APB2FZR register  ***********/
3498 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos    (11U)
3499 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk    (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)
3500 #define DBGMCU_APB2FZR_DBG_TIM1_STOP        DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
3501 
3502 /********************  Bit definition for DBGMCU_APB3FZR register  ***********/
3503 #define DBGMCU_APB3FZR_DBG_I3C2_STOP_Pos    (12U)
3504 #define DBGMCU_APB3FZR_DBG_I3C2_STOP_Msk    (0x1UL << DBGMCU_APB3FZR_DBG_I3C2_STOP_Pos)
3505 #define DBGMCU_APB3FZR_DBG_I3C2_STOP        DBGMCU_APB3FZR_DBG_I3C2_STOP_Msk
3506 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos  (17U)
3507 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos)
3508 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP      DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk
3509 #define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos     (30U)
3510 #define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk     (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos)
3511 #define DBGMCU_APB3FZR_DBG_RTC_STOP         DBGMCU_APB3FZR_DBG_RTC_STOP_Msk
3512 
3513 /********************  Bit definition for DBGMCU_AHB1FZR register  ***********/
3514 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos  (0U)
3515 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos)
3516 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk
3517 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos  (1U)
3518 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos)
3519 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk
3520 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos  (2U)
3521 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos)
3522 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk
3523 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos  (3U)
3524 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos)
3525 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk
3526 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos  (4U)
3527 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos)
3528 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk
3529 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos  (5U)
3530 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos)
3531 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk
3532 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos  (6U)
3533 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos)
3534 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk
3535 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos  (7U)
3536 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos)
3537 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk
3538 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Pos  (8U)
3539 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Pos)
3540 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Msk
3541 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Pos  (9U)
3542 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Pos)
3543 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Msk
3544 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Pos (10U)
3545 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Pos)
3546 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Msk
3547 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Pos (11U)
3548 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Pos)
3549 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Msk
3550 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Pos (12U)
3551 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Pos)
3552 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Msk
3553 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Pos (13U)
3554 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Pos)
3555 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Msk
3556 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Pos (14U)
3557 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Pos)
3558 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Msk
3559 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Pos (15U)
3560 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Pos)
3561 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Msk
3562 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Pos  (16U)
3563 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Pos)
3564 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP      DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Msk
3565 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Pos (17U)
3566 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Pos)
3567 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP      DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Msk
3568 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Pos (18U)
3569 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Pos)
3570 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Msk
3571 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Pos (19U)
3572 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Pos)
3573 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Msk
3574 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Pos (20U)
3575 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Pos)
3576 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Msk
3577 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Pos (21U)
3578 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Pos)
3579 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Msk
3580 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Pos (22U)
3581 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Pos)
3582 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Msk
3583 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Pos (23U)
3584 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Pos)
3585 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Msk
3586 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Pos (24U)
3587 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Pos)
3588 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Msk
3589 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Pos (25U)
3590 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Pos)
3591 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Msk
3592 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Pos (26U)
3593 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Pos)
3594 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Msk
3595 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Pos (27U)
3596 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Pos)
3597 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Msk
3598 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Pos (28U)
3599 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Pos)
3600 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Msk
3601 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Pos (29U)
3602 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Pos)
3603 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Msk
3604 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Pos (30U)
3605 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Pos)
3606 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Msk
3607 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Pos (31U)
3608 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Pos)
3609 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Msk
3610 
3611 /********************  Bit definition for DBGMCU_SR register  ***********/
3612 #define DBGMCU_SR_ACC_PORT_PRES_Pos          (0U)
3613 #define DBGMCU_SR_ACC_PORT_PRES_Msk          (0xFFFFUL << DBGMCU_SR_ACC_PORT_PRES_Pos)   /*!< 0x0000FFFF */
3614 #define DBGMCU_SR_ACC_PORT_PRES              DBGMCU_SR_ACC_PORT_PRES_Msk
3615 #define DBGMCU_SR_ACC_PORT_ENBL_Pos          (16U)
3616 #define DBGMCU_SR_ACC_PORT_ENBL_Msk          (0xFFFFUL << DBGMCU_SR_ACC_PORT_ENBL_Pos)   /*!< 0xFFFF0000 */
3617 #define DBGMCU_SR_ACC_PORT_ENBL              DBGMCU_SR_ACC_PORT_ENBL_Msk
3618 
3619 /********************  Bit definition for DBGMCU_DBG_AUTH_HOST register  ***********/
3620 #define DBGMCU_DBG_AUTH_HOST_Pos             (0U)
3621 #define DBGMCU_DBG_AUTH_HOST_Msk             (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_Pos)  /*!< 0xFFFFFFFF */
3622 #define DBGMCU_DBG_AUTH_HOST                 DBGMCU_DBG_AUTH_HOST_Msk
3623 
3624 /********************  Bit definition for DBGMCU_DBG_AUTH_DEV register  ***********/
3625 #define DBGMCU_DBG_AUTH_DEV_Pos              (0U)
3626 #define DBGMCU_DBG_AUTH_DEV_Msk              (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_Pos)   /*!< 0xFFFFFFFF */
3627 #define DBGMCU_DBG_AUTH_DEV                  DBGMCU_DBG_AUTH_DEV_Msk
3628 
3629 /********************  Bit definition for DBGMCU_DBG_AUTH_ACK register  ***********/
3630 #define DBGMCU_DBG_AUTH_ACK_HOST_Pos         (0U)
3631 #define DBGMCU_DBG_AUTH_ACK_HOST_Msk         (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_Pos)     /*!< 0x00000001 */
3632 #define DBGMCU_DBG_AUTH_ACK_HOST             DBGMCU_DBG_AUTH_ACK_HOST_Msk
3633 #define DBGMCU_DBG_AUTH_ACK_DEV_Pos          (1U)
3634 #define DBGMCU_DBG_AUTH_ACK_DEV_Msk          (0x1UL << DBGMCU_DBG_AUTH_ACK_DEV_Pos)      /*!< 0x00000002 */
3635 #define DBGMCU_DBG_AUTH_ACK_DEV              DBGMCU_DBG_AUTH_ACK_DEV_Msk
3636 
3637 /********************  Bit definition for DBGMCU_PIDR4 register  ************/
3638 #define DBGMCU_PIDR4_JEP106CON_Pos           (0U)
3639 #define DBGMCU_PIDR4_JEP106CON_Msk           (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)    /*!< 0x0000000F */
3640 #define DBGMCU_PIDR4_JEP106CON               DBGMCU_PIDR4_JEP106CON_Msk
3641 #define DBGMCU_PIDR4_4KCOUNT_Pos             (4U)
3642 #define DBGMCU_PIDR4_4KCOUNT_Msk             (0xFUL << DBGMCU_PIDR4_4KCOUNT_Pos)      /*!< 0x000000F0 */
3643 #define DBGMCU_PIDR4_4KCOUNT                 DBGMCU_PIDR4_4KCOUNT_Msk
3644 
3645 /********************  Bit definition for DBGMCU_PIDR0 register  ************/
3646 #define DBGMCU_PIDR0_PARTNUM_Pos             (0U)
3647 #define DBGMCU_PIDR0_PARTNUM_Msk             (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)     /*!< 0x000000FF */
3648 #define DBGMCU_PIDR0_PARTNUM                 DBGMCU_PIDR0_PARTNUM_Msk
3649 
3650 /********************  Bit definition for DBGMCU_PIDR1 register  ************/
3651 #define DBGMCU_PIDR1_PARTNUM_Pos             (0U)
3652 #define DBGMCU_PIDR1_PARTNUM_Msk             (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)      /*!< 0x0000000F */
3653 #define DBGMCU_PIDR1_PARTNUM                 DBGMCU_PIDR1_PARTNUM_Msk
3654 #define DBGMCU_PIDR1_JEP106ID_Pos            (4U)
3655 #define DBGMCU_PIDR1_JEP106ID_Msk            (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)     /*!< 0x000000F0 */
3656 #define DBGMCU_PIDR1_JEP106ID                DBGMCU_PIDR1_JEP106ID_Msk
3657 
3658 /********************  Bit definition for DBGMCU_PIDR2 register  ************/
3659 #define DBGMCU_PIDR2_JEP106ID_Pos            (0U)
3660 #define DBGMCU_PIDR2_JEP106ID_Msk            (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)     /*!< 0x00000007 */
3661 #define DBGMCU_PIDR2_JEP106ID                DBGMCU_PIDR2_JEP106ID_Msk
3662 #define DBGMCU_PIDR2_JEDEC_Pos               (3U)
3663 #define DBGMCU_PIDR2_JEDEC_Msk               (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)        /*!< 0x00000008 */
3664 #define DBGMCU_PIDR2_JEDEC                   DBGMCU_PIDR2_JEDEC_Msk
3665 #define DBGMCU_PIDR2_REVISION_Pos            (4U)
3666 #define DBGMCU_PIDR2_REVISION_Msk            (0xFUL << DBGMCU_PIDR2_REVISION_Pos)     /*!< 0x000000F0 */
3667 #define DBGMCU_PIDR2_REVISION                DBGMCU_PIDR2_REVISION_Msk
3668 
3669 /********************  Bit definition for DBGMCU_PIDR3 register  ************/
3670 #define DBGMCU_PIDR3_CMOD_Pos                (0U)
3671 #define DBGMCU_PIDR3_CMOD_Msk                (0xFUL << DBGMCU_PIDR3_CMOD_Pos)         /*!< 0x0000000F */
3672 #define DBGMCU_PIDR3_CMOD                    DBGMCU_PIDR3_CMOD_Msk
3673 #define DBGMCU_PIDR3_REVAND_Pos              (4U)
3674 #define DBGMCU_PIDR3_REVAND_Msk              (0xFUL << DBGMCU_PIDR3_REVAND_Pos)       /*!< 0x000000F0 */
3675 #define DBGMCU_PIDR3_REVAND                  DBGMCU_PIDR3_REVAND_Msk
3676 
3677 /********************  Bit definition for DBGMCU_CIDR0 register  ************/
3678 #define DBGMCU_CIDR0_PREAMBLE_Pos            (0U)
3679 #define DBGMCU_CIDR0_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos)    /*!< 0x000000FF */
3680 #define DBGMCU_CIDR0_PREAMBLE                DBGMCU_CIDR0_PREAMBLE_Msk
3681 
3682 /********************  Bit definition for DBGMCU_CIDR1 register  ************/
3683 #define DBGMCU_CIDR1_PREAMBLE_Pos            (0U)
3684 #define DBGMCU_CIDR1_PREAMBLE_Msk            (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos)     /*!< 0x0000000F */
3685 #define DBGMCU_CIDR1_PREAMBLE                DBGMCU_CIDR1_PREAMBLE_Msk
3686 #define DBGMCU_CIDR1_CLASS_Pos               (4U)
3687 #define DBGMCU_CIDR1_CLASS_Msk               (0xFUL << DBGMCU_CIDR1_CLASS_Pos)        /*!< 0x000000F0 */
3688 #define DBGMCU_CIDR1_CLASS                   DBGMCU_CIDR1_CLASS_Msk
3689 
3690 /********************  Bit definition for DBGMCU_CIDR2 register  ************/
3691 #define DBGMCU_CIDR2_PREAMBLE_Pos            (0U)
3692 #define DBGMCU_CIDR2_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos)    /*!< 0x000000FF */
3693 #define DBGMCU_CIDR2_PREAMBLE                DBGMCU_CIDR2_PREAMBLE_Msk
3694 
3695 /********************  Bit definition for DBGMCU_CIDR3 register  ************/
3696 #define DBGMCU_CIDR3_PREAMBLE_Pos            (0U)
3697 #define DBGMCU_CIDR3_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos)    /*!< 0x000000FF */
3698 #define DBGMCU_CIDR3_PREAMBLE                DBGMCU_CIDR3_PREAMBLE_Msk
3699 /******************************************************************************/
3700 /*                                                                            */
3701 /*                           DMA Controller (DMA)                             */
3702 /*                                                                            */
3703 /******************************************************************************/
3704 
3705 /*******************  Bit definition for DMA_PRIVCFGR register  ****************/
3706 #define DMA_PRIVCFGR_PRIV0_Pos              (0U)
3707 #define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
3708 #define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0  */
3709 #define DMA_PRIVCFGR_PRIV1_Pos              (1U)
3710 #define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
3711 #define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1  */
3712 #define DMA_PRIVCFGR_PRIV2_Pos              (2U)
3713 #define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
3714 #define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2  */
3715 #define DMA_PRIVCFGR_PRIV3_Pos              (3U)
3716 #define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
3717 #define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3  */
3718 #define DMA_PRIVCFGR_PRIV4_Pos              (4U)
3719 #define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
3720 #define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4  */
3721 #define DMA_PRIVCFGR_PRIV5_Pos              (5U)
3722 #define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
3723 #define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5  */
3724 #define DMA_PRIVCFGR_PRIV6_Pos              (6U)
3725 #define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
3726 #define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6  */
3727 #define DMA_PRIVCFGR_PRIV7_Pos              (7U)
3728 #define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
3729 #define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7  */
3730 
3731 
3732 /*******************  Bit definition for DMA_MISR register  ****************/
3733 #define DMA_MISR_MIS0_Pos                   (0U)
3734 #define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
3735 #define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0  */
3736 #define DMA_MISR_MIS1_Pos                   (1U)
3737 #define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
3738 #define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1  */
3739 #define DMA_MISR_MIS2_Pos                   (2U)
3740 #define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
3741 #define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2  */
3742 #define DMA_MISR_MIS3_Pos                   (3U)
3743 #define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
3744 #define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3  */
3745 #define DMA_MISR_MIS4_Pos                   (4U)
3746 #define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
3747 #define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4  */
3748 #define DMA_MISR_MIS5_Pos                   (5U)
3749 #define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
3750 #define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5  */
3751 #define DMA_MISR_MIS6_Pos                   (6U)
3752 #define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
3753 #define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6  */
3754 #define DMA_MISR_MIS7_Pos                   (7U)
3755 #define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
3756 #define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7  */
3757 
3758 
3759 /*******************  Bit definition for DMA_CLBAR register  ****************/
3760 #define DMA_CLBAR_LBA_Pos                   (16U)
3761 #define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
3762 #define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */
3763 
3764 /*******************  Bit definition for DMA_CFCR register  *******************/
3765 #define DMA_CFCR_TCF_Pos                    (8U)
3766 #define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
3767 #define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear             */
3768 #define DMA_CFCR_HTF_Pos                    (9U)
3769 #define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
3770 #define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear        */
3771 #define DMA_CFCR_DTEF_Pos                   (10U)
3772 #define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
3773 #define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear           */
3774 #define DMA_CFCR_ULEF_Pos                   (11U)
3775 #define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
3776 #define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
3777 #define DMA_CFCR_USEF_Pos                   (12U)
3778 #define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
3779 #define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear            */
3780 #define DMA_CFCR_SUSPF_Pos                  (13U)
3781 #define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
3782 #define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear          */
3783 #define DMA_CFCR_TOF_Pos                    (14U)
3784 #define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
3785 #define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun flag clear               */
3786 
3787 /*******************  Bit definition for DMA_CSR register  *******************/
3788 #define DMA_CSR_IDLEF_Pos                   (0U)
3789 #define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
3790 #define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag                          */
3791 #define DMA_CSR_TCF_Pos                     (8U)
3792 #define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
3793 #define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag             */
3794 #define DMA_CSR_HTF_Pos                     (9U)
3795 #define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
3796 #define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag        */
3797 #define DMA_CSR_DTEF_Pos                    (10U)
3798 #define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
3799 #define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag           */
3800 #define DMA_CSR_ULEF_Pos                    (11U)
3801 #define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
3802 #define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
3803 #define DMA_CSR_USEF_Pos                    (12U)
3804 #define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
3805 #define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag            */
3806 #define DMA_CSR_SUSPF_Pos                   (13U)
3807 #define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
3808 #define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< User setting error flag            */
3809 #define DMA_CSR_TOF_Pos                     (14U)
3810 #define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
3811 #define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag               */
3812 #define DMA_CSR_FIFOL_Pos                   (16U)
3813 #define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
3814 #define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes      */
3815 
3816 /*******************  Bit definition for DMA_CCR register  ********************/
3817 #define DMA_CCR_EN_Pos                      (0U)
3818 #define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
3819 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable                                 */
3820 #define DMA_CCR_RESET_Pos                   (1U)
3821 #define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
3822 #define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset                                  */
3823 #define DMA_CCR_SUSP_Pos                    (2U)
3824 #define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
3825 #define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend                                */
3826 #define DMA_CCR_TCIE_Pos                    (8U)
3827 #define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
3828 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable             */
3829 #define DMA_CCR_HTIE_Pos                    (9U)
3830 #define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
3831 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable        */
3832 #define DMA_CCR_DTEIE_Pos                   (10U)
3833 #define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
3834 #define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable           */
3835 #define DMA_CCR_ULEIE_Pos                   (11U)
3836 #define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
3837 #define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
3838 #define DMA_CCR_USEIE_Pos                   (12U)
3839 #define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
3840 #define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable            */
3841 #define DMA_CCR_SUSPIE_Pos                  (13U)
3842 #define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
3843 #define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable          */
3844 #define DMA_CCR_TOIE_Pos                    (14U)
3845 #define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
3846 #define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable               */
3847 #define DMA_CCR_LSM_Pos                     (16U)
3848 #define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
3849 #define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode                                 */
3850 #define DMA_CCR_LAP_Pos                     (17U)
3851 #define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
3852 #define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port                     */
3853 #define DMA_CCR_PRIO_Pos                    (22U)
3854 #define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
3855 #define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level                                 */
3856 #define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
3857 #define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */
3858 
3859 /*******************  Bit definition for DMA_CTR1 register  *******************/
3860 #define DMA_CTR1_SDW_LOG2_Pos               (0U)
3861 #define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
3862 #define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst                    */
3863 #define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
3864 #define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
3865 #define DMA_CTR1_SINC_Pos                   (3U)
3866 #define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
3867 #define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst                                               */
3868 #define DMA_CTR1_SBL_1_Pos                  (4U)
3869 #define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
3870 #define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1                                             */
3871 #define DMA_CTR1_PAM_Pos                    (11U)
3872 #define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
3873 #define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode                                                */
3874 #define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
3875 #define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
3876 #define DMA_CTR1_SBX_Pos                    (13U)
3877 #define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
3878 #define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
3879 #define DMA_CTR1_SAP_Pos                    (14U)
3880 #define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
3881 #define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port                                                   */
3882 #define DMA_CTR1_DDW_LOG2_Pos               (16U)
3883 #define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
3884 #define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst               */
3885 #define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
3886 #define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
3887 #define DMA_CTR1_DINC_Pos                   (19U)
3888 #define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
3889 #define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst                                          */
3890 #define DMA_CTR1_DBL_1_Pos                  (20U)
3891 #define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
3892 #define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1                                        */
3893 #define DMA_CTR1_DBX_Pos                    (26U)
3894 #define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
3895 #define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange                                               */
3896 #define DMA_CTR1_DHX_Pos                    (27U)
3897 #define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
3898 #define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange                                          */
3899 #define DMA_CTR1_DAP_Pos                    (30U)
3900 #define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
3901 #define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port                                              */
3902 
3903 /******************  Bit definition for DMA_CTR2 register  *******************/
3904 #define DMA_CTR2_REQSEL_Pos                 (0U)
3905 #define DMA_CTR2_REQSEL_Msk                 (0xFFUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x000000FF */
3906 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
3907 #define DMA_CTR2_SWREQ_Pos                  (9U)
3908 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
3909 #define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request               */
3910 #define DMA_CTR2_DREQ_Pos                   (10U)
3911 #define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
3912 #define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request   */
3913 #define DMA_CTR2_BREQ_Pos                   (11U)
3914 #define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
3915 #define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request         */
3916 #define DMA_CTR2_PFREQ_Pos                  (12U)
3917 #define DMA_CTR2_PFREQ_Msk                  (0x1U << DMA_CTR2_PFREQ_Pos)            /*!< 0x00001000 */
3918 #define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                      /*!< Block hardware request */
3919 #define DMA_CTR2_TRIGM_Pos                  (14U)
3920 #define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
3921 #define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode                   */
3922 #define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
3923 #define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
3924 #define DMA_CTR2_TRIGSEL_Pos                (16U)
3925 #define DMA_CTR2_TRIGSEL_Msk                (0x3FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x003F0000 */
3926 #define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection  */
3927 #define DMA_CTR2_TRIGPOL_Pos                (24U)
3928 #define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
3929 #define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity         */
3930 #define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
3931 #define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
3932 #define DMA_CTR2_TCEM_Pos                   (30U)
3933 #define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
3934 #define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode   */
3935 #define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
3936 #define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */
3937 
3938 /******************  Bit definition for DMA_CBR1 register  *******************/
3939 #define DMA_CBR1_BNDT_Pos                   (0U)
3940 #define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
3941 #define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
3942 #define DMA_CBR1_BRC_Pos                    (16U)
3943 #define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
3944 #define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter                                   */
3945 #define DMA_CBR1_SDEC_Pos                   (28U)
3946 #define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
3947 #define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement                               */
3948 #define DMA_CBR1_DDEC_Pos                   (29U)
3949 #define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
3950 #define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement                          */
3951 #define DMA_CBR1_BRSDEC_Pos                 (30U)
3952 #define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
3953 #define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement                  */
3954 #define DMA_CBR1_BRDDEC_Pos                 (31U)
3955 #define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
3956 #define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement             */
3957 
3958 /******************  Bit definition for DMA_CSAR register  ********************/
3959 #define DMA_CSAR_SA_Pos                     (0U)
3960 #define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
3961 #define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */
3962 
3963 /******************  Bit definition for DMA_CDAR register  *******************/
3964 #define DMA_CDAR_DA_Pos                     (0U)
3965 #define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
3966 #define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */
3967 
3968 /******************  Bit definition for DMA_CTR3 register  *******************/
3969 #define DMA_CTR3_SAO_Pos                    (0U)
3970 #define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
3971 #define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment      */
3972 #define DMA_CTR3_DAO_Pos                    (16U)
3973 #define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
3974 #define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */
3975 
3976 /******************  Bit definition for DMA_CBR2 register  *******************/
3977 #define DMA_CBR2_BRSAO_Pos                  (0U)
3978 #define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
3979 #define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset      */
3980 #define DMA_CBR2_BRDAO_Pos                  (16U)
3981 #define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
3982 #define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */
3983 
3984 /******************  Bit definition for DMA_CLLR register  *******************/
3985 #define DMA_CLLR_LA_Pos                     (2U)
3986 #define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
3987 #define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
3988 #define DMA_CLLR_ULL_Pos                    (16U)
3989 #define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
3990 #define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory       */
3991 #define DMA_CLLR_UB2_Pos                    (25U)
3992 #define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
3993 #define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory            */
3994 #define DMA_CLLR_UT3_Pos                    (26U)
3995 #define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
3996 #define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM           */
3997 #define DMA_CLLR_UDA_Pos                    (27U)
3998 #define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
3999 #define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM  */
4000 #define DMA_CLLR_USA_Pos                    (28U)
4001 #define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
4002 #define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM       */
4003 #define DMA_CLLR_UB1_Pos                    (29U)
4004 #define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
4005 #define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM              */
4006 #define DMA_CLLR_UT2_Pos                    (30U)
4007 #define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
4008 #define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM           */
4009 #define DMA_CLLR_UT1_Pos                    (31U)
4010 #define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
4011 #define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM           */
4012 
4013 /******************************************************************************/
4014 /*                                                                            */
4015 /*                    External Interrupt/Event Controller                     */
4016 /*                                                                            */
4017 /******************************************************************************/
4018 /******************  Bit definition for EXTI_RTSR1 register  ******************/
4019 #define EXTI_RTSR1_RT0_Pos                  (0U)
4020 #define EXTI_RTSR1_RT0_Msk                  (0x1UL << EXTI_RTSR1_RT0_Pos)           /*!< 0x00000001 */
4021 #define EXTI_RTSR1_RT0                      EXTI_RTSR1_RT0_Msk                      /*!< Rising trigger configuration for input line 0 */
4022 #define EXTI_RTSR1_RT1_Pos                  (1U)
4023 #define EXTI_RTSR1_RT1_Msk                  (0x1UL << EXTI_RTSR1_RT1_Pos)           /*!< 0x00000002 */
4024 #define EXTI_RTSR1_RT1                      EXTI_RTSR1_RT1_Msk                      /*!< Rising trigger configuration for input line 1 */
4025 #define EXTI_RTSR1_RT2_Pos                  (2U)
4026 #define EXTI_RTSR1_RT2_Msk                  (0x1UL << EXTI_RTSR1_RT2_Pos)           /*!< 0x00000004 */
4027 #define EXTI_RTSR1_RT2                      EXTI_RTSR1_RT2_Msk                      /*!< Rising trigger configuration for input line 2 */
4028 #define EXTI_RTSR1_RT3_Pos                  (3U)
4029 #define EXTI_RTSR1_RT3_Msk                  (0x1UL << EXTI_RTSR1_RT3_Pos)           /*!< 0x00000008 */
4030 #define EXTI_RTSR1_RT3                      EXTI_RTSR1_RT3_Msk                      /*!< Rising trigger configuration for input line 3 */
4031 #define EXTI_RTSR1_RT4_Pos                  (4U)
4032 #define EXTI_RTSR1_RT4_Msk                  (0x1UL << EXTI_RTSR1_RT4_Pos)           /*!< 0x00000010 */
4033 #define EXTI_RTSR1_RT4                      EXTI_RTSR1_RT4_Msk                      /*!< Rising trigger configuration for input line 4 */
4034 #define EXTI_RTSR1_RT5_Pos                  (5U)
4035 #define EXTI_RTSR1_RT5_Msk                  (0x1UL << EXTI_RTSR1_RT5_Pos)           /*!< 0x00000020 */
4036 #define EXTI_RTSR1_RT5                      EXTI_RTSR1_RT5_Msk                      /*!< Rising trigger configuration for input line 5 */
4037 #define EXTI_RTSR1_RT6_Pos                  (6U)
4038 #define EXTI_RTSR1_RT6_Msk                  (0x1UL << EXTI_RTSR1_RT6_Pos)           /*!< 0x00000040 */
4039 #define EXTI_RTSR1_RT6                      EXTI_RTSR1_RT6_Msk                      /*!< Rising trigger configuration for input line 6 */
4040 #define EXTI_RTSR1_RT7_Pos                  (7U)
4041 #define EXTI_RTSR1_RT7_Msk                  (0x1UL << EXTI_RTSR1_RT7_Pos)           /*!< 0x00000080 */
4042 #define EXTI_RTSR1_RT7                      EXTI_RTSR1_RT7_Msk                      /*!< Rising trigger configuration for input line 7 */
4043 #define EXTI_RTSR1_RT8_Pos                  (8U)
4044 #define EXTI_RTSR1_RT8_Msk                  (0x1UL << EXTI_RTSR1_RT8_Pos)           /*!< 0x00000100 */
4045 #define EXTI_RTSR1_RT8                      EXTI_RTSR1_RT8_Msk                      /*!< Rising trigger configuration for input line 8 */
4046 #define EXTI_RTSR1_RT9_Pos                  (9U)
4047 #define EXTI_RTSR1_RT9_Msk                  (0x1UL << EXTI_RTSR1_RT9_Pos)           /*!< 0x00000200 */
4048 #define EXTI_RTSR1_RT9                      EXTI_RTSR1_RT9_Msk                      /*!< Rising trigger configuration for input line 9 */
4049 #define EXTI_RTSR1_RT10_Pos                 (10U)
4050 #define EXTI_RTSR1_RT10_Msk                 (0x1UL << EXTI_RTSR1_RT10_Pos)          /*!< 0x00000400 */
4051 #define EXTI_RTSR1_RT10                     EXTI_RTSR1_RT10_Msk                     /*!< Rising trigger configuration for input line 10 */
4052 #define EXTI_RTSR1_RT11_Pos                 (11U)
4053 #define EXTI_RTSR1_RT11_Msk                 (0x1UL << EXTI_RTSR1_RT11_Pos)          /*!< 0x00000800 */
4054 #define EXTI_RTSR1_RT11                     EXTI_RTSR1_RT11_Msk                     /*!< Rising trigger configuration for input line 11 */
4055 #define EXTI_RTSR1_RT12_Pos                 (12U)
4056 #define EXTI_RTSR1_RT12_Msk                 (0x1UL << EXTI_RTSR1_RT12_Pos)          /*!< 0x00001000 */
4057 #define EXTI_RTSR1_RT12                     EXTI_RTSR1_RT12_Msk                     /*!< Rising trigger configuration for input line 12 */
4058 #define EXTI_RTSR1_RT13_Pos                 (13U)
4059 #define EXTI_RTSR1_RT13_Msk                 (0x1UL << EXTI_RTSR1_RT13_Pos)          /*!< 0x00002000 */
4060 #define EXTI_RTSR1_RT13                     EXTI_RTSR1_RT13_Msk                     /*!< Rising trigger configuration for input line 13 */
4061 #define EXTI_RTSR1_RT14_Pos                 (14U)
4062 #define EXTI_RTSR1_RT14_Msk                 (0x1UL << EXTI_RTSR1_RT14_Pos)          /*!< 0x00004000 */
4063 #define EXTI_RTSR1_RT14                     EXTI_RTSR1_RT14_Msk                     /*!< Rising trigger configuration for input line 14 */
4064 #define EXTI_RTSR1_RT15_Pos                 (15U)
4065 #define EXTI_RTSR1_RT15_Msk                 (0x1UL << EXTI_RTSR1_RT15_Pos)          /*!< 0x00008000 */
4066 #define EXTI_RTSR1_RT15                     EXTI_RTSR1_RT15_Msk                     /*!< Rising trigger configuration for input line 15 */
4067 #define EXTI_RTSR1_RT16_Pos                 (16U)
4068 #define EXTI_RTSR1_RT16_Msk                 (0x1UL << EXTI_RTSR1_RT16_Pos)          /*!< 0x00010000 */
4069 #define EXTI_RTSR1_RT16                     EXTI_RTSR1_RT16_Msk                     /*!< Rising trigger configuration for input line 16 */
4070 
4071 /******************  Bit definition for EXTI_FTSR1 register  ******************/
4072 #define EXTI_FTSR1_FT0_Pos                  (0U)
4073 #define EXTI_FTSR1_FT0_Msk                  (0x1UL << EXTI_FTSR1_FT0_Pos)           /*!< 0x00000001 */
4074 #define EXTI_FTSR1_FT0                      EXTI_FTSR1_FT0_Msk                      /*!< Falling trigger configuration for input line 0 */
4075 #define EXTI_FTSR1_FT1_Pos                  (1U)
4076 #define EXTI_FTSR1_FT1_Msk                  (0x1UL << EXTI_FTSR1_FT1_Pos)           /*!< 0x00000002 */
4077 #define EXTI_FTSR1_FT1                      EXTI_FTSR1_FT1_Msk                      /*!< Falling trigger configuration for input line 1 */
4078 #define EXTI_FTSR1_FT2_Pos                  (2U)
4079 #define EXTI_FTSR1_FT2_Msk                  (0x1UL << EXTI_FTSR1_FT2_Pos)           /*!< 0x00000004 */
4080 #define EXTI_FTSR1_FT2                      EXTI_FTSR1_FT2_Msk                      /*!< Falling trigger configuration for input line 2 */
4081 #define EXTI_FTSR1_FT3_Pos                  (3U)
4082 #define EXTI_FTSR1_FT3_Msk                  (0x1UL << EXTI_FTSR1_FT3_Pos)           /*!< 0x00000008 */
4083 #define EXTI_FTSR1_FT3                      EXTI_FTSR1_FT3_Msk                      /*!< Falling trigger configuration for input line 3 */
4084 #define EXTI_FTSR1_FT4_Pos                  (4U)
4085 #define EXTI_FTSR1_FT4_Msk                  (0x1UL << EXTI_FTSR1_FT4_Pos)           /*!< 0x00000010 */
4086 #define EXTI_FTSR1_FT4                      EXTI_FTSR1_FT4_Msk                      /*!< Falling trigger configuration for input line 4 */
4087 #define EXTI_FTSR1_FT5_Pos                  (5U)
4088 #define EXTI_FTSR1_FT5_Msk                  (0x1UL << EXTI_FTSR1_FT5_Pos)           /*!< 0x00000020 */
4089 #define EXTI_FTSR1_FT5                      EXTI_FTSR1_FT5_Msk                      /*!< Falling trigger configuration for input line 5 */
4090 #define EXTI_FTSR1_FT6_Pos                  (6U)
4091 #define EXTI_FTSR1_FT6_Msk                  (0x1UL << EXTI_FTSR1_FT6_Pos)           /*!< 0x00000040 */
4092 #define EXTI_FTSR1_FT6                      EXTI_FTSR1_FT6_Msk                      /*!< Falling trigger configuration for input line 6 */
4093 #define EXTI_FTSR1_FT7_Pos                  (7U)
4094 #define EXTI_FTSR1_FT7_Msk                  (0x1UL << EXTI_FTSR1_FT7_Pos)           /*!< 0x00000080 */
4095 #define EXTI_FTSR1_FT7                      EXTI_FTSR1_FT7_Msk                      /*!< Falling trigger configuration for input line 7 */
4096 #define EXTI_FTSR1_FT8_Pos                  (8U)
4097 #define EXTI_FTSR1_FT8_Msk                  (0x1UL << EXTI_FTSR1_FT8_Pos)           /*!< 0x00000100 */
4098 #define EXTI_FTSR1_FT8                      EXTI_FTSR1_FT8_Msk                      /*!< Falling trigger configuration for input line 8 */
4099 #define EXTI_FTSR1_FT9_Pos                  (9U)
4100 #define EXTI_FTSR1_FT9_Msk                  (0x1UL << EXTI_FTSR1_FT9_Pos)           /*!< 0x00000200 */
4101 #define EXTI_FTSR1_FT9                      EXTI_FTSR1_FT9_Msk                      /*!< Falling trigger configuration for input line 9 */
4102 #define EXTI_FTSR1_FT10_Pos                 (10U)
4103 #define EXTI_FTSR1_FT10_Msk                 (0x1UL << EXTI_FTSR1_FT10_Pos)          /*!< 0x00000400 */
4104 #define EXTI_FTSR1_FT10                     EXTI_FTSR1_FT10_Msk                     /*!< Falling trigger configuration for input line 10 */
4105 #define EXTI_FTSR1_FT11_Pos                 (11U)
4106 #define EXTI_FTSR1_FT11_Msk                 (0x1UL << EXTI_FTSR1_FT11_Pos)          /*!< 0x00000800 */
4107 #define EXTI_FTSR1_FT11                     EXTI_FTSR1_FT11_Msk                     /*!< Falling trigger configuration for input line 11 */
4108 #define EXTI_FTSR1_FT12_Pos                 (12U)
4109 #define EXTI_FTSR1_FT12_Msk                 (0x1UL << EXTI_FTSR1_FT12_Pos)          /*!< 0x00001000 */
4110 #define EXTI_FTSR1_FT12                     EXTI_FTSR1_FT12_Msk                     /*!< Falling trigger configuration for input line 12 */
4111 #define EXTI_FTSR1_FT13_Pos                 (13U)
4112 #define EXTI_FTSR1_FT13_Msk                 (0x1UL << EXTI_FTSR1_FT13_Pos)          /*!< 0x00002000 */
4113 #define EXTI_FTSR1_FT13                     EXTI_FTSR1_FT13_Msk                     /*!< Falling trigger configuration for input line 13 */
4114 #define EXTI_FTSR1_FT14_Pos                 (14U)
4115 #define EXTI_FTSR1_FT14_Msk                 (0x1UL << EXTI_FTSR1_FT14_Pos)          /*!< 0x00004000 */
4116 #define EXTI_FTSR1_FT14                     EXTI_FTSR1_FT14_Msk                     /*!< Falling trigger configuration for input line 14 */
4117 #define EXTI_FTSR1_FT15_Pos                 (15U)
4118 #define EXTI_FTSR1_FT15_Msk                 (0x1UL << EXTI_FTSR1_FT15_Pos)          /*!< 0x00008000 */
4119 #define EXTI_FTSR1_FT15                     EXTI_FTSR1_FT15_Msk                     /*!< Falling trigger configuration for input line 15 */
4120 #define EXTI_FTSR1_FT16_Pos                 (16U)
4121 #define EXTI_FTSR1_FT16_Msk                 (0x1UL << EXTI_FTSR1_FT16_Pos)          /*!< 0x00010000 */
4122 #define EXTI_FTSR1_FT16                     EXTI_FTSR1_FT16_Msk                     /*!< Falling trigger configuration for input line 16 */
4123 
4124 /******************  Bit definition for EXTI_SWIER1 register  *****************/
4125 #define EXTI_SWIER1_SWI0_Pos                (0U)
4126 #define EXTI_SWIER1_SWI0_Msk                (0x1UL << EXTI_SWIER1_SWI0_Pos)         /*!< 0x00000001 */
4127 #define EXTI_SWIER1_SWI0                    EXTI_SWIER1_SWI0_Msk                    /*!< Software Interrupt on line 0 */
4128 #define EXTI_SWIER1_SWI1_Pos                (1U)
4129 #define EXTI_SWIER1_SWI1_Msk                (0x1UL << EXTI_SWIER1_SWI1_Pos)         /*!< 0x00000002 */
4130 #define EXTI_SWIER1_SWI1                    EXTI_SWIER1_SWI1_Msk                    /*!< Software Interrupt on line 1 */
4131 #define EXTI_SWIER1_SWI2_Pos                (2U)
4132 #define EXTI_SWIER1_SWI2_Msk                (0x1UL << EXTI_SWIER1_SWI2_Pos)         /*!< 0x00000004 */
4133 #define EXTI_SWIER1_SWI2                    EXTI_SWIER1_SWI2_Msk                    /*!< Software Interrupt on line 2 */
4134 #define EXTI_SWIER1_SWI3_Pos                (3U)
4135 #define EXTI_SWIER1_SWI3_Msk                (0x1UL << EXTI_SWIER1_SWI3_Pos)         /*!< 0x00000008 */
4136 #define EXTI_SWIER1_SWI3                    EXTI_SWIER1_SWI3_Msk                    /*!< Software Interrupt on line 3 */
4137 #define EXTI_SWIER1_SWI4_Pos                (4U)
4138 #define EXTI_SWIER1_SWI4_Msk                (0x1UL << EXTI_SWIER1_SWI4_Pos)         /*!< 0x00000010 */
4139 #define EXTI_SWIER1_SWI4                    EXTI_SWIER1_SWI4_Msk                    /*!< Software Interrupt on line 4 */
4140 #define EXTI_SWIER1_SWI5_Pos                (5U)
4141 #define EXTI_SWIER1_SWI5_Msk                (0x1UL << EXTI_SWIER1_SWI5_Pos)         /*!< 0x00000020 */
4142 #define EXTI_SWIER1_SWI5                    EXTI_SWIER1_SWI5_Msk                    /*!< Software Interrupt on line 5 */
4143 #define EXTI_SWIER1_SWI6_Pos                (6U)
4144 #define EXTI_SWIER1_SWI6_Msk                (0x1UL << EXTI_SWIER1_SWI6_Pos)         /*!< 0x00000040 */
4145 #define EXTI_SWIER1_SWI6                    EXTI_SWIER1_SWI6_Msk                    /*!< Software Interrupt on line 6 */
4146 #define EXTI_SWIER1_SWI7_Pos                (7U)
4147 #define EXTI_SWIER1_SWI7_Msk                (0x1UL << EXTI_SWIER1_SWI7_Pos)         /*!< 0x00000080 */
4148 #define EXTI_SWIER1_SWI7                    EXTI_SWIER1_SWI7_Msk                    /*!< Software Interrupt on line 7 */
4149 #define EXTI_SWIER1_SWI8_Pos                (8U)
4150 #define EXTI_SWIER1_SWI8_Msk                (0x1UL << EXTI_SWIER1_SWI8_Pos)         /*!< 0x00000100 */
4151 #define EXTI_SWIER1_SWI8                    EXTI_SWIER1_SWI8_Msk                    /*!< Software Interrupt on line 8 */
4152 #define EXTI_SWIER1_SWI9_Pos                (9U)
4153 #define EXTI_SWIER1_SWI9_Msk                (0x1UL << EXTI_SWIER1_SWI9_Pos)         /*!< 0x00000200 */
4154 #define EXTI_SWIER1_SWI9                    EXTI_SWIER1_SWI9_Msk                    /*!< Software Interrupt on line 9 */
4155 #define EXTI_SWIER1_SWI10_Pos               (10U)
4156 #define EXTI_SWIER1_SWI10_Msk               (0x1UL << EXTI_SWIER1_SWI10_Pos)        /*!< 0x00000400 */
4157 #define EXTI_SWIER1_SWI10                   EXTI_SWIER1_SWI10_Msk                   /*!< Software Interrupt on line 10 */
4158 #define EXTI_SWIER1_SWI11_Pos               (11U)
4159 #define EXTI_SWIER1_SWI11_Msk               (0x1UL << EXTI_SWIER1_SWI11_Pos)        /*!< 0x00000800 */
4160 #define EXTI_SWIER1_SWI11                   EXTI_SWIER1_SWI11_Msk                   /*!< Software Interrupt on line 11 */
4161 #define EXTI_SWIER1_SWI12_Pos               (12U)
4162 #define EXTI_SWIER1_SWI12_Msk               (0x1UL << EXTI_SWIER1_SWI12_Pos)        /*!< 0x00001000 */
4163 #define EXTI_SWIER1_SWI12                   EXTI_SWIER1_SWI12_Msk                   /*!< Software Interrupt on line 12 */
4164 #define EXTI_SWIER1_SWI13_Pos               (13U)
4165 #define EXTI_SWIER1_SWI13_Msk               (0x1UL << EXTI_SWIER1_SWI13_Pos)        /*!< 0x00002000 */
4166 #define EXTI_SWIER1_SWI13                   EXTI_SWIER1_SWI13_Msk                   /*!< Software Interrupt on line 13 */
4167 #define EXTI_SWIER1_SWI14_Pos               (14U)
4168 #define EXTI_SWIER1_SWI14_Msk               (0x1UL << EXTI_SWIER1_SWI14_Pos)        /*!< 0x00004000 */
4169 #define EXTI_SWIER1_SWI14                   EXTI_SWIER1_SWI14_Msk                   /*!< Software Interrupt on line 14 */
4170 #define EXTI_SWIER1_SWI15_Pos               (15U)
4171 #define EXTI_SWIER1_SWI15_Msk               (0x1UL << EXTI_SWIER1_SWI15_Pos)        /*!< 0x00008000 */
4172 #define EXTI_SWIER1_SWI15                   EXTI_SWIER1_SWI15_Msk                   /*!< Software Interrupt on line 15 */
4173 #define EXTI_SWIER1_SWI16_Pos               (16U)
4174 #define EXTI_SWIER1_SWI16_Msk               (0x1UL << EXTI_SWIER1_SWI16_Pos)        /*!< 0x00010000 */
4175 #define EXTI_SWIER1_SWI16                   EXTI_SWIER1_SWI16_Msk                   /*!< Software Interrupt on line 16 */
4176 
4177 
4178 /*******************  Bit definition for EXTI_RPR1 register  ******************/
4179 #define EXTI_RPR1_RPIF0_Pos                 (0U)
4180 #define EXTI_RPR1_RPIF0_Msk                 (0x1UL << EXTI_RPR1_RPIF0_Pos)          /*!< 0x00000001 */
4181 #define EXTI_RPR1_RPIF0                     EXTI_RPR1_RPIF0_Msk                     /*!< Rising Pending Interrupt Flag on line 0 */
4182 #define EXTI_RPR1_RPIF1_Pos                 (1U)
4183 #define EXTI_RPR1_RPIF1_Msk                 (0x1UL << EXTI_RPR1_RPIF1_Pos)          /*!< 0x00000002 */
4184 #define EXTI_RPR1_RPIF1                     EXTI_RPR1_RPIF1_Msk                     /*!< Rising Pending Interrupt Flag on line 1 */
4185 #define EXTI_RPR1_RPIF2_Pos                 (2U)
4186 #define EXTI_RPR1_RPIF2_Msk                 (0x1UL << EXTI_RPR1_RPIF2_Pos)          /*!< 0x00000004 */
4187 #define EXTI_RPR1_RPIF2                     EXTI_RPR1_RPIF2_Msk                     /*!< Rising Pending Interrupt Flag on line 2 */
4188 #define EXTI_RPR1_RPIF3_Pos                 (3U)
4189 #define EXTI_RPR1_RPIF3_Msk                 (0x1UL << EXTI_RPR1_RPIF3_Pos)          /*!< 0x00000008 */
4190 #define EXTI_RPR1_RPIF3                     EXTI_RPR1_RPIF3_Msk                     /*!< Rising Pending Interrupt Flag on line 3 */
4191 #define EXTI_RPR1_RPIF4_Pos                 (4U)
4192 #define EXTI_RPR1_RPIF4_Msk                 (0x1UL << EXTI_RPR1_RPIF4_Pos)          /*!< 0x00000010 */
4193 #define EXTI_RPR1_RPIF4                     EXTI_RPR1_RPIF4_Msk                     /*!< Rising Pending Interrupt Flag on line 4 */
4194 #define EXTI_RPR1_RPIF5_Pos                 (5U)
4195 #define EXTI_RPR1_RPIF5_Msk                 (0x1UL << EXTI_RPR1_RPIF5_Pos)          /*!< 0x00000020 */
4196 #define EXTI_RPR1_RPIF5                     EXTI_RPR1_RPIF5_Msk                     /*!< Rising Pending Interrupt Flag on line 5 */
4197 #define EXTI_RPR1_RPIF6_Pos                 (6U)
4198 #define EXTI_RPR1_RPIF6_Msk                 (0x1UL << EXTI_RPR1_RPIF6_Pos)          /*!< 0x00000040 */
4199 #define EXTI_RPR1_RPIF6                     EXTI_RPR1_RPIF6_Msk                     /*!< Rising Pending Interrupt Flag on line 6 */
4200 #define EXTI_RPR1_RPIF7_Pos                 (7U)
4201 #define EXTI_RPR1_RPIF7_Msk                 (0x1UL << EXTI_RPR1_RPIF7_Pos)          /*!< 0x00000080 */
4202 #define EXTI_RPR1_RPIF7                     EXTI_RPR1_RPIF7_Msk                     /*!< Rising Pending Interrupt Flag on line 7 */
4203 #define EXTI_RPR1_RPIF8_Pos                 (8U)
4204 #define EXTI_RPR1_RPIF8_Msk                 (0x1UL << EXTI_RPR1_RPIF8_Pos)          /*!< 0x00000100 */
4205 #define EXTI_RPR1_RPIF8                     EXTI_RPR1_RPIF8_Msk                     /*!< Rising Pending Interrupt Flag on line 8 */
4206 #define EXTI_RPR1_RPIF9_Pos                 (9U)
4207 #define EXTI_RPR1_RPIF9_Msk                 (0x1UL << EXTI_RPR1_RPIF9_Pos)          /*!< 0x00000200 */
4208 #define EXTI_RPR1_RPIF9                     EXTI_RPR1_RPIF9_Msk                     /*!< Rising Pending Interrupt Flag on line 9 */
4209 #define EXTI_RPR1_RPIF10_Pos                (10U)
4210 #define EXTI_RPR1_RPIF10_Msk                (0x1UL << EXTI_RPR1_RPIF10_Pos)         /*!< 0x00000400 */
4211 #define EXTI_RPR1_RPIF10                    EXTI_RPR1_RPIF10_Msk                    /*!< Rising Pending Interrupt Flag on line 10 */
4212 #define EXTI_RPR1_RPIF11_Pos                (11U)
4213 #define EXTI_RPR1_RPIF11_Msk                (0x1UL << EXTI_RPR1_RPIF11_Pos)         /*!< 0x00000800 */
4214 #define EXTI_RPR1_RPIF11                    EXTI_RPR1_RPIF11_Msk                    /*!< Rising Pending Interrupt Flag on line 11 */
4215 #define EXTI_RPR1_RPIF12_Pos                (12U)
4216 #define EXTI_RPR1_RPIF12_Msk                (0x1UL << EXTI_RPR1_RPIF12_Pos)         /*!< 0x00001000 */
4217 #define EXTI_RPR1_RPIF12                    EXTI_RPR1_RPIF12_Msk                    /*!< Rising Pending Interrupt Flag on line 12 */
4218 #define EXTI_RPR1_RPIF13_Pos                (13U)
4219 #define EXTI_RPR1_RPIF13_Msk                (0x1UL << EXTI_RPR1_RPIF13_Pos)         /*!< 0x00002000 */
4220 #define EXTI_RPR1_RPIF13                    EXTI_RPR1_RPIF13_Msk                    /*!< Rising Pending Interrupt Flag on line 13 */
4221 #define EXTI_RPR1_RPIF14_Pos                (14U)
4222 #define EXTI_RPR1_RPIF14_Msk                (0x1UL << EXTI_RPR1_RPIF14_Pos)         /*!< 0x00004000 */
4223 #define EXTI_RPR1_RPIF14                    EXTI_RPR1_RPIF14_Msk                    /*!< Rising Pending Interrupt Flag on line 14 */
4224 #define EXTI_RPR1_RPIF15_Pos                (15U)
4225 #define EXTI_RPR1_RPIF15_Msk                (0x1UL << EXTI_RPR1_RPIF15_Pos)         /*!< 0x00008000 */
4226 #define EXTI_RPR1_RPIF15                    EXTI_RPR1_RPIF15_Msk                    /*!< Rising Pending Interrupt Flag on line 15 */
4227 #define EXTI_RPR1_RPIF16_Pos                (16U)
4228 #define EXTI_RPR1_RPIF16_Msk                (0x1UL << EXTI_RPR1_RPIF16_Pos)         /*!< 0x00010000 */
4229 #define EXTI_RPR1_RPIF16                    EXTI_RPR1_RPIF16_Msk                    /*!< Rising Pending Interrupt Flag on line 16 */
4230 
4231 /*******************  Bit definition for EXTI_FPR1 register  ******************/
4232 #define EXTI_FPR1_FPIF0_Pos                 (0U)
4233 #define EXTI_FPR1_FPIF0_Msk                 (0x1UL << EXTI_FPR1_FPIF0_Pos)          /*!< 0x00000001 */
4234 #define EXTI_FPR1_FPIF0                     EXTI_FPR1_FPIF0_Msk                     /*!< Falling Pending Interrupt Flag on line 0 */
4235 #define EXTI_FPR1_FPIF1_Pos                 (1U)
4236 #define EXTI_FPR1_FPIF1_Msk                 (0x1UL << EXTI_FPR1_FPIF1_Pos)          /*!< 0x00000002 */
4237 #define EXTI_FPR1_FPIF1                     EXTI_FPR1_FPIF1_Msk                     /*!< Falling Pending Interrupt Flag on line 1 */
4238 #define EXTI_FPR1_FPIF2_Pos                 (2U)
4239 #define EXTI_FPR1_FPIF2_Msk                 (0x1UL << EXTI_FPR1_FPIF2_Pos)          /*!< 0x00000004 */
4240 #define EXTI_FPR1_FPIF2                     EXTI_FPR1_FPIF2_Msk                     /*!< Falling Pending Interrupt Flag on line 2 */
4241 #define EXTI_FPR1_FPIF3_Pos                 (3U)
4242 #define EXTI_FPR1_FPIF3_Msk                 (0x1UL << EXTI_FPR1_FPIF3_Pos)          /*!< 0x00000008 */
4243 #define EXTI_FPR1_FPIF3                     EXTI_FPR1_FPIF3_Msk                     /*!< Falling Pending Interrupt Flag on line 3 */
4244 #define EXTI_FPR1_FPIF4_Pos                 (4U)
4245 #define EXTI_FPR1_FPIF4_Msk                 (0x1UL << EXTI_FPR1_FPIF4_Pos)          /*!< 0x00000010 */
4246 #define EXTI_FPR1_FPIF4                     EXTI_FPR1_FPIF4_Msk                     /*!< Falling Pending Interrupt Flag on line 4 */
4247 #define EXTI_FPR1_FPIF5_Pos                 (5U)
4248 #define EXTI_FPR1_FPIF5_Msk                 (0x1UL << EXTI_FPR1_FPIF5_Pos)          /*!< 0x00000020 */
4249 #define EXTI_FPR1_FPIF5                     EXTI_FPR1_FPIF5_Msk                     /*!< Falling Pending Interrupt Flag on line 5 */
4250 #define EXTI_FPR1_FPIF6_Pos                 (6U)
4251 #define EXTI_FPR1_FPIF6_Msk                 (0x1UL << EXTI_FPR1_FPIF6_Pos)          /*!< 0x00000040 */
4252 #define EXTI_FPR1_FPIF6                     EXTI_FPR1_FPIF6_Msk                     /*!< Falling Pending Interrupt Flag on line 6 */
4253 #define EXTI_FPR1_FPIF7_Pos                 (7U)
4254 #define EXTI_FPR1_FPIF7_Msk                 (0x1UL << EXTI_FPR1_FPIF7_Pos)          /*!< 0x00000080 */
4255 #define EXTI_FPR1_FPIF7                     EXTI_FPR1_FPIF7_Msk                     /*!< Falling Pending Interrupt Flag on line 7 */
4256 #define EXTI_FPR1_FPIF8_Pos                 (8U)
4257 #define EXTI_FPR1_FPIF8_Msk                 (0x1UL << EXTI_FPR1_FPIF8_Pos)          /*!< 0x00000100 */
4258 #define EXTI_FPR1_FPIF8                     EXTI_FPR1_FPIF8_Msk                     /*!< Falling Pending Interrupt Flag on line 8 */
4259 #define EXTI_FPR1_FPIF9_Pos                 (9U)
4260 #define EXTI_FPR1_FPIF9_Msk                 (0x1UL << EXTI_FPR1_FPIF9_Pos)          /*!< 0x00000200 */
4261 #define EXTI_FPR1_FPIF9                     EXTI_FPR1_FPIF9_Msk                     /*!< Falling Pending Interrupt Flag on line 9 */
4262 #define EXTI_FPR1_FPIF10_Pos                (10U)
4263 #define EXTI_FPR1_FPIF10_Msk                (0x1UL << EXTI_FPR1_FPIF10_Pos)         /*!< 0x00000400 */
4264 #define EXTI_FPR1_FPIF10                    EXTI_FPR1_FPIF10_Msk                    /*!< Falling Pending Interrupt Flag on line 10 */
4265 #define EXTI_FPR1_FPIF11_Pos                (11U)
4266 #define EXTI_FPR1_FPIF11_Msk                (0x1UL << EXTI_FPR1_FPIF11_Pos)         /*!< 0x00000800 */
4267 #define EXTI_FPR1_FPIF11                    EXTI_FPR1_FPIF11_Msk                    /*!< Falling Pending Interrupt Flag on line 11 */
4268 #define EXTI_FPR1_FPIF12_Pos                (12U)
4269 #define EXTI_FPR1_FPIF12_Msk                (0x1UL << EXTI_FPR1_FPIF12_Pos)         /*!< 0x00001000 */
4270 #define EXTI_FPR1_FPIF12                    EXTI_FPR1_FPIF12_Msk                    /*!< Falling Pending Interrupt Flag on line 12 */
4271 #define EXTI_FPR1_FPIF13_Pos                (13U)
4272 #define EXTI_FPR1_FPIF13_Msk                (0x1UL << EXTI_FPR1_FPIF13_Pos)         /*!< 0x00002000 */
4273 #define EXTI_FPR1_FPIF13                    EXTI_FPR1_FPIF13_Msk                    /*!< Falling Pending Interrupt Flag on line 13 */
4274 #define EXTI_FPR1_FPIF14_Pos                (14U)
4275 #define EXTI_FPR1_FPIF14_Msk                (0x1UL << EXTI_FPR1_FPIF14_Pos)         /*!< 0x00004000 */
4276 #define EXTI_FPR1_FPIF14                    EXTI_FPR1_FPIF14_Msk                    /*!< Falling Pending Interrupt Flag on line 14 */
4277 #define EXTI_FPR1_FPIF15_Pos                (15U)
4278 #define EXTI_FPR1_FPIF15_Msk                (0x1UL << EXTI_FPR1_FPIF15_Pos)         /*!< 0x00008000 */
4279 #define EXTI_FPR1_FPIF15                    EXTI_FPR1_FPIF15_Msk                    /*!< Falling Pending Interrupt Flag on line 15 */
4280 #define EXTI_FPR1_FPIF16_Pos                (16U)
4281 #define EXTI_FPR1_FPIF16_Msk                (0x1UL << EXTI_FPR1_FPIF16_Pos)         /*!< 0x00010000 */
4282 #define EXTI_FPR1_FPIF16                    EXTI_FPR1_FPIF16_Msk                    /*!< Falling Pending Interrupt Flag on line 16 */
4283 
4284 
4285 /*******************  Bit definition for EXTI_PRIVENR1 register  ******************/
4286 #define EXTI_PRIVENR1_PRIV0_Pos             (0U)
4287 #define EXTI_PRIVENR1_PRIV0_Msk             (0x1UL << EXTI_PRIVENR1_PRIV0_Pos)      /*!< 0x00000001 */
4288 #define EXTI_PRIVENR1_PRIV0                 EXTI_PRIVENR1_PRIV0_Msk                 /*!< Privilege enable on line 0 */
4289 #define EXTI_PRIVENR1_PRIV1_Pos             (1U)
4290 #define EXTI_PRIVENR1_PRIV1_Msk             (0x1UL << EXTI_PRIVENR1_PRIV1_Pos)      /*!< 0x00000002 */
4291 #define EXTI_PRIVENR1_PRIV1                 EXTI_PRIVENR1_PRIV1_Msk                 /*!< Privilege enable on line 1 */
4292 #define EXTI_PRIVENR1_PRIV2_Pos             (2U)
4293 #define EXTI_PRIVENR1_PRIV2_Msk             (0x1UL << EXTI_PRIVENR1_PRIV2_Pos)      /*!< 0x00000004 */
4294 #define EXTI_PRIVENR1_PRIV2                 EXTI_PRIVENR1_PRIV2_Msk                 /*!< Privilege enable on line 2 */
4295 #define EXTI_PRIVENR1_PRIV3_Pos             (3U)
4296 #define EXTI_PRIVENR1_PRIV3_Msk             (0x1UL << EXTI_PRIVENR1_PRIV3_Pos)      /*!< 0x00000008 */
4297 #define EXTI_PRIVENR1_PRIV3                 EXTI_PRIVENR1_PRIV3_Msk                 /*!< Privilege enable on line 3 */
4298 #define EXTI_PRIVENR1_PRIV4_Pos             (4U)
4299 #define EXTI_PRIVENR1_PRIV4_Msk             (0x1UL << EXTI_PRIVENR1_PRIV4_Pos)      /*!< 0x00000010 */
4300 #define EXTI_PRIVENR1_PRIV4                 EXTI_PRIVENR1_PRIV4_Msk                 /*!< Privilege enable on line 4 */
4301 #define EXTI_PRIVENR1_PRIV5_Pos             (5U)
4302 #define EXTI_PRIVENR1_PRIV5_Msk             (0x1UL << EXTI_PRIVENR1_PRIV5_Pos)      /*!< 0x00000020 */
4303 #define EXTI_PRIVENR1_PRIV5                 EXTI_PRIVENR1_PRIV5_Msk                 /*!< Privilege enable on line 5 */
4304 #define EXTI_PRIVENR1_PRIV6_Pos             (6U)
4305 #define EXTI_PRIVENR1_PRIV6_Msk             (0x1UL << EXTI_PRIVENR1_PRIV6_Pos)      /*!< 0x00000040 */
4306 #define EXTI_PRIVENR1_PRIV6                 EXTI_PRIVENR1_PRIV6_Msk                 /*!< Privilege enable on line 6 */
4307 #define EXTI_PRIVENR1_PRIV7_Pos             (7U)
4308 #define EXTI_PRIVENR1_PRIV7_Msk             (0x1UL << EXTI_PRIVENR1_PRIV7_Pos)      /*!< 0x00000080 */
4309 #define EXTI_PRIVENR1_PRIV7                 EXTI_PRIVENR1_PRIV7_Msk                 /*!< Privilege enable on line 7 */
4310 #define EXTI_PRIVENR1_PRIV8_Pos             (8U)
4311 #define EXTI_PRIVENR1_PRIV8_Msk             (0x1UL << EXTI_PRIVENR1_PRIV8_Pos)      /*!< 0x00000100 */
4312 #define EXTI_PRIVENR1_PRIV8                 EXTI_PRIVENR1_PRIV8_Msk                 /*!< Privilege enable on line 8 */
4313 #define EXTI_PRIVENR1_PRIV9_Pos             (9U)
4314 #define EXTI_PRIVENR1_PRIV9_Msk             (0x1UL << EXTI_PRIVENR1_PRIV9_Pos)      /*!< 0x00000200 */
4315 #define EXTI_PRIVENR1_PRIV9                 EXTI_PRIVENR1_PRIV9_Msk                 /*!< Privilege enable on line 9 */
4316 #define EXTI_PRIVENR1_PRIV10_Pos            (10U)
4317 #define EXTI_PRIVENR1_PRIV10_Msk            (0x1UL << EXTI_PRIVENR1_PRIV10_Pos)     /*!< 0x00000400 */
4318 #define EXTI_PRIVENR1_PRIV10                EXTI_PRIVENR1_PRIV10_Msk                /*!< Privilege enable on line 10 */
4319 #define EXTI_PRIVENR1_PRIV11_Pos            (11U)
4320 #define EXTI_PRIVENR1_PRIV11_Msk            (0x1UL << EXTI_PRIVENR1_PRIV11_Pos)     /*!< 0x00000800 */
4321 #define EXTI_PRIVENR1_PRIV11                EXTI_PRIVENR1_PRIV11_Msk                /*!< Privilege enable on line 11 */
4322 #define EXTI_PRIVENR1_PRIV12_Pos            (12U)
4323 #define EXTI_PRIVENR1_PRIV12_Msk            (0x1UL << EXTI_PRIVENR1_PRIV12_Pos)     /*!< 0x00001000 */
4324 #define EXTI_PRIVENR1_PRIV12                EXTI_PRIVENR1_PRIV12_Msk                /*!< Privilege enable on line 12 */
4325 #define EXTI_PRIVENR1_PRIV13_Pos            (13U)
4326 #define EXTI_PRIVENR1_PRIV13_Msk            (0x1UL << EXTI_PRIVENR1_PRIV13_Pos)     /*!< 0x00002000 */
4327 #define EXTI_PRIVENR1_PRIV13                EXTI_PRIVENR1_PRIV13_Msk                /*!< Privilege enable on line 13 */
4328 #define EXTI_PRIVENR1_PRIV14_Pos            (14U)
4329 #define EXTI_PRIVENR1_PRIV14_Msk            (0x1UL << EXTI_PRIVENR1_PRIV14_Pos)     /*!< 0x00004000 */
4330 #define EXTI_PRIVENR1_PRIV14                EXTI_PRIVENR1_PRIV14_Msk                /*!< Privilege enable on line 14 */
4331 #define EXTI_PRIVENR1_PRIV15_Pos            (15U)
4332 #define EXTI_PRIVENR1_PRIV15_Msk            (0x1UL << EXTI_PRIVENR1_PRIV15_Pos)     /*!< 0x00008000 */
4333 #define EXTI_PRIVENR1_PRIV15                EXTI_PRIVENR1_PRIV15_Msk                /*!< Privilege enable on line 15 */
4334 #define EXTI_PRIVENR1_PRIV16_Pos            (16U)
4335 #define EXTI_PRIVENR1_PRIV16_Msk            (0x1UL << EXTI_PRIVENR1_PRIV16_Pos)     /*!< 0x00010000 */
4336 #define EXTI_PRIVENR1_PRIV16                EXTI_PRIVENR1_PRIV16_Msk                /*!< Privilege enable on line 16 */
4337 #define EXTI_PRIVENR1_PRIV17_Pos            (17U)
4338 #define EXTI_PRIVENR1_PRIV17_Msk            (0x1UL << EXTI_PRIVENR1_PRIV17_Pos)     /*!< 0x00020000 */
4339 #define EXTI_PRIVENR1_PRIV17                EXTI_PRIVENR1_PRIV17_Msk                /*!< Privilege enable on line 17 */
4340 #define EXTI_PRIVENR1_PRIV19_Pos            (19U)
4341 #define EXTI_PRIVENR1_PRIV19_Msk            (0x1UL << EXTI_PRIVENR1_PRIV19_Pos)     /*!< 0x00080000 */
4342 #define EXTI_PRIVENR1_PRIV19                EXTI_PRIVENR1_PRIV19_Msk                /*!< Privilege enable on line 19 */
4343 #define EXTI_PRIVENR1_PRIV21_Pos            (21U)
4344 #define EXTI_PRIVENR1_PRIV21_Msk            (0x1UL << EXTI_PRIVENR1_PRIV21_Pos)     /*!< 0x00200000 */
4345 #define EXTI_PRIVENR1_PRIV21                EXTI_PRIVENR1_PRIV21_Msk                /*!< Privilege enable on line 21 */
4346 #define EXTI_PRIVENR1_PRIV22_Pos            (22U)
4347 #define EXTI_PRIVENR1_PRIV22_Msk            (0x1UL << EXTI_PRIVENR1_PRIV22_Pos)     /*!< 0x00400000 */
4348 #define EXTI_PRIVENR1_PRIV22                EXTI_PRIVENR1_PRIV22_Msk                /*!< Privilege enable on line 22 */
4349 #define EXTI_PRIVENR1_PRIV24_Pos            (24U)
4350 #define EXTI_PRIVENR1_PRIV24_Msk            (0x1UL << EXTI_PRIVENR1_PRIV24_Pos)     /*!< 0x01000000 */
4351 #define EXTI_PRIVENR1_PRIV24                EXTI_PRIVENR1_PRIV24_Msk                /*!< Privilege enable on line 24 */
4352 #define EXTI_PRIVENR1_PRIV25_Pos            (25U)
4353 #define EXTI_PRIVENR1_PRIV25_Msk            (0x1UL << EXTI_PRIVENR1_PRIV25_Pos)      /*!< 0x02000000 */
4354 #define EXTI_PRIVENR1_PRIV25                EXTI_PRIVENR1_PRIV25_Msk                 /*!< Privilege enable on line 25 */
4355 #define EXTI_PRIVENR1_PRIV26_Pos            (26U)
4356 #define EXTI_PRIVENR1_PRIV26_Msk            (0x1UL << EXTI_PRIVENR1_PRIV26_Pos)      /*!< 0x04000000 */
4357 #define EXTI_PRIVENR1_PRIV26                EXTI_PRIVENR1_PRIV26_Msk                 /*!< Privilege enable on line 26 */
4358 #define EXTI_PRIVENR1_PRIV27_Pos            (27U)
4359 #define EXTI_PRIVENR1_PRIV27_Msk            (0x1UL << EXTI_PRIVENR1_PRIV27_Pos)      /*!< 0x08000000 */
4360 #define EXTI_PRIVENR1_PRIV27                EXTI_PRIVENR1_PRIV27_Msk                 /*!< Privilege enable on line 27 */
4361 #define EXTI_PRIVENR1_PRIV28_Pos            (28U)
4362 #define EXTI_PRIVENR1_PRIV28_Msk            (0x1UL << EXTI_PRIVENR1_PRIV28_Pos)      /*!< 0x10000000 */
4363 #define EXTI_PRIVENR1_PRIV28                EXTI_PRIVENR1_PRIV28_Msk                 /*!< Privilege enable on line 28 */
4364 #define EXTI_PRIVENR1_PRIV29_Pos            (29U)
4365 #define EXTI_PRIVENR1_PRIV29_Msk            (0x1UL << EXTI_PRIVENR1_PRIV29_Pos)      /*!< 0x20000000 */
4366 #define EXTI_PRIVENR1_PRIV29                EXTI_PRIVENR1_PRIV29_Msk                 /*!< Privilege enable on line 29 */
4367 
4368 /******************  Bit definition for EXTI_RTSR2 register  *******************/
4369 #define EXTI_RTSR2_RT_Pos                   (16U)
4370 #define EXTI_RTSR2_RT_Msk                   (0x24UL << EXTI_RTSR2_RT_Pos)               /*!< 0x00240000 */
4371 #define EXTI_RTSR2_RT                       EXTI_RTSR2_RT_Msk                           /*!< Rising trigger event configuration bit */
4372 #define EXTI_RTSR2_RT50_Pos                 (18U)
4373 #define EXTI_RTSR2_RT50_Msk                 (0x1UL << EXTI_RTSR2_RT50_Pos)              /*!< 0x00040000 */
4374 #define EXTI_RTSR2_RT50                     EXTI_RTSR2_RT50_Msk                         /*!< Rising trigger event configuration bit of line 50 */
4375 #define EXTI_RTSR2_RT53_Pos                 (21U)
4376 #define EXTI_RTSR2_RT53_Msk                 (0x1UL << EXTI_RTSR2_RT53_Pos)              /*!< 0x00200000 */
4377 #define EXTI_RTSR2_RT53                     EXTI_RTSR2_RT53_Msk                         /*!< Rising trigger event configuration bit of line 53 */
4378 
4379 /******************  Bit definition for EXTI_FTSR2 register  *******************/
4380 #define EXTI_FTSR2_FT_Pos                   (16U)
4381 #define EXTI_FTSR2_FT_Msk                   (0x24 << EXTI_FTSR2_FT_Pos)                 /*!< 0x00240000 */
4382 #define EXTI_FTSR2_FT                       EXTI_FTSR2_FT_Msk                           /*!< Falling trigger event configuration bit */
4383 #define EXTI_FTSR2_FT50_Pos                 (18U)
4384 #define EXTI_FTSR2_FT50_Msk                 (0x1UL << EXTI_FTSR2_FT50_Pos)              /*!< 0x00040000 */
4385 #define EXTI_FTSR2_FT50                     EXTI_FTSR2_FT50_Msk                         /*!< Falling trigger event configuration bit of line 50 */
4386 #define EXTI_FTSR2_FT53_Pos                 (21U)
4387 #define EXTI_FTSR2_FT53_Msk                 (0x1UL << EXTI_FTSR2_FT53_Pos)              /*!< 0x00200000 */
4388 #define EXTI_FTSR2_FT53                     EXTI_FTSR2_FT53_Msk                         /*!< Falling trigger event configuration bit of line 53 */
4389 
4390 /******************  Bit definition for EXTI_SWIER2 register  ******************/
4391 #define EXTI_SWIER2_SWIER50_Pos            (18U)
4392 #define EXTI_SWIER2_SWIER50_Msk            (0x1UL << EXTI_SWIER2_SWIER50_Pos)          /*!< 0x00040000 */
4393 #define EXTI_SWIER2_SWIER50                EXTI_SWIER2_SWIER50_Msk                     /*!< Software Interrupt on line 50 */
4394 #define EXTI_SWIER2_SWIER53_Pos            (21U)
4395 #define EXTI_SWIER2_SWIER53_Msk            (0x1UL << EXTI_SWIER2_SWIER53_Pos)          /*!< 0x00200000 */
4396 #define EXTI_SWIER2_SWIER53                EXTI_SWIER2_SWIER53_Msk                     /*!< Software Interrupt on line 53 */
4397 
4398 /******************  Bit definition for EXTI_RPR2 register  *******************/
4399 #define EXTI_RPR2_RPIF_Pos                   (16U)
4400 #define EXTI_RPR2_RPIF_Msk                   (0x24UL << EXTI_RPR2_RPIF_Pos)         /*!< 0x00240000 */
4401 #define EXTI_RPR2_RPIF                       EXTI_RPR2_RPIF_Msk                     /*!< Rising pending edge configuration bits */
4402 #define EXTI_RPR2_RPIF50_Pos                 (18U)
4403 #define EXTI_RPR2_RPIF50_Msk                 (0x1UL << EXTI_RPR2_RPIF50_Pos)        /*!< 0x00040000 */
4404 #define EXTI_RPR2_RPIF50                     EXTI_RPR2_RPIF50_Msk                   /*!< Rising pending edge configuration bit of line 50 */
4405 #define EXTI_RPR2_RPIF53_Pos                 (21U)
4406 #define EXTI_RPR2_RPIF53_Msk                 (0x1UL << EXTI_RPR2_RPIF53_Pos)        /*!< 0x00200000 */
4407 #define EXTI_RPR2_RPIF53                     EXTI_RPR2_RPIF53_Msk                   /*!< Rising pending edge configuration bit of line 53 */
4408 
4409 /******************  Bit definition for EXTI_FPR2 register  *******************/
4410 #define EXTI_FPR2_FPIF_Pos                   (16U)
4411 #define EXTI_FPR2_FPIF_Msk                   (0x24UL << EXTI_FPR2_FPIF_Pos)         /*!< 0x00240000 */
4412 #define EXTI_FPR2_FPIF                       EXTI_FPR2_FPIF_Msk                     /*!< Rising falling edge configuration bits */
4413 #define EXTI_FPR2_FPIF50_Pos                 (18U)
4414 #define EXTI_FPR2_FPIF50_Msk                 (0x1UL << EXTI_FPR2_FPIF50_Pos)        /*!< 0x00040000 */
4415 #define EXTI_FPR2_FPIF50                     EXTI_FPR2_FPIF50_Msk                   /*!< Rising falling edge configuration bit of line 50 */
4416 #define EXTI_FPR2_FPIF53_Pos                 (21U)
4417 #define EXTI_FPR2_FPIF53_Msk                 (0x1UL << EXTI_FPR2_FPIF53_Pos)        /*!< 0x00200000 */
4418 #define EXTI_FPR2_FPIF53                     EXTI_FPR2_FPIF53_Msk                   /*!< Rising falling edge configuration bit of line 53 */
4419 
4420 /*******************  Bit definition for EXTI_PRIVENR2 register  ******************/
4421 #define EXTI_PRIVENR2_PRIV37_Pos              (5U)
4422 #define EXTI_PRIVENR2_PRIV37_Msk              (0x1UL << EXTI_PRIVENR2_PRIV37_Pos)       /*!< 0x00000020 */
4423 #define EXTI_PRIVENR2_PRIV37                  EXTI_PRIVENR2_PRIV37_Msk                  /*!< Security enable on line 5 */
4424 #define EXTI_PRIVENR2_PRIV38_Pos              (6U)
4425 #define EXTI_PRIVENR2_PRIV38_Msk              (0x1UL << EXTI_PRIVENR2_PRIV38_Pos)       /*!< 0x00000040 */
4426 #define EXTI_PRIVENR2_PRIV38                  EXTI_PRIVENR2_PRIV38_Msk                  /*!< Security enable on line 6 */
4427 #define EXTI_PRIVENR2_PRIV39_Pos              (7U)
4428 #define EXTI_PRIVENR2_PRIV39_Msk              (0x1UL << EXTI_PRIVENR2_PRIV39_Pos)       /*!< 0x00000080 */
4429 #define EXTI_PRIVENR2_PRIV39                  EXTI_PRIVENR2_PRIV39_Msk                  /*!< Security enable on line 7 */
4430 #define EXTI_PRIVENR2_PRIV40_Pos              (8U)
4431 #define EXTI_PRIVENR2_PRIV40_Msk              (0x1UL << EXTI_PRIVENR2_PRIV40_Pos)       /*!< 0x00000100 */
4432 #define EXTI_PRIVENR2_PRIV40                  EXTI_PRIVENR2_PRIV40_Msk                  /*!< Security enable on line 8 */
4433 #define EXTI_PRIVENR2_PRIV41_Pos              (9U)
4434 #define EXTI_PRIVENR2_PRIV41_Msk              (0x1UL << EXTI_PRIVENR2_PRIV41_Pos)       /*!< 0x00000200 */
4435 #define EXTI_PRIVENR2_PRIV41                  EXTI_PRIVENR2_PRIV41_Msk                  /*!< Security enable on line 9 */
4436 #define EXTI_PRIVENR2_PRIV42_Pos             (10U)
4437 #define EXTI_PRIVENR2_PRIV42_Msk             (0x1UL << EXTI_PRIVENR2_PRIV42_Pos)        /*!< 0x00000400 */
4438 #define EXTI_PRIVENR2_PRIV42                 EXTI_PRIVENR2_PRIV42_Msk                   /*!< Security enable on line 10 */
4439 #define EXTI_PRIVENR2_PRIV47_Pos             (15U)
4440 #define EXTI_PRIVENR2_PRIV47_Msk             (0x1UL << EXTI_PRIVENR2_PRIV47_Pos)        /*!< 0x00008000 */
4441 #define EXTI_PRIVENR2_PRIV47                 EXTI_PRIVENR2_PRIV47_Msk                   /*!< Security enable on line 15 */
4442 #define EXTI_PRIVENR2_PRIV49_Pos             (17U)
4443 #define EXTI_PRIVENR2_PRIV49_Msk             (0x1UL << EXTI_PRIVENR2_PRIV49_Pos)        /*!< 0x00020000 */
4444 #define EXTI_PRIVENR2_PRIV49                 EXTI_PRIVENR2_PRIV49_Msk                   /*!< Security enable on line 17 */
4445 #define EXTI_PRIVENR2_PRIV50_Pos             (18U)
4446 #define EXTI_PRIVENR2_PRIV50_Msk             (0x1UL << EXTI_PRIVENR2_PRIV50_Pos)        /*!< 0x00040000 */
4447 #define EXTI_PRIVENR2_PRIV50                 EXTI_PRIVENR2_PRIV50_Msk                   /*!< Security enable on line 18 */
4448 #define EXTI_PRIVENR2_PRIV53_Pos             (21U)
4449 #define EXTI_PRIVENR2_PRIV53_Msk             (0x1UL << EXTI_PRIVENR2_PRIV53_Pos)        /*!< 0x00200000 */
4450 #define EXTI_PRIVENR2_PRIV53                 EXTI_PRIVENR2_PRIV53_Msk                   /*!< Security enable on line 21 */
4451 
4452 /*****************  Bit definition for EXTI_EXTICR1 register  **************/
4453 #define EXTI_EXTICR1_EXTI0_Pos              (0U)
4454 #define EXTI_EXTICR1_EXTI0_Msk              (0xFUL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000007 */
4455 #define EXTI_EXTICR1_EXTI0                  EXTI_EXTICR1_EXTI0_Msk                  /*!< EXTI 0 configuration */
4456 #define EXTI_EXTICR1_EXTI0_0                (0x1UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000001 */
4457 #define EXTI_EXTICR1_EXTI0_1                (0x2UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000002 */
4458 #define EXTI_EXTICR1_EXTI0_2                (0x4UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000004 */
4459 #define EXTI_EXTICR1_EXTI0_3                (0x8UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000008 */
4460 #define EXTI_EXTICR1_EXTI1_Pos              (8U)
4461 #define EXTI_EXTICR1_EXTI1_Msk              (0xFUL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000700 */
4462 #define EXTI_EXTICR1_EXTI1                  EXTI_EXTICR1_EXTI1_Msk                  /*!< EXTI 1 configuration */
4463 #define EXTI_EXTICR1_EXTI1_0                (0x1UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000100 */
4464 #define EXTI_EXTICR1_EXTI1_1                (0x2UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000200 */
4465 #define EXTI_EXTICR1_EXTI1_2                (0x4UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000400 */
4466 #define EXTI_EXTICR1_EXTI1_3                (0x8UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000800 */
4467 #define EXTI_EXTICR1_EXTI2_Pos              (16U)
4468 #define EXTI_EXTICR1_EXTI2_Msk              (0xFUL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00070000 */
4469 #define EXTI_EXTICR1_EXTI2                  EXTI_EXTICR1_EXTI2_Msk                  /*!< EXTI 2 configuration */
4470 #define EXTI_EXTICR1_EXTI2_0                (0x1UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00010000 */
4471 #define EXTI_EXTICR1_EXTI2_1                (0x2UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00020000 */
4472 #define EXTI_EXTICR1_EXTI2_2                (0x4UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00040000 */
4473 #define EXTI_EXTICR1_EXTI2_3                (0x8UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00080000 */
4474 #define EXTI_EXTICR1_EXTI3_Pos              (24U)
4475 #define EXTI_EXTICR1_EXTI3_Msk              (0xFUL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x07000000 */
4476 #define EXTI_EXTICR1_EXTI3                  EXTI_EXTICR1_EXTI3_Msk                  /*!< EXTI 3 configuration */
4477 #define EXTI_EXTICR1_EXTI3_0                (0x1UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x01000000 */
4478 #define EXTI_EXTICR1_EXTI3_1                (0x2UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x02000000 */
4479 #define EXTI_EXTICR1_EXTI3_2                (0x4UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x04000000 */
4480 #define EXTI_EXTICR1_EXTI3_3                (0x8UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x08000000 */
4481 
4482 /*****************  Bit definition for EXTI_EXTICR2 register  **************/
4483 #define EXTI_EXTICR2_EXTI4_Pos              (0U)
4484 #define EXTI_EXTICR2_EXTI4_Msk              (0xFUL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000007 */
4485 #define EXTI_EXTICR2_EXTI4                  EXTI_EXTICR2_EXTI4_Msk                  /*!< EXTI 4 configuration */
4486 #define EXTI_EXTICR2_EXTI4_0                (0x1UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000001 */
4487 #define EXTI_EXTICR2_EXTI4_1                (0x2UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000002 */
4488 #define EXTI_EXTICR2_EXTI4_2                (0x4UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000004 */
4489 #define EXTI_EXTICR2_EXTI4_3                (0x8UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000008 */
4490 #define EXTI_EXTICR2_EXTI5_Pos              (8U)
4491 #define EXTI_EXTICR2_EXTI5_Msk              (0xFUL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000700 */
4492 #define EXTI_EXTICR2_EXTI5                  EXTI_EXTICR2_EXTI5_Msk                  /*!< EXTI 5 configuration */
4493 #define EXTI_EXTICR2_EXTI5_0                (0x1UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000100 */
4494 #define EXTI_EXTICR2_EXTI5_1                (0x2UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000200 */
4495 #define EXTI_EXTICR2_EXTI5_2                (0x4UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000400 */
4496 #define EXTI_EXTICR2_EXTI5_3                (0x8UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000800 */
4497 #define EXTI_EXTICR2_EXTI6_Pos              (16U)
4498 #define EXTI_EXTICR2_EXTI6_Msk              (0xFUL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00070000 */
4499 #define EXTI_EXTICR2_EXTI6                  EXTI_EXTICR2_EXTI6_Msk                  /*!< EXTI 6 configuration */
4500 #define EXTI_EXTICR2_EXTI6_0                (0x1UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00010000 */
4501 #define EXTI_EXTICR2_EXTI6_1                (0x2UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00020000 */
4502 #define EXTI_EXTICR2_EXTI6_2                (0x4UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00040000 */
4503 #define EXTI_EXTICR2_EXTI6_3                (0x8UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00080000 */
4504 #define EXTI_EXTICR2_EXTI7_Pos              (24U)
4505 #define EXTI_EXTICR2_EXTI7_Msk              (0xFUL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x07000000 */
4506 #define EXTI_EXTICR2_EXTI7                  EXTI_EXTICR2_EXTI7_Msk                  /*!< EXTI 7 configuration */
4507 #define EXTI_EXTICR2_EXTI7_0                (0x1UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x01000000 */
4508 #define EXTI_EXTICR2_EXTI7_1                (0x2UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x02000000 */
4509 #define EXTI_EXTICR2_EXTI7_2                (0x4UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x04000000 */
4510 #define EXTI_EXTICR2_EXTI7_3                (0x8UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x08000000 */
4511 
4512 /*****************  Bit definition for EXTI_EXTICR3 register  **************/
4513 #define EXTI_EXTICR3_EXTI8_Pos              (0U)
4514 #define EXTI_EXTICR3_EXTI8_Msk              (0xFUL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000007 */
4515 #define EXTI_EXTICR3_EXTI8                  EXTI_EXTICR3_EXTI8_Msk                  /*!< EXTI 8 configuration */
4516 #define EXTI_EXTICR3_EXTI8_0                (0x1UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000001 */
4517 #define EXTI_EXTICR3_EXTI8_1                (0x2UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000002 */
4518 #define EXTI_EXTICR3_EXTI8_2                (0x4UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000004 */
4519 #define EXTI_EXTICR3_EXTI8_3                (0x8UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000008 */
4520 #define EXTI_EXTICR3_EXTI9_Pos              (8U)
4521 #define EXTI_EXTICR3_EXTI9_Msk              (0xFUL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000700 */
4522 #define EXTI_EXTICR3_EXTI9                  EXTI_EXTICR3_EXTI9_Msk                  /*!< EXTI 9 configuration */
4523 #define EXTI_EXTICR3_EXTI9_0                (0x1UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000100 */
4524 #define EXTI_EXTICR3_EXTI9_1                (0x2UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000200 */
4525 #define EXTI_EXTICR3_EXTI9_2                (0x4UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000400 */
4526 #define EXTI_EXTICR3_EXTI9_3                (0x8UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000800 */
4527 #define EXTI_EXTICR3_EXTI10_Pos             (16U)
4528 #define EXTI_EXTICR3_EXTI10_Msk             (0xFUL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00070000 */
4529 #define EXTI_EXTICR3_EXTI10                 EXTI_EXTICR3_EXTI10_Msk                 /*!< EXTI 10 configuration */
4530 #define EXTI_EXTICR3_EXTI10_0               (0x1UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00010000 */
4531 #define EXTI_EXTICR3_EXTI10_1               (0x2UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00020000 */
4532 #define EXTI_EXTICR3_EXTI10_2               (0x4UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00040000 */
4533 #define EXTI_EXTICR3_EXTI10_3               (0x8UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00080000 */
4534 #define EXTI_EXTICR3_EXTI11_Pos             (24U)
4535 #define EXTI_EXTICR3_EXTI11_Msk             (0xFUL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x07000000 */
4536 #define EXTI_EXTICR3_EXTI11                 EXTI_EXTICR3_EXTI11_Msk                 /*!< EXTI 11 configuration */
4537 #define EXTI_EXTICR3_EXTI11_0               (0x1UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x01000000 */
4538 #define EXTI_EXTICR3_EXTI11_1               (0x2UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x02000000 */
4539 #define EXTI_EXTICR3_EXTI11_2               (0x4UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x04000000 */
4540 #define EXTI_EXTICR3_EXTI11_3               (0x8UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x08000000 */
4541 
4542 /*****************  Bit definition for EXTI_EXTICR4 register  **************/
4543 #define EXTI_EXTICR4_EXTI12_Pos             (0U)
4544 #define EXTI_EXTICR4_EXTI12_Msk             (0xFUL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000007 */
4545 #define EXTI_EXTICR4_EXTI12                 EXTI_EXTICR4_EXTI12_Msk                 /*!< EXTI 12 configuration */
4546 #define EXTI_EXTICR4_EXTI12_0               (0x1UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000001 */
4547 #define EXTI_EXTICR4_EXTI12_1               (0x2UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000002 */
4548 #define EXTI_EXTICR4_EXTI12_2               (0x4UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000004 */
4549 #define EXTI_EXTICR4_EXTI12_3               (0x8UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000008 */
4550 #define EXTI_EXTICR4_EXTI13_Pos             (8U)
4551 #define EXTI_EXTICR4_EXTI13_Msk             (0xFUL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000700 */
4552 #define EXTI_EXTICR4_EXTI13                 EXTI_EXTICR4_EXTI13_Msk                 /*!< EXTI 13 configuration */
4553 #define EXTI_EXTICR4_EXTI13_0               (0x1UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000100 */
4554 #define EXTI_EXTICR4_EXTI13_1               (0x2UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000200 */
4555 #define EXTI_EXTICR4_EXTI13_2               (0x4UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000400 */
4556 #define EXTI_EXTICR4_EXTI13_3               (0x8UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000800 */
4557 #define EXTI_EXTICR4_EXTI14_Pos             (16U)
4558 #define EXTI_EXTICR4_EXTI14_Msk             (0xFUL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00070000 */
4559 #define EXTI_EXTICR4_EXTI14                 EXTI_EXTICR4_EXTI14_Msk                 /*!< EXTI 14 configuration */
4560 #define EXTI_EXTICR4_EXTI14_0               (0x1UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00010000 */
4561 #define EXTI_EXTICR4_EXTI14_1               (0x2UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00020000 */
4562 #define EXTI_EXTICR4_EXTI14_2               (0x4UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00040000 */
4563 #define EXTI_EXTICR4_EXTI14_3               (0x8UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00080000 */
4564 #define EXTI_EXTICR4_EXTI15_Pos             (24U)
4565 #define EXTI_EXTICR4_EXTI15_Msk             (0xFUL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x07000000 */
4566 #define EXTI_EXTICR4_EXTI15                 EXTI_EXTICR4_EXTI15_Msk                 /*!< EXTI 15 configuration */
4567 #define EXTI_EXTICR4_EXTI15_0               (0x1UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x01000000 */
4568 #define EXTI_EXTICR4_EXTI15_1               (0x2UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x02000000 */
4569 #define EXTI_EXTICR4_EXTI15_2               (0x4UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x04000000 */
4570 #define EXTI_EXTICR4_EXTI15_3               (0x8UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x08000000 */
4571 
4572 /*******************  Bit definition for EXTI_IMR1 register  ******************/
4573 #define EXTI_IMR1_IM_Pos                    (0U)
4574 #define EXTI_IMR1_IM_Msk                    (0x3F6BFFFFUL << EXTI_IMR1_IM_Pos)      /*!< 0x3F6BFFFF */
4575 #define EXTI_IMR1_IM                        EXTI_IMR1_IM_Msk                        /*!< Interrupt Mask */
4576 #define EXTI_IMR1_IM0_Pos                   (0U)
4577 #define EXTI_IMR1_IM0_Msk                   (0x1UL << EXTI_IMR1_IM0_Pos)            /*!< 0x00000001 */
4578 #define EXTI_IMR1_IM0                       EXTI_IMR1_IM0_Msk                       /*!< Interrupt Mask on line 0 */
4579 #define EXTI_IMR1_IM1_Pos                   (1U)
4580 #define EXTI_IMR1_IM1_Msk                   (0x1UL << EXTI_IMR1_IM1_Pos)            /*!< 0x00000002 */
4581 #define EXTI_IMR1_IM1                       EXTI_IMR1_IM1_Msk                       /*!< Interrupt Mask on line 1 */
4582 #define EXTI_IMR1_IM2_Pos                   (2U)
4583 #define EXTI_IMR1_IM2_Msk                   (0x1UL << EXTI_IMR1_IM2_Pos)            /*!< 0x00000004 */
4584 #define EXTI_IMR1_IM2                       EXTI_IMR1_IM2_Msk                       /*!< Interrupt Mask on line 2 */
4585 #define EXTI_IMR1_IM3_Pos                   (3U)
4586 #define EXTI_IMR1_IM3_Msk                   (0x1UL << EXTI_IMR1_IM3_Pos)            /*!< 0x00000008 */
4587 #define EXTI_IMR1_IM3                       EXTI_IMR1_IM3_Msk                       /*!< Interrupt Mask on line 3 */
4588 #define EXTI_IMR1_IM4_Pos                   (4U)
4589 #define EXTI_IMR1_IM4_Msk                   (0x1UL << EXTI_IMR1_IM4_Pos)            /*!< 0x00000010 */
4590 #define EXTI_IMR1_IM4                       EXTI_IMR1_IM4_Msk                       /*!< Interrupt Mask on line 4 */
4591 #define EXTI_IMR1_IM5_Pos                   (5U)
4592 #define EXTI_IMR1_IM5_Msk                   (0x1UL << EXTI_IMR1_IM5_Pos)            /*!< 0x00000020 */
4593 #define EXTI_IMR1_IM5                       EXTI_IMR1_IM5_Msk                       /*!< Interrupt Mask on line 5 */
4594 #define EXTI_IMR1_IM6_Pos                   (6U)
4595 #define EXTI_IMR1_IM6_Msk                   (0x1UL << EXTI_IMR1_IM6_Pos)            /*!< 0x00000040 */
4596 #define EXTI_IMR1_IM6                       EXTI_IMR1_IM6_Msk                       /*!< Interrupt Mask on line 6 */
4597 #define EXTI_IMR1_IM7_Pos                   (7U)
4598 #define EXTI_IMR1_IM7_Msk                   (0x1UL << EXTI_IMR1_IM7_Pos)            /*!< 0x00000080 */
4599 #define EXTI_IMR1_IM7                       EXTI_IMR1_IM7_Msk                       /*!< Interrupt Mask on line 7 */
4600 #define EXTI_IMR1_IM8_Pos                   (8U)
4601 #define EXTI_IMR1_IM8_Msk                   (0x1UL << EXTI_IMR1_IM8_Pos)            /*!< 0x00000100 */
4602 #define EXTI_IMR1_IM8                       EXTI_IMR1_IM8_Msk                       /*!< Interrupt Mask on line 8 */
4603 #define EXTI_IMR1_IM9_Pos                   (9U)
4604 #define EXTI_IMR1_IM9_Msk                   (0x1UL << EXTI_IMR1_IM9_Pos)            /*!< 0x00000200 */
4605 #define EXTI_IMR1_IM9                       EXTI_IMR1_IM9_Msk                       /*!< Interrupt Mask on line 9 */
4606 #define EXTI_IMR1_IM10_Pos                  (10U)
4607 #define EXTI_IMR1_IM10_Msk                  (0x1UL << EXTI_IMR1_IM10_Pos)           /*!< 0x00000400 */
4608 #define EXTI_IMR1_IM10                      EXTI_IMR1_IM10_Msk                      /*!< Interrupt Mask on line 10 */
4609 #define EXTI_IMR1_IM11_Pos                  (11U)
4610 #define EXTI_IMR1_IM11_Msk                  (0x1UL << EXTI_IMR1_IM11_Pos)           /*!< 0x00000800 */
4611 #define EXTI_IMR1_IM11                      EXTI_IMR1_IM11_Msk                      /*!< Interrupt Mask on line 11 */
4612 #define EXTI_IMR1_IM12_Pos                  (12U)
4613 #define EXTI_IMR1_IM12_Msk                  (0x1UL << EXTI_IMR1_IM12_Pos)           /*!< 0x00001000 */
4614 #define EXTI_IMR1_IM12                      EXTI_IMR1_IM12_Msk                      /*!< Interrupt Mask on line 12 */
4615 #define EXTI_IMR1_IM13_Pos                  (13U)
4616 #define EXTI_IMR1_IM13_Msk                  (0x1UL << EXTI_IMR1_IM13_Pos)           /*!< 0x00002000 */
4617 #define EXTI_IMR1_IM13                      EXTI_IMR1_IM13_Msk                      /*!< Interrupt Mask on line 13 */
4618 #define EXTI_IMR1_IM14_Pos                  (14U)
4619 #define EXTI_IMR1_IM14_Msk                  (0x1UL << EXTI_IMR1_IM14_Pos)           /*!< 0x00004000 */
4620 #define EXTI_IMR1_IM14                      EXTI_IMR1_IM14_Msk                      /*!< Interrupt Mask on line 14 */
4621 #define EXTI_IMR1_IM15_Pos                  (15U)
4622 #define EXTI_IMR1_IM15_Msk                  (0x1UL << EXTI_IMR1_IM15_Pos)           /*!< 0x00008000 */
4623 #define EXTI_IMR1_IM15                      EXTI_IMR1_IM15_Msk                      /*!< Interrupt Mask on line 15 */
4624 #define EXTI_IMR1_IM16_Pos                  (16U)
4625 #define EXTI_IMR1_IM16_Msk                  (0x1UL << EXTI_IMR1_IM16_Pos)           /*!< 0x00010000 */
4626 #define EXTI_IMR1_IM16                      EXTI_IMR1_IM16_Msk                      /*!< Interrupt Mask on line 16 */
4627 #define EXTI_IMR1_IM17_Pos                  (17U)
4628 #define EXTI_IMR1_IM17_Msk                  (0x1UL << EXTI_IMR1_IM17_Pos)           /*!< 0x00020000 */
4629 #define EXTI_IMR1_IM17                      EXTI_IMR1_IM17_Msk                      /*!< Interrupt Mask on line 17 */
4630 #define EXTI_IMR1_IM19_Pos                  (19U)
4631 #define EXTI_IMR1_IM19_Msk                  (0x1UL << EXTI_IMR1_IM19_Pos)           /*!< 0x00080000 */
4632 #define EXTI_IMR1_IM19                      EXTI_IMR1_IM19_Msk                      /*!< Interrupt Mask on line 19 */
4633 #define EXTI_IMR1_IM21_Pos                  (21U)
4634 #define EXTI_IMR1_IM21_Msk                  (0x1UL << EXTI_IMR1_IM21_Pos)           /*!< 0x00200000 */
4635 #define EXTI_IMR1_IM21                      EXTI_IMR1_IM21_Msk                      /*!< Interrupt Mask on line 21 */
4636 #define EXTI_IMR1_IM22_Pos                  (22U)
4637 #define EXTI_IMR1_IM22_Msk                  (0x1UL << EXTI_IMR1_IM22_Pos)           /*!< 0x00400000 */
4638 #define EXTI_IMR1_IM22                      EXTI_IMR1_IM22_Msk                      /*!< Interrupt Mask on line 22 */
4639 #define EXTI_IMR1_IM24_Pos                  (24U)
4640 #define EXTI_IMR1_IM24_Msk                  (0x1UL << EXTI_IMR1_IM24_Pos)           /*!< 0x01000000 */
4641 #define EXTI_IMR1_IM24                      EXTI_IMR1_IM24_Msk                      /*!< Interrupt Mask on line 24 */
4642 #define EXTI_IMR1_IM25_Pos                  (25U)
4643 #define EXTI_IMR1_IM25_Msk                  (0x1UL << EXTI_IMR1_IM25_Pos)           /*!< 0x02000000 */
4644 #define EXTI_IMR1_IM25                      EXTI_IMR1_IM25_Msk                      /*!< Interrupt Mask on line 25 */
4645 #define EXTI_IMR1_IM26_Pos                  (26U)
4646 #define EXTI_IMR1_IM26_Msk                  (0x1UL << EXTI_IMR1_IM26_Pos)           /*!< 0x04000000 */
4647 #define EXTI_IMR1_IM26                      EXTI_IMR1_IM26_Msk                      /*!< Interrupt Mask on line 26 */
4648 #define EXTI_IMR1_IM27_Pos                  (27U)
4649 #define EXTI_IMR1_IM27_Msk                  (0x1UL << EXTI_IMR1_IM27_Pos)           /*!< 0x08000000 */
4650 #define EXTI_IMR1_IM27                      EXTI_IMR1_IM27_Msk                      /*!< Interrupt Mask on line 27 */
4651 #define EXTI_IMR1_IM28_Pos                  (28U)
4652 #define EXTI_IMR1_IM28_Msk                  (0x1UL << EXTI_IMR1_IM28_Pos)           /*!< 0x10000000 */
4653 #define EXTI_IMR1_IM28                      EXTI_IMR1_IM28_Msk                      /*!< Interrupt Mask on line 28 */
4654 #define EXTI_IMR1_IM29_Pos                  (29U)
4655 #define EXTI_IMR1_IM29_Msk                  (0x1UL << EXTI_IMR1_IM29_Pos)           /*!< 0x20000000 */
4656 #define EXTI_IMR1_IM29                      EXTI_IMR1_IM29_Msk                      /*!< Interrupt Mask on line 29 */
4657 
4658 /*******************  Bit definition for EXTI_EMR1 register  ******************/
4659 #define EXTI_EMR1_EM_Pos                    (0U)
4660 #define EXTI_EMR1_EM_Msk                    (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)      /*!< 0xFFFFFFFF */
4661 #define EXTI_EMR1_EM                        EXTI_EMR1_EM_Msk                        /*!< Event Mask */
4662 #define EXTI_EMR1_EM0_Pos                   (0U)
4663 #define EXTI_EMR1_EM0_Msk                   (0x1UL << EXTI_EMR1_EM0_Pos)            /*!< 0x00000001 */
4664 #define EXTI_EMR1_EM0                       EXTI_EMR1_EM0_Msk                       /*!< Event Mask on line 0 */
4665 #define EXTI_EMR1_EM1_Pos                   (1U)
4666 #define EXTI_EMR1_EM1_Msk                   (0x1UL << EXTI_EMR1_EM1_Pos)            /*!< 0x00000002 */
4667 #define EXTI_EMR1_EM1                       EXTI_EMR1_EM1_Msk                       /*!< Event Mask on line 1 */
4668 #define EXTI_EMR1_EM2_Pos                   (2U)
4669 #define EXTI_EMR1_EM2_Msk                   (0x1UL << EXTI_EMR1_EM2_Pos)            /*!< 0x00000004 */
4670 #define EXTI_EMR1_EM2                       EXTI_EMR1_EM2_Msk                       /*!< Event Mask on line 2 */
4671 #define EXTI_EMR1_EM3_Pos                   (3U)
4672 #define EXTI_EMR1_EM3_Msk                   (0x1UL << EXTI_EMR1_EM3_Pos)            /*!< 0x00000008 */
4673 #define EXTI_EMR1_EM3                       EXTI_EMR1_EM3_Msk                       /*!< Event Mask on line 3 */
4674 #define EXTI_EMR1_EM4_Pos                   (4U)
4675 #define EXTI_EMR1_EM4_Msk                   (0x1UL << EXTI_EMR1_EM4_Pos)            /*!< 0x00000010 */
4676 #define EXTI_EMR1_EM4                       EXTI_EMR1_EM4_Msk                       /*!< Event Mask on line 4 */
4677 #define EXTI_EMR1_EM5_Pos                   (5U)
4678 #define EXTI_EMR1_EM5_Msk                   (0x1UL << EXTI_EMR1_EM5_Pos)            /*!< 0x00000020 */
4679 #define EXTI_EMR1_EM5                       EXTI_EMR1_EM5_Msk                       /*!< Event Mask on line 5 */
4680 #define EXTI_EMR1_EM6_Pos                   (6U)
4681 #define EXTI_EMR1_EM6_Msk                   (0x1UL << EXTI_EMR1_EM6_Pos)            /*!< 0x00000040 */
4682 #define EXTI_EMR1_EM6                       EXTI_EMR1_EM6_Msk                       /*!< Event Mask on line 6 */
4683 #define EXTI_EMR1_EM7_Pos                   (7U)
4684 #define EXTI_EMR1_EM7_Msk                   (0x1UL << EXTI_EMR1_EM7_Pos)            /*!< 0x00000080 */
4685 #define EXTI_EMR1_EM7                       EXTI_EMR1_EM7_Msk                       /*!< Event Mask on line 7 */
4686 #define EXTI_EMR1_EM8_Pos                   (8U)
4687 #define EXTI_EMR1_EM8_Msk                   (0x1UL << EXTI_EMR1_EM8_Pos)            /*!< 0x00000100 */
4688 #define EXTI_EMR1_EM8                       EXTI_EMR1_EM8_Msk                       /*!< Event Mask on line 8 */
4689 #define EXTI_EMR1_EM9_Pos                   (9U)
4690 #define EXTI_EMR1_EM9_Msk                   (0x1UL << EXTI_EMR1_EM9_Pos)            /*!< 0x00000200 */
4691 #define EXTI_EMR1_EM9                       EXTI_EMR1_EM9_Msk                       /*!< Event Mask on line 9 */
4692 #define EXTI_EMR1_EM10_Pos                  (10U)
4693 #define EXTI_EMR1_EM10_Msk                  (0x1UL << EXTI_EMR1_EM10_Pos)           /*!< 0x00000400 */
4694 #define EXTI_EMR1_EM10                      EXTI_EMR1_EM10_Msk                      /*!< Event Mask on line 10 */
4695 #define EXTI_EMR1_EM11_Pos                  (11U)
4696 #define EXTI_EMR1_EM11_Msk                  (0x1UL << EXTI_EMR1_EM11_Pos)           /*!< 0x00000800 */
4697 #define EXTI_EMR1_EM11                      EXTI_EMR1_EM11_Msk                      /*!< Event Mask on line 11 */
4698 #define EXTI_EMR1_EM12_Pos                  (12U)
4699 #define EXTI_EMR1_EM12_Msk                  (0x1UL << EXTI_EMR1_EM12_Pos)           /*!< 0x00001000 */
4700 #define EXTI_EMR1_EM12                      EXTI_EMR1_EM12_Msk                      /*!< Event Mask on line 12 */
4701 #define EXTI_EMR1_EM13_Pos                  (13U)
4702 #define EXTI_EMR1_EM13_Msk                  (0x1UL << EXTI_EMR1_EM13_Pos)           /*!< 0x00002000 */
4703 #define EXTI_EMR1_EM13                      EXTI_EMR1_EM13_Msk                      /*!< Event Mask on line 13 */
4704 #define EXTI_EMR1_EM14_Pos                  (14U)
4705 #define EXTI_EMR1_EM14_Msk                  (0x1UL << EXTI_EMR1_EM14_Pos)           /*!< 0x00004000 */
4706 #define EXTI_EMR1_EM14                      EXTI_EMR1_EM14_Msk                      /*!< Event Mask on line 14 */
4707 #define EXTI_EMR1_EM15_Pos                  (15U)
4708 #define EXTI_EMR1_EM15_Msk                  (0x1UL << EXTI_EMR1_EM15_Pos)           /*!< 0x00008000 */
4709 #define EXTI_EMR1_EM15                      EXTI_EMR1_EM15_Msk                      /*!< Event Mask on line 15 */
4710 #define EXTI_EMR1_EM16_Pos                  (16U)
4711 #define EXTI_EMR1_EM16_Msk                  (0x1UL << EXTI_EMR1_EM16_Pos)           /*!< 0x00010000 */
4712 #define EXTI_EMR1_EM16                      EXTI_EMR1_EM16_Msk                      /*!< Event Mask on line 16 */
4713 #define EXTI_EMR1_EM17_Pos                  (17U)
4714 #define EXTI_EMR1_EM17_Msk                  (0x1UL << EXTI_EMR1_EM17_Pos)           /*!< 0x00020000 */
4715 #define EXTI_EMR1_EM17                      EXTI_EMR1_EM17_Msk                      /*!< Event Mask on line 17 */
4716 #define EXTI_EMR1_EM19_Pos                  (19U)
4717 #define EXTI_EMR1_EM19_Msk                  (0x1UL << EXTI_EMR1_EM19_Pos)           /*!< 0x00080000 */
4718 #define EXTI_EMR1_EM19                      EXTI_EMR1_EM19_Msk                      /*!< Event Mask on line 19 */
4719 #define EXTI_EMR1_EM21_Pos                  (21U)
4720 #define EXTI_EMR1_EM21_Msk                  (0x1UL << EXTI_EMR1_EM21_Pos)           /*!< 0x00200000 */
4721 #define EXTI_EMR1_EM21                      EXTI_EMR1_EM21_Msk                      /*!< Event Mask on line 21 */
4722 #define EXTI_EMR1_EM22_Pos                  (22U)
4723 #define EXTI_EMR1_EM22_Msk                  (0x1UL << EXTI_EMR1_EM22_Pos)           /*!< 0x00400000 */
4724 #define EXTI_EMR1_EM22                      EXTI_EMR1_EM22_Msk                      /*!< Event Mask on line 22 */
4725 #define EXTI_EMR1_EM24_Pos                  (24U)
4726 #define EXTI_EMR1_EM24_Msk                  (0x1UL << EXTI_EMR1_EM24_Pos)           /*!< 0x01000000 */
4727 #define EXTI_EMR1_EM24                      EXTI_EMR1_EM24_Msk                      /*!< Event Mask on line 24 */
4728 #define EXTI_EMR1_EM25_Pos                  (25U)
4729 #define EXTI_EMR1_EM25_Msk                  (0x1UL << EXTI_EMR1_EM25_Pos)           /*!< 0x02000000 */
4730 #define EXTI_EMR1_EM25                      EXTI_EMR1_EM25_Msk                      /*!< Event Mask on line 25 */
4731 #define EXTI_EMR1_EM26_Pos                  (26U)
4732 #define EXTI_EMR1_EM26_Msk                  (0x1UL << EXTI_EMR1_EM26_Pos)           /*!< 0x04000000 */
4733 #define EXTI_EMR1_EM26                      EXTI_EMR1_EM26_Msk                      /*!< Event Mask on line 26 */
4734 #define EXTI_EMR1_EM27_Pos                  (27U)
4735 #define EXTI_EMR1_EM27_Msk                  (0x1UL << EXTI_EMR1_EM27_Pos)           /*!< 0x08000000 */
4736 #define EXTI_EMR1_EM27                      EXTI_EMR1_EM27_Msk                      /*!< Event Mask on line 27 */
4737 #define EXTI_EMR1_EM28_Pos                  (28U)
4738 #define EXTI_EMR1_EM28_Msk                  (0x1UL << EXTI_EMR1_EM28_Pos)           /*!< 0x10000000 */
4739 #define EXTI_EMR1_EM28                      EXTI_EMR1_EM28_Msk                      /*!< Event Mask on line 28 */
4740 #define EXTI_EMR1_EM29_Pos                  (29U)
4741 #define EXTI_EMR1_EM29_Msk                  (0x1UL << EXTI_EMR1_EM29_Pos)           /*!< 0x20000000 */
4742 #define EXTI_EMR1_EM29                      EXTI_EMR1_EM29_Msk                      /*!< Event Mask on line 29 */
4743 
4744 /*******************  Bit definition for EXTI_IMR2 register  *******************/
4745 #define EXTI_IMR2_IM_Pos                    (0U)
4746 #define EXTI_IMR2_IM_Msk                    (0x002687E0UL << EXTI_IMR2_IM_Pos)      /*!< 0x002687E0 */
4747 #define EXTI_IMR2_IM                        EXTI_IMR2_IM_Msk                        /*!< Interrupt Mask */
4748 #define EXTI_IMR2_IM37_Pos                  (5U)
4749 #define EXTI_IMR2_IM37_Msk                  (0x1UL << EXTI_IMR2_IM37_Pos)           /*!< 0x00000020 */
4750 #define EXTI_IMR2_IM37                      EXTI_IMR2_IM37_Msk                      /*!< Interrupt Mask on line 37 */
4751 #define EXTI_IMR2_IM38_Pos                  (6U)
4752 #define EXTI_IMR2_IM38_Msk                  (0x1UL << EXTI_IMR2_IM38_Pos)           /*!< 0x00000040 */
4753 #define EXTI_IMR2_IM38                      EXTI_IMR2_IM38_Msk                      /*!< Interrupt Mask on line 38 */
4754 #define EXTI_IMR2_IM39_Pos                  (7U)
4755 #define EXTI_IMR2_IM39_Msk                  (0x1UL << EXTI_IMR2_IM39_Pos)           /*!< 0x00000080 */
4756 #define EXTI_IMR2_IM39                      EXTI_IMR2_IM39_Msk                      /*!< Interrupt Mask on line 39 */
4757 #define EXTI_IMR2_IM40_Pos                  (8U)
4758 #define EXTI_IMR2_IM40_Msk                  (0x1UL << EXTI_IMR2_IM40_Pos)           /*!< 0x00000100 */
4759 #define EXTI_IMR2_IM40                      EXTI_IMR2_IM40_Msk                      /*!< Interrupt Mask on line 40 */
4760 #define EXTI_IMR2_IM41_Pos                  (9U)
4761 #define EXTI_IMR2_IM41_Msk                  (0x1UL << EXTI_IMR2_IM41_Pos)           /*!< 0x00000200 */
4762 #define EXTI_IMR2_IM41                      EXTI_IMR2_IM41_Msk                      /*!< Interrupt Mask on line 41 */
4763 #define EXTI_IMR2_IM42_Pos                  (10U)
4764 #define EXTI_IMR2_IM42_Msk                  (0x1UL << EXTI_IMR2_IM42_Pos)           /*!< 0x00000400 */
4765 #define EXTI_IMR2_IM42                      EXTI_IMR2_IM42_Msk                      /*!< Interrupt Mask on line 42 */
4766 #define EXTI_IMR2_IM47_Pos                  (15U)
4767 #define EXTI_IMR2_IM47_Msk                  (0x1UL << EXTI_IMR2_IM47_Pos)           /*!< 0x00008000 */
4768 #define EXTI_IMR2_IM47                      EXTI_IMR2_IM47_Msk                      /*!< Interrupt Mask on line 47 */
4769 #define EXTI_IMR2_IM49_Pos                  (17U)
4770 #define EXTI_IMR2_IM49_Msk                  (0x1UL << EXTI_IMR2_IM49_Pos)           /*!< 0x00020000 */
4771 #define EXTI_IMR2_IM49                      EXTI_IMR2_IM49_Msk                      /*!< Interrupt Mask on line 49 */
4772 #define EXTI_IMR2_IM50_Pos                  (18U)
4773 #define EXTI_IMR2_IM50_Msk                  (0x1UL << EXTI_IMR2_IM50_Pos)           /*!< 0x00040000 */
4774 #define EXTI_IMR2_IM50                      EXTI_IMR2_IM50_Msk                      /*!< Interrupt Mask on line 50 */
4775 #define EXTI_IMR2_IM53_Pos                  (21U)
4776 #define EXTI_IMR2_IM53_Msk                  (0x1UL << EXTI_IMR2_IM53_Pos)           /*!< 0x00200000 */
4777 #define EXTI_IMR2_IM53                      EXTI_IMR2_IM53_Msk                      /*!< Interrupt Mask on line 53 */
4778 
4779 
4780 /*******************  Bit definition for EXTI_EMR2 register  *******************/
4781 #define EXTI_EMR2_EM_Pos                    (0U)
4782 #define EXTI_EMR2_EM_Msk                    (0x002687E0UL << EXTI_EMR2_EM_Pos)      /*!< 0x002687E0 */
4783 #define EXTI_EMR2_EM                        EXTI_EMR2_EM_Msk                        /*!< Event Mask */
4784 #define EXTI_EMR2_EM37_Pos                  (5U)
4785 #define EXTI_EMR2_EM37_Msk                  (0x1UL << EXTI_EMR2_EM37_Pos)           /*!< 0x00000020 */
4786 #define EXTI_EMR2_EM37                      EXTI_EMR2_EM37_Msk                      /*!< Event Mask on line 37*/
4787 #define EXTI_EMR2_EM38_Pos                  (6U)
4788 #define EXTI_EMR2_EM38_Msk                  (0x1UL << EXTI_EMR2_EM38_Pos)           /*!< 0x00000040 */
4789 #define EXTI_EMR2_EM38                      EXTI_EMR2_EM38_Msk                      /*!< Event Mask on line 38*/
4790 #define EXTI_EMR2_EM39_Pos                  (7U)
4791 #define EXTI_EMR2_EM39_Msk                  (0x1UL << EXTI_EMR2_EM39_Pos)           /*!< 0x00000080 */
4792 #define EXTI_EMR2_EM39                      EXTI_EMR2_EM39_Msk                      /*!< Event Mask on line 39*/
4793 #define EXTI_EMR2_EM40_Pos                  (8U)
4794 #define EXTI_EMR2_EM40_Msk                  (0x1UL << EXTI_EMR2_EM40_Pos)           /*!< 0x00000100 */
4795 #define EXTI_EMR2_EM40                      EXTI_EMR2_EM40_Msk                      /*!< Event Mask on line 40*/
4796 #define EXTI_EMR2_EM41_Pos                  (9U)
4797 #define EXTI_EMR2_EM41_Msk                  (0x1UL << EXTI_EMR2_EM41_Pos)           /*!< 0x00000200 */
4798 #define EXTI_EMR2_EM41                      EXTI_EMR2_EM41_Msk                      /*!< Event Mask on line 41*/
4799 #define EXTI_EMR2_EM42_Pos                  (10U)
4800 #define EXTI_EMR2_EM42_Msk                  (0x1UL << EXTI_EMR2_EM42_Pos)           /*!< 0x00000400 */
4801 #define EXTI_EMR2_EM42                      EXTI_EMR2_EM42_Msk                      /*!< Event Mask on line 42 */
4802 #define EXTI_EMR2_EM47_Pos                  (15U)
4803 #define EXTI_EMR2_EM47_Msk                  (0x1UL << EXTI_EMR2_EM47_Pos)           /*!< 0x00008000 */
4804 #define EXTI_EMR2_EM47                      EXTI_EMR2_EM47_Msk                      /*!< Event Mask on line 47 */
4805 #define EXTI_EMR2_EM49_Pos                  (17U)
4806 #define EXTI_EMR2_EM49_Msk                  (0x1UL << EXTI_EMR2_EM49_Pos)           /*!< 0x00020000 */
4807 #define EXTI_EMR2_EM49                      EXTI_EMR2_EM49_Msk                      /*!< Event Mask on line 49 */
4808 #define EXTI_EMR2_EM50_Pos                  (18U)
4809 #define EXTI_EMR2_EM50_Msk                  (0x1UL << EXTI_EMR2_EM50_Pos)           /*!< 0x00040000 */
4810 #define EXTI_EMR2_EM50                      EXTI_EMR2_EM50_Msk                      /*!< Event Mask on line 50 */
4811 #define EXTI_EMR2_EM53_Pos                  (21U)
4812 #define EXTI_EMR2_EM53_Msk                  (0x1UL << EXTI_EMR2_EM53_Pos)           /*!< 0x00200000 */
4813 #define EXTI_EMR2_EM53                      EXTI_EMR2_EM53_Msk                      /*!< Event Mask on line 53 */
4814 
4815 /******************************************************************************/
4816 /*                                                                            */
4817 /*                 Flexible Datarate Controller Area Network                  */
4818 /*                                                                            */
4819 /******************************************************************************/
4820 /*!<FDCAN control and status registers */
4821 /*****************  Bit definition for FDCAN_CREL register  *******************/
4822 #define FDCAN_CREL_DAY_Pos                  (0U)
4823 #define FDCAN_CREL_DAY_Msk                  (0xFFUL << FDCAN_CREL_DAY_Pos)          /*!< 0x000000FF */
4824 #define FDCAN_CREL_DAY                      FDCAN_CREL_DAY_Msk                      /*!<Timestamp Day                           */
4825 #define FDCAN_CREL_MON_Pos                  (8U)
4826 #define FDCAN_CREL_MON_Msk                  (0xFFUL << FDCAN_CREL_MON_Pos)          /*!< 0x0000FF00 */
4827 #define FDCAN_CREL_MON                      FDCAN_CREL_MON_Msk                      /*!<Timestamp Month                         */
4828 #define FDCAN_CREL_YEAR_Pos                 (16U)
4829 #define FDCAN_CREL_YEAR_Msk                 (0xFUL << FDCAN_CREL_YEAR_Pos)          /*!< 0x000F0000 */
4830 #define FDCAN_CREL_YEAR                     FDCAN_CREL_YEAR_Msk                     /*!<Timestamp Year                          */
4831 #define FDCAN_CREL_SUBSTEP_Pos              (20U)
4832 #define FDCAN_CREL_SUBSTEP_Msk              (0xFUL << FDCAN_CREL_SUBSTEP_Pos)       /*!< 0x00F00000 */
4833 #define FDCAN_CREL_SUBSTEP                  FDCAN_CREL_SUBSTEP_Msk                  /*!<Sub-step of Core release                */
4834 #define FDCAN_CREL_STEP_Pos                 (24U)
4835 #define FDCAN_CREL_STEP_Msk                 (0xFUL << FDCAN_CREL_STEP_Pos)          /*!< 0x0F000000 */
4836 #define FDCAN_CREL_STEP                     FDCAN_CREL_STEP_Msk                     /*!<Step of Core release                    */
4837 #define FDCAN_CREL_REL_Pos                  (28U)
4838 #define FDCAN_CREL_REL_Msk                  (0xFUL << FDCAN_CREL_REL_Pos)           /*!< 0xF0000000 */
4839 #define FDCAN_CREL_REL                      FDCAN_CREL_REL_Msk                      /*!<Core release                            */
4840 
4841 /*****************  Bit definition for FDCAN_ENDN register  *******************/
4842 #define FDCAN_ENDN_ETV_Pos                  (0U)
4843 #define FDCAN_ENDN_ETV_Msk                  (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)    /*!< 0xFFFFFFFF */
4844 #define FDCAN_ENDN_ETV                      FDCAN_ENDN_ETV_Msk                      /*!<Endianness Test Value                   */
4845 
4846 /*****************  Bit definition for FDCAN_DBTP register  *******************/
4847 #define FDCAN_DBTP_DSJW_Pos                 (0U)
4848 #define FDCAN_DBTP_DSJW_Msk                 (0xFUL << FDCAN_DBTP_DSJW_Pos)          /*!< 0x0000000F */
4849 #define FDCAN_DBTP_DSJW                     FDCAN_DBTP_DSJW_Msk                     /*!<Synchronization Jump Width              */
4850 #define FDCAN_DBTP_DTSEG2_Pos               (4U)
4851 #define FDCAN_DBTP_DTSEG2_Msk               (0xFUL << FDCAN_DBTP_DTSEG2_Pos)        /*!< 0x000000F0 */
4852 #define FDCAN_DBTP_DTSEG2                   FDCAN_DBTP_DTSEG2_Msk                   /*!<Data time segment after sample point    */
4853 #define FDCAN_DBTP_DTSEG1_Pos               (8U)
4854 #define FDCAN_DBTP_DTSEG1_Msk               (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)       /*!< 0x00001F00 */
4855 #define FDCAN_DBTP_DTSEG1                   FDCAN_DBTP_DTSEG1_Msk                   /*!<Data time segment before sample point   */
4856 #define FDCAN_DBTP_DBRP_Pos                 (16U)
4857 #define FDCAN_DBTP_DBRP_Msk                 (0x1FUL << FDCAN_DBTP_DBRP_Pos)         /*!< 0x001F0000 */
4858 #define FDCAN_DBTP_DBRP                     FDCAN_DBTP_DBRP_Msk                     /*!<Data BIt Rate Prescaler                 */
4859 #define FDCAN_DBTP_TDC_Pos                  (23U)
4860 #define FDCAN_DBTP_TDC_Msk                  (0x1UL << FDCAN_DBTP_TDC_Pos)           /*!< 0x00800000 */
4861 #define FDCAN_DBTP_TDC                      FDCAN_DBTP_TDC_Msk                      /*!<Transceiver Delay Compensation          */
4862 
4863 /*****************  Bit definition for FDCAN_TEST register  *******************/
4864 #define FDCAN_TEST_LBCK_Pos                 (4U)
4865 #define FDCAN_TEST_LBCK_Msk                 (0x1UL << FDCAN_TEST_LBCK_Pos)          /*!< 0x00000010 */
4866 #define FDCAN_TEST_LBCK                     FDCAN_TEST_LBCK_Msk                     /*!<Loop Back mode                           */
4867 #define FDCAN_TEST_TX_Pos                   (5U)
4868 #define FDCAN_TEST_TX_Msk                   (0x3UL << FDCAN_TEST_TX_Pos)            /*!< 0x00000060 */
4869 #define FDCAN_TEST_TX                       FDCAN_TEST_TX_Msk                       /*!<Control of Transmit Pin                  */
4870 #define FDCAN_TEST_RX_Pos                   (7U)
4871 #define FDCAN_TEST_RX_Msk                   (0x1UL << FDCAN_TEST_RX_Pos)            /*!< 0x00000080 */
4872 #define FDCAN_TEST_RX                       FDCAN_TEST_RX_Msk                       /*!<Receive Pin                              */
4873 
4874 /*****************  Bit definition for FDCAN_RWD register  ********************/
4875 #define FDCAN_RWD_WDC_Pos                   (0U)
4876 #define FDCAN_RWD_WDC_Msk                   (0xFFUL << FDCAN_RWD_WDC_Pos)           /*!< 0x000000FF */
4877 #define FDCAN_RWD_WDC                       FDCAN_RWD_WDC_Msk                       /*!<Watchdog configuration                   */
4878 #define FDCAN_RWD_WDV_Pos                   (8U)
4879 #define FDCAN_RWD_WDV_Msk                   (0xFFUL << FDCAN_RWD_WDV_Pos)           /*!< 0x0000FF00 */
4880 #define FDCAN_RWD_WDV                       FDCAN_RWD_WDV_Msk                       /*!<Watchdog value                           */
4881 
4882 /*****************  Bit definition for FDCAN_CCCR register  ********************/
4883 #define FDCAN_CCCR_INIT_Pos                 (0U)
4884 #define FDCAN_CCCR_INIT_Msk                 (0x1UL << FDCAN_CCCR_INIT_Pos)          /*!< 0x00000001 */
4885 #define FDCAN_CCCR_INIT                     FDCAN_CCCR_INIT_Msk                     /*!<Initialization                           */
4886 #define FDCAN_CCCR_CCE_Pos                  (1U)
4887 #define FDCAN_CCCR_CCE_Msk                  (0x1UL << FDCAN_CCCR_CCE_Pos)           /*!< 0x00000002 */
4888 #define FDCAN_CCCR_CCE                      FDCAN_CCCR_CCE_Msk                      /*!<Configuration Change Enable              */
4889 #define FDCAN_CCCR_ASM_Pos                  (2U)
4890 #define FDCAN_CCCR_ASM_Msk                  (0x1UL << FDCAN_CCCR_ASM_Pos)           /*!< 0x00000004 */
4891 #define FDCAN_CCCR_ASM                      FDCAN_CCCR_ASM_Msk                      /*!<ASM Restricted Operation Mode            */
4892 #define FDCAN_CCCR_CSA_Pos                  (3U)
4893 #define FDCAN_CCCR_CSA_Msk                  (0x1UL << FDCAN_CCCR_CSA_Pos)           /*!< 0x00000008 */
4894 #define FDCAN_CCCR_CSA                      FDCAN_CCCR_CSA_Msk                      /*!<Clock Stop Acknowledge                   */
4895 #define FDCAN_CCCR_CSR_Pos                  (4U)
4896 #define FDCAN_CCCR_CSR_Msk                  (0x1UL << FDCAN_CCCR_CSR_Pos)           /*!< 0x00000010 */
4897 #define FDCAN_CCCR_CSR                      FDCAN_CCCR_CSR_Msk                      /*!<Clock Stop Request                       */
4898 #define FDCAN_CCCR_MON_Pos                  (5U)
4899 #define FDCAN_CCCR_MON_Msk                  (0x1UL << FDCAN_CCCR_MON_Pos)           /*!< 0x00000020 */
4900 #define FDCAN_CCCR_MON                      FDCAN_CCCR_MON_Msk                      /*!<Bus Monitoring Mode                      */
4901 #define FDCAN_CCCR_DAR_Pos                  (6U)
4902 #define FDCAN_CCCR_DAR_Msk                  (0x1UL << FDCAN_CCCR_DAR_Pos)           /*!< 0x00000040 */
4903 #define FDCAN_CCCR_DAR                      FDCAN_CCCR_DAR_Msk                      /*!<Disable Automatic Retransmission         */
4904 #define FDCAN_CCCR_TEST_Pos                 (7U)
4905 #define FDCAN_CCCR_TEST_Msk                 (0x1UL << FDCAN_CCCR_TEST_Pos)          /*!< 0x00000080 */
4906 #define FDCAN_CCCR_TEST                     FDCAN_CCCR_TEST_Msk                     /*!<Test Mode Enable                         */
4907 #define FDCAN_CCCR_FDOE_Pos                 (8U)
4908 #define FDCAN_CCCR_FDOE_Msk                 (0x1UL << FDCAN_CCCR_FDOE_Pos)          /*!< 0x00000100 */
4909 #define FDCAN_CCCR_FDOE                     FDCAN_CCCR_FDOE_Msk                     /*!<FD Operation Enable                      */
4910 #define FDCAN_CCCR_BRSE_Pos                 (9U)
4911 #define FDCAN_CCCR_BRSE_Msk                 (0x1UL << FDCAN_CCCR_BRSE_Pos)          /*!< 0x00000200 */
4912 #define FDCAN_CCCR_BRSE                     FDCAN_CCCR_BRSE_Msk                     /*!<FDCAN Bit Rate Switching                 */
4913 #define FDCAN_CCCR_PXHD_Pos                 (12U)
4914 #define FDCAN_CCCR_PXHD_Msk                 (0x1UL << FDCAN_CCCR_PXHD_Pos)          /*!< 0x00001000 */
4915 #define FDCAN_CCCR_PXHD                     FDCAN_CCCR_PXHD_Msk                     /*!<Protocol Exception Handling Disable      */
4916 #define FDCAN_CCCR_EFBI_Pos                 (13U)
4917 #define FDCAN_CCCR_EFBI_Msk                 (0x1UL << FDCAN_CCCR_EFBI_Pos)          /*!< 0x00002000 */
4918 #define FDCAN_CCCR_EFBI                     FDCAN_CCCR_EFBI_Msk                     /*!<Edge Filtering during Bus Integration    */
4919 #define FDCAN_CCCR_TXP_Pos                  (14U)
4920 #define FDCAN_CCCR_TXP_Msk                  (0x1UL << FDCAN_CCCR_TXP_Pos)           /*!< 0x00004000 */
4921 #define FDCAN_CCCR_TXP                      FDCAN_CCCR_TXP_Msk                      /*!<Two CAN bit times Pause                  */
4922 #define FDCAN_CCCR_NISO_Pos                 (15U)
4923 #define FDCAN_CCCR_NISO_Msk                 (0x1UL << FDCAN_CCCR_NISO_Pos)          /*!< 0x00008000 */
4924 #define FDCAN_CCCR_NISO                     FDCAN_CCCR_NISO_Msk                     /*!<Non ISO Operation                        */
4925 
4926 /*****************  Bit definition for FDCAN_NBTP register  ******************* */
4927 #define FDCAN_NBTP_NTSEG2_Pos               (0U)
4928 #define FDCAN_NBTP_NTSEG2_Msk               (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)       /*!< 0x0000007F */
4929 #define FDCAN_NBTP_NTSEG2                   FDCAN_NBTP_NTSEG2_Msk                   /*!<Nominal Time segment after sample point  */
4930 #define FDCAN_NBTP_NTSEG1_Pos               (8U)
4931 #define FDCAN_NBTP_NTSEG1_Msk               (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)       /*!< 0x0000FF00 */
4932 #define FDCAN_NBTP_NTSEG1                   FDCAN_NBTP_NTSEG1_Msk                   /*!<Nominal Time segment before sample point */
4933 #define FDCAN_NBTP_NBRP_Pos                 (16U)
4934 #define FDCAN_NBTP_NBRP_Msk                 (0x1FFUL << FDCAN_NBTP_NBRP_Pos)        /*!< 0x01FF0000 */
4935 #define FDCAN_NBTP_NBRP                     FDCAN_NBTP_NBRP_Msk                     /*!<Bit Rate Prescaler                       */
4936 #define FDCAN_NBTP_NSJW_Pos                 (25U)
4937 #define FDCAN_NBTP_NSJW_Msk                 (0x7FUL << FDCAN_NBTP_NSJW_Pos)         /*!< 0xFE000000 */
4938 #define FDCAN_NBTP_NSJW                     FDCAN_NBTP_NSJW_Msk                     /*!<Nominal (Re)Synchronization Jump Width   */
4939 
4940 /*****************  Bit definition for FDCAN_TSCC register  ********************/
4941 #define FDCAN_TSCC_TSS_Pos                  (0U)
4942 #define FDCAN_TSCC_TSS_Msk                  (0x3UL << FDCAN_TSCC_TSS_Pos)           /*!< 0x00000003 */
4943 #define FDCAN_TSCC_TSS                      FDCAN_TSCC_TSS_Msk                      /*!<Timestamp Select                         */
4944 #define FDCAN_TSCC_TCP_Pos                  (16U)
4945 #define FDCAN_TSCC_TCP_Msk                  (0xFUL << FDCAN_TSCC_TCP_Pos)           /*!< 0x000F0000 */
4946 #define FDCAN_TSCC_TCP                      FDCAN_TSCC_TCP_Msk                      /*!<Timestamp Counter Prescaler              */
4947 
4948 /*****************  Bit definition for FDCAN_TSCV register  ********************/
4949 #define FDCAN_TSCV_TSC_Pos                  (0U)
4950 #define FDCAN_TSCV_TSC_Msk                  (0xFFFFUL << FDCAN_TSCV_TSC_Pos)        /*!< 0x0000FFFF */
4951 #define FDCAN_TSCV_TSC                      FDCAN_TSCV_TSC_Msk                      /*!<Timestamp Counter                        */
4952 
4953 /*****************  Bit definition for FDCAN_TOCC register  ********************/
4954 #define FDCAN_TOCC_ETOC_Pos                 (0U)
4955 #define FDCAN_TOCC_ETOC_Msk                 (0x1UL << FDCAN_TOCC_ETOC_Pos)          /*!< 0x00000001 */
4956 #define FDCAN_TOCC_ETOC                     FDCAN_TOCC_ETOC_Msk                     /*!<Enable Timeout Counter                   */
4957 #define FDCAN_TOCC_TOS_Pos                  (1U)
4958 #define FDCAN_TOCC_TOS_Msk                  (0x3UL << FDCAN_TOCC_TOS_Pos)           /*!< 0x00000006 */
4959 #define FDCAN_TOCC_TOS                      FDCAN_TOCC_TOS_Msk                      /*!<Timeout Select                           */
4960 #define FDCAN_TOCC_TOP_Pos                  (16U)
4961 #define FDCAN_TOCC_TOP_Msk                  (0xFFFFUL << FDCAN_TOCC_TOP_Pos)        /*!< 0xFFFF0000 */
4962 #define FDCAN_TOCC_TOP                      FDCAN_TOCC_TOP_Msk                      /*!<Timeout Period                           */
4963 
4964 /*****************  Bit definition for FDCAN_TOCV register  ******************* */
4965 #define FDCAN_TOCV_TOC_Pos                  (0U)
4966 #define FDCAN_TOCV_TOC_Msk                  (0xFFFFUL << FDCAN_TOCV_TOC_Pos)        /*!< 0x0000FFFF */
4967 #define FDCAN_TOCV_TOC                      FDCAN_TOCV_TOC_Msk                      /*!<Timeout Counter                          */
4968 
4969 /*****************  Bit definition for FDCAN_ECR register  ******************** */
4970 #define FDCAN_ECR_TEC_Pos                   (0U)
4971 #define FDCAN_ECR_TEC_Msk                   (0xFFUL << FDCAN_ECR_TEC_Pos)           /*!< 0x000000FF */
4972 #define FDCAN_ECR_TEC                       FDCAN_ECR_TEC_Msk                       /*!<Transmit Error Counter                   */
4973 #define FDCAN_ECR_REC_Pos                   (8U)
4974 #define FDCAN_ECR_REC_Msk                   (0x7FUL << FDCAN_ECR_REC_Pos)           /*!< 0x00007F00 */
4975 #define FDCAN_ECR_REC                       FDCAN_ECR_REC_Msk                       /*!<Receive Error Counter                    */
4976 #define FDCAN_ECR_RP_Pos                    (15U)
4977 #define FDCAN_ECR_RP_Msk                    (0x1UL << FDCAN_ECR_RP_Pos)             /*!< 0x00008000 */
4978 #define FDCAN_ECR_RP                        FDCAN_ECR_RP_Msk                        /*!<Receive Error Passive                    */
4979 #define FDCAN_ECR_CEL_Pos                   (16U)
4980 #define FDCAN_ECR_CEL_Msk                   (0xFFUL << FDCAN_ECR_CEL_Pos)           /*!< 0x00FF0000 */
4981 #define FDCAN_ECR_CEL                       FDCAN_ECR_CEL_Msk                       /*!<CAN Error Logging                        */
4982 
4983 /*****************  Bit definition for FDCAN_PSR register  ******************** */
4984 #define FDCAN_PSR_LEC_Pos                   (0U)
4985 #define FDCAN_PSR_LEC_Msk                   (0x7UL << FDCAN_PSR_LEC_Pos)            /*!< 0x00000007 */
4986 #define FDCAN_PSR_LEC                       FDCAN_PSR_LEC_Msk                       /*!<Last Error Code                          */
4987 #define FDCAN_PSR_ACT_Pos                   (3U)
4988 #define FDCAN_PSR_ACT_Msk                   (0x3UL << FDCAN_PSR_ACT_Pos)            /*!< 0x00000018 */
4989 #define FDCAN_PSR_ACT                       FDCAN_PSR_ACT_Msk                       /*!<Activity                                 */
4990 #define FDCAN_PSR_EP_Pos                    (5U)
4991 #define FDCAN_PSR_EP_Msk                    (0x1UL << FDCAN_PSR_EP_Pos)             /*!< 0x00000020 */
4992 #define FDCAN_PSR_EP                        FDCAN_PSR_EP_Msk                        /*!<Error Passive                            */
4993 #define FDCAN_PSR_EW_Pos                    (6U)
4994 #define FDCAN_PSR_EW_Msk                    (0x1UL << FDCAN_PSR_EW_Pos)             /*!< 0x00000040 */
4995 #define FDCAN_PSR_EW                        FDCAN_PSR_EW_Msk                        /*!<Warning Status                           */
4996 #define FDCAN_PSR_BO_Pos                    (7U)
4997 #define FDCAN_PSR_BO_Msk                    (0x1UL << FDCAN_PSR_BO_Pos)             /*!< 0x00000080 */
4998 #define FDCAN_PSR_BO                        FDCAN_PSR_BO_Msk                        /*!<Bus_Off Status                           */
4999 #define FDCAN_PSR_DLEC_Pos                  (8U)
5000 #define FDCAN_PSR_DLEC_Msk                  (0x7UL << FDCAN_PSR_DLEC_Pos)           /*!< 0x00000700 */
5001 #define FDCAN_PSR_DLEC                      FDCAN_PSR_DLEC_Msk                      /*!<Data Last Error Code                     */
5002 #define FDCAN_PSR_RESI_Pos                  (11U)
5003 #define FDCAN_PSR_RESI_Msk                  (0x1UL << FDCAN_PSR_RESI_Pos)           /*!< 0x00000800 */
5004 #define FDCAN_PSR_RESI                      FDCAN_PSR_RESI_Msk                      /*!<ESI flag of last received FDCAN Message  */
5005 #define FDCAN_PSR_RBRS_Pos                  (12U)
5006 #define FDCAN_PSR_RBRS_Msk                  (0x1UL << FDCAN_PSR_RBRS_Pos)           /*!< 0x00001000 */
5007 #define FDCAN_PSR_RBRS                      FDCAN_PSR_RBRS_Msk                      /*!<BRS flag of last received FDCAN Message  */
5008 #define FDCAN_PSR_REDL_Pos                  (13U)
5009 #define FDCAN_PSR_REDL_Msk                  (0x1UL << FDCAN_PSR_REDL_Pos)           /*!< 0x00002000 */
5010 #define FDCAN_PSR_REDL                      FDCAN_PSR_REDL_Msk                      /*!<Received FDCAN Message                   */
5011 #define FDCAN_PSR_PXE_Pos                   (14U)
5012 #define FDCAN_PSR_PXE_Msk                   (0x1UL << FDCAN_PSR_PXE_Pos)            /*!< 0x00004000 */
5013 #define FDCAN_PSR_PXE                       FDCAN_PSR_PXE_Msk                       /*!<Protocol Exception Event                 */
5014 #define FDCAN_PSR_TDCV_Pos                  (16U)
5015 #define FDCAN_PSR_TDCV_Msk                  (0x7FUL << FDCAN_PSR_TDCV_Pos)          /*!< 0x007F0000 */
5016 #define FDCAN_PSR_TDCV                      FDCAN_PSR_TDCV_Msk                      /*!<Transmitter Delay Compensation Value     */
5017 
5018 /*****************  Bit definition for FDCAN_TDCR register  ******************* */
5019 #define FDCAN_TDCR_TDCF_Pos                 (0U)
5020 #define FDCAN_TDCR_TDCF_Msk                 (0x7FUL << FDCAN_TDCR_TDCF_Pos)         /*!< 0x0000007F */
5021 #define FDCAN_TDCR_TDCF                     FDCAN_TDCR_TDCF_Msk                     /*!<Transmitter Delay Compensation Filter    */
5022 #define FDCAN_TDCR_TDCO_Pos                 (8U)
5023 #define FDCAN_TDCR_TDCO_Msk                 (0x7FUL << FDCAN_TDCR_TDCO_Pos)         /*!< 0x00007F00 */
5024 #define FDCAN_TDCR_TDCO                     FDCAN_TDCR_TDCO_Msk                     /*!<Transmitter Delay Compensation Offset    */
5025 
5026 /*****************  Bit definition for FDCAN_IR register  ********************* */
5027 #define FDCAN_IR_RF0N_Pos                   (0U)
5028 #define FDCAN_IR_RF0N_Msk                   (0x1UL << FDCAN_IR_RF0N_Pos)            /*!< 0x00000001 */
5029 #define FDCAN_IR_RF0N                       FDCAN_IR_RF0N_Msk                       /*!<Rx FIFO 0 New Message                    */
5030 #define FDCAN_IR_RF0F_Pos                   (1U)
5031 #define FDCAN_IR_RF0F_Msk                   (0x1UL << FDCAN_IR_RF0F_Pos)            /*!< 0x00000002 */
5032 #define FDCAN_IR_RF0F                       FDCAN_IR_RF0F_Msk                       /*!<Rx FIFO 0 Full                           */
5033 #define FDCAN_IR_RF0L_Pos                   (2U)
5034 #define FDCAN_IR_RF0L_Msk                   (0x1UL << FDCAN_IR_RF0L_Pos)            /*!< 0x00000004 */
5035 #define FDCAN_IR_RF0L                       FDCAN_IR_RF0L_Msk                       /*!<Rx FIFO 0 Message Lost                   */
5036 #define FDCAN_IR_RF1N_Pos                   (3U)
5037 #define FDCAN_IR_RF1N_Msk                   (0x1UL << FDCAN_IR_RF1N_Pos)            /*!< 0x00000008 */
5038 #define FDCAN_IR_RF1N                       FDCAN_IR_RF1N_Msk                       /*!<Rx FIFO 1 New Message                    */
5039 #define FDCAN_IR_RF1F_Pos                   (4U)
5040 #define FDCAN_IR_RF1F_Msk                   (0x1UL << FDCAN_IR_RF1F_Pos)            /*!< 0x00000010 */
5041 #define FDCAN_IR_RF1F                       FDCAN_IR_RF1F_Msk                       /*!<Rx FIFO 1 Full                           */
5042 #define FDCAN_IR_RF1L_Pos                   (5U)
5043 #define FDCAN_IR_RF1L_Msk                   (0x1UL << FDCAN_IR_RF1L_Pos)            /*!< 0x00000020 */
5044 #define FDCAN_IR_RF1L                       FDCAN_IR_RF1L_Msk                       /*!<Rx FIFO 1 Message Lost                   */
5045 #define FDCAN_IR_HPM_Pos                    (6U)
5046 #define FDCAN_IR_HPM_Msk                    (0x1UL << FDCAN_IR_HPM_Pos)             /*!< 0x00000040 */
5047 #define FDCAN_IR_HPM                        FDCAN_IR_HPM_Msk                        /*!<High Priority Message                    */
5048 #define FDCAN_IR_TC_Pos                     (7U)
5049 #define FDCAN_IR_TC_Msk                     (0x1UL << FDCAN_IR_TC_Pos)              /*!< 0x00000080 */
5050 #define FDCAN_IR_TC                         FDCAN_IR_TC_Msk                         /*!<Transmission Completed                   */
5051 #define FDCAN_IR_TCF_Pos                    (8U)
5052 #define FDCAN_IR_TCF_Msk                    (0x1UL << FDCAN_IR_TCF_Pos)             /*!< 0x00000100 */
5053 #define FDCAN_IR_TCF                        FDCAN_IR_TCF_Msk                        /*!<Transmission Cancellation Finished       */
5054 #define FDCAN_IR_TFE_Pos                    (9U)
5055 #define FDCAN_IR_TFE_Msk                    (0x1UL << FDCAN_IR_TFE_Pos)             /*!< 0x00000200 */
5056 #define FDCAN_IR_TFE                        FDCAN_IR_TFE_Msk                        /*!<Tx FIFO Empty                            */
5057 #define FDCAN_IR_TEFN_Pos                   (10U)
5058 #define FDCAN_IR_TEFN_Msk                   (0x1UL << FDCAN_IR_TEFN_Pos)            /*!< 0x00000400 */
5059 #define FDCAN_IR_TEFN                       FDCAN_IR_TEFN_Msk                       /*!<Tx Event FIFO New Entry                  */
5060 #define FDCAN_IR_TEFF_Pos                   (11U)
5061 #define FDCAN_IR_TEFF_Msk                   (0x1UL << FDCAN_IR_TEFF_Pos)            /*!< 0x00000800 */
5062 #define FDCAN_IR_TEFF                       FDCAN_IR_TEFF_Msk                       /*!<Tx Event FIFO Full                       */
5063 #define FDCAN_IR_TEFL_Pos                   (12U)
5064 #define FDCAN_IR_TEFL_Msk                   (0x1UL << FDCAN_IR_TEFL_Pos)            /*!< 0x00001000 */
5065 #define FDCAN_IR_TEFL                       FDCAN_IR_TEFL_Msk                       /*!<Tx Event FIFO Element Lost               */
5066 #define FDCAN_IR_TSW_Pos                    (13U)
5067 #define FDCAN_IR_TSW_Msk                    (0x1UL << FDCAN_IR_TSW_Pos)             /*!< 0x00002000 */
5068 #define FDCAN_IR_TSW                        FDCAN_IR_TSW_Msk                        /*!<Timestamp Wraparound                     */
5069 #define FDCAN_IR_MRAF_Pos                   (14U)
5070 #define FDCAN_IR_MRAF_Msk                   (0x1UL << FDCAN_IR_MRAF_Pos)            /*!< 0x00004000 */
5071 #define FDCAN_IR_MRAF                       FDCAN_IR_MRAF_Msk                       /*!<Message RAM Access Failure               */
5072 #define FDCAN_IR_TOO_Pos                    (15U)
5073 #define FDCAN_IR_TOO_Msk                    (0x1UL << FDCAN_IR_TOO_Pos)             /*!< 0x00008000 */
5074 #define FDCAN_IR_TOO                        FDCAN_IR_TOO_Msk                        /*!<Timeout Occurred                         */
5075 #define FDCAN_IR_ELO_Pos                    (16U)
5076 #define FDCAN_IR_ELO_Msk                    (0x1UL << FDCAN_IR_ELO_Pos)             /*!< 0x00010000 */
5077 #define FDCAN_IR_ELO                        FDCAN_IR_ELO_Msk                        /*!<Error Logging Overflow                   */
5078 #define FDCAN_IR_EP_Pos                     (17U)
5079 #define FDCAN_IR_EP_Msk                     (0x1UL << FDCAN_IR_EP_Pos)              /*!< 0x00020000 */
5080 #define FDCAN_IR_EP                         FDCAN_IR_EP_Msk                         /*!<Error Passive                            */
5081 #define FDCAN_IR_EW_Pos                     (18U)
5082 #define FDCAN_IR_EW_Msk                     (0x1UL << FDCAN_IR_EW_Pos)              /*!< 0x00040000 */
5083 #define FDCAN_IR_EW                         FDCAN_IR_EW_Msk                         /*!<Warning Status                           */
5084 #define FDCAN_IR_BO_Pos                     (19U)
5085 #define FDCAN_IR_BO_Msk                     (0x1UL << FDCAN_IR_BO_Pos)              /*!< 0x00080000 */
5086 #define FDCAN_IR_BO                         FDCAN_IR_BO_Msk                         /*!<Bus_Off Status                           */
5087 #define FDCAN_IR_WDI_Pos                    (20U)
5088 #define FDCAN_IR_WDI_Msk                    (0x1UL << FDCAN_IR_WDI_Pos)             /*!< 0x00100000 */
5089 #define FDCAN_IR_WDI                        FDCAN_IR_WDI_Msk                        /*!<Watchdog Interrupt                       */
5090 #define FDCAN_IR_PEA_Pos                    (21U)
5091 #define FDCAN_IR_PEA_Msk                    (0x1UL << FDCAN_IR_PEA_Pos)             /*!< 0x00200000 */
5092 #define FDCAN_IR_PEA                        FDCAN_IR_PEA_Msk                        /*!<Protocol Error in Arbitration Phase      */
5093 #define FDCAN_IR_PED_Pos                    (22U)
5094 #define FDCAN_IR_PED_Msk                    (0x1UL << FDCAN_IR_PED_Pos)             /*!< 0x00400000 */
5095 #define FDCAN_IR_PED                        FDCAN_IR_PED_Msk                        /*!<Protocol Error in Data Phase             */
5096 #define FDCAN_IR_ARA_Pos                    (23U)
5097 #define FDCAN_IR_ARA_Msk                    (0x1UL << FDCAN_IR_ARA_Pos)             /*!< 0x00800000 */
5098 #define FDCAN_IR_ARA                        FDCAN_IR_ARA_Msk                        /*!<Access to Reserved Address               */
5099 
5100 /*****************  Bit definition for FDCAN_IE register  ********************* */
5101 #define FDCAN_IE_RF0NE_Pos                  (0U)
5102 #define FDCAN_IE_RF0NE_Msk                  (0x1UL << FDCAN_IE_RF0NE_Pos)           /*!< 0x00000001 */
5103 #define FDCAN_IE_RF0NE                      FDCAN_IE_RF0NE_Msk                      /*!<Rx FIFO 0 New Message Enable             */
5104 #define FDCAN_IE_RF0FE_Pos                  (1U)
5105 #define FDCAN_IE_RF0FE_Msk                  (0x1UL << FDCAN_IE_RF0FE_Pos)           /*!< 0x00000002 */
5106 #define FDCAN_IE_RF0FE                      FDCAN_IE_RF0FE_Msk                      /*!<Rx FIFO 0 Full Enable                    */
5107 #define FDCAN_IE_RF0LE_Pos                  (2U)
5108 #define FDCAN_IE_RF0LE_Msk                  (0x1UL << FDCAN_IE_RF0LE_Pos)           /*!< 0x00000004 */
5109 #define FDCAN_IE_RF0LE                      FDCAN_IE_RF0LE_Msk                      /*!<Rx FIFO 0 Message Lost Enable            */
5110 #define FDCAN_IE_RF1NE_Pos                  (3U)
5111 #define FDCAN_IE_RF1NE_Msk                  (0x1UL << FDCAN_IE_RF1NE_Pos)           /*!< 0x00000008 */
5112 #define FDCAN_IE_RF1NE                      FDCAN_IE_RF1NE_Msk                      /*!<Rx FIFO 1 New Message Enable             */
5113 #define FDCAN_IE_RF1FE_Pos                  (4U)
5114 #define FDCAN_IE_RF1FE_Msk                  (0x1UL << FDCAN_IE_RF1FE_Pos)           /*!< 0x00000010 */
5115 #define FDCAN_IE_RF1FE                      FDCAN_IE_RF1FE_Msk                      /*!<Rx FIFO 1 Full Enable                    */
5116 #define FDCAN_IE_RF1LE_Pos                  (5U)
5117 #define FDCAN_IE_RF1LE_Msk                  (0x1UL << FDCAN_IE_RF1LE_Pos)           /*!< 0x00000020 */
5118 #define FDCAN_IE_RF1LE                      FDCAN_IE_RF1LE_Msk                      /*!<Rx FIFO 1 Message Lost Enable            */
5119 #define FDCAN_IE_HPME_Pos                   (6U)
5120 #define FDCAN_IE_HPME_Msk                   (0x1UL << FDCAN_IE_HPME_Pos)            /*!< 0x00000040 */
5121 #define FDCAN_IE_HPME                       FDCAN_IE_HPME_Msk                       /*!<High Priority Message Enable             */
5122 #define FDCAN_IE_TCE_Pos                    (7U)
5123 #define FDCAN_IE_TCE_Msk                    (0x1UL << FDCAN_IE_TCE_Pos)             /*!< 0x00000080 */
5124 #define FDCAN_IE_TCE                        FDCAN_IE_TCE_Msk                        /*!<Transmission Completed Enable            */
5125 #define FDCAN_IE_TCFE_Pos                   (8U)
5126 #define FDCAN_IE_TCFE_Msk                   (0x1UL << FDCAN_IE_TCFE_Pos)            /*!< 0x00000100 */
5127 #define FDCAN_IE_TCFE                       FDCAN_IE_TCFE_Msk                       /*!<Transmission Cancellation Finished Enable*/
5128 #define FDCAN_IE_TFEE_Pos                   (9U)
5129 #define FDCAN_IE_TFEE_Msk                   (0x1UL << FDCAN_IE_TFEE_Pos)            /*!< 0x00000200 */
5130 #define FDCAN_IE_TFEE                       FDCAN_IE_TFEE_Msk                       /*!<Tx FIFO Empty Enable                     */
5131 #define FDCAN_IE_TEFNE_Pos                  (10U)
5132 #define FDCAN_IE_TEFNE_Msk                  (0x1UL << FDCAN_IE_TEFNE_Pos)           /*!< 0x00000400 */
5133 #define FDCAN_IE_TEFNE                      FDCAN_IE_TEFNE_Msk                      /*!<Tx Event FIFO New Entry Enable           */
5134 #define FDCAN_IE_TEFFE_Pos                  (11U)
5135 #define FDCAN_IE_TEFFE_Msk                  (0x1UL << FDCAN_IE_TEFFE_Pos)           /*!< 0x00000800 */
5136 #define FDCAN_IE_TEFFE                      FDCAN_IE_TEFFE_Msk                      /*!<Tx Event FIFO Full Enable                */
5137 #define FDCAN_IE_TEFLE_Pos                  (12U)
5138 #define FDCAN_IE_TEFLE_Msk                  (0x1UL << FDCAN_IE_TEFLE_Pos)           /*!< 0x00001000 */
5139 #define FDCAN_IE_TEFLE                      FDCAN_IE_TEFLE_Msk                      /*!<Tx Event FIFO Element Lost Enable        */
5140 #define FDCAN_IE_TSWE_Pos                   (13U)
5141 #define FDCAN_IE_TSWE_Msk                   (0x1UL << FDCAN_IE_TSWE_Pos)            /*!< 0x00002000 */
5142 #define FDCAN_IE_TSWE                       FDCAN_IE_TSWE_Msk                       /*!<Timestamp Wraparound Enable              */
5143 #define FDCAN_IE_MRAFE_Pos                  (14U)
5144 #define FDCAN_IE_MRAFE_Msk                  (0x1UL << FDCAN_IE_MRAFE_Pos)           /*!< 0x00004000 */
5145 #define FDCAN_IE_MRAFE                      FDCAN_IE_MRAFE_Msk                      /*!<Message RAM Access Failure Enable        */
5146 #define FDCAN_IE_TOOE_Pos                   (15U)
5147 #define FDCAN_IE_TOOE_Msk                   (0x1UL << FDCAN_IE_TOOE_Pos)            /*!< 0x00008000 */
5148 #define FDCAN_IE_TOOE                       FDCAN_IE_TOOE_Msk                       /*!<Timeout Occurred Enable                  */
5149 #define FDCAN_IE_ELOE_Pos                   (16U)
5150 #define FDCAN_IE_ELOE_Msk                   (0x1UL << FDCAN_IE_ELOE_Pos)            /*!< 0x00010000 */
5151 #define FDCAN_IE_ELOE                       FDCAN_IE_ELOE_Msk                       /*!<Error Logging Overflow Enable            */
5152 #define FDCAN_IE_EPE_Pos                    (17U)
5153 #define FDCAN_IE_EPE_Msk                    (0x1UL << FDCAN_IE_EPE_Pos)             /*!< 0x00020000 */
5154 #define FDCAN_IE_EPE                        FDCAN_IE_EPE_Msk                        /*!<Error Passive Enable                     */
5155 #define FDCAN_IE_EWE_Pos                    (18U)
5156 #define FDCAN_IE_EWE_Msk                    (0x1UL << FDCAN_IE_EWE_Pos)             /*!< 0x00040000 */
5157 #define FDCAN_IE_EWE                        FDCAN_IE_EWE_Msk                        /*!<Warning Status Enable                    */
5158 #define FDCAN_IE_BOE_Pos                    (19U)
5159 #define FDCAN_IE_BOE_Msk                    (0x1UL << FDCAN_IE_BOE_Pos)             /*!< 0x00080000 */
5160 #define FDCAN_IE_BOE                        FDCAN_IE_BOE_Msk                        /*!<Bus_Off Status Enable                    */
5161 #define FDCAN_IE_WDIE_Pos                   (20U)
5162 #define FDCAN_IE_WDIE_Msk                   (0x1UL << FDCAN_IE_WDIE_Pos)            /*!< 0x00100000 */
5163 #define FDCAN_IE_WDIE                       FDCAN_IE_WDIE_Msk                       /*!<Watchdog Interrupt Enable                */
5164 #define FDCAN_IE_PEAE_Pos                   (21U)
5165 #define FDCAN_IE_PEAE_Msk                   (0x1UL << FDCAN_IE_PEAE_Pos)            /*!< 0x00200000 */
5166 #define FDCAN_IE_PEAE                       FDCAN_IE_PEAE_Msk                       /*!<Protocol Error in Arbitration Phase Enable*/
5167 #define FDCAN_IE_PEDE_Pos                   (22U)
5168 #define FDCAN_IE_PEDE_Msk                   (0x1UL << FDCAN_IE_PEDE_Pos)            /*!< 0x00400000 */
5169 #define FDCAN_IE_PEDE                       FDCAN_IE_PEDE_Msk                       /*!<Protocol Error in Data Phase Enable      */
5170 #define FDCAN_IE_ARAE_Pos                   (23U)
5171 #define FDCAN_IE_ARAE_Msk                   (0x1UL << FDCAN_IE_ARAE_Pos)            /*!< 0x00800000 */
5172 #define FDCAN_IE_ARAE                       FDCAN_IE_ARAE_Msk                       /*!<Access to Reserved Address Enable        */
5173 
5174 /*****************  Bit definition for FDCAN_ILS register  ******************** **/
5175 #define FDCAN_ILS_RXFIFO0_Pos               (0U)
5176 #define FDCAN_ILS_RXFIFO0_Msk               (0x1UL << FDCAN_ILS_RXFIFO0_Pos)        /*!< 0x00000001 */
5177 #define FDCAN_ILS_RXFIFO0                   FDCAN_ILS_RXFIFO0_Msk                   /*!<Rx FIFO 0 Message Lost
5178                                                                                         Rx FIFO 0 is Full
5179                                                                                         Rx FIFO 0 Has New Message                */
5180 #define FDCAN_ILS_RXFIFO1_Pos               (1U)
5181 #define FDCAN_ILS_RXFIFO1_Msk               (0x1UL << FDCAN_ILS_RXFIFO1_Pos)        /*!< 0x00000002 */
5182 #define FDCAN_ILS_RXFIFO1                   FDCAN_ILS_RXFIFO1_Msk                   /*!<Rx FIFO 1 Message Lost
5183                                                                                         Rx FIFO 1 is Full
5184                                                                                         Rx FIFO 1 Has New Message                */
5185 #define FDCAN_ILS_SMSG_Pos                  (2U)
5186 #define FDCAN_ILS_SMSG_Msk                  (0x1UL << FDCAN_ILS_SMSG_Pos)           /*!< 0x00000004 */
5187 #define FDCAN_ILS_SMSG                      FDCAN_ILS_SMSG_Msk                      /*!<Transmission Cancellation Finished
5188                                                                                         Transmission Completed
5189                                                                                         High Priority Message                    */
5190 #define FDCAN_ILS_TFERR_Pos                 (3U)
5191 #define FDCAN_ILS_TFERR_Msk                 (0x1UL << FDCAN_ILS_TFERR_Pos)          /*!< 0x00000008 */
5192 #define FDCAN_ILS_TFERR                     FDCAN_ILS_TFERR_Msk                     /*!<Tx Event FIFO Element Lost
5193                                                                                         Tx Event FIFO Full
5194                                                                                         Tx Event FIFO New Entry
5195                                                                                         Tx FIFO Empty Interrupt Line             */
5196 #define FDCAN_ILS_MISC_Pos                  (4U)
5197 #define FDCAN_ILS_MISC_Msk                  (0x1UL << FDCAN_ILS_MISC_Pos)           /*!< 0x00000010 */
5198 #define FDCAN_ILS_MISC                      FDCAN_ILS_MISC_Msk                      /*!<Timeout Occurred
5199                                                                                         Message RAM Access Failure
5200                                                                                         Timestamp Wraparound                    */
5201 #define FDCAN_ILS_BERR_Pos                  (5U)
5202 #define FDCAN_ILS_BERR_Msk                  (0x1UL << FDCAN_ILS_BERR_Pos)           /*!< 0x00000020 */
5203 #define FDCAN_ILS_BERR                      FDCAN_ILS_BERR_Msk                      /*!<Error Passive
5204                                                                                         Error Logging Overflow                   */
5205 #define FDCAN_ILS_PERR_Pos                  (6U)
5206 #define FDCAN_ILS_PERR_Msk                  (0x1UL << FDCAN_ILS_PERR_Pos)           /*!< 0x00000040 */
5207 #define FDCAN_ILS_PERR                      FDCAN_ILS_PERR_Msk                      /*!<Access to Reserved Address Line
5208                                                                                         Protocol Error in Data Phase Line
5209                                                                                         Protocol Error in Arbitration Phase Line
5210                                                                                         Watchdog Interrupt Line
5211                                                                                         Bus_Off Status
5212                                                                                         Warning Status                           */
5213 
5214 /*****************  Bit definition for FDCAN_ILE register  ******************** **/
5215 #define FDCAN_ILE_EINT0_Pos                 (0U)
5216 #define FDCAN_ILE_EINT0_Msk                 (0x1UL << FDCAN_ILE_EINT0_Pos)          /*!< 0x00000001 */
5217 #define FDCAN_ILE_EINT0                     FDCAN_ILE_EINT0_Msk                     /*!<Enable Interrupt Line 0                  */
5218 #define FDCAN_ILE_EINT1_Pos                 (1U)
5219 #define FDCAN_ILE_EINT1_Msk                 (0x1UL << FDCAN_ILE_EINT1_Pos)          /*!< 0x00000002 */
5220 #define FDCAN_ILE_EINT1                     FDCAN_ILE_EINT1_Msk                     /*!<Enable Interrupt Line 1                  */
5221 
5222 /*****************  Bit definition for FDCAN_RXGFC register  ****************** **/
5223 #define FDCAN_RXGFC_RRFE_Pos                (0U)
5224 #define FDCAN_RXGFC_RRFE_Msk                (0x1UL << FDCAN_RXGFC_RRFE_Pos)         /*!< 0x00000001 */
5225 #define FDCAN_RXGFC_RRFE                    FDCAN_RXGFC_RRFE_Msk                    /*!<Reject Remote Frames Extended            */
5226 #define FDCAN_RXGFC_RRFS_Pos                (1U)
5227 #define FDCAN_RXGFC_RRFS_Msk                (0x1UL << FDCAN_RXGFC_RRFS_Pos)         /*!< 0x00000002 */
5228 #define FDCAN_RXGFC_RRFS                    FDCAN_RXGFC_RRFS_Msk                    /*!<Reject Remote Frames Standard            */
5229 #define FDCAN_RXGFC_ANFE_Pos                (2U)
5230 #define FDCAN_RXGFC_ANFE_Msk                (0x3UL << FDCAN_RXGFC_ANFE_Pos)         /*!< 0x0000000C */
5231 #define FDCAN_RXGFC_ANFE                    FDCAN_RXGFC_ANFE_Msk                    /*!<Accept Non-matching Frames Extended      */
5232 #define FDCAN_RXGFC_ANFS_Pos                (4U)
5233 #define FDCAN_RXGFC_ANFS_Msk                (0x3UL << FDCAN_RXGFC_ANFS_Pos)         /*!< 0x00000030 */
5234 #define FDCAN_RXGFC_ANFS                    FDCAN_RXGFC_ANFS_Msk                    /*!<Accept Non-matching Frames Standard      */
5235 #define FDCAN_RXGFC_F1OM_Pos                (8U)
5236 #define FDCAN_RXGFC_F1OM_Msk                (0x1UL << FDCAN_RXGFC_F1OM_Pos)         /*!< 0x00000100 */
5237 #define FDCAN_RXGFC_F1OM                    FDCAN_RXGFC_F1OM_Msk                    /*!<FIFO 1 operation mode                    */
5238 #define FDCAN_RXGFC_F0OM_Pos                (9U)
5239 #define FDCAN_RXGFC_F0OM_Msk                (0x1UL << FDCAN_RXGFC_F0OM_Pos)         /*!< 0x00000200 */
5240 #define FDCAN_RXGFC_F0OM                    FDCAN_RXGFC_F0OM_Msk                    /*!<FIFO 0 operation mode                    */
5241 #define FDCAN_RXGFC_LSS_Pos                 (16U)
5242 #define FDCAN_RXGFC_LSS_Msk                 (0x1FUL << FDCAN_RXGFC_LSS_Pos)         /*!< 0x001F0000 */
5243 #define FDCAN_RXGFC_LSS                     FDCAN_RXGFC_LSS_Msk                     /*!<List Size Standard                       */
5244 #define FDCAN_RXGFC_LSE_Pos                 (24U)
5245 #define FDCAN_RXGFC_LSE_Msk                 (0xFUL << FDCAN_RXGFC_LSE_Pos)          /*!< 0x0F000000 */
5246 #define FDCAN_RXGFC_LSE                     FDCAN_RXGFC_LSE_Msk                     /*!<List Size Extended                       */
5247 
5248 /*****************  Bit definition for FDCAN_XIDAM register  ****************** **/
5249 #define FDCAN_XIDAM_EIDM_Pos                (0U)
5250 #define FDCAN_XIDAM_EIDM_Msk                (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)  /*!< 0x1FFFFFFF */
5251 #define FDCAN_XIDAM_EIDM                    FDCAN_XIDAM_EIDM_Msk                    /*!<Extended ID Mask                         */
5252 
5253 /*****************  Bit definition for FDCAN_HPMS register  ******************* **/
5254 #define FDCAN_HPMS_BIDX_Pos                 (0U)
5255 #define FDCAN_HPMS_BIDX_Msk                 (0x7UL << FDCAN_HPMS_BIDX_Pos)          /*!< 0x00000007 */
5256 #define FDCAN_HPMS_BIDX                     FDCAN_HPMS_BIDX_Msk                     /*!<Buffer Index                             */
5257 #define FDCAN_HPMS_MSI_Pos                  (6U)
5258 #define FDCAN_HPMS_MSI_Msk                  (0x3UL << FDCAN_HPMS_MSI_Pos)           /*!< 0x000000C0 */
5259 #define FDCAN_HPMS_MSI                      FDCAN_HPMS_MSI_Msk                      /*!<Message Storage Indicator                */
5260 #define FDCAN_HPMS_FIDX_Pos                 (8U)
5261 #define FDCAN_HPMS_FIDX_Msk                 (0x1FUL << FDCAN_HPMS_FIDX_Pos)         /*!< 0x00001F00 */
5262 #define FDCAN_HPMS_FIDX                     FDCAN_HPMS_FIDX_Msk                     /*!<Filter Index                             */
5263 #define FDCAN_HPMS_FLST_Pos                 (15U)
5264 #define FDCAN_HPMS_FLST_Msk                 (0x1UL << FDCAN_HPMS_FLST_Pos)          /*!< 0x00008000 */
5265 #define FDCAN_HPMS_FLST                     FDCAN_HPMS_FLST_Msk                     /*!<Filter List                              */
5266 
5267 /*****************  Bit definition for FDCAN_RXF0S register  ****************** **/
5268 #define FDCAN_RXF0S_F0FL_Pos                (0U)
5269 #define FDCAN_RXF0S_F0FL_Msk                (0xFUL << FDCAN_RXF0S_F0FL_Pos)         /*!< 0x0000000F */
5270 #define FDCAN_RXF0S_F0FL                    FDCAN_RXF0S_F0FL_Msk                    /*!<Rx FIFO 0 Fill Level                     */
5271 #define FDCAN_RXF0S_F0GI_Pos                (8U)
5272 #define FDCAN_RXF0S_F0GI_Msk                (0x3UL << FDCAN_RXF0S_F0GI_Pos)         /*!< 0x00000300 */
5273 #define FDCAN_RXF0S_F0GI                    FDCAN_RXF0S_F0GI_Msk                    /*!<Rx FIFO 0 Get Index                      */
5274 #define FDCAN_RXF0S_F0PI_Pos                (16U)
5275 #define FDCAN_RXF0S_F0PI_Msk                (0x3UL << FDCAN_RXF0S_F0PI_Pos)         /*!< 0x00030000 */
5276 #define FDCAN_RXF0S_F0PI                    FDCAN_RXF0S_F0PI_Msk                    /*!<Rx FIFO 0 Put Index                      */
5277 #define FDCAN_RXF0S_F0F_Pos                 (24U)
5278 #define FDCAN_RXF0S_F0F_Msk                 (0x1UL << FDCAN_RXF0S_F0F_Pos)          /*!< 0x01000000 */
5279 #define FDCAN_RXF0S_F0F                     FDCAN_RXF0S_F0F_Msk                     /*!<Rx FIFO 0 Full                           */
5280 #define FDCAN_RXF0S_RF0L_Pos                (25U)
5281 #define FDCAN_RXF0S_RF0L_Msk                (0x1UL << FDCAN_RXF0S_RF0L_Pos)         /*!< 0x02000000 */
5282 #define FDCAN_RXF0S_RF0L                    FDCAN_RXF0S_RF0L_Msk                    /*!<Rx FIFO 0 Message Lost                   */
5283 
5284 /*****************  Bit definition for FDCAN_RXF0A register  ****************** **/
5285 #define FDCAN_RXF0A_F0AI_Pos                (0U)
5286 #define FDCAN_RXF0A_F0AI_Msk                (0x7UL << FDCAN_RXF0A_F0AI_Pos)         /*!< 0x00000007 */
5287 #define FDCAN_RXF0A_F0AI                    FDCAN_RXF0A_F0AI_Msk                    /*!<Rx FIFO 0 Acknowledge Index              */
5288 
5289 /*****************  Bit definition for FDCAN_RXF1S register  ****************** **/
5290 #define FDCAN_RXF1S_F1FL_Pos                (0U)
5291 #define FDCAN_RXF1S_F1FL_Msk                (0xFUL << FDCAN_RXF1S_F1FL_Pos)         /*!< 0x0000000F */
5292 #define FDCAN_RXF1S_F1FL                    FDCAN_RXF1S_F1FL_Msk                    /*!<Rx FIFO 1 Fill Level                     */
5293 #define FDCAN_RXF1S_F1GI_Pos                (8U)
5294 #define FDCAN_RXF1S_F1GI_Msk                (0x3UL << FDCAN_RXF1S_F1GI_Pos)         /*!< 0x00000300 */
5295 #define FDCAN_RXF1S_F1GI                    FDCAN_RXF1S_F1GI_Msk                    /*!<Rx FIFO 1 Get Index                      */
5296 #define FDCAN_RXF1S_F1PI_Pos                (16U)
5297 #define FDCAN_RXF1S_F1PI_Msk                (0x3UL << FDCAN_RXF1S_F1PI_Pos)         /*!< 0x00030000 */
5298 #define FDCAN_RXF1S_F1PI                    FDCAN_RXF1S_F1PI_Msk                    /*!<Rx FIFO 1 Put Index                      */
5299 #define FDCAN_RXF1S_F1F_Pos                 (24U)
5300 #define FDCAN_RXF1S_F1F_Msk                 (0x1UL << FDCAN_RXF1S_F1F_Pos)          /*!< 0x01000000 */
5301 #define FDCAN_RXF1S_F1F                     FDCAN_RXF1S_F1F_Msk                     /*!<Rx FIFO 1 Full                           */
5302 #define FDCAN_RXF1S_RF1L_Pos                (25U)
5303 #define FDCAN_RXF1S_RF1L_Msk                (0x1UL << FDCAN_RXF1S_RF1L_Pos)         /*!< 0x02000000 */
5304 #define FDCAN_RXF1S_RF1L                    FDCAN_RXF1S_RF1L_Msk                    /*!<Rx FIFO 1 Message Lost                   */
5305 
5306 /*****************  Bit definition for FDCAN_RXF1A register  ****************** **/
5307 #define FDCAN_RXF1A_F1AI_Pos                (0U)
5308 #define FDCAN_RXF1A_F1AI_Msk                (0x7UL << FDCAN_RXF1A_F1AI_Pos)         /*!< 0x00000007 */
5309 #define FDCAN_RXF1A_F1AI                    FDCAN_RXF1A_F1AI_Msk                    /*!<Rx FIFO 1 Acknowledge Index              */
5310 
5311 /*****************  Bit definition for FDCAN_TXBC register  ******************* **/
5312 #define FDCAN_TXBC_TFQM_Pos                 (24U)
5313 #define FDCAN_TXBC_TFQM_Msk                 (0x1UL << FDCAN_TXBC_TFQM_Pos)          /*!< 0x01000000 */
5314 #define FDCAN_TXBC_TFQM                     FDCAN_TXBC_TFQM_Msk                     /*!<Tx FIFO/Queue Mode                       */
5315 
5316 /*****************  Bit definition for FDCAN_TXFQS register  ****************** ***/
5317 #define FDCAN_TXFQS_TFFL_Pos                (0U)
5318 #define FDCAN_TXFQS_TFFL_Msk                (0x7UL << FDCAN_TXFQS_TFFL_Pos)         /*!< 0x00000007 */
5319 #define FDCAN_TXFQS_TFFL                    FDCAN_TXFQS_TFFL_Msk                    /*!<Tx FIFO Free Level                       */
5320 #define FDCAN_TXFQS_TFGI_Pos                (8U)
5321 #define FDCAN_TXFQS_TFGI_Msk                (0x3UL << FDCAN_TXFQS_TFGI_Pos)         /*!< 0x00000300 */
5322 #define FDCAN_TXFQS_TFGI                    FDCAN_TXFQS_TFGI_Msk                    /*!<Tx FIFO Get Index                        */
5323 #define FDCAN_TXFQS_TFQPI_Pos               (16U)
5324 #define FDCAN_TXFQS_TFQPI_Msk               (0x3UL << FDCAN_TXFQS_TFQPI_Pos)        /*!< 0x00030000 */
5325 #define FDCAN_TXFQS_TFQPI                   FDCAN_TXFQS_TFQPI_Msk                   /*!<Tx FIFO/Queue Put Index                  */
5326 #define FDCAN_TXFQS_TFQF_Pos                (21U)
5327 #define FDCAN_TXFQS_TFQF_Msk                (0x1UL << FDCAN_TXFQS_TFQF_Pos)         /*!< 0x00200000 */
5328 #define FDCAN_TXFQS_TFQF                    FDCAN_TXFQS_TFQF_Msk                    /*!<Tx FIFO/Queue Full                       */
5329 
5330 /*****************  Bit definition for FDCAN_TXBRP register  ****************** ***/
5331 #define FDCAN_TXBRP_TRP_Pos                 (0U)
5332 #define FDCAN_TXBRP_TRP_Msk                 (0x7UL << FDCAN_TXBRP_TRP_Pos)          /*!< 0x00000007 */
5333 #define FDCAN_TXBRP_TRP                     FDCAN_TXBRP_TRP_Msk                     /*!<Transmission Request Pending             */
5334 
5335 /*****************  Bit definition for FDCAN_TXBAR register  ****************** ***/
5336 #define FDCAN_TXBAR_AR_Pos                  (0U)
5337 #define FDCAN_TXBAR_AR_Msk                  (0x7UL << FDCAN_TXBAR_AR_Pos)           /*!< 0x00000007 */
5338 #define FDCAN_TXBAR_AR                      FDCAN_TXBAR_AR_Msk                      /*!<Add Request                              */
5339 
5340 /*****************  Bit definition for FDCAN_TXBCR register  ****************** ***/
5341 #define FDCAN_TXBCR_CR_Pos                  (0U)
5342 #define FDCAN_TXBCR_CR_Msk                  (0x7UL << FDCAN_TXBCR_CR_Pos)           /*!< 0x00000007 */
5343 #define FDCAN_TXBCR_CR                      FDCAN_TXBCR_CR_Msk                      /*!<Cancellation Request                     */
5344 
5345 /*****************  Bit definition for FDCAN_TXBTO register  ****************** ***/
5346 #define FDCAN_TXBTO_TO_Pos                  (0U)
5347 #define FDCAN_TXBTO_TO_Msk                  (0x7UL << FDCAN_TXBTO_TO_Pos)           /*!< 0x00000007 */
5348 #define FDCAN_TXBTO_TO                      FDCAN_TXBTO_TO_Msk                      /*!<Transmission Occurred                    */
5349 
5350 /*****************  Bit definition for FDCAN_TXBCF register  ****************** ***/
5351 #define FDCAN_TXBCF_CF_Pos                  (0U)
5352 #define FDCAN_TXBCF_CF_Msk                  (0x7UL << FDCAN_TXBCF_CF_Pos)           /*!< 0x00000007 */
5353 #define FDCAN_TXBCF_CF                      FDCAN_TXBCF_CF_Msk                      /*!<Cancellation Finished                    */
5354 
5355 /*****************  Bit definition for FDCAN_TXBTIE register  ***************** ***/
5356 #define FDCAN_TXBTIE_TIE_Pos                (0U)
5357 #define FDCAN_TXBTIE_TIE_Msk                (0x7UL << FDCAN_TXBTIE_TIE_Pos)         /*!< 0x00000007 */
5358 #define FDCAN_TXBTIE_TIE                    FDCAN_TXBTIE_TIE_Msk                    /*!<Transmission Interrupt Enable            */
5359 
5360 /*****************  Bit definition for FDCAN_ TXBCIE register  **************** ***/
5361 #define FDCAN_TXBCIE_CFIE_Pos               (0U)
5362 #define FDCAN_TXBCIE_CFIE_Msk               (0x7UL << FDCAN_TXBCIE_CFIE_Pos)        /*!< 0x00000007 */
5363 #define FDCAN_TXBCIE_CFIE                   FDCAN_TXBCIE_CFIE_Msk                   /*!<Cancellation Finished Interrupt Enable   */
5364 
5365 /*****************  Bit definition for FDCAN_TXEFS register  ****************** ***/
5366 #define FDCAN_TXEFS_EFFL_Pos                (0U)
5367 #define FDCAN_TXEFS_EFFL_Msk                (0x7UL << FDCAN_TXEFS_EFFL_Pos)         /*!< 0x00000007 */
5368 #define FDCAN_TXEFS_EFFL                    FDCAN_TXEFS_EFFL_Msk                    /*!<Event FIFO Fill Level                    */
5369 #define FDCAN_TXEFS_EFGI_Pos                (8U)
5370 #define FDCAN_TXEFS_EFGI_Msk                (0x3UL << FDCAN_TXEFS_EFGI_Pos)         /*!< 0x00000300 */
5371 #define FDCAN_TXEFS_EFGI                    FDCAN_TXEFS_EFGI_Msk                    /*!<Event FIFO Get Index                     */
5372 #define FDCAN_TXEFS_EFPI_Pos                (16U)
5373 #define FDCAN_TXEFS_EFPI_Msk                (0x3UL << FDCAN_TXEFS_EFPI_Pos)         /*!< 0x00030000 */
5374 #define FDCAN_TXEFS_EFPI                    FDCAN_TXEFS_EFPI_Msk                    /*!<Event FIFO Put Index                     */
5375 #define FDCAN_TXEFS_EFF_Pos                 (24U)
5376 #define FDCAN_TXEFS_EFF_Msk                 (0x1UL << FDCAN_TXEFS_EFF_Pos)          /*!< 0x01000000 */
5377 #define FDCAN_TXEFS_EFF                     FDCAN_TXEFS_EFF_Msk                     /*!<Event FIFO Full                          */
5378 #define FDCAN_TXEFS_TEFL_Pos                (25U)
5379 #define FDCAN_TXEFS_TEFL_Msk                (0x1UL << FDCAN_TXEFS_TEFL_Pos)         /*!< 0x02000000 */
5380 #define FDCAN_TXEFS_TEFL                    FDCAN_TXEFS_TEFL_Msk                    /*!<Tx Event FIFO Element Lost               */
5381 
5382 /*****************  Bit definition for FDCAN_TXEFA register  ****************** ***/
5383 #define FDCAN_TXEFA_EFAI_Pos                (0U)
5384 #define FDCAN_TXEFA_EFAI_Msk                (0x3UL << FDCAN_TXEFA_EFAI_Pos)         /*!< 0x00000003 */
5385 #define FDCAN_TXEFA_EFAI                    FDCAN_TXEFA_EFAI_Msk                    /*!<Event FIFO Acknowledge Index             */
5386 
5387 /*!<FDCAN config registers */
5388 /*****************  Bit definition for FDCAN_CKDIV register  ****************** ***/
5389 #define FDCAN_CKDIV_PDIV_Pos                (0U)
5390 #define FDCAN_CKDIV_PDIV_Msk                (0xFUL << FDCAN_CKDIV_PDIV_Pos)         /*!< 0x0000000F */
5391 #define FDCAN_CKDIV_PDIV                    FDCAN_CKDIV_PDIV_Msk                    /*!<Input Clock Divider                      */
5392 /******************************************************************************/
5393 /*                                                                            */
5394 /*                                    FLASH                                   */
5395 /*                                                                            */
5396 /******************************************************************************/
5397 #define FLASH_LATENCY_DEFAULT               FLASH_ACR_LATENCY_3WS                   /*!< FLASH Three Latency cycle */
5398 #define FLASH_BLOCKBASED_NB_REG             (1U)                                    /*!< 1 Block-based registers for each Flash bank */
5399 #define FLASH_SIZE_DEFAULT                  (0x20000U)                              /*!< FLASH Size */
5400 #define FLASH_SECTOR_NB                     (8U)                                    /*!< Flash Sector number */
5401 #define FLASH_SIZE                          ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \
5402                                             ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \
5403                                             (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U)))
5404 #define FLASH_BANK_SIZE                     (FLASH_SIZE >> 1U)                      /*!< FLASH Bank Size */
5405 #define FLASH_SECTOR_SIZE                   0x2000U                                 /*!< Flash Sector Size: 8 KB */
5406 
5407 /*******************  Bits definition for FLASH_ACR register  *****************/
5408 #define FLASH_ACR_LATENCY_Pos               (0U)
5409 #define FLASH_ACR_LATENCY_Msk               (0xFUL << FLASH_ACR_LATENCY_Pos)        /*!< 0x0000000F */
5410 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk                   /*!< Latency    */
5411 #define FLASH_ACR_LATENCY_0WS               (0x00000000U)
5412 #define FLASH_ACR_LATENCY_1WS               (0x00000001U)
5413 #define FLASH_ACR_LATENCY_2WS               (0x00000002U)
5414 #define FLASH_ACR_LATENCY_3WS               (0x00000003U)
5415 #define FLASH_ACR_LATENCY_4WS               (0x00000004U)
5416 #define FLASH_ACR_LATENCY_5WS               (0x00000005U)
5417 #define FLASH_ACR_LATENCY_6WS               (0x00000006U)
5418 #define FLASH_ACR_LATENCY_7WS               (0x00000007U)
5419 #define FLASH_ACR_LATENCY_8WS               (0x00000008U)
5420 #define FLASH_ACR_LATENCY_9WS               (0x00000009U)
5421 #define FLASH_ACR_LATENCY_10WS              (0x0000000AU)
5422 #define FLASH_ACR_LATENCY_11WS              (0x0000000BU)
5423 #define FLASH_ACR_LATENCY_12WS              (0x0000000CU)
5424 #define FLASH_ACR_LATENCY_13WS              (0x0000000DU)
5425 #define FLASH_ACR_LATENCY_14WS              (0x0000000EU)
5426 #define FLASH_ACR_LATENCY_15WS              (0x0000000FU)
5427 #define FLASH_ACR_WRHIGHFREQ_Pos            (4U)
5428 #define FLASH_ACR_WRHIGHFREQ_Msk            (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)     /*!< 0x00000030 */
5429 #define FLASH_ACR_WRHIGHFREQ                FLASH_ACR_WRHIGHFREQ_Msk                /*!< Flash signal delay */
5430 #define FLASH_ACR_WRHIGHFREQ_0              (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)     /*!< 0x00000010 */
5431 #define FLASH_ACR_WRHIGHFREQ_1              (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)     /*!< 0x00000020 */
5432 #define FLASH_ACR_PRFTEN_Pos                (8U)
5433 #define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)         /*!< 0x00000100 */
5434 #define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk                    /*!< Prefetch enable */
5435 
5436 /*******************  Bits definition for FLASH_OPSR register  ***************/
5437 #define FLASH_OPSR_ADDR_OP_Pos              (0U)
5438 #define FLASH_OPSR_ADDR_OP_Msk              (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos)   /*!< 0x000FFFFF */
5439 #define FLASH_OPSR_ADDR_OP                  FLASH_OPSR_ADDR_OP_Msk                  /*!< Interrupted operation address */
5440 #define FLASH_OPSR_BK_OP_Pos                (22U)
5441 #define FLASH_OPSR_BK_OP_Msk                (0x1UL << FLASH_OPSR_BK_OP_Pos)         /*!< 0x00400000 */
5442 #define FLASH_OPSR_BK_OP                    FLASH_OPSR_BK_OP_Msk                    /*!< Interrupted operation bank */
5443 #define FLASH_OPSR_SYSF_OP_Pos              (23U)
5444 #define FLASH_OPSR_SYSF_OP_Msk              (0x1UL << FLASH_OPSR_SYSF_OP_Pos)       /*!< 0x00800000 */
5445 #define FLASH_OPSR_SYSF_OP                  FLASH_OPSR_SYSF_OP_Msk                  /*!< Operation in System Flash interrupted */
5446 #define FLASH_OPSR_OTP_OP_Pos               (24U)
5447 #define FLASH_OPSR_OTP_OP_Msk               (0x1UL << FLASH_OPSR_OTP_OP_Pos)        /*!< 0x01000000 */
5448 #define FLASH_OPSR_OTP_OP                   FLASH_OPSR_OTP_OP_Msk                   /*!< Operation in OTP area interrupted */
5449 #define FLASH_OPSR_CODE_OP_Pos              (29U)
5450 #define FLASH_OPSR_CODE_OP_Msk              (0x7UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0xE0000000 */
5451 #define FLASH_OPSR_CODE_OP                  FLASH_OPSR_CODE_OP_Msk                  /*!< Flash memory operation code */
5452 #define FLASH_OPSR_CODE_OP_0                (0x1UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x20000000 */
5453 #define FLASH_OPSR_CODE_OP_1                (0x2UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x40000000 */
5454 #define FLASH_OPSR_CODE_OP_2                (0x4UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x80000000 */
5455 
5456 /*******************  Bits definition for FLASH_OPTCR register  *******************/
5457 #define FLASH_OPTCR_OPTLOCK_Pos             (0U)
5458 #define FLASH_OPTCR_OPTLOCK_Msk             (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)      /*!< 0x00000001 */
5459 #define FLASH_OPTCR_OPTLOCK                 FLASH_OPTCR_OPTLOCK_Msk                 /*!< FLASH_OPTCR lock option configuration bit */
5460 #define FLASH_OPTCR_OPTSTART_Pos            (1U)
5461 #define FLASH_OPTCR_OPTSTART_Msk            (0x1UL << FLASH_OPTCR_OPTSTART_Pos)     /*!< 0x00000002 */
5462 #define FLASH_OPTCR_OPTSTART                FLASH_OPTCR_OPTSTART_Msk                /*!< Option byte start change option configuration bit */
5463 #define FLASH_OPTCR_SWAP_BANK_Pos           (31U)
5464 #define FLASH_OPTCR_SWAP_BANK_Msk           (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos)    /*!< 0x80000000 */
5465 #define FLASH_OPTCR_SWAP_BANK               FLASH_OPTCR_SWAP_BANK_Msk               /*!< Bank swapping option configuration bit */
5466 
5467 /*******************  Bits definition for FLASH_SR register  ***********************/
5468 #define FLASH_SR_BSY_Pos                    (0U)
5469 #define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)             /*!< 0x00000001 */
5470 #define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                        /*!< Busy flag */
5471 #define FLASH_SR_WBNE_Pos                   (1U)
5472 #define FLASH_SR_WBNE_Msk                   (0x1UL << FLASH_SR_WBNE_Pos)            /*!< 0x00000002 */
5473 #define FLASH_SR_WBNE                       FLASH_SR_WBNE_Msk                       /*!< Write buffer not empty flag */
5474 #define FLASH_SR_DBNE_Pos                   (3U)
5475 #define FLASH_SR_DBNE_Msk                   (0x1UL << FLASH_SR_DBNE_Pos)            /*!< 0x00000008 */
5476 #define FLASH_SR_DBNE                       FLASH_SR_DBNE_Msk                       /*!< Data buffer not empty flag */
5477 #define FLASH_SR_EOP_Pos                    (16U)
5478 #define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)             /*!< 0x00010000 */
5479 #define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                        /*!< End-of-program flag */
5480 #define FLASH_SR_WRPERR_Pos                 (17U)
5481 #define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)          /*!< 0x00020000 */
5482 #define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                     /*!< Write protection error flag */
5483 #define FLASH_SR_PGSERR_Pos                 (18U)
5484 #define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)          /*!< 0x00040000 */
5485 #define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                     /*!< Programming sequence error flag */
5486 #define FLASH_SR_STRBERR_Pos                (19U)
5487 #define FLASH_SR_STRBERR_Msk                (0x1UL << FLASH_SR_STRBERR_Pos)         /*!< 0x00080000 */
5488 #define FLASH_SR_STRBERR                    FLASH_SR_STRBERR_Msk                    /*!< Strobe error flag */
5489 #define FLASH_SR_INCERR_Pos                 (20U)
5490 #define FLASH_SR_INCERR_Msk                 (0x1UL << FLASH_SR_INCERR_Pos)          /*!< 0x00100000 */
5491 #define FLASH_SR_INCERR                     FLASH_SR_INCERR_Msk                     /*!< Inconsistency error flag */
5492 #define FLASH_SR_OPTCHANGEERR_Pos           (23U)
5493 #define FLASH_SR_OPTCHANGEERR_Msk           (0x1UL << FLASH_SR_OPTCHANGEERR_Pos)    /*!< 0x00800000 */
5494 #define FLASH_SR_OPTCHANGEERR               FLASH_SR_OPTCHANGEERR_Msk               /*!< Option byte change error flag */
5495 
5496 /*******************  Bits definition for FLASH_CR register  ***********************/
5497 #define FLASH_CR_LOCK_Pos                   (0U)
5498 #define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)            /*!< 0x00000001 */
5499 #define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                       /*!< Configuration lock bit */
5500 #define FLASH_CR_PG_Pos                     (1U)
5501 #define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)              /*!< 0x00000002 */
5502 #define FLASH_CR_PG                         FLASH_CR_PG_Msk                         /*!< Programming control bit */
5503 #define FLASH_CR_SER_Pos                    (2U)
5504 #define FLASH_CR_SER_Msk                    (0x1UL << FLASH_CR_SER_Pos)             /*!< 0x00000004 */
5505 #define FLASH_CR_SER                        FLASH_CR_SER_Msk                        /*!< Sector erase request */
5506 #define FLASH_CR_BER_Pos                    (3U)
5507 #define FLASH_CR_BER_Msk                    (0x1UL << FLASH_CR_BER_Pos)             /*!< 0x00000008 */
5508 #define FLASH_CR_BER                        FLASH_CR_BER_Msk                        /*!< Bank erase request */
5509 #define FLASH_CR_FW_Pos                     (4U)
5510 #define FLASH_CR_FW_Msk                     (0x1UL << FLASH_CR_FW_Pos)              /*!< 0x00000010 */
5511 #define FLASH_CR_FW                         FLASH_CR_FW_Msk                         /*!< Write forcing control bit */
5512 #define FLASH_CR_START_Pos                  (5U)
5513 #define FLASH_CR_START_Msk                  (0x1UL << FLASH_CR_START_Pos)           /*!< 0x00000020 */
5514 #define FLASH_CR_START                      FLASH_CR_START_Msk                      /*!< Erase start control bit */
5515 #define FLASH_CR_SNB_Pos                    (6U)
5516 #define FLASH_CR_SNB_Msk                    (0x7FUL << FLASH_CR_SNB_Pos)            /*!< 0x00001FC0 */
5517 #define FLASH_CR_SNB                        FLASH_CR_SNB_Msk                        /*!< Sector erase selection number */
5518 #define FLASH_CR_SNB_0                      (0x01UL << FLASH_CR_SNB_Pos)            /*!< 0x00000040 */
5519 #define FLASH_CR_SNB_1                      (0x02UL << FLASH_CR_SNB_Pos)            /*!< 0x00000080 */
5520 #define FLASH_CR_SNB_2                      (0x04UL << FLASH_CR_SNB_Pos)            /*!< 0x00000100 */
5521 #define FLASH_CR_SNB_3                      (0x08UL << FLASH_CR_SNB_Pos)            /*!< 0x00000200 */
5522 #define FLASH_CR_SNB_4                      (0x10UL << FLASH_CR_SNB_Pos)            /*!< 0x00000400 */
5523 #define FLASH_CR_SNB_5                      (0x20UL << FLASH_CR_SNB_Pos)            /*!< 0x00000800 */
5524 #define FLASH_CR_SNB_6                      (0x40UL << FLASH_CR_SNB_Pos)            /*!< 0x00001000 */
5525 #define FLASH_CR_MER_Pos                    (15U)
5526 #define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)             /*!< 0x00008000 */
5527 #define FLASH_CR_MER                        FLASH_CR_MER_Msk                        /*!< Mass erase */
5528 #define FLASH_CR_EOPIE_Pos                  (16U)
5529 #define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)           /*!< 0x00010000 */
5530 #define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                      /*!< End-of-operation interrupt control bit */
5531 #define FLASH_CR_WRPERRIE_Pos               (17U)
5532 #define FLASH_CR_WRPERRIE_Msk               (0x1UL << FLASH_CR_WRPERRIE_Pos)        /*!< 0x00020000 */
5533 #define FLASH_CR_WRPERRIE                   FLASH_CR_WRPERRIE_Msk                   /*!< Write protection error interrupt enable bit */
5534 #define FLASH_CR_PGSERRIE_Pos               (18U)
5535 #define FLASH_CR_PGSERRIE_Msk               (0x1UL << FLASH_CR_PGSERRIE_Pos)        /*!< 0x00040000 */
5536 #define FLASH_CR_PGSERRIE                   FLASH_CR_PGSERRIE_Msk                   /*!< Programming sequence error interrupt enable bit */
5537 #define FLASH_CR_STRBERRIE_Pos              (19U)
5538 #define FLASH_CR_STRBERRIE_Msk              (0x1UL << FLASH_CR_STRBERRIE_Pos)       /*!< 0x00080000 */
5539 #define FLASH_CR_STRBERRIE                  FLASH_CR_STRBERRIE_Msk                  /*!< Strobe error interrupt enable bit */
5540 #define FLASH_CR_INCERRIE_Pos               (20U)
5541 #define FLASH_CR_INCERRIE_Msk               (0x1UL << FLASH_CR_INCERRIE_Pos)        /*!< 0x00100000 */
5542 #define FLASH_CR_INCERRIE                   FLASH_CR_INCERRIE_Msk                   /*!< Inconsistency error interrupt enable bit */
5543 #define FLASH_CR_OPTCHANGEERRIE_Pos         (23U)
5544 #define FLASH_CR_OPTCHANGEERRIE_Msk         (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos)  /*!< 0x00800000 */
5545 #define FLASH_CR_OPTCHANGEERRIE             FLASH_CR_OPTCHANGEERRIE_Msk             /*!< Option byte change error interrupt enable bit */
5546 #define FLASH_CR_INV_Pos                    (29U)
5547 #define FLASH_CR_INV_Msk                    (0x1UL << FLASH_CR_INV_Pos)             /*!< 0x20000000 */
5548 #define FLASH_CR_INV                        FLASH_CR_INV_Msk                        /*!< Flash Security State Invert */
5549 #define FLASH_CR_BKSEL_Pos                  (31U)
5550 #define FLASH_CR_BKSEL_Msk                  (0x1UL << FLASH_CR_BKSEL_Pos)           /*!< 0x10000000 */
5551 #define FLASH_CR_BKSEL                      FLASH_CR_BKSEL_Msk                      /*!< Bank selector */
5552 
5553 /*******************  Bits definition for FLASH_CCR register  *******************/
5554 #define FLASH_CCR_CLR_EOP_Pos               (16U)
5555 #define FLASH_CCR_CLR_EOP_Msk               (0x1UL << FLASH_CCR_CLR_EOP_Pos)        /*!< 0x00010000 */
5556 #define FLASH_CCR_CLR_EOP                   FLASH_CCR_CLR_EOP_Msk                   /*!< EOP flag clear bit */
5557 #define FLASH_CCR_CLR_WRPERR_Pos            (17U)
5558 #define FLASH_CCR_CLR_WRPERR_Msk            (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)     /*!< 0x00020000 */
5559 #define FLASH_CCR_CLR_WRPERR                FLASH_CCR_CLR_WRPERR_Msk                /*!< WRPERR flag clear bit */
5560 #define FLASH_CCR_CLR_PGSERR_Pos            (18U)
5561 #define FLASH_CCR_CLR_PGSERR_Msk            (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)     /*!< 0x00040000 */
5562 #define FLASH_CCR_CLR_PGSERR                FLASH_CCR_CLR_PGSERR_Msk                /*!< PGSERR flag clear bit */
5563 #define FLASH_CCR_CLR_STRBERR_Pos           (19U)
5564 #define FLASH_CCR_CLR_STRBERR_Msk           (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)    /*!< 0x00080000 */
5565 #define FLASH_CCR_CLR_STRBERR               FLASH_CCR_CLR_STRBERR_Msk               /*!< STRBERR flag clear bit */
5566 #define FLASH_CCR_CLR_INCERR_Pos            (20U)
5567 #define FLASH_CCR_CLR_INCERR_Msk            (0x1UL << FLASH_CCR_CLR_INCERR_Pos)     /*!< 0x00100000 */
5568 #define FLASH_CCR_CLR_INCERR                FLASH_CCR_CLR_INCERR_Msk                /*!< INCERR flag clear bit */
5569 #define FLASH_CCR_CLR_OPTCHANGEERR_Pos      (23U)
5570 #define FLASH_CCR_CLR_OPTCHANGEERR_Msk      (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */
5571 #define FLASH_CCR_CLR_OPTCHANGEERR          FLASH_CCR_CLR_OPTCHANGEERR_Msk            /*!< Option byte change error clear bit */
5572 
5573 /******************  Bits definition for FLASH_PRIVCFGR register  ***********/
5574 #define FLASH_PRIVCFGR_NSPRIV_Pos           (1U)
5575 #define FLASH_PRIVCFGR_NSPRIV_Msk           (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos)    /*!< 0x00000002 */
5576 #define FLASH_PRIVCFGR_NSPRIV               FLASH_PRIVCFGR_NSPRIV_Msk               /*!< Privilege protection for non-secure registers */
5577 
5578 
5579 /******************  Bits definition for FLASH_HDPEXTR register  *****************/
5580 #define FLASH_HDPEXTR_HDP1_EXT_Pos          (0U)
5581 #define FLASH_HDPEXTR_HDP1_EXT_Msk          (0x7UL << FLASH_HDPEXTR_HDP1_EXT_Pos)   /*!< 0x00000007 */
5582 #define FLASH_HDPEXTR_HDP1_EXT              FLASH_HDPEXTR_HDP1_EXT_Msk              /*!< HDP area extension in 8kB sectors in bank 1 */
5583 #define FLASH_HDPEXTR_HDP2_EXT_Pos          (16U)
5584 #define FLASH_HDPEXTR_HDP2_EXT_Msk          (0x7UL << FLASH_HDPEXTR_HDP2_EXT_Pos)   /*!< 0x00070000 */
5585 #define FLASH_HDPEXTR_HDP2_EXT              FLASH_HDPEXTR_HDP2_EXT_Msk              /*!< HDP area extension in 8kB sectors in bank 2 */
5586 
5587 /*******************  Bits definition for FLASH_OPTSR register  ***************/
5588 #define FLASH_OPTSR_BOR_LEV_Pos             (0U)
5589 #define FLASH_OPTSR_BOR_LEV_Msk             (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)      /*!< 0x00000003 */
5590 #define FLASH_OPTSR_BOR_LEV                 FLASH_OPTSR_BOR_LEV_Msk                 /*!< Brownout level option bit */
5591 #define FLASH_OPTSR_BOR_LEV_0               (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)      /*!< 0x00000001 */
5592 #define FLASH_OPTSR_BOR_LEV_1               (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)      /*!< 0x00000002 */
5593 #define FLASH_OPTSR_BORH_EN_Pos             (2U)
5594 #define FLASH_OPTSR_BORH_EN_Msk             (0x1UL << FLASH_OPTSR_BORH_EN_Pos)      /*!< 0x00000004 */
5595 #define FLASH_OPTSR_BORH_EN                 FLASH_OPTSR_BORH_EN_Msk                 /*!< Brownout high enable configuration bit */
5596 #define FLASH_OPTSR_IWDG_SW_Pos             (3U)
5597 #define FLASH_OPTSR_IWDG_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG_SW_Pos)      /*!< 0x00000008 */
5598 #define FLASH_OPTSR_IWDG_SW                 FLASH_OPTSR_IWDG_SW_Msk                 /*!< IWDG control mode option bit */
5599 #define FLASH_OPTSR_WWDG_SW_Pos             (4U)
5600 #define FLASH_OPTSR_WWDG_SW_Msk             (0x1UL << FLASH_OPTSR_WWDG_SW_Pos)      /*!< 0x00000010 */
5601 #define FLASH_OPTSR_WWDG_SW                 FLASH_OPTSR_WWDG_SW_Msk                 /*!< WWDG control mode option bit */
5602 #define FLASH_OPTSR_NRST_STOP_Pos           (6U)
5603 #define FLASH_OPTSR_NRST_STOP_Msk           (0x1UL << FLASH_OPTSR_NRST_STOP_Pos)    /*!< 0x00000040 */
5604 #define FLASH_OPTSR_NRST_STOP               FLASH_OPTSR_NRST_STOP_Msk               /*!< Stop mode entry reset option bit */
5605 #define FLASH_OPTSR_NRST_STDBY_Pos          (7U)
5606 #define FLASH_OPTSR_NRST_STDBY_Msk          (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos)   /*!< 0x00000080 */
5607 #define FLASH_OPTSR_NRST_STDBY              FLASH_OPTSR_NRST_STDBY_Msk              /*!< Standby mode entry reset option bit */
5608 #define FLASH_OPTSR_PRODUCT_STATE_Pos       (8U)
5609 #define FLASH_OPTSR_PRODUCT_STATE_Msk       (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */
5610 #define FLASH_OPTSR_PRODUCT_STATE           FLASH_OPTSR_PRODUCT_STATE_Msk             /*!< Life state code option byte */
5611 #define FLASH_OPTSR_IO_VDD_HSLV_Pos         (16U)
5612 #define FLASH_OPTSR_IO_VDD_HSLV_Msk         (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos)  /*!< 0x00010000 */
5613 #define FLASH_OPTSR_IO_VDD_HSLV             FLASH_OPTSR_IO_VDD_HSLV_Msk             /*!< VDD I/O high-speed at low-voltage option bit */
5614 #define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos      (17U)
5615 #define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk      (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */
5616 #define FLASH_OPTSR_IO_VDDIO2_HSLV          FLASH_OPTSR_IO_VDDIO2_HSLV_Msk            /*!< VDDIO2 I/O high-speed at low-voltage option bit */
5617 #define FLASH_OPTSR_IWDG_STOP_Pos           (20U)
5618 #define FLASH_OPTSR_IWDG_STOP_Msk           (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos)    /*!< 0x00100000 */
5619 #define FLASH_OPTSR_IWDG_STOP               FLASH_OPTSR_IWDG_STOP_Msk               /*!< Independent watchdog counter freeze in Stop mode */
5620 #define FLASH_OPTSR_IWDG_STDBY_Pos          (21U)
5621 #define FLASH_OPTSR_IWDG_STDBY_Msk          (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos)   /*!< 0x00200000 */
5622 #define FLASH_OPTSR_IWDG_STDBY              FLASH_OPTSR_IWDG_STDBY_Msk              /*!< Independent watchdog counter freeze in Standby mode */
5623 #define FLASH_OPTSR_SWAP_BANK_Pos           (31U)
5624 #define FLASH_OPTSR_SWAP_BANK_Msk           (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos)    /*!< 0x80000000 */
5625 #define FLASH_OPTSR_SWAP_BANK               FLASH_OPTSR_SWAP_BANK_Msk               /*!< Bank swapping option bit */
5626 
5627 /*******************  Bits definition for FLASH_EPOCHR register  ***************/
5628 #define FLASH_EPOCHR_EPOCH_Pos              (0U)
5629 #define FLASH_EPOCHR_EPOCH_Msk              (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos)  /*!< 0x00FFFFFF */
5630 #define FLASH_EPOCHR_EPOCH                  FLASH_EPOCHR_EPOCH_Msk                  /*!< EPOCH counter */
5631 
5632 /*******************  Bits definition for FLASH_OPTSR2 register  ***************/
5633 #define FLASH_OPTSR2_SRAM2_RST_Pos          (3U)
5634 #define FLASH_OPTSR2_SRAM2_RST_Msk          (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos)   /*!< 0x00000008 */
5635 #define FLASH_OPTSR2_SRAM2_RST              FLASH_OPTSR2_SRAM2_RST_Msk              /*!< SRAM2 erased when a system reset occurs*/
5636 #define FLASH_OPTSR2_BKPRAM_ECC_Pos         (4U)
5637 #define FLASH_OPTSR2_BKPRAM_ECC_Msk         (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos)  /*!< 0x00000010 */
5638 #define FLASH_OPTSR2_BKPRAM_ECC             FLASH_OPTSR2_BKPRAM_ECC_Msk             /*!< Backup RAM ECC detection and correction enable */
5639 #define FLASH_OPTSR2_SRAM2_ECC_Pos          (6U)
5640 #define FLASH_OPTSR2_SRAM2_ECC_Msk          (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos)   /*!< 0x00000040 */
5641 #define FLASH_OPTSR2_SRAM2_ECC              FLASH_OPTSR2_SRAM2_ECC_Msk              /*!< SRAM2 ECC detection and correction disable */
5642 #define FLASH_OPTSR2_SRAM1_RST_Pos          (9U)
5643 #define FLASH_OPTSR2_SRAM1_RST_Msk          (0x1UL << FLASH_OPTSR2_SRAM1_RST_Pos)    /*!< 0x00000200 */
5644 #define FLASH_OPTSR2_SRAM1_RST              FLASH_OPTSR2_SRAM1_RST_Msk               /*!< SRAM1 erase upon a system reset */
5645 #define FLASH_OPTSR2_SRAM1_ECC_Pos          (10U)
5646 #define FLASH_OPTSR2_SRAM1_ECC_Msk          (0x1UL << FLASH_OPTSR2_SRAM1_ECC_Pos)    /*!< 0x00000400 */
5647 #define FLASH_OPTSR2_SRAM1_ECC              FLASH_OPTSR2_SRAM1_ECC_Msk               /*!< SRAM1 ECC detection and correction disable */
5648 
5649 /****************  Bits definition for FLASH_BOOTR register  **********************/
5650 #define FLASH_BOOTR_BOOT_LOCK_Pos           (0U)
5651 #define FLASH_BOOTR_BOOT_LOCK_Msk           (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos)   /*!< 0x000000FF */
5652 #define FLASH_BOOTR_BOOT_LOCK               FLASH_BOOTR_BOOT_LOCK_Msk               /*!< Boot Lock */
5653 #define FLASH_BOOTR_BOOTADD_Pos             (8U)
5654 #define FLASH_BOOTR_BOOTADD_Msk             (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */
5655 #define FLASH_BOOTR_BOOTADD                 FLASH_BOOTR_BOOTADD_Msk                 /*!< Boot address */
5656 
5657 /****************  Bits definition for FLASH_PRIVBBR register  *******************/
5658 #define FLASH_PRIVBBR_PRIVBB_Pos            (0U)
5659 #define FLASH_PRIVBBR_PRIVBB_Msk            (0x000000FFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0x000000FF */
5660 #define FLASH_PRIVBBR_PRIVBB                FLASH_PRIVBBR_PRIVBB_Msk                   /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */
5661 
5662 
5663 /*****************  Bits definition for FLASH_WRPR register  *********************/
5664 #define FLASH_WRPR_WRPSG_Pos                (0U)
5665 #define FLASH_WRPR_WRPSG_Msk                (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */
5666 #define FLASH_WRPR_WRPSG                    FLASH_WRPR_WRPSG_Msk  /*!< Sector group protection option status */
5667 
5668 
5669 /*****************  Bits definition for FLASH_HDPR register  ********************/
5670 #define FLASH_HDPR_HDP_STRT_Pos             (0U)
5671 #define FLASH_HDPR_HDP_STRT_Msk             (0x07UL << FLASH_HDPR_HDP_STRT_Pos)     /*!< 0x00000007 */
5672 #define FLASH_HDPR_HDP_STRT                 FLASH_HDPR_HDP_STRT_Msk                 /*!< Start sector of hide protection area */
5673 #define FLASH_HDPR_HDP_END_Pos              (16U)
5674 #define FLASH_HDPR_HDP_END_Msk              (0x07UL << FLASH_HDPR_HDP_END_Pos)      /*!< 0x00070000 */
5675 #define FLASH_HDPR_HDP_END                  FLASH_HDPR_HDP_END_Msk                  /*!< End sector of hide protection area */
5676 
5677 /*******************  Bits definition for FLASH_ECCR register  ***************/
5678 #define FLASH_ECCR_ADDR_ECC_Pos             (0U)
5679 #define FLASH_ECCR_ADDR_ECC_Msk             (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos)   /*!< 0x0000FFFF */
5680 #define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk                 /*!< ECC fail address */
5681 #define FLASH_ECCR_BK_ECC_Pos               (22U)
5682 #define FLASH_ECCR_BK_ECC_Msk               (0x1UL << FLASH_ECCR_BK_ECC_Pos)        /*!< 0x00400000 */
5683 #define FLASH_ECCR_BK_ECC                   FLASH_ECCR_BK_ECC_Msk                   /*!< ECC fail bank */
5684 #define FLASH_ECCR_SYSF_ECC_Pos             (23U)
5685 #define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)      /*!< 0x00800000 */
5686 #define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk                 /*!< System Flash ECC fail */
5687 #define FLASH_ECCR_OTP_ECC_Pos              (24U)
5688 #define FLASH_ECCR_OTP_ECC_Msk              (0x1UL << FLASH_ECCR_OTP_ECC_Pos)       /*!< 0x01000000 */
5689 #define FLASH_ECCR_OTP_ECC                  FLASH_ECCR_OTP_ECC_Msk                  /*!< Flash OTP ECC fail */
5690 #define FLASH_ECCR_ECCIE_Pos                (25U)
5691 #define FLASH_ECCR_ECCIE_Msk                (0x1UL << FLASH_ECCR_ECCIE_Pos)         /*!< 0x02000000 */
5692 #define FLASH_ECCR_ECCIE                    FLASH_ECCR_ECCIE_Msk                    /*!< ECC correction interrupt enable */
5693 #define FLASH_ECCR_ECCC_Pos                 (30U)
5694 #define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)          /*!< 0x40000000 */
5695 #define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk                     /*!< ECC correction */
5696 #define FLASH_ECCR_ECCD_Pos                 (31U)
5697 #define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)          /*!< 0x80000000 */
5698 #define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk                     /*!< ECC detection */
5699 
5700 /*******************  Bits definition for FLASH_ECCDR register  ***************/
5701 #define FLASH_ECCDR_FAIL_DATA_Pos           (0U)
5702 #define FLASH_ECCDR_FAIL_DATA_Msk           (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */
5703 #define FLASH_ECCDR_FAIL_DATA               FLASH_ECCDR_FAIL_DATA_Msk               /*!< ECC fail data */
5704 
5705 
5706 /******************************************************************************/
5707 /*                                                                            */
5708 /*                       General Purpose IOs (GPIO)                           */
5709 /*                                                                            */
5710 /******************************************************************************/
5711 /******************  Bits definition for GPIO_MODER register  *****************/
5712 #define GPIO_MODER_MODE0_Pos                (0U)
5713 #define GPIO_MODER_MODE0_Msk                (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
5714 #define GPIO_MODER_MODE0                    GPIO_MODER_MODE0_Msk
5715 #define GPIO_MODER_MODE0_0                  (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
5716 #define GPIO_MODER_MODE0_1                  (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
5717 #define GPIO_MODER_MODE1_Pos                (2U)
5718 #define GPIO_MODER_MODE1_Msk                (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
5719 #define GPIO_MODER_MODE1                    GPIO_MODER_MODE1_Msk
5720 #define GPIO_MODER_MODE1_0                  (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
5721 #define GPIO_MODER_MODE1_1                  (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
5722 #define GPIO_MODER_MODE2_Pos                (4U)
5723 #define GPIO_MODER_MODE2_Msk                (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
5724 #define GPIO_MODER_MODE2                    GPIO_MODER_MODE2_Msk
5725 #define GPIO_MODER_MODE2_0                  (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
5726 #define GPIO_MODER_MODE2_1                  (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
5727 #define GPIO_MODER_MODE3_Pos                (6U)
5728 #define GPIO_MODER_MODE3_Msk                (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
5729 #define GPIO_MODER_MODE3                    GPIO_MODER_MODE3_Msk
5730 #define GPIO_MODER_MODE3_0                  (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
5731 #define GPIO_MODER_MODE3_1                  (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
5732 #define GPIO_MODER_MODE4_Pos                (8U)
5733 #define GPIO_MODER_MODE4_Msk                (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
5734 #define GPIO_MODER_MODE4                    GPIO_MODER_MODE4_Msk
5735 #define GPIO_MODER_MODE4_0                  (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
5736 #define GPIO_MODER_MODE4_1                  (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
5737 #define GPIO_MODER_MODE5_Pos                (10U)
5738 #define GPIO_MODER_MODE5_Msk                (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
5739 #define GPIO_MODER_MODE5                    GPIO_MODER_MODE5_Msk
5740 #define GPIO_MODER_MODE5_0                  (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
5741 #define GPIO_MODER_MODE5_1                  (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
5742 #define GPIO_MODER_MODE6_Pos                (12U)
5743 #define GPIO_MODER_MODE6_Msk                (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
5744 #define GPIO_MODER_MODE6                    GPIO_MODER_MODE6_Msk
5745 #define GPIO_MODER_MODE6_0                  (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
5746 #define GPIO_MODER_MODE6_1                  (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
5747 #define GPIO_MODER_MODE7_Pos                (14U)
5748 #define GPIO_MODER_MODE7_Msk                (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
5749 #define GPIO_MODER_MODE7                    GPIO_MODER_MODE7_Msk
5750 #define GPIO_MODER_MODE7_0                  (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
5751 #define GPIO_MODER_MODE7_1                  (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
5752 #define GPIO_MODER_MODE8_Pos                (16U)
5753 #define GPIO_MODER_MODE8_Msk                (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
5754 #define GPIO_MODER_MODE8                    GPIO_MODER_MODE8_Msk
5755 #define GPIO_MODER_MODE8_0                  (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
5756 #define GPIO_MODER_MODE8_1                  (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
5757 #define GPIO_MODER_MODE9_Pos                (18U)
5758 #define GPIO_MODER_MODE9_Msk                (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
5759 #define GPIO_MODER_MODE9                    GPIO_MODER_MODE9_Msk
5760 #define GPIO_MODER_MODE9_0                  (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
5761 #define GPIO_MODER_MODE9_1                  (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
5762 #define GPIO_MODER_MODE10_Pos               (20U)
5763 #define GPIO_MODER_MODE10_Msk               (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
5764 #define GPIO_MODER_MODE10                   GPIO_MODER_MODE10_Msk
5765 #define GPIO_MODER_MODE10_0                 (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
5766 #define GPIO_MODER_MODE10_1                 (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
5767 #define GPIO_MODER_MODE11_Pos               (22U)
5768 #define GPIO_MODER_MODE11_Msk               (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
5769 #define GPIO_MODER_MODE11                   GPIO_MODER_MODE11_Msk
5770 #define GPIO_MODER_MODE11_0                 (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
5771 #define GPIO_MODER_MODE11_1                 (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
5772 #define GPIO_MODER_MODE12_Pos               (24U)
5773 #define GPIO_MODER_MODE12_Msk               (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
5774 #define GPIO_MODER_MODE12                   GPIO_MODER_MODE12_Msk
5775 #define GPIO_MODER_MODE12_0                 (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
5776 #define GPIO_MODER_MODE12_1                 (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
5777 #define GPIO_MODER_MODE13_Pos               (26U)
5778 #define GPIO_MODER_MODE13_Msk               (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
5779 #define GPIO_MODER_MODE13                   GPIO_MODER_MODE13_Msk
5780 #define GPIO_MODER_MODE13_0                 (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
5781 #define GPIO_MODER_MODE13_1                 (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
5782 #define GPIO_MODER_MODE14_Pos               (28U)
5783 #define GPIO_MODER_MODE14_Msk               (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
5784 #define GPIO_MODER_MODE14                   GPIO_MODER_MODE14_Msk
5785 #define GPIO_MODER_MODE14_0                 (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
5786 #define GPIO_MODER_MODE14_1                 (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
5787 #define GPIO_MODER_MODE15_Pos               (30U)
5788 #define GPIO_MODER_MODE15_Msk               (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
5789 #define GPIO_MODER_MODE15                   GPIO_MODER_MODE15_Msk
5790 #define GPIO_MODER_MODE15_0                 (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
5791 #define GPIO_MODER_MODE15_1                 (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
5792 
5793 /******************  Bits definition for GPIO_OTYPER register  ****************/
5794 #define GPIO_OTYPER_OT0_Pos                 (0U)
5795 #define GPIO_OTYPER_OT0_Msk                 (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
5796 #define GPIO_OTYPER_OT0                     GPIO_OTYPER_OT0_Msk
5797 #define GPIO_OTYPER_OT1_Pos                 (1U)
5798 #define GPIO_OTYPER_OT1_Msk                 (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
5799 #define GPIO_OTYPER_OT1                     GPIO_OTYPER_OT1_Msk
5800 #define GPIO_OTYPER_OT2_Pos                 (2U)
5801 #define GPIO_OTYPER_OT2_Msk                 (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
5802 #define GPIO_OTYPER_OT2                     GPIO_OTYPER_OT2_Msk
5803 #define GPIO_OTYPER_OT3_Pos                 (3U)
5804 #define GPIO_OTYPER_OT3_Msk                 (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
5805 #define GPIO_OTYPER_OT3                     GPIO_OTYPER_OT3_Msk
5806 #define GPIO_OTYPER_OT4_Pos                 (4U)
5807 #define GPIO_OTYPER_OT4_Msk                 (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
5808 #define GPIO_OTYPER_OT4                     GPIO_OTYPER_OT4_Msk
5809 #define GPIO_OTYPER_OT5_Pos                 (5U)
5810 #define GPIO_OTYPER_OT5_Msk                 (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
5811 #define GPIO_OTYPER_OT5                     GPIO_OTYPER_OT5_Msk
5812 #define GPIO_OTYPER_OT6_Pos                 (6U)
5813 #define GPIO_OTYPER_OT6_Msk                 (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
5814 #define GPIO_OTYPER_OT6                     GPIO_OTYPER_OT6_Msk
5815 #define GPIO_OTYPER_OT7_Pos                 (7U)
5816 #define GPIO_OTYPER_OT7_Msk                 (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
5817 #define GPIO_OTYPER_OT7                     GPIO_OTYPER_OT7_Msk
5818 #define GPIO_OTYPER_OT8_Pos                 (8U)
5819 #define GPIO_OTYPER_OT8_Msk                 (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
5820 #define GPIO_OTYPER_OT8                     GPIO_OTYPER_OT8_Msk
5821 #define GPIO_OTYPER_OT9_Pos                 (9U)
5822 #define GPIO_OTYPER_OT9_Msk                 (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
5823 #define GPIO_OTYPER_OT9                     GPIO_OTYPER_OT9_Msk
5824 #define GPIO_OTYPER_OT10_Pos                (10U)
5825 #define GPIO_OTYPER_OT10_Msk                (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
5826 #define GPIO_OTYPER_OT10                    GPIO_OTYPER_OT10_Msk
5827 #define GPIO_OTYPER_OT11_Pos                (11U)
5828 #define GPIO_OTYPER_OT11_Msk                (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
5829 #define GPIO_OTYPER_OT11                    GPIO_OTYPER_OT11_Msk
5830 #define GPIO_OTYPER_OT12_Pos                (12U)
5831 #define GPIO_OTYPER_OT12_Msk                (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
5832 #define GPIO_OTYPER_OT12                    GPIO_OTYPER_OT12_Msk
5833 #define GPIO_OTYPER_OT13_Pos                (13U)
5834 #define GPIO_OTYPER_OT13_Msk                (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
5835 #define GPIO_OTYPER_OT13                    GPIO_OTYPER_OT13_Msk
5836 #define GPIO_OTYPER_OT14_Pos                (14U)
5837 #define GPIO_OTYPER_OT14_Msk                (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
5838 #define GPIO_OTYPER_OT14                    GPIO_OTYPER_OT14_Msk
5839 #define GPIO_OTYPER_OT15_Pos                (15U)
5840 #define GPIO_OTYPER_OT15_Msk                (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
5841 #define GPIO_OTYPER_OT15                    GPIO_OTYPER_OT15_Msk
5842 
5843 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
5844 #define GPIO_OSPEEDR_OSPEED0_Pos            (0U)
5845 #define GPIO_OSPEEDR_OSPEED0_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
5846 #define GPIO_OSPEEDR_OSPEED0                GPIO_OSPEEDR_OSPEED0_Msk
5847 #define GPIO_OSPEEDR_OSPEED0_0              (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
5848 #define GPIO_OSPEEDR_OSPEED0_1              (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
5849 #define GPIO_OSPEEDR_OSPEED1_Pos            (2U)
5850 #define GPIO_OSPEEDR_OSPEED1_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
5851 #define GPIO_OSPEEDR_OSPEED1                GPIO_OSPEEDR_OSPEED1_Msk
5852 #define GPIO_OSPEEDR_OSPEED1_0              (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
5853 #define GPIO_OSPEEDR_OSPEED1_1              (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
5854 #define GPIO_OSPEEDR_OSPEED2_Pos            (4U)
5855 #define GPIO_OSPEEDR_OSPEED2_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
5856 #define GPIO_OSPEEDR_OSPEED2                GPIO_OSPEEDR_OSPEED2_Msk
5857 #define GPIO_OSPEEDR_OSPEED2_0              (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
5858 #define GPIO_OSPEEDR_OSPEED2_1              (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
5859 #define GPIO_OSPEEDR_OSPEED3_Pos            (6U)
5860 #define GPIO_OSPEEDR_OSPEED3_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
5861 #define GPIO_OSPEEDR_OSPEED3                GPIO_OSPEEDR_OSPEED3_Msk
5862 #define GPIO_OSPEEDR_OSPEED3_0              (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
5863 #define GPIO_OSPEEDR_OSPEED3_1              (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
5864 #define GPIO_OSPEEDR_OSPEED4_Pos            (8U)
5865 #define GPIO_OSPEEDR_OSPEED4_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
5866 #define GPIO_OSPEEDR_OSPEED4                GPIO_OSPEEDR_OSPEED4_Msk
5867 #define GPIO_OSPEEDR_OSPEED4_0              (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
5868 #define GPIO_OSPEEDR_OSPEED4_1              (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
5869 #define GPIO_OSPEEDR_OSPEED5_Pos            (10U)
5870 #define GPIO_OSPEEDR_OSPEED5_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
5871 #define GPIO_OSPEEDR_OSPEED5                GPIO_OSPEEDR_OSPEED5_Msk
5872 #define GPIO_OSPEEDR_OSPEED5_0              (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
5873 #define GPIO_OSPEEDR_OSPEED5_1              (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
5874 #define GPIO_OSPEEDR_OSPEED6_Pos            (12U)
5875 #define GPIO_OSPEEDR_OSPEED6_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
5876 #define GPIO_OSPEEDR_OSPEED6                GPIO_OSPEEDR_OSPEED6_Msk
5877 #define GPIO_OSPEEDR_OSPEED6_0              (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
5878 #define GPIO_OSPEEDR_OSPEED6_1              (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
5879 #define GPIO_OSPEEDR_OSPEED7_Pos            (14U)
5880 #define GPIO_OSPEEDR_OSPEED7_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
5881 #define GPIO_OSPEEDR_OSPEED7                GPIO_OSPEEDR_OSPEED7_Msk
5882 #define GPIO_OSPEEDR_OSPEED7_0              (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
5883 #define GPIO_OSPEEDR_OSPEED7_1              (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
5884 #define GPIO_OSPEEDR_OSPEED8_Pos            (16U)
5885 #define GPIO_OSPEEDR_OSPEED8_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
5886 #define GPIO_OSPEEDR_OSPEED8                GPIO_OSPEEDR_OSPEED8_Msk
5887 #define GPIO_OSPEEDR_OSPEED8_0              (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
5888 #define GPIO_OSPEEDR_OSPEED8_1              (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
5889 #define GPIO_OSPEEDR_OSPEED9_Pos            (18U)
5890 #define GPIO_OSPEEDR_OSPEED9_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
5891 #define GPIO_OSPEEDR_OSPEED9                GPIO_OSPEEDR_OSPEED9_Msk
5892 #define GPIO_OSPEEDR_OSPEED9_0              (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
5893 #define GPIO_OSPEEDR_OSPEED9_1              (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
5894 #define GPIO_OSPEEDR_OSPEED10_Pos           (20U)
5895 #define GPIO_OSPEEDR_OSPEED10_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
5896 #define GPIO_OSPEEDR_OSPEED10               GPIO_OSPEEDR_OSPEED10_Msk
5897 #define GPIO_OSPEEDR_OSPEED10_0             (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
5898 #define GPIO_OSPEEDR_OSPEED10_1             (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
5899 #define GPIO_OSPEEDR_OSPEED11_Pos           (22U)
5900 #define GPIO_OSPEEDR_OSPEED11_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
5901 #define GPIO_OSPEEDR_OSPEED11               GPIO_OSPEEDR_OSPEED11_Msk
5902 #define GPIO_OSPEEDR_OSPEED11_0             (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
5903 #define GPIO_OSPEEDR_OSPEED11_1             (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
5904 #define GPIO_OSPEEDR_OSPEED12_Pos           (24U)
5905 #define GPIO_OSPEEDR_OSPEED12_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
5906 #define GPIO_OSPEEDR_OSPEED12               GPIO_OSPEEDR_OSPEED12_Msk
5907 #define GPIO_OSPEEDR_OSPEED12_0             (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
5908 #define GPIO_OSPEEDR_OSPEED12_1             (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
5909 #define GPIO_OSPEEDR_OSPEED13_Pos           (26U)
5910 #define GPIO_OSPEEDR_OSPEED13_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
5911 #define GPIO_OSPEEDR_OSPEED13               GPIO_OSPEEDR_OSPEED13_Msk
5912 #define GPIO_OSPEEDR_OSPEED13_0             (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
5913 #define GPIO_OSPEEDR_OSPEED13_1             (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
5914 #define GPIO_OSPEEDR_OSPEED14_Pos           (28U)
5915 #define GPIO_OSPEEDR_OSPEED14_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
5916 #define GPIO_OSPEEDR_OSPEED14               GPIO_OSPEEDR_OSPEED14_Msk
5917 #define GPIO_OSPEEDR_OSPEED14_0             (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
5918 #define GPIO_OSPEEDR_OSPEED14_1             (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
5919 #define GPIO_OSPEEDR_OSPEED15_Pos           (30U)
5920 #define GPIO_OSPEEDR_OSPEED15_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
5921 #define GPIO_OSPEEDR_OSPEED15               GPIO_OSPEEDR_OSPEED15_Msk
5922 #define GPIO_OSPEEDR_OSPEED15_0             (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
5923 #define GPIO_OSPEEDR_OSPEED15_1             (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
5924 
5925 /******************  Bits definition for GPIO_PUPDR register  *****************/
5926 #define GPIO_PUPDR_PUPD0_Pos                (0U)
5927 #define GPIO_PUPDR_PUPD0_Msk                (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
5928 #define GPIO_PUPDR_PUPD0                    GPIO_PUPDR_PUPD0_Msk
5929 #define GPIO_PUPDR_PUPD0_0                  (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
5930 #define GPIO_PUPDR_PUPD0_1                  (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
5931 #define GPIO_PUPDR_PUPD1_Pos                (2U)
5932 #define GPIO_PUPDR_PUPD1_Msk                (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
5933 #define GPIO_PUPDR_PUPD1                    GPIO_PUPDR_PUPD1_Msk
5934 #define GPIO_PUPDR_PUPD1_0                  (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
5935 #define GPIO_PUPDR_PUPD1_1                  (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
5936 #define GPIO_PUPDR_PUPD2_Pos                (4U)
5937 #define GPIO_PUPDR_PUPD2_Msk                (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
5938 #define GPIO_PUPDR_PUPD2                    GPIO_PUPDR_PUPD2_Msk
5939 #define GPIO_PUPDR_PUPD2_0                  (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
5940 #define GPIO_PUPDR_PUPD2_1                  (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
5941 #define GPIO_PUPDR_PUPD3_Pos                (6U)
5942 #define GPIO_PUPDR_PUPD3_Msk                (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
5943 #define GPIO_PUPDR_PUPD3                    GPIO_PUPDR_PUPD3_Msk
5944 #define GPIO_PUPDR_PUPD3_0                  (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
5945 #define GPIO_PUPDR_PUPD3_1                  (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
5946 #define GPIO_PUPDR_PUPD4_Pos                (8U)
5947 #define GPIO_PUPDR_PUPD4_Msk                (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
5948 #define GPIO_PUPDR_PUPD4                    GPIO_PUPDR_PUPD4_Msk
5949 #define GPIO_PUPDR_PUPD4_0                  (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
5950 #define GPIO_PUPDR_PUPD4_1                  (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
5951 #define GPIO_PUPDR_PUPD5_Pos                (10U)
5952 #define GPIO_PUPDR_PUPD5_Msk                (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
5953 #define GPIO_PUPDR_PUPD5                    GPIO_PUPDR_PUPD5_Msk
5954 #define GPIO_PUPDR_PUPD5_0                  (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
5955 #define GPIO_PUPDR_PUPD5_1                  (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
5956 #define GPIO_PUPDR_PUPD6_Pos                (12U)
5957 #define GPIO_PUPDR_PUPD6_Msk                (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
5958 #define GPIO_PUPDR_PUPD6                    GPIO_PUPDR_PUPD6_Msk
5959 #define GPIO_PUPDR_PUPD6_0                  (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
5960 #define GPIO_PUPDR_PUPD6_1                  (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
5961 #define GPIO_PUPDR_PUPD7_Pos                (14U)
5962 #define GPIO_PUPDR_PUPD7_Msk                (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
5963 #define GPIO_PUPDR_PUPD7                    GPIO_PUPDR_PUPD7_Msk
5964 #define GPIO_PUPDR_PUPD7_0                  (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
5965 #define GPIO_PUPDR_PUPD7_1                  (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
5966 #define GPIO_PUPDR_PUPD8_Pos                (16U)
5967 #define GPIO_PUPDR_PUPD8_Msk                (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
5968 #define GPIO_PUPDR_PUPD8                    GPIO_PUPDR_PUPD8_Msk
5969 #define GPIO_PUPDR_PUPD8_0                  (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
5970 #define GPIO_PUPDR_PUPD8_1                  (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
5971 #define GPIO_PUPDR_PUPD9_Pos                (18U)
5972 #define GPIO_PUPDR_PUPD9_Msk                (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
5973 #define GPIO_PUPDR_PUPD9                    GPIO_PUPDR_PUPD9_Msk
5974 #define GPIO_PUPDR_PUPD9_0                  (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
5975 #define GPIO_PUPDR_PUPD9_1                  (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
5976 #define GPIO_PUPDR_PUPD10_Pos               (20U)
5977 #define GPIO_PUPDR_PUPD10_Msk               (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
5978 #define GPIO_PUPDR_PUPD10                   GPIO_PUPDR_PUPD10_Msk
5979 #define GPIO_PUPDR_PUPD10_0                 (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
5980 #define GPIO_PUPDR_PUPD10_1                 (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
5981 #define GPIO_PUPDR_PUPD11_Pos               (22U)
5982 #define GPIO_PUPDR_PUPD11_Msk               (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
5983 #define GPIO_PUPDR_PUPD11                   GPIO_PUPDR_PUPD11_Msk
5984 #define GPIO_PUPDR_PUPD11_0                 (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
5985 #define GPIO_PUPDR_PUPD11_1                 (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
5986 #define GPIO_PUPDR_PUPD12_Pos               (24U)
5987 #define GPIO_PUPDR_PUPD12_Msk               (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
5988 #define GPIO_PUPDR_PUPD12                   GPIO_PUPDR_PUPD12_Msk
5989 #define GPIO_PUPDR_PUPD12_0                 (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
5990 #define GPIO_PUPDR_PUPD12_1                 (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
5991 #define GPIO_PUPDR_PUPD13_Pos               (26U)
5992 #define GPIO_PUPDR_PUPD13_Msk               (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
5993 #define GPIO_PUPDR_PUPD13                   GPIO_PUPDR_PUPD13_Msk
5994 #define GPIO_PUPDR_PUPD13_0                 (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
5995 #define GPIO_PUPDR_PUPD13_1                 (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
5996 #define GPIO_PUPDR_PUPD14_Pos               (28U)
5997 #define GPIO_PUPDR_PUPD14_Msk               (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
5998 #define GPIO_PUPDR_PUPD14                   GPIO_PUPDR_PUPD14_Msk
5999 #define GPIO_PUPDR_PUPD14_0                 (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
6000 #define GPIO_PUPDR_PUPD14_1                 (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
6001 #define GPIO_PUPDR_PUPD15_Pos               (30U)
6002 #define GPIO_PUPDR_PUPD15_Msk               (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
6003 #define GPIO_PUPDR_PUPD15                   GPIO_PUPDR_PUPD15_Msk
6004 #define GPIO_PUPDR_PUPD15_0                 (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
6005 #define GPIO_PUPDR_PUPD15_1                 (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
6006 
6007 /******************  Bits definition for GPIO_IDR register  *******************/
6008 #define GPIO_IDR_ID0_Pos                    (0U)
6009 #define GPIO_IDR_ID0_Msk                    (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
6010 #define GPIO_IDR_ID0                        GPIO_IDR_ID0_Msk
6011 #define GPIO_IDR_ID1_Pos                    (1U)
6012 #define GPIO_IDR_ID1_Msk                    (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
6013 #define GPIO_IDR_ID1                        GPIO_IDR_ID1_Msk
6014 #define GPIO_IDR_ID2_Pos                    (2U)
6015 #define GPIO_IDR_ID2_Msk                    (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
6016 #define GPIO_IDR_ID2                        GPIO_IDR_ID2_Msk
6017 #define GPIO_IDR_ID3_Pos                    (3U)
6018 #define GPIO_IDR_ID3_Msk                    (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
6019 #define GPIO_IDR_ID3                        GPIO_IDR_ID3_Msk
6020 #define GPIO_IDR_ID4_Pos                    (4U)
6021 #define GPIO_IDR_ID4_Msk                    (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
6022 #define GPIO_IDR_ID4                        GPIO_IDR_ID4_Msk
6023 #define GPIO_IDR_ID5_Pos                    (5U)
6024 #define GPIO_IDR_ID5_Msk                    (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
6025 #define GPIO_IDR_ID5                        GPIO_IDR_ID5_Msk
6026 #define GPIO_IDR_ID6_Pos                    (6U)
6027 #define GPIO_IDR_ID6_Msk                    (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
6028 #define GPIO_IDR_ID6                        GPIO_IDR_ID6_Msk
6029 #define GPIO_IDR_ID7_Pos                    (7U)
6030 #define GPIO_IDR_ID7_Msk                    (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
6031 #define GPIO_IDR_ID7                        GPIO_IDR_ID7_Msk
6032 #define GPIO_IDR_ID8_Pos                    (8U)
6033 #define GPIO_IDR_ID8_Msk                    (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
6034 #define GPIO_IDR_ID8                        GPIO_IDR_ID8_Msk
6035 #define GPIO_IDR_ID9_Pos                    (9U)
6036 #define GPIO_IDR_ID9_Msk                    (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
6037 #define GPIO_IDR_ID9                        GPIO_IDR_ID9_Msk
6038 #define GPIO_IDR_ID10_Pos                   (10U)
6039 #define GPIO_IDR_ID10_Msk                   (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
6040 #define GPIO_IDR_ID10                       GPIO_IDR_ID10_Msk
6041 #define GPIO_IDR_ID11_Pos                   (11U)
6042 #define GPIO_IDR_ID11_Msk                   (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
6043 #define GPIO_IDR_ID11                       GPIO_IDR_ID11_Msk
6044 #define GPIO_IDR_ID12_Pos                   (12U)
6045 #define GPIO_IDR_ID12_Msk                   (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
6046 #define GPIO_IDR_ID12                       GPIO_IDR_ID12_Msk
6047 #define GPIO_IDR_ID13_Pos                   (13U)
6048 #define GPIO_IDR_ID13_Msk                   (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
6049 #define GPIO_IDR_ID13                       GPIO_IDR_ID13_Msk
6050 #define GPIO_IDR_ID14_Pos                   (14U)
6051 #define GPIO_IDR_ID14_Msk                   (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
6052 #define GPIO_IDR_ID14                       GPIO_IDR_ID14_Msk
6053 #define GPIO_IDR_ID15_Pos                   (15U)
6054 #define GPIO_IDR_ID15_Msk                   (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
6055 #define GPIO_IDR_ID15                       GPIO_IDR_ID15_Msk
6056 
6057 /******************  Bits definition for GPIO_ODR register  *******************/
6058 #define GPIO_ODR_OD0_Pos                    (0U)
6059 #define GPIO_ODR_OD0_Msk                    (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
6060 #define GPIO_ODR_OD0                        GPIO_ODR_OD0_Msk
6061 #define GPIO_ODR_OD1_Pos                    (1U)
6062 #define GPIO_ODR_OD1_Msk                    (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
6063 #define GPIO_ODR_OD1                        GPIO_ODR_OD1_Msk
6064 #define GPIO_ODR_OD2_Pos                    (2U)
6065 #define GPIO_ODR_OD2_Msk                    (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
6066 #define GPIO_ODR_OD2                        GPIO_ODR_OD2_Msk
6067 #define GPIO_ODR_OD3_Pos                    (3U)
6068 #define GPIO_ODR_OD3_Msk                    (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
6069 #define GPIO_ODR_OD3                        GPIO_ODR_OD3_Msk
6070 #define GPIO_ODR_OD4_Pos                    (4U)
6071 #define GPIO_ODR_OD4_Msk                    (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
6072 #define GPIO_ODR_OD4                        GPIO_ODR_OD4_Msk
6073 #define GPIO_ODR_OD5_Pos                    (5U)
6074 #define GPIO_ODR_OD5_Msk                    (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
6075 #define GPIO_ODR_OD5                        GPIO_ODR_OD5_Msk
6076 #define GPIO_ODR_OD6_Pos                    (6U)
6077 #define GPIO_ODR_OD6_Msk                    (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
6078 #define GPIO_ODR_OD6                        GPIO_ODR_OD6_Msk
6079 #define GPIO_ODR_OD7_Pos                    (7U)
6080 #define GPIO_ODR_OD7_Msk                    (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
6081 #define GPIO_ODR_OD7                        GPIO_ODR_OD7_Msk
6082 #define GPIO_ODR_OD8_Pos                    (8U)
6083 #define GPIO_ODR_OD8_Msk                    (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
6084 #define GPIO_ODR_OD8                        GPIO_ODR_OD8_Msk
6085 #define GPIO_ODR_OD9_Pos                    (9U)
6086 #define GPIO_ODR_OD9_Msk                    (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
6087 #define GPIO_ODR_OD9                        GPIO_ODR_OD9_Msk
6088 #define GPIO_ODR_OD10_Pos                   (10U)
6089 #define GPIO_ODR_OD10_Msk                   (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
6090 #define GPIO_ODR_OD10                       GPIO_ODR_OD10_Msk
6091 #define GPIO_ODR_OD11_Pos                   (11U)
6092 #define GPIO_ODR_OD11_Msk                   (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
6093 #define GPIO_ODR_OD11                       GPIO_ODR_OD11_Msk
6094 #define GPIO_ODR_OD12_Pos                   (12U)
6095 #define GPIO_ODR_OD12_Msk                   (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
6096 #define GPIO_ODR_OD12                       GPIO_ODR_OD12_Msk
6097 #define GPIO_ODR_OD13_Pos                   (13U)
6098 #define GPIO_ODR_OD13_Msk                   (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
6099 #define GPIO_ODR_OD13                       GPIO_ODR_OD13_Msk
6100 #define GPIO_ODR_OD14_Pos                   (14U)
6101 #define GPIO_ODR_OD14_Msk                   (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
6102 #define GPIO_ODR_OD14                       GPIO_ODR_OD14_Msk
6103 #define GPIO_ODR_OD15_Pos                   (15U)
6104 #define GPIO_ODR_OD15_Msk                   (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
6105 #define GPIO_ODR_OD15                       GPIO_ODR_OD15_Msk
6106 
6107 /******************  Bits definition for GPIO_BSRR register  ******************/
6108 #define GPIO_BSRR_BS0_Pos                   (0U)
6109 #define GPIO_BSRR_BS0_Msk                   (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
6110 #define GPIO_BSRR_BS0                       GPIO_BSRR_BS0_Msk
6111 #define GPIO_BSRR_BS1_Pos                   (1U)
6112 #define GPIO_BSRR_BS1_Msk                   (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
6113 #define GPIO_BSRR_BS1                       GPIO_BSRR_BS1_Msk
6114 #define GPIO_BSRR_BS2_Pos                   (2U)
6115 #define GPIO_BSRR_BS2_Msk                   (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
6116 #define GPIO_BSRR_BS2                       GPIO_BSRR_BS2_Msk
6117 #define GPIO_BSRR_BS3_Pos                   (3U)
6118 #define GPIO_BSRR_BS3_Msk                   (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
6119 #define GPIO_BSRR_BS3                       GPIO_BSRR_BS3_Msk
6120 #define GPIO_BSRR_BS4_Pos                   (4U)
6121 #define GPIO_BSRR_BS4_Msk                   (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
6122 #define GPIO_BSRR_BS4                       GPIO_BSRR_BS4_Msk
6123 #define GPIO_BSRR_BS5_Pos                   (5U)
6124 #define GPIO_BSRR_BS5_Msk                   (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
6125 #define GPIO_BSRR_BS5                       GPIO_BSRR_BS5_Msk
6126 #define GPIO_BSRR_BS6_Pos                   (6U)
6127 #define GPIO_BSRR_BS6_Msk                   (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
6128 #define GPIO_BSRR_BS6                       GPIO_BSRR_BS6_Msk
6129 #define GPIO_BSRR_BS7_Pos                   (7U)
6130 #define GPIO_BSRR_BS7_Msk                   (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
6131 #define GPIO_BSRR_BS7                       GPIO_BSRR_BS7_Msk
6132 #define GPIO_BSRR_BS8_Pos                   (8U)
6133 #define GPIO_BSRR_BS8_Msk                   (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
6134 #define GPIO_BSRR_BS8                       GPIO_BSRR_BS8_Msk
6135 #define GPIO_BSRR_BS9_Pos                   (9U)
6136 #define GPIO_BSRR_BS9_Msk                   (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
6137 #define GPIO_BSRR_BS9                       GPIO_BSRR_BS9_Msk
6138 #define GPIO_BSRR_BS10_Pos                  (10U)
6139 #define GPIO_BSRR_BS10_Msk                  (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
6140 #define GPIO_BSRR_BS10                      GPIO_BSRR_BS10_Msk
6141 #define GPIO_BSRR_BS11_Pos                  (11U)
6142 #define GPIO_BSRR_BS11_Msk                  (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
6143 #define GPIO_BSRR_BS11                      GPIO_BSRR_BS11_Msk
6144 #define GPIO_BSRR_BS12_Pos                  (12U)
6145 #define GPIO_BSRR_BS12_Msk                  (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
6146 #define GPIO_BSRR_BS12                      GPIO_BSRR_BS12_Msk
6147 #define GPIO_BSRR_BS13_Pos                  (13U)
6148 #define GPIO_BSRR_BS13_Msk                  (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
6149 #define GPIO_BSRR_BS13                      GPIO_BSRR_BS13_Msk
6150 #define GPIO_BSRR_BS14_Pos                  (14U)
6151 #define GPIO_BSRR_BS14_Msk                  (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
6152 #define GPIO_BSRR_BS14                      GPIO_BSRR_BS14_Msk
6153 #define GPIO_BSRR_BS15_Pos                  (15U)
6154 #define GPIO_BSRR_BS15_Msk                  (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
6155 #define GPIO_BSRR_BS15                      GPIO_BSRR_BS15_Msk
6156 #define GPIO_BSRR_BR0_Pos                   (16U)
6157 #define GPIO_BSRR_BR0_Msk                   (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
6158 #define GPIO_BSRR_BR0                       GPIO_BSRR_BR0_Msk
6159 #define GPIO_BSRR_BR1_Pos                   (17U)
6160 #define GPIO_BSRR_BR1_Msk                   (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
6161 #define GPIO_BSRR_BR1                       GPIO_BSRR_BR1_Msk
6162 #define GPIO_BSRR_BR2_Pos                   (18U)
6163 #define GPIO_BSRR_BR2_Msk                   (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
6164 #define GPIO_BSRR_BR2                       GPIO_BSRR_BR2_Msk
6165 #define GPIO_BSRR_BR3_Pos                   (19U)
6166 #define GPIO_BSRR_BR3_Msk                   (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
6167 #define GPIO_BSRR_BR3                       GPIO_BSRR_BR3_Msk
6168 #define GPIO_BSRR_BR4_Pos                   (20U)
6169 #define GPIO_BSRR_BR4_Msk                   (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
6170 #define GPIO_BSRR_BR4                       GPIO_BSRR_BR4_Msk
6171 #define GPIO_BSRR_BR5_Pos                   (21U)
6172 #define GPIO_BSRR_BR5_Msk                   (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
6173 #define GPIO_BSRR_BR5                       GPIO_BSRR_BR5_Msk
6174 #define GPIO_BSRR_BR6_Pos                   (22U)
6175 #define GPIO_BSRR_BR6_Msk                   (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
6176 #define GPIO_BSRR_BR6                       GPIO_BSRR_BR6_Msk
6177 #define GPIO_BSRR_BR7_Pos                   (23U)
6178 #define GPIO_BSRR_BR7_Msk                   (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
6179 #define GPIO_BSRR_BR7                       GPIO_BSRR_BR7_Msk
6180 #define GPIO_BSRR_BR8_Pos                   (24U)
6181 #define GPIO_BSRR_BR8_Msk                   (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
6182 #define GPIO_BSRR_BR8                       GPIO_BSRR_BR8_Msk
6183 #define GPIO_BSRR_BR9_Pos                   (25U)
6184 #define GPIO_BSRR_BR9_Msk                   (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
6185 #define GPIO_BSRR_BR9                       GPIO_BSRR_BR9_Msk
6186 #define GPIO_BSRR_BR10_Pos                  (26U)
6187 #define GPIO_BSRR_BR10_Msk                  (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
6188 #define GPIO_BSRR_BR10                      GPIO_BSRR_BR10_Msk
6189 #define GPIO_BSRR_BR11_Pos                  (27U)
6190 #define GPIO_BSRR_BR11_Msk                  (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
6191 #define GPIO_BSRR_BR11                      GPIO_BSRR_BR11_Msk
6192 #define GPIO_BSRR_BR12_Pos                  (28U)
6193 #define GPIO_BSRR_BR12_Msk                  (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
6194 #define GPIO_BSRR_BR12                      GPIO_BSRR_BR12_Msk
6195 #define GPIO_BSRR_BR13_Pos                  (29U)
6196 #define GPIO_BSRR_BR13_Msk                  (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
6197 #define GPIO_BSRR_BR13                      GPIO_BSRR_BR13_Msk
6198 #define GPIO_BSRR_BR14_Pos                  (30U)
6199 #define GPIO_BSRR_BR14_Msk                  (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
6200 #define GPIO_BSRR_BR14                      GPIO_BSRR_BR14_Msk
6201 #define GPIO_BSRR_BR15_Pos                  (31U)
6202 #define GPIO_BSRR_BR15_Msk                  (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
6203 #define GPIO_BSRR_BR15                      GPIO_BSRR_BR15_Msk
6204 
6205 /****************** Bit definition for GPIO_LCKR register *********************/
6206 #define GPIO_LCKR_LCK0_Pos                  (0U)
6207 #define GPIO_LCKR_LCK0_Msk                  (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
6208 #define GPIO_LCKR_LCK0                      GPIO_LCKR_LCK0_Msk
6209 #define GPIO_LCKR_LCK1_Pos                  (1U)
6210 #define GPIO_LCKR_LCK1_Msk                  (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
6211 #define GPIO_LCKR_LCK1                      GPIO_LCKR_LCK1_Msk
6212 #define GPIO_LCKR_LCK2_Pos                  (2U)
6213 #define GPIO_LCKR_LCK2_Msk                  (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
6214 #define GPIO_LCKR_LCK2                      GPIO_LCKR_LCK2_Msk
6215 #define GPIO_LCKR_LCK3_Pos                  (3U)
6216 #define GPIO_LCKR_LCK3_Msk                  (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
6217 #define GPIO_LCKR_LCK3                      GPIO_LCKR_LCK3_Msk
6218 #define GPIO_LCKR_LCK4_Pos                  (4U)
6219 #define GPIO_LCKR_LCK4_Msk                  (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
6220 #define GPIO_LCKR_LCK4                      GPIO_LCKR_LCK4_Msk
6221 #define GPIO_LCKR_LCK5_Pos                  (5U)
6222 #define GPIO_LCKR_LCK5_Msk                  (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
6223 #define GPIO_LCKR_LCK5                      GPIO_LCKR_LCK5_Msk
6224 #define GPIO_LCKR_LCK6_Pos                  (6U)
6225 #define GPIO_LCKR_LCK6_Msk                  (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
6226 #define GPIO_LCKR_LCK6                      GPIO_LCKR_LCK6_Msk
6227 #define GPIO_LCKR_LCK7_Pos                  (7U)
6228 #define GPIO_LCKR_LCK7_Msk                  (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
6229 #define GPIO_LCKR_LCK7                      GPIO_LCKR_LCK7_Msk
6230 #define GPIO_LCKR_LCK8_Pos                  (8U)
6231 #define GPIO_LCKR_LCK8_Msk                  (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
6232 #define GPIO_LCKR_LCK8                      GPIO_LCKR_LCK8_Msk
6233 #define GPIO_LCKR_LCK9_Pos                  (9U)
6234 #define GPIO_LCKR_LCK9_Msk                  (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
6235 #define GPIO_LCKR_LCK9                      GPIO_LCKR_LCK9_Msk
6236 #define GPIO_LCKR_LCK10_Pos                 (10U)
6237 #define GPIO_LCKR_LCK10_Msk                 (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
6238 #define GPIO_LCKR_LCK10                     GPIO_LCKR_LCK10_Msk
6239 #define GPIO_LCKR_LCK11_Pos                 (11U)
6240 #define GPIO_LCKR_LCK11_Msk                 (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
6241 #define GPIO_LCKR_LCK11                     GPIO_LCKR_LCK11_Msk
6242 #define GPIO_LCKR_LCK12_Pos                 (12U)
6243 #define GPIO_LCKR_LCK12_Msk                 (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
6244 #define GPIO_LCKR_LCK12                     GPIO_LCKR_LCK12_Msk
6245 #define GPIO_LCKR_LCK13_Pos                 (13U)
6246 #define GPIO_LCKR_LCK13_Msk                 (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
6247 #define GPIO_LCKR_LCK13                     GPIO_LCKR_LCK13_Msk
6248 #define GPIO_LCKR_LCK14_Pos                 (14U)
6249 #define GPIO_LCKR_LCK14_Msk                 (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
6250 #define GPIO_LCKR_LCK14                     GPIO_LCKR_LCK14_Msk
6251 #define GPIO_LCKR_LCK15_Pos                 (15U)
6252 #define GPIO_LCKR_LCK15_Msk                 (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
6253 #define GPIO_LCKR_LCK15                     GPIO_LCKR_LCK15_Msk
6254 #define GPIO_LCKR_LCKK_Pos                  (16U)
6255 #define GPIO_LCKR_LCKK_Msk                  (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
6256 #define GPIO_LCKR_LCKK                      GPIO_LCKR_LCKK_Msk
6257 
6258 /****************** Bit definition for GPIO_AFRL register *********************/
6259 #define GPIO_AFRL_AFSEL0_Pos                (0U)
6260 #define GPIO_AFRL_AFSEL0_Msk                (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
6261 #define GPIO_AFRL_AFSEL0                    GPIO_AFRL_AFSEL0_Msk
6262 #define GPIO_AFRL_AFSEL0_0                  (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
6263 #define GPIO_AFRL_AFSEL0_1                  (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
6264 #define GPIO_AFRL_AFSEL0_2                  (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
6265 #define GPIO_AFRL_AFSEL0_3                  (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
6266 #define GPIO_AFRL_AFSEL1_Pos                (4U)
6267 #define GPIO_AFRL_AFSEL1_Msk                (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
6268 #define GPIO_AFRL_AFSEL1                    GPIO_AFRL_AFSEL1_Msk
6269 #define GPIO_AFRL_AFSEL1_0                  (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
6270 #define GPIO_AFRL_AFSEL1_1                  (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
6271 #define GPIO_AFRL_AFSEL1_2                  (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
6272 #define GPIO_AFRL_AFSEL1_3                  (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
6273 #define GPIO_AFRL_AFSEL2_Pos                (8U)
6274 #define GPIO_AFRL_AFSEL2_Msk                (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
6275 #define GPIO_AFRL_AFSEL2                    GPIO_AFRL_AFSEL2_Msk
6276 #define GPIO_AFRL_AFSEL2_0                  (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
6277 #define GPIO_AFRL_AFSEL2_1                  (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
6278 #define GPIO_AFRL_AFSEL2_2                  (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
6279 #define GPIO_AFRL_AFSEL2_3                  (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
6280 #define GPIO_AFRL_AFSEL3_Pos                (12U)
6281 #define GPIO_AFRL_AFSEL3_Msk                (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
6282 #define GPIO_AFRL_AFSEL3                    GPIO_AFRL_AFSEL3_Msk
6283 #define GPIO_AFRL_AFSEL3_0                  (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
6284 #define GPIO_AFRL_AFSEL3_1                  (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
6285 #define GPIO_AFRL_AFSEL3_2                  (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
6286 #define GPIO_AFRL_AFSEL3_3                  (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
6287 #define GPIO_AFRL_AFSEL4_Pos                (16U)
6288 #define GPIO_AFRL_AFSEL4_Msk                (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
6289 #define GPIO_AFRL_AFSEL4                    GPIO_AFRL_AFSEL4_Msk
6290 #define GPIO_AFRL_AFSEL4_0                  (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
6291 #define GPIO_AFRL_AFSEL4_1                  (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
6292 #define GPIO_AFRL_AFSEL4_2                  (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
6293 #define GPIO_AFRL_AFSEL4_3                  (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
6294 #define GPIO_AFRL_AFSEL5_Pos                (20U)
6295 #define GPIO_AFRL_AFSEL5_Msk                (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
6296 #define GPIO_AFRL_AFSEL5                    GPIO_AFRL_AFSEL5_Msk
6297 #define GPIO_AFRL_AFSEL5_0                  (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
6298 #define GPIO_AFRL_AFSEL5_1                  (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
6299 #define GPIO_AFRL_AFSEL5_2                  (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
6300 #define GPIO_AFRL_AFSEL5_3                  (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
6301 #define GPIO_AFRL_AFSEL6_Pos                (24U)
6302 #define GPIO_AFRL_AFSEL6_Msk                (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
6303 #define GPIO_AFRL_AFSEL6                    GPIO_AFRL_AFSEL6_Msk
6304 #define GPIO_AFRL_AFSEL6_0                  (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
6305 #define GPIO_AFRL_AFSEL6_1                  (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
6306 #define GPIO_AFRL_AFSEL6_2                  (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
6307 #define GPIO_AFRL_AFSEL6_3                  (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
6308 #define GPIO_AFRL_AFSEL7_Pos                (28U)
6309 #define GPIO_AFRL_AFSEL7_Msk                (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
6310 #define GPIO_AFRL_AFSEL7                    GPIO_AFRL_AFSEL7_Msk
6311 #define GPIO_AFRL_AFSEL7_0                  (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
6312 #define GPIO_AFRL_AFSEL7_1                  (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
6313 #define GPIO_AFRL_AFSEL7_2                  (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
6314 #define GPIO_AFRL_AFSEL7_3                  (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
6315 
6316 /****************** Bit definition for GPIO_AFRH register *********************/
6317 #define GPIO_AFRH_AFSEL8_Pos                (0U)
6318 #define GPIO_AFRH_AFSEL8_Msk                (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
6319 #define GPIO_AFRH_AFSEL8                    GPIO_AFRH_AFSEL8_Msk
6320 #define GPIO_AFRH_AFSEL8_0                  (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
6321 #define GPIO_AFRH_AFSEL8_1                  (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
6322 #define GPIO_AFRH_AFSEL8_2                  (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
6323 #define GPIO_AFRH_AFSEL8_3                  (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
6324 #define GPIO_AFRH_AFSEL9_Pos                (4U)
6325 #define GPIO_AFRH_AFSEL9_Msk                (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
6326 #define GPIO_AFRH_AFSEL9                    GPIO_AFRH_AFSEL9_Msk
6327 #define GPIO_AFRH_AFSEL9_0                  (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
6328 #define GPIO_AFRH_AFSEL9_1                  (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
6329 #define GPIO_AFRH_AFSEL9_2                  (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
6330 #define GPIO_AFRH_AFSEL9_3                  (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
6331 #define GPIO_AFRH_AFSEL10_Pos               (8U)
6332 #define GPIO_AFRH_AFSEL10_Msk               (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
6333 #define GPIO_AFRH_AFSEL10                   GPIO_AFRH_AFSEL10_Msk
6334 #define GPIO_AFRH_AFSEL10_0                 (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
6335 #define GPIO_AFRH_AFSEL10_1                 (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
6336 #define GPIO_AFRH_AFSEL10_2                 (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
6337 #define GPIO_AFRH_AFSEL10_3                 (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
6338 #define GPIO_AFRH_AFSEL11_Pos               (12U)
6339 #define GPIO_AFRH_AFSEL11_Msk               (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
6340 #define GPIO_AFRH_AFSEL11                   GPIO_AFRH_AFSEL11_Msk
6341 #define GPIO_AFRH_AFSEL11_0                 (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
6342 #define GPIO_AFRH_AFSEL11_1                 (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
6343 #define GPIO_AFRH_AFSEL11_2                 (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
6344 #define GPIO_AFRH_AFSEL11_3                 (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
6345 #define GPIO_AFRH_AFSEL12_Pos               (16U)
6346 #define GPIO_AFRH_AFSEL12_Msk               (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
6347 #define GPIO_AFRH_AFSEL12                   GPIO_AFRH_AFSEL12_Msk
6348 #define GPIO_AFRH_AFSEL12_0                 (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
6349 #define GPIO_AFRH_AFSEL12_1                 (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
6350 #define GPIO_AFRH_AFSEL12_2                 (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
6351 #define GPIO_AFRH_AFSEL12_3                 (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
6352 #define GPIO_AFRH_AFSEL13_Pos               (20U)
6353 #define GPIO_AFRH_AFSEL13_Msk               (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
6354 #define GPIO_AFRH_AFSEL13                   GPIO_AFRH_AFSEL13_Msk
6355 #define GPIO_AFRH_AFSEL13_0                 (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
6356 #define GPIO_AFRH_AFSEL13_1                 (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
6357 #define GPIO_AFRH_AFSEL13_2                 (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
6358 #define GPIO_AFRH_AFSEL13_3                 (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
6359 #define GPIO_AFRH_AFSEL14_Pos               (24U)
6360 #define GPIO_AFRH_AFSEL14_Msk               (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
6361 #define GPIO_AFRH_AFSEL14                   GPIO_AFRH_AFSEL14_Msk
6362 #define GPIO_AFRH_AFSEL14_0                 (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
6363 #define GPIO_AFRH_AFSEL14_1                 (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
6364 #define GPIO_AFRH_AFSEL14_2                 (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
6365 #define GPIO_AFRH_AFSEL14_3                 (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
6366 #define GPIO_AFRH_AFSEL15_Pos               (28U)
6367 #define GPIO_AFRH_AFSEL15_Msk               (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
6368 #define GPIO_AFRH_AFSEL15                   GPIO_AFRH_AFSEL15_Msk
6369 #define GPIO_AFRH_AFSEL15_0                 (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
6370 #define GPIO_AFRH_AFSEL15_1                 (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
6371 #define GPIO_AFRH_AFSEL15_2                 (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
6372 #define GPIO_AFRH_AFSEL15_3                 (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
6373 
6374 /******************  Bits definition for GPIO_BRR register  ******************/
6375 #define GPIO_BRR_BR0_Pos                    (0U)
6376 #define GPIO_BRR_BR0_Msk                    (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
6377 #define GPIO_BRR_BR0                        GPIO_BRR_BR0_Msk
6378 #define GPIO_BRR_BR1_Pos                    (1U)
6379 #define GPIO_BRR_BR1_Msk                    (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
6380 #define GPIO_BRR_BR1                        GPIO_BRR_BR1_Msk
6381 #define GPIO_BRR_BR2_Pos                    (2U)
6382 #define GPIO_BRR_BR2_Msk                    (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
6383 #define GPIO_BRR_BR2                        GPIO_BRR_BR2_Msk
6384 #define GPIO_BRR_BR3_Pos                    (3U)
6385 #define GPIO_BRR_BR3_Msk                    (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
6386 #define GPIO_BRR_BR3                        GPIO_BRR_BR3_Msk
6387 #define GPIO_BRR_BR4_Pos                    (4U)
6388 #define GPIO_BRR_BR4_Msk                    (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
6389 #define GPIO_BRR_BR4                        GPIO_BRR_BR4_Msk
6390 #define GPIO_BRR_BR5_Pos                    (5U)
6391 #define GPIO_BRR_BR5_Msk                    (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
6392 #define GPIO_BRR_BR5                        GPIO_BRR_BR5_Msk
6393 #define GPIO_BRR_BR6_Pos                    (6U)
6394 #define GPIO_BRR_BR6_Msk                    (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
6395 #define GPIO_BRR_BR6                        GPIO_BRR_BR6_Msk
6396 #define GPIO_BRR_BR7_Pos                    (7U)
6397 #define GPIO_BRR_BR7_Msk                    (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
6398 #define GPIO_BRR_BR7                        GPIO_BRR_BR7_Msk
6399 #define GPIO_BRR_BR8_Pos                    (8U)
6400 #define GPIO_BRR_BR8_Msk                    (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
6401 #define GPIO_BRR_BR8                        GPIO_BRR_BR8_Msk
6402 #define GPIO_BRR_BR9_Pos                    (9U)
6403 #define GPIO_BRR_BR9_Msk                    (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
6404 #define GPIO_BRR_BR9                        GPIO_BRR_BR9_Msk
6405 #define GPIO_BRR_BR10_Pos                   (10U)
6406 #define GPIO_BRR_BR10_Msk                   (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
6407 #define GPIO_BRR_BR10                       GPIO_BRR_BR10_Msk
6408 #define GPIO_BRR_BR11_Pos                   (11U)
6409 #define GPIO_BRR_BR11_Msk                   (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
6410 #define GPIO_BRR_BR11                       GPIO_BRR_BR11_Msk
6411 #define GPIO_BRR_BR12_Pos                   (12U)
6412 #define GPIO_BRR_BR12_Msk                   (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
6413 #define GPIO_BRR_BR12                       GPIO_BRR_BR12_Msk
6414 #define GPIO_BRR_BR13_Pos                   (13U)
6415 #define GPIO_BRR_BR13_Msk                   (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
6416 #define GPIO_BRR_BR13                       GPIO_BRR_BR13_Msk
6417 #define GPIO_BRR_BR14_Pos                   (14U)
6418 #define GPIO_BRR_BR14_Msk                   (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
6419 #define GPIO_BRR_BR14                       GPIO_BRR_BR14_Msk
6420 #define GPIO_BRR_BR15_Pos                   (15U)
6421 #define GPIO_BRR_BR15_Msk                   (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
6422 #define GPIO_BRR_BR15                       GPIO_BRR_BR15_Msk
6423 
6424 /******************  Bits definition for GPIO_HSLVR register  ******************/
6425 #define GPIO_HSLVR_HSLV0_Pos                (0U)
6426 #define GPIO_HSLVR_HSLV0_Msk                (0x1UL << GPIO_HSLVR_HSLV0_Pos)         /*!< 0x00000001 */
6427 #define GPIO_HSLVR_HSLV0                    GPIO_HSLVR_HSLV0_Msk
6428 #define GPIO_HSLVR_HSLV1_Pos                (1U)
6429 #define GPIO_HSLVR_HSLV1_Msk                (0x1UL << GPIO_HSLVR_HSLV1_Pos)         /*!< 0x00000002 */
6430 #define GPIO_HSLVR_HSLV1                    GPIO_HSLVR_HSLV1_Msk
6431 #define GPIO_HSLVR_HSLV2_Pos                (2U)
6432 #define GPIO_HSLVR_HSLV2_Msk                (0x1UL << GPIO_HSLVR_HSLV2_Pos)         /*!< 0x00000004 */
6433 #define GPIO_HSLVR_HSLV2                    GPIO_HSLVR_HSLV2_Msk
6434 #define GPIO_HSLVR_HSLV3_Pos                (3U)
6435 #define GPIO_HSLVR_HSLV3_Msk                (0x1UL << GPIO_HSLVR_HSLV3_Pos)         /*!< 0x00000008 */
6436 #define GPIO_HSLVR_HSLV3                    GPIO_HSLVR_HSLV3_Msk
6437 #define GPIO_HSLVR_HSLV4_Pos                (4U)
6438 #define GPIO_HSLVR_HSLV4_Msk                (0x1UL << GPIO_HSLVR_HSLV4_Pos)         /*!< 0x00000010 */
6439 #define GPIO_HSLVR_HSLV4                    GPIO_HSLVR_HSLV4_Msk
6440 #define GPIO_HSLVR_HSLV5_Pos                (5U)
6441 #define GPIO_HSLVR_HSLV5_Msk                (0x1UL << GPIO_HSLVR_HSLV5_Pos)         /*!< 0x00000020 */
6442 #define GPIO_HSLVR_HSLV5                    GPIO_HSLVR_HSLV5_Msk
6443 #define GPIO_HSLVR_HSLV6_Pos                (6U)
6444 #define GPIO_HSLVR_HSLV6_Msk                (0x1UL << GPIO_HSLVR_HSLV6_Pos)         /*!< 0x00000040 */
6445 #define GPIO_HSLVR_HSLV6                    GPIO_HSLVR_HSLV6_Msk
6446 #define GPIO_HSLVR_HSLV7_Pos                (7U)
6447 #define GPIO_HSLVR_HSLV7_Msk                (0x1UL << GPIO_HSLVR_HSLV7_Pos)         /*!< 0x00000080 */
6448 #define GPIO_HSLVR_HSLV7                    GPIO_HSLVR_HSLV7_Msk
6449 #define GPIO_HSLVR_HSLV8_Pos                (8U)
6450 #define GPIO_HSLVR_HSLV8_Msk                (0x1UL << GPIO_HSLVR_HSLV8_Pos)         /*!< 0x00000100 */
6451 #define GPIO_HSLVR_HSLV8                    GPIO_HSLVR_HSLV8_Msk
6452 #define GPIO_HSLVR_HSLV9_Pos                (9U)
6453 #define GPIO_HSLVR_HSLV9_Msk                (0x1UL << GPIO_HSLVR_HSLV9_Pos)         /*!< 0x00000200 */
6454 #define GPIO_HSLVR_HSLV9                    GPIO_HSLVR_HSLV9_Msk
6455 #define GPIO_HSLVR_HSLV10_Pos               (10U)
6456 #define GPIO_HSLVR_HSLV10_Msk               (0x1UL << GPIO_HSLVR_HSLV10_Pos)        /*!< 0x00000400 */
6457 #define GPIO_HSLVR_HSLV10                   GPIO_HSLVR_HSLV10_Msk
6458 #define GPIO_HSLVR_HSLV11_Pos               (11U)
6459 #define GPIO_HSLVR_HSLV11_Msk               (x1UL << GPIO_HSLVR_HSLV11_Pos)         /*!< 0x00000800 */
6460 #define GPIO_HSLVR_HSLV11                   GPIO_HSLVR_HSLV11_Msk
6461 #define GPIO_HSLVR_HSLV12_Pos               (12U)
6462 #define GPIO_HSLVR_HSLV12_Msk               (0x1UL << GPIO_HSLVR_HSLV12_Pos)        /*!< 0x00001000 */
6463 #define GPIO_HSLVR_HSLV12                   GPIO_HSLVR_HSLV12_Msk
6464 #define GPIO_HSLVR_HSLV13_Pos               (13U)
6465 #define GPIO_HSLVR_HSLV13_Msk               (0x1UL << GPIO_HSLVR_HSLV13_Pos)        /*!< 0x00002000 */
6466 #define GPIO_HSLVR_HSLV13                   GPIO_HSLVR_HSLV13_Msk
6467 #define GPIO_HSLVR_HSLV14_Pos               (14U)
6468 #define GPIO_HSLVR_HSLV14_Msk               (0x1UL << GPIO_HSLVR_HSLV14_Pos)        /*!< 0x00004000 */
6469 #define GPIO_HSLVR_HSLV14                   GPIO_HSLVR_HSLV14_Msk
6470 #define GPIO_HSLVR_HSLV15_Pos               (15U)
6471 #define GPIO_HSLVR_HSLV15_Msk               (0x1UL << GPIO_HSLVR_HSLV15_Pos)        /*!< 0x00008000 */
6472 #define GPIO_HSLVR_HSLV15                   GPIO_HSLVR_HSLV15_Msk
6473 
6474 /******************  Bits definition for GPIO_SECCFGR register  ******************/
6475 #define GPIO_SECCFGR_SEC0_Pos               (0U)
6476 #define GPIO_SECCFGR_SEC0_Msk               (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
6477 #define GPIO_SECCFGR_SEC0                   GPIO_SECCFGR_SEC0_Msk
6478 #define GPIO_SECCFGR_SEC1_Pos               (1U)
6479 #define GPIO_SECCFGR_SEC1_Msk               (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
6480 #define GPIO_SECCFGR_SEC1                   GPIO_SECCFGR_SEC1_Msk
6481 #define GPIO_SECCFGR_SEC2_Pos               (2U)
6482 #define GPIO_SECCFGR_SEC2_Msk               (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
6483 #define GPIO_SECCFGR_SEC2                   GPIO_SECCFGR_SEC2_Msk
6484 #define GPIO_SECCFGR_SEC3_Pos               (3U)
6485 #define GPIO_SECCFGR_SEC3_Msk               (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
6486 #define GPIO_SECCFGR_SEC3                   GPIO_SECCFGR_SEC3_Msk
6487 #define GPIO_SECCFGR_SEC4_Pos               (4U)
6488 #define GPIO_SECCFGR_SEC4_Msk               (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
6489 #define GPIO_SECCFGR_SEC4                   GPIO_SECCFGR_SEC4_Msk
6490 #define GPIO_SECCFGR_SEC5_Pos               (5U)
6491 #define GPIO_SECCFGR_SEC5_Msk               (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
6492 #define GPIO_SECCFGR_SEC5                   GPIO_SECCFGR_SEC5_Msk
6493 #define GPIO_SECCFGR_SEC6_Pos               (6U)
6494 #define GPIO_SECCFGR_SEC6_Msk               (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
6495 #define GPIO_SECCFGR_SEC6                   GPIO_SECCFGR_SEC6_Msk
6496 #define GPIO_SECCFGR_SEC7_Pos               (7U)
6497 #define GPIO_SECCFGR_SEC7_Msk               (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
6498 #define GPIO_SECCFGR_SEC7                   GPIO_SECCFGR_SEC7_Msk
6499 #define GPIO_SECCFGR_SEC8_Pos               (8U)
6500 #define GPIO_SECCFGR_SEC8_Msk               (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
6501 #define GPIO_SECCFGR_SEC8                   GPIO_SECCFGR_SEC8_Msk
6502 #define GPIO_SECCFGR_SEC9_Pos               (9U)
6503 #define GPIO_SECCFGR_SEC9_Msk               (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
6504 #define GPIO_SECCFGR_SEC9                   GPIO_SECCFGR_SEC9_Msk
6505 #define GPIO_SECCFGR_SEC10_Pos              (10U)
6506 #define GPIO_SECCFGR_SEC10_Msk              (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
6507 #define GPIO_SECCFGR_SEC10                  GPIO_SECCFGR_SEC10_Msk
6508 #define GPIO_SECCFGR_SEC11_Pos              (11U)
6509 #define GPIO_SECCFGR_SEC11_Msk              (x1UL << GPIO_SECCFGR_SEC11_Pos)        /*!< 0x00000800 */
6510 #define GPIO_SECCFGR_SEC11                  GPIO_SECCFGR_SEC11_Msk
6511 #define GPIO_SECCFGR_SEC12_Pos              (12U)
6512 #define GPIO_SECCFGR_SEC12_Msk              (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
6513 #define GPIO_SECCFGR_SEC12                  GPIO_SECCFGR_SEC12_Msk
6514 #define GPIO_SECCFGR_SEC13_Pos              (13U)
6515 #define GPIO_SECCFGR_SEC13_Msk              (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
6516 #define GPIO_SECCFGR_SEC13                  GPIO_SECCFGR_SEC13_Msk
6517 #define GPIO_SECCFGR_SEC14_Pos              (14U)
6518 #define GPIO_SECCFGR_SEC14_Msk              (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
6519 #define GPIO_SECCFGR_SEC14                  GPIO_SECCFGR_SEC14_Msk
6520 #define GPIO_SECCFGR_SEC15_Pos              (15U)
6521 #define GPIO_SECCFGR_SEC15_Msk              (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
6522 #define GPIO_SECCFGR_SEC15                  GPIO_SECCFGR_SEC15_Msk
6523 
6524 /******************************************************************************/
6525 /*                                                                            */
6526 /*                                 ICACHE                                     */
6527 /*                                                                            */
6528 /******************************************************************************/
6529 /******************  Bit definition for ICACHE_CR register  *******************/
6530 #define ICACHE_CR_EN_Pos                    (0U)
6531 #define ICACHE_CR_EN_Msk                    (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
6532 #define ICACHE_CR_EN                        ICACHE_CR_EN_Msk                        /*!< Enable */
6533 #define ICACHE_CR_CACHEINV_Pos              (1U)
6534 #define ICACHE_CR_CACHEINV_Msk              (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
6535 #define ICACHE_CR_CACHEINV                  ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
6536 #define ICACHE_CR_WAYSEL_Pos                (2U)
6537 #define ICACHE_CR_WAYSEL_Msk                (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
6538 #define ICACHE_CR_WAYSEL                    ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
6539 #define ICACHE_CR_HITMEN_Pos                (16U)
6540 #define ICACHE_CR_HITMEN_Msk                (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
6541 #define ICACHE_CR_HITMEN                    ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
6542 #define ICACHE_CR_MISSMEN_Pos               (17U)
6543 #define ICACHE_CR_MISSMEN_Msk               (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
6544 #define ICACHE_CR_MISSMEN                   ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
6545 #define ICACHE_CR_HITMRST_Pos               (18U)
6546 #define ICACHE_CR_HITMRST_Msk               (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
6547 #define ICACHE_CR_HITMRST                   ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
6548 #define ICACHE_CR_MISSMRST_Pos              (19U)
6549 #define ICACHE_CR_MISSMRST_Msk              (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
6550 #define ICACHE_CR_MISSMRST                  ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */
6551 
6552 /******************  Bit definition for ICACHE_SR register  *******************/
6553 #define ICACHE_SR_BUSYF_Pos                 (0U)
6554 #define ICACHE_SR_BUSYF_Msk                 (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
6555 #define ICACHE_SR_BUSYF                     ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
6556 #define ICACHE_SR_BSYENDF_Pos               (1U)
6557 #define ICACHE_SR_BSYENDF_Msk               (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
6558 #define ICACHE_SR_BSYENDF                   ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
6559 #define ICACHE_SR_ERRF_Pos                  (2U)
6560 #define ICACHE_SR_ERRF_Msk                  (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
6561 #define ICACHE_SR_ERRF                      ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */
6562 
6563 /******************  Bit definition for ICACHE_IER register  ******************/
6564 #define ICACHE_IER_BSYENDIE_Pos             (1U)
6565 #define ICACHE_IER_BSYENDIE_Msk             (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
6566 #define ICACHE_IER_BSYENDIE                 ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
6567 #define ICACHE_IER_ERRIE_Pos                (2U)
6568 #define ICACHE_IER_ERRIE_Msk                (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
6569 #define ICACHE_IER_ERRIE                    ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
6570 
6571 /******************  Bit definition for ICACHE_FCR register  ******************/
6572 #define ICACHE_FCR_CBSYENDF_Pos             (1U)
6573 #define ICACHE_FCR_CBSYENDF_Msk             (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
6574 #define ICACHE_FCR_CBSYENDF                 ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
6575 #define ICACHE_FCR_CERRF_Pos                (2U)
6576 #define ICACHE_FCR_CERRF_Msk                (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
6577 #define ICACHE_FCR_CERRF                    ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
6578 
6579 /******************  Bit definition for ICACHE_HMONR register  ****************/
6580 #define ICACHE_HMONR_HITMON_Pos             (0U)
6581 #define ICACHE_HMONR_HITMON_Msk             (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */
6582 #define ICACHE_HMONR_HITMON                 ICACHE_HMONR_HITMON_Msk                 /*!< Cache hit monitor register */
6583 
6584 /******************  Bit definition for ICACHE_MMONR register  ****************/
6585 #define ICACHE_MMONR_MISSMON_Pos            (0U)
6586 #define ICACHE_MMONR_MISSMON_Msk            (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos)  /*!< 0x0000FFFF */
6587 #define ICACHE_MMONR_MISSMON                ICACHE_MMONR_MISSMON_Msk                /*!< Cache miss monitor register */
6588 
6589 
6590 /******************************************************************************/
6591 /*                                                                            */
6592 /*                    Digital Temperature Sensor (DTS)                        */
6593 /*                                                                            */
6594 /******************************************************************************/
6595 
6596 /******************  Bit definition for DTS_CFGR1 register  ******************/
6597 #define DTS_CFGR1_TS1_EN_Pos               (0U)
6598 #define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
6599 #define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */
6600 #define DTS_CFGR1_TS1_START_Pos            (4U)
6601 #define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
6602 #define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */
6603 #define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)
6604 #define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
6605 #define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */
6606 #define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
6607 #define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
6608 #define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
6609 #define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
6610 #define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)
6611 #define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
6612 #define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */
6613 #define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
6614 #define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
6615 #define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
6616 #define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
6617 #define DTS_CFGR1_REFCLK_SEL_Pos           (20U)
6618 #define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
6619 #define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */
6620 #define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)
6621 #define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
6622 #define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */
6623 #define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)
6624 #define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
6625 #define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/
6626 
6627 /******************  Bit definition for DTS_T0VALR1 register  ******************/
6628 #define DTS_T0VALR1_TS1_FMT0_Pos           (0U)
6629 #define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
6630 #define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */
6631 #define DTS_T0VALR1_TS1_T0_Pos             (16U)
6632 #define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
6633 #define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */
6634 
6635 /******************  Bit definition for DTS_RAMPVALR register  ******************/
6636 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)
6637 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
6638 #define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */
6639 
6640 /******************  Bit definition for DTS_ITR1 register      ******************/
6641 #define DTS_ITR1_TS1_LITTHD_Pos            (0U)
6642 #define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
6643 #define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */
6644 #define DTS_ITR1_TS1_HITTHD_Pos            (16U)
6645 #define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
6646 #define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */
6647 
6648 /******************  Bit definition for DTS_DR register        ******************/
6649 #define DTS_DR_TS1_MFREQ_Pos               (0U)
6650 #define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
6651 #define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */
6652 
6653 /******************  Bit definition for DTS_SR register        ******************/
6654 #define DTS_SR_TS1_ITEF_Pos                (0U)
6655 #define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
6656 #define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */
6657 #define DTS_SR_TS1_ITLF_Pos                (1U)
6658 #define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
6659 #define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */
6660 #define DTS_SR_TS1_ITHF_Pos                (2U)
6661 #define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
6662 #define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */
6663 #define DTS_SR_TS1_AITEF_Pos               (4U)
6664 #define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
6665 #define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */
6666 #define DTS_SR_TS1_AITLF_Pos               (5U)
6667 #define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
6668 #define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */
6669 #define DTS_SR_TS1_AITHF_Pos               (6U)
6670 #define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
6671 #define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */
6672 #define DTS_SR_TS1_RDY_Pos                 (15U)
6673 #define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
6674 #define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */
6675 
6676 /******************  Bit definition for DTS_ITENR register      ******************/
6677 #define DTS_ITENR_TS1_ITEEN_Pos            (0U)
6678 #define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
6679 #define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */
6680 #define DTS_ITENR_TS1_ITLEN_Pos            (1U)
6681 #define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
6682 #define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */
6683 #define DTS_ITENR_TS1_ITHEN_Pos            (2U)
6684 #define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
6685 #define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */
6686 #define DTS_ITENR_TS1_AITEEN_Pos           (4U)
6687 #define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
6688 #define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */
6689 #define DTS_ITENR_TS1_AITLEN_Pos           (5U)
6690 #define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
6691 #define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */
6692 #define DTS_ITENR_TS1_AITHEN_Pos           (6U)
6693 #define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
6694 #define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */
6695 
6696 /******************  Bit definition for DTS_ICIFR register      ******************/
6697 #define DTS_ICIFR_TS1_CITEF_Pos            (0U)
6698 #define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
6699 #define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */
6700 #define DTS_ICIFR_TS1_CITLF_Pos            (1U)
6701 #define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
6702 #define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */
6703 #define DTS_ICIFR_TS1_CITHF_Pos            (2U)
6704 #define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
6705 #define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */
6706 #define DTS_ICIFR_TS1_CAITEF_Pos           (4U)
6707 #define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
6708 #define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */
6709 #define DTS_ICIFR_TS1_CAITLF_Pos           (5U)
6710 #define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
6711 #define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */
6712 #define DTS_ICIFR_TS1_CAITHF_Pos           (6U)
6713 #define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
6714 #define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */
6715 
6716 /******************************************************************************/
6717 /*                                                                            */
6718 /*                                    TIM                                     */
6719 /*                                                                            */
6720 /******************************************************************************/
6721 /*******************  Bit definition for TIM_CR1 register  ********************/
6722 #define TIM_CR1_CEN_Pos                     (0U)
6723 #define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)              /*!< 0x00000001 */
6724 #define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                         /*!<Counter enable */
6725 #define TIM_CR1_UDIS_Pos                    (1U)
6726 #define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)             /*!< 0x00000002 */
6727 #define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                        /*!<Update disable */
6728 #define TIM_CR1_URS_Pos                     (2U)
6729 #define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)              /*!< 0x00000004 */
6730 #define TIM_CR1_URS                         TIM_CR1_URS_Msk                         /*!<Update request source */
6731 #define TIM_CR1_OPM_Pos                     (3U)
6732 #define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)              /*!< 0x00000008 */
6733 #define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                         /*!<One pulse mode */
6734 #define TIM_CR1_DIR_Pos                     (4U)
6735 #define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)              /*!< 0x00000010 */
6736 #define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                         /*!<Direction */
6737 #define TIM_CR1_CMS_Pos                     (5U)
6738 #define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)              /*!< 0x00000060 */
6739 #define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                         /*!<CMS[1:0] bits (Center-aligned mode selection) */
6740 #define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)              /*!< 0x00000020 */
6741 #define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)              /*!< 0x00000040 */
6742 #define TIM_CR1_ARPE_Pos                    (7U)
6743 #define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)             /*!< 0x00000080 */
6744 #define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                        /*!<Auto-reload preload enable */
6745 #define TIM_CR1_CKD_Pos                     (8U)
6746 #define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)              /*!< 0x00000300 */
6747 #define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                         /*!<CKD[1:0] bits (clock division) */
6748 #define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)              /*!< 0x00000100 */
6749 #define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)              /*!< 0x00000200 */
6750 #define TIM_CR1_UIFREMAP_Pos                (11U)
6751 #define TIM_CR1_UIFREMAP_Msk                (0x1UL << TIM_CR1_UIFREMAP_Pos)         /*!< 0x00000800 */
6752 #define TIM_CR1_UIFREMAP                    TIM_CR1_UIFREMAP_Msk                    /*!<Update interrupt flag remap */
6753 #define TIM_CR1_DITHEN_Pos                  (12U)
6754 #define TIM_CR1_DITHEN_Msk                  (0x1UL << TIM_CR1_DITHEN_Pos)           /*!< 0x00001000 */
6755 #define TIM_CR1_DITHEN                      TIM_CR1_DITHEN_Msk                      /*!<Dithering enable */
6756 
6757 /*******************  Bit definition for TIM_CR2 register  ********************/
6758 #define TIM_CR2_CCPC_Pos                    (0U)
6759 #define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)             /*!< 0x00000001 */
6760 #define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                        /*!<Capture/Compare Preloaded Control */
6761 #define TIM_CR2_CCUS_Pos                    (2U)
6762 #define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)             /*!< 0x00000004 */
6763 #define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                        /*!<Capture/Compare Control Update Selection */
6764 #define TIM_CR2_CCDS_Pos                    (3U)
6765 #define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)             /*!< 0x00000008 */
6766 #define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                        /*!<Capture/Compare DMA Selection */
6767 #define TIM_CR2_MMS_Pos                     (4U)
6768 #define TIM_CR2_MMS_Msk                     (0x200007UL << TIM_CR2_MMS_Pos)         /*!< 0x02000070 */
6769 #define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                         /*!<MMS[3:0] bits (Master Mode Selection) */
6770 #define TIM_CR2_MMS_0                       (0x000001UL << TIM_CR2_MMS_Pos)         /*!< 0x00000010 */
6771 #define TIM_CR2_MMS_1                       (0x000002UL << TIM_CR2_MMS_Pos)         /*!< 0x00000020 */
6772 #define TIM_CR2_MMS_2                       (0x000004UL << TIM_CR2_MMS_Pos)         /*!< 0x00000040 */
6773 #define TIM_CR2_MMS_3                       (0x200000UL << TIM_CR2_MMS_Pos)         /*!< 0x02000000 */
6774 #define TIM_CR2_TI1S_Pos                    (7U)
6775 #define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)             /*!< 0x00000080 */
6776 #define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                        /*!<TI1 Selection */
6777 #define TIM_CR2_OIS1_Pos                    (8U)
6778 #define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)             /*!< 0x00000100 */
6779 #define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                        /*!<Output Idle state 1 (OC1 output) */
6780 #define TIM_CR2_OIS1N_Pos                   (9U)
6781 #define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)            /*!< 0x00000200 */
6782 #define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                       /*!<Output Idle state 1 (OC1N output) */
6783 #define TIM_CR2_OIS2_Pos                    (10U)
6784 #define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)             /*!< 0x00000400 */
6785 #define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                        /*!<Output Idle state 2 (OC2 output) */
6786 #define TIM_CR2_OIS2N_Pos                   (11U)
6787 #define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)            /*!< 0x00000800 */
6788 #define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                       /*!<Output Idle state 2 (OC2N output) */
6789 #define TIM_CR2_OIS3_Pos                    (12U)
6790 #define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)             /*!< 0x00001000 */
6791 #define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                        /*!<Output Idle state 3 (OC3 output) */
6792 #define TIM_CR2_OIS3N_Pos                   (13U)
6793 #define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)            /*!< 0x00002000 */
6794 #define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                       /*!<Output Idle state 3 (OC3N output) */
6795 #define TIM_CR2_OIS4_Pos                    (14U)
6796 #define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)             /*!< 0x00004000 */
6797 #define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                        /*!<Output Idle state 4 (OC4 output) */
6798 #define TIM_CR2_OIS4N_Pos                   (15U)
6799 #define TIM_CR2_OIS4N_Msk                   (0x1UL << TIM_CR2_OIS4N_Pos)            /*!< 0x00008000 */
6800 #define TIM_CR2_OIS4N                       TIM_CR2_OIS4N_Msk                       /*!<Output Idle state 4 (OC4N output) */
6801 #define TIM_CR2_OIS5_Pos                    (16U)
6802 #define TIM_CR2_OIS5_Msk                    (0x1UL << TIM_CR2_OIS5_Pos)             /*!< 0x00010000 */
6803 #define TIM_CR2_OIS5                        TIM_CR2_OIS5_Msk                        /*!<Output Idle state 5 (OC5 output) */
6804 #define TIM_CR2_OIS6_Pos                    (18U)
6805 #define TIM_CR2_OIS6_Msk                    (0x1UL << TIM_CR2_OIS6_Pos)             /*!< 0x00040000 */
6806 #define TIM_CR2_OIS6                        TIM_CR2_OIS6_Msk                        /*!<Output Idle state 6 (OC6 output) */
6807 #define TIM_CR2_MMS2_Pos                    (20U)
6808 #define TIM_CR2_MMS2_Msk                    (0xFUL << TIM_CR2_MMS2_Pos)             /*!< 0x00F00000 */
6809 #define TIM_CR2_MMS2                        TIM_CR2_MMS2_Msk                        /*!<MMS[2:0] bits (Master Mode Selection) */
6810 #define TIM_CR2_MMS2_0                      (0x1UL << TIM_CR2_MMS2_Pos)             /*!< 0x00100000 */
6811 #define TIM_CR2_MMS2_1                      (0x2UL << TIM_CR2_MMS2_Pos)             /*!< 0x00200000 */
6812 #define TIM_CR2_MMS2_2                      (0x4UL << TIM_CR2_MMS2_Pos)             /*!< 0x00400000 */
6813 #define TIM_CR2_MMS2_3                      (0x8UL << TIM_CR2_MMS2_Pos)             /*!< 0x00800000 */
6814 
6815 /*******************  Bit definition for TIM_SMCR register  *******************/
6816 #define TIM_SMCR_SMS_Pos                    (0U)
6817 #define TIM_SMCR_SMS_Msk                    (0x10007UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010007 */
6818 #define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                        /*!<SMS[2:0] bits (Slave mode selection) */
6819 #define TIM_SMCR_SMS_0                      (0x00001UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
6820 #define TIM_SMCR_SMS_1                      (0x00002UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
6821 #define TIM_SMCR_SMS_2                      (0x00004UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
6822 #define TIM_SMCR_SMS_3                      (0x10000UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010000 */
6823 #define TIM_SMCR_OCCS_Pos                   (3U)
6824 #define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)            /*!< 0x00000008 */
6825 #define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                       /*!< OCREF clear selection */
6826 #define TIM_SMCR_TS_Pos                     (4U)
6827 #define TIM_SMCR_TS_Msk                     (0x30007UL << TIM_SMCR_TS_Pos)          /*!< 0x00300070 */
6828 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                         /*!<TS[2:0] bits (Trigger selection) */
6829 #define TIM_SMCR_TS_0                       (0x00001UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
6830 #define TIM_SMCR_TS_1                       (0x00002UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
6831 #define TIM_SMCR_TS_2                       (0x00004UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
6832 #define TIM_SMCR_TS_3                       (0x10000UL << TIM_SMCR_TS_Pos)          /*!< 0x00100000 */
6833 #define TIM_SMCR_TS_4                       (0x20000UL << TIM_SMCR_TS_Pos)          /*!< 0x00200000 */
6834 #define TIM_SMCR_MSM_Pos                    (7U)
6835 #define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)             /*!< 0x00000080 */
6836 #define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                        /*!<Master/slave mode */
6837 #define TIM_SMCR_ETF_Pos                    (8U)
6838 #define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)             /*!< 0x00000F00 */
6839 #define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                        /*!<ETF[3:0] bits (External trigger filter) */
6840 #define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000100 */
6841 #define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000200 */
6842 #define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000400 */
6843 #define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000800 */
6844 #define TIM_SMCR_ETPS_Pos                   (12U)
6845 #define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00003000 */
6846 #define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                       /*!<ETPS[1:0] bits (External trigger prescaler) */
6847 #define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00001000 */
6848 #define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00002000 */
6849 #define TIM_SMCR_ECE_Pos                    (14U)
6850 #define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)             /*!< 0x00004000 */
6851 #define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                        /*!<External clock enable */
6852 #define TIM_SMCR_ETP_Pos                    (15U)
6853 #define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)             /*!< 0x00008000 */
6854 #define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                        /*!<External trigger polarity */
6855 #define TIM_SMCR_SMSPE_Pos                  (24U)
6856 #define TIM_SMCR_SMSPE_Msk                  (0x1UL << TIM_SMCR_SMSPE_Pos)           /*!< 0x02000000 */
6857 #define TIM_SMCR_SMSPE                      TIM_SMCR_SMSPE_Msk                      /*!<SMS preload enable */
6858 #define TIM_SMCR_SMSPS_Pos                  (25U)
6859 #define TIM_SMCR_SMSPS_Msk                  (0x1UL << TIM_SMCR_SMSPS_Pos)           /*!< 0x04000000 */
6860 #define TIM_SMCR_SMSPS                      TIM_SMCR_SMSPS_Msk                      /*!<SMS preload source */
6861 
6862 /*******************  Bit definition for TIM_DIER register  *******************/
6863 #define TIM_DIER_UIE_Pos                    (0U)
6864 #define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)             /*!< 0x00000001 */
6865 #define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                        /*!<Update interrupt enable */
6866 #define TIM_DIER_CC1IE_Pos                  (1U)
6867 #define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)           /*!< 0x00000002 */
6868 #define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                      /*!<Capture/Compare 1 interrupt enable */
6869 #define TIM_DIER_CC2IE_Pos                  (2U)
6870 #define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)           /*!< 0x00000004 */
6871 #define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                      /*!<Capture/Compare 2 interrupt enable */
6872 #define TIM_DIER_CC3IE_Pos                  (3U)
6873 #define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)           /*!< 0x00000008 */
6874 #define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                      /*!<Capture/Compare 3 interrupt enable */
6875 #define TIM_DIER_CC4IE_Pos                  (4U)
6876 #define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)           /*!< 0x00000010 */
6877 #define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                      /*!<Capture/Compare 4 interrupt enable */
6878 #define TIM_DIER_COMIE_Pos                  (5U)
6879 #define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)           /*!< 0x00000020 */
6880 #define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                      /*!<COM interrupt enable */
6881 #define TIM_DIER_TIE_Pos                    (6U)
6882 #define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)             /*!< 0x00000040 */
6883 #define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                        /*!<Trigger interrupt enable */
6884 #define TIM_DIER_BIE_Pos                    (7U)
6885 #define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)             /*!< 0x00000080 */
6886 #define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                        /*!<Break interrupt enable */
6887 #define TIM_DIER_UDE_Pos                    (8U)
6888 #define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)             /*!< 0x00000100 */
6889 #define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                        /*!<Update DMA request enable */
6890 #define TIM_DIER_CC1DE_Pos                  (9U)
6891 #define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)           /*!< 0x00000200 */
6892 #define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                      /*!<Capture/Compare 1 DMA request enable */
6893 #define TIM_DIER_CC2DE_Pos                  (10U)
6894 #define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)           /*!< 0x00000400 */
6895 #define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                      /*!<Capture/Compare 2 DMA request enable */
6896 #define TIM_DIER_CC3DE_Pos                  (11U)
6897 #define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)           /*!< 0x00000800 */
6898 #define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                      /*!<Capture/Compare 3 DMA request enable */
6899 #define TIM_DIER_CC4DE_Pos                  (12U)
6900 #define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)           /*!< 0x00001000 */
6901 #define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                      /*!<Capture/Compare 4 DMA request enable */
6902 #define TIM_DIER_COMDE_Pos                  (13U)
6903 #define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)           /*!< 0x00002000 */
6904 #define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                      /*!<COM DMA request enable */
6905 #define TIM_DIER_TDE_Pos                    (14U)
6906 #define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)             /*!< 0x00004000 */
6907 #define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                        /*!<Trigger DMA request enable */
6908 #define TIM_DIER_IDXIE_Pos                  (20U)
6909 #define TIM_DIER_IDXIE_Msk                  (0x1UL << TIM_DIER_IDXIE_Pos)           /*!< 0x00100000 */
6910 #define TIM_DIER_IDXIE                      TIM_DIER_IDXIE_Msk                      /*!<Encoder index interrupt enable */
6911 #define TIM_DIER_DIRIE_Pos                  (21U)
6912 #define TIM_DIER_DIRIE_Msk                  (0x1UL << TIM_DIER_DIRIE_Pos)           /*!< 0x00200000 */
6913 #define TIM_DIER_DIRIE                      TIM_DIER_DIRIE_Msk                      /*!<Encoder direction change interrupt enable */
6914 #define TIM_DIER_IERRIE_Pos                 (22U)
6915 #define TIM_DIER_IERRIE_Msk                 (0x1UL << TIM_DIER_IERRIE_Pos)          /*!< 0x00400000 */
6916 #define TIM_DIER_IERRIE                     TIM_DIER_IERRIE_Msk                     /*!<Encoder index error enable */
6917 #define TIM_DIER_TERRIE_Pos                 (23U)
6918 #define TIM_DIER_TERRIE_Msk                 (0x1UL << TIM_DIER_TERRIE_Pos)          /*!< 0x00800000 */
6919 #define TIM_DIER_TERRIE                     TIM_DIER_TERRIE_Msk                     /*!<Encoder transition error enable */
6920 
6921 /********************  Bit definition for TIM_SR register  ********************/
6922 #define TIM_SR_UIF_Pos                      (0U)
6923 #define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)               /*!< 0x00000001 */
6924 #define TIM_SR_UIF                          TIM_SR_UIF_Msk                          /*!<Update interrupt Flag */
6925 #define TIM_SR_CC1IF_Pos                    (1U)
6926 #define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)             /*!< 0x00000002 */
6927 #define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                        /*!<Capture/Compare 1 interrupt Flag */
6928 #define TIM_SR_CC2IF_Pos                    (2U)
6929 #define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)             /*!< 0x00000004 */
6930 #define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                        /*!<Capture/Compare 2 interrupt Flag */
6931 #define TIM_SR_CC3IF_Pos                    (3U)
6932 #define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)             /*!< 0x00000008 */
6933 #define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                        /*!<Capture/Compare 3 interrupt Flag */
6934 #define TIM_SR_CC4IF_Pos                    (4U)
6935 #define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)             /*!< 0x00000010 */
6936 #define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                        /*!<Capture/Compare 4 interrupt Flag */
6937 #define TIM_SR_COMIF_Pos                    (5U)
6938 #define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)             /*!< 0x00000020 */
6939 #define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                        /*!<COM interrupt Flag */
6940 #define TIM_SR_TIF_Pos                      (6U)
6941 #define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)               /*!< 0x00000040 */
6942 #define TIM_SR_TIF                          TIM_SR_TIF_Msk                          /*!<Trigger interrupt Flag */
6943 #define TIM_SR_BIF_Pos                      (7U)
6944 #define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)               /*!< 0x00000080 */
6945 #define TIM_SR_BIF                          TIM_SR_BIF_Msk                          /*!<Break interrupt Flag */
6946 #define TIM_SR_B2IF_Pos                     (8U)
6947 #define TIM_SR_B2IF_Msk                     (0x1UL << TIM_SR_B2IF_Pos)              /*!< 0x00000100 */
6948 #define TIM_SR_B2IF                         TIM_SR_B2IF_Msk                         /*!<Break 2 interrupt Flag */
6949 #define TIM_SR_CC1OF_Pos                    (9U)
6950 #define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)             /*!< 0x00000200 */
6951 #define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                        /*!<Capture/Compare 1 Overcapture Flag */
6952 #define TIM_SR_CC2OF_Pos                    (10U)
6953 #define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)             /*!< 0x00000400 */
6954 #define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                        /*!<Capture/Compare 2 Overcapture Flag */
6955 #define TIM_SR_CC3OF_Pos                    (11U)
6956 #define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)             /*!< 0x00000800 */
6957 #define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                        /*!<Capture/Compare 3 Overcapture Flag */
6958 #define TIM_SR_CC4OF_Pos                    (12U)
6959 #define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)             /*!< 0x00001000 */
6960 #define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                        /*!<Capture/Compare 4 Overcapture Flag */
6961 #define TIM_SR_SBIF_Pos                     (13U)
6962 #define TIM_SR_SBIF_Msk                     (0x1UL << TIM_SR_SBIF_Pos)              /*!< 0x00002000 */
6963 #define TIM_SR_SBIF                         TIM_SR_SBIF_Msk                         /*!<System Break interrupt Flag */
6964 #define TIM_SR_CC5IF_Pos                    (16U)
6965 #define TIM_SR_CC5IF_Msk                    (0x1UL << TIM_SR_CC5IF_Pos)             /*!< 0x00010000 */
6966 #define TIM_SR_CC5IF                        TIM_SR_CC5IF_Msk                        /*!<Capture/Compare 5 interrupt Flag */
6967 #define TIM_SR_CC6IF_Pos                    (17U)
6968 #define TIM_SR_CC6IF_Msk                    (0x1UL << TIM_SR_CC6IF_Pos)             /*!< 0x00020000 */
6969 #define TIM_SR_CC6IF                        TIM_SR_CC6IF_Msk                        /*!<Capture/Compare 6 interrupt Flag */
6970 #define TIM_SR_IDXF_Pos                     (20U)
6971 #define TIM_SR_IDXF_Msk                     (0x1UL << TIM_SR_IDXF_Pos)              /*!< 0x00100000 */
6972 #define TIM_SR_IDXF                         TIM_SR_IDXF_Msk                         /*!<Encoder index interrupt flag */
6973 #define TIM_SR_DIRF_Pos                     (21U)
6974 #define TIM_SR_DIRF_Msk                     (0x1UL << TIM_SR_DIRF_Pos)              /*!< 0x00200000 */
6975 #define TIM_SR_DIRF                         TIM_SR_DIRF_Msk                         /*!<Encoder direction change interrupt flag */
6976 #define TIM_SR_IERRF_Pos                    (22U)
6977 #define TIM_SR_IERRF_Msk                    (0x1UL << TIM_SR_IERRF_Pos)             /*!< 0x00400000 */
6978 #define TIM_SR_IERRF                        TIM_SR_IERRF_Msk                        /*!<Encoder index error flag */
6979 #define TIM_SR_TERRF_Pos                    (23U)
6980 #define TIM_SR_TERRF_Msk                    (0x1UL << TIM_SR_TERRF_Pos)             /*!< 0x00800000 */
6981 #define TIM_SR_TERRF                        TIM_SR_TERRF_Msk                        /*!<Encoder transition error flag */
6982 
6983 /*******************  Bit definition for TIM_EGR register  ********************/
6984 #define TIM_EGR_UG_Pos                      (0U)
6985 #define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)               /*!< 0x00000001 */
6986 #define TIM_EGR_UG                          TIM_EGR_UG_Msk                          /*!<Update Generation */
6987 #define TIM_EGR_CC1G_Pos                    (1U)
6988 #define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)             /*!< 0x00000002 */
6989 #define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                        /*!<Capture/Compare 1 Generation */
6990 #define TIM_EGR_CC2G_Pos                    (2U)
6991 #define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)             /*!< 0x00000004 */
6992 #define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                        /*!<Capture/Compare 2 Generation */
6993 #define TIM_EGR_CC3G_Pos                    (3U)
6994 #define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)             /*!< 0x00000008 */
6995 #define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                        /*!<Capture/Compare 3 Generation */
6996 #define TIM_EGR_CC4G_Pos                    (4U)
6997 #define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)             /*!< 0x00000010 */
6998 #define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                        /*!<Capture/Compare 4 Generation */
6999 #define TIM_EGR_COMG_Pos                    (5U)
7000 #define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)             /*!< 0x00000020 */
7001 #define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                        /*!<Capture/Compare Control Update Generation */
7002 #define TIM_EGR_TG_Pos                      (6U)
7003 #define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)               /*!< 0x00000040 */
7004 #define TIM_EGR_TG                          TIM_EGR_TG_Msk                          /*!<Trigger Generation */
7005 #define TIM_EGR_BG_Pos                      (7U)
7006 #define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)               /*!< 0x00000080 */
7007 #define TIM_EGR_BG                          TIM_EGR_BG_Msk                          /*!<Break Generation */
7008 #define TIM_EGR_B2G_Pos                     (8U)
7009 #define TIM_EGR_B2G_Msk                     (0x1UL << TIM_EGR_B2G_Pos)              /*!< 0x00000100 */
7010 #define TIM_EGR_B2G                         TIM_EGR_B2G_Msk                         /*!<Break 2 Generation */
7011 
7012 
7013 /******************  Bit definition for TIM_CCMR1 register  *******************/
7014 #define TIM_CCMR1_CC1S_Pos                  (0U)
7015 #define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000003 */
7016 #define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                      /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7017 #define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000001 */
7018 #define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000002 */
7019 #define TIM_CCMR1_OC1FE_Pos                 (2U)
7020 #define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)          /*!< 0x00000004 */
7021 #define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                     /*!<Output Compare 1 Fast enable */
7022 #define TIM_CCMR1_OC1PE_Pos                 (3U)
7023 #define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)          /*!< 0x00000008 */
7024 #define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                     /*!<Output Compare 1 Preload enable */
7025 #define TIM_CCMR1_OC1M_Pos                  (4U)
7026 #define TIM_CCMR1_OC1M_Msk                  (0x1007UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010070 */
7027 #define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                      /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7028 #define TIM_CCMR1_OC1M_0                    (0x0001UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000010 */
7029 #define TIM_CCMR1_OC1M_1                    (0x0002UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000020 */
7030 #define TIM_CCMR1_OC1M_2                    (0x0004UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000040 */
7031 #define TIM_CCMR1_OC1M_3                    (0x1000UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010000 */
7032 #define TIM_CCMR1_OC1CE_Pos                 (7U)
7033 #define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)          /*!< 0x00000080 */
7034 #define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                     /*!<Output Compare 1 Clear Enable */
7035 #define TIM_CCMR1_CC2S_Pos                  (8U)
7036 #define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000300 */
7037 #define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                      /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7038 #define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000100 */
7039 #define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000200 */
7040 #define TIM_CCMR1_OC2FE_Pos                 (10U)
7041 #define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)          /*!< 0x00000400 */
7042 #define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                     /*!<Output Compare 2 Fast enable */
7043 #define TIM_CCMR1_OC2PE_Pos                 (11U)
7044 #define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)          /*!< 0x00000800 */
7045 #define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                     /*!<Output Compare 2 Preload enable */
7046 #define TIM_CCMR1_OC2M_Pos                  (12U)
7047 #define TIM_CCMR1_OC2M_Msk                  (0x1007UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01007000 */
7048 #define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                      /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7049 #define TIM_CCMR1_OC2M_0                    (0x0001UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00001000 */
7050 #define TIM_CCMR1_OC2M_1                    (0x0002UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00002000 */
7051 #define TIM_CCMR1_OC2M_2                    (0x0004UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00004000 */
7052 #define TIM_CCMR1_OC2M_3                    (0x1000UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01000000 */
7053 #define TIM_CCMR1_OC2CE_Pos                 (15U)
7054 #define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)          /*!< 0x00008000 */
7055 #define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                     /*!<Output Compare 2 Clear Enable */
7056 
7057 /*----------------------------------------------------------------------------*/
7058 #define TIM_CCMR1_IC1PSC_Pos                (2U)
7059 #define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x0000000C */
7060 #define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk                    /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7061 #define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000004 */
7062 #define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000008 */
7063 #define TIM_CCMR1_IC1F_Pos                  (4U)
7064 #define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)           /*!< 0x000000F0 */
7065 #define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                      /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7066 #define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000010 */
7067 #define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000020 */
7068 #define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000040 */
7069 #define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000080 */
7070 #define TIM_CCMR1_IC2PSC_Pos                (10U)
7071 #define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000C00 */
7072 #define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk                    /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7073 #define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000400 */
7074 #define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000800 */
7075 #define TIM_CCMR1_IC2F_Pos                  (12U)
7076 #define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)           /*!< 0x0000F000 */
7077 #define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                      /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7078 #define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00001000 */
7079 #define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00002000 */
7080 #define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00004000 */
7081 #define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00008000 */
7082 
7083 /******************  Bit definition for TIM_CCMR2 register  *******************/
7084 #define TIM_CCMR2_CC3S_Pos                  (0U)
7085 #define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000003 */
7086 #define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                      /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7087 #define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000001 */
7088 #define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000002 */
7089 #define TIM_CCMR2_OC3FE_Pos                 (2U)
7090 #define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)          /*!< 0x00000004 */
7091 #define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                     /*!<Output Compare 3 Fast enable */
7092 #define TIM_CCMR2_OC3PE_Pos                 (3U)
7093 #define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)          /*!< 0x00000008 */
7094 #define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                     /*!<Output Compare 3 Preload enable */
7095 #define TIM_CCMR2_OC3M_Pos                  (4U)
7096 #define TIM_CCMR2_OC3M_Msk                  (0x1007UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010070 */
7097 #define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                      /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7098 #define TIM_CCMR2_OC3M_0                    (0x0001UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000010 */
7099 #define TIM_CCMR2_OC3M_1                    (0x0002UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000020 */
7100 #define TIM_CCMR2_OC3M_2                    (0x0004UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000040 */
7101 #define TIM_CCMR2_OC3M_3                    (0x1000UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010000 */
7102 #define TIM_CCMR2_OC3CE_Pos                 (7U)
7103 #define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)          /*!< 0x00000080 */
7104 #define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                     /*!<Output Compare 3 Clear Enable */
7105 #define TIM_CCMR2_CC4S_Pos                  (8U)
7106 #define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000300 */
7107 #define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                      /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7108 #define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000100 */
7109 #define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000200 */
7110 #define TIM_CCMR2_OC4FE_Pos                 (10U)
7111 #define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)          /*!< 0x00000400 */
7112 #define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                     /*!<Output Compare 4 Fast enable */
7113 #define TIM_CCMR2_OC4PE_Pos                 (11U)
7114 #define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)          /*!< 0x00000800 */
7115 #define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                     /*!<Output Compare 4 Preload enable */
7116 #define TIM_CCMR2_OC4M_Pos                  (12U)
7117 #define TIM_CCMR2_OC4M_Msk                  (0x1007UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01007000 */
7118 #define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                      /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7119 #define TIM_CCMR2_OC4M_0                    (0x0001UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00001000 */
7120 #define TIM_CCMR2_OC4M_1                    (0x0002UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00002000 */
7121 #define TIM_CCMR2_OC4M_2                    (0x0004UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00004000 */
7122 #define TIM_CCMR2_OC4M_3                    (0x1000UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01000000 */
7123 #define TIM_CCMR2_OC4CE_Pos                 (15U)
7124 #define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)          /*!< 0x00008000 */
7125 #define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                     /*!<Output Compare 4 Clear Enable */
7126 
7127 /*----------------------------------------------------------------------------*/
7128 #define TIM_CCMR2_IC3PSC_Pos                (2U)
7129 #define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x0000000C */
7130 #define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk                    /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7131 #define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000004 */
7132 #define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000008 */
7133 #define TIM_CCMR2_IC3F_Pos                  (4U)
7134 #define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)           /*!< 0x000000F0 */
7135 #define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                      /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7136 #define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000010 */
7137 #define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000020 */
7138 #define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000040 */
7139 #define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000080 */
7140 #define TIM_CCMR2_IC4PSC_Pos                (10U)
7141 #define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000C00 */
7142 #define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk                    /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7143 #define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000400 */
7144 #define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000800 */
7145 #define TIM_CCMR2_IC4F_Pos                  (12U)
7146 #define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)           /*!< 0x0000F000 */
7147 #define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                      /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7148 #define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00001000 */
7149 #define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00002000 */
7150 #define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00004000 */
7151 #define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00008000 */
7152 
7153 /******************  Bit definition for TIM_CCMR3 register  *******************/
7154 #define TIM_CCMR3_OC5FE_Pos                 (2U)
7155 #define TIM_CCMR3_OC5FE_Msk                 (0x1UL << TIM_CCMR3_OC5FE_Pos)          /*!< 0x00000004 */
7156 #define TIM_CCMR3_OC5FE                     TIM_CCMR3_OC5FE_Msk                     /*!<Output Compare 5 Fast enable */
7157 #define TIM_CCMR3_OC5PE_Pos                 (3U)
7158 #define TIM_CCMR3_OC5PE_Msk                 (0x1UL << TIM_CCMR3_OC5PE_Pos)          /*!< 0x00000008 */
7159 #define TIM_CCMR3_OC5PE                     TIM_CCMR3_OC5PE_Msk                     /*!<Output Compare 5 Preload enable */
7160 #define TIM_CCMR3_OC5M_Pos                  (4U)
7161 #define TIM_CCMR3_OC5M_Msk                  (0x1007UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010070 */
7162 #define TIM_CCMR3_OC5M                      TIM_CCMR3_OC5M_Msk                      /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
7163 #define TIM_CCMR3_OC5M_0                    (0x0001UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000010 */
7164 #define TIM_CCMR3_OC5M_1                    (0x0002UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000020 */
7165 #define TIM_CCMR3_OC5M_2                    (0x0004UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000040 */
7166 #define TIM_CCMR3_OC5M_3                    (0x1000UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010000 */
7167 #define TIM_CCMR3_OC5CE_Pos                 (7U)
7168 #define TIM_CCMR3_OC5CE_Msk                 (0x1UL << TIM_CCMR3_OC5CE_Pos)          /*!< 0x00000080 */
7169 #define TIM_CCMR3_OC5CE                     TIM_CCMR3_OC5CE_Msk                     /*!<Output Compare 5 Clear Enable */
7170 #define TIM_CCMR3_OC6FE_Pos                 (10U)
7171 #define TIM_CCMR3_OC6FE_Msk                 (0x1UL << TIM_CCMR3_OC6FE_Pos)          /*!< 0x00000400 */
7172 #define TIM_CCMR3_OC6FE                     TIM_CCMR3_OC6FE_Msk                     /*!<Output Compare 6 Fast enable */
7173 #define TIM_CCMR3_OC6PE_Pos                 (11U)
7174 #define TIM_CCMR3_OC6PE_Msk                 (0x1UL << TIM_CCMR3_OC6PE_Pos)          /*!< 0x00000800 */
7175 #define TIM_CCMR3_OC6PE                     TIM_CCMR3_OC6PE_Msk                     /*!<Output Compare 6 Preload enable */
7176 #define TIM_CCMR3_OC6M_Pos                  (12U)
7177 #define TIM_CCMR3_OC6M_Msk                  (0x1007UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01007000 */
7178 #define TIM_CCMR3_OC6M                      TIM_CCMR3_OC6M_Msk                      /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
7179 #define TIM_CCMR3_OC6M_0                    (0x0001UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00001000 */
7180 #define TIM_CCMR3_OC6M_1                    (0x0002UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00002000 */
7181 #define TIM_CCMR3_OC6M_2                    (0x0004UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00004000 */
7182 #define TIM_CCMR3_OC6M_3                    (0x1000UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01000000 */
7183 #define TIM_CCMR3_OC6CE_Pos                 (15U)
7184 #define TIM_CCMR3_OC6CE_Msk                 (0x1UL << TIM_CCMR3_OC6CE_Pos)          /*!< 0x00008000 */
7185 #define TIM_CCMR3_OC6CE                     TIM_CCMR3_OC6CE_Msk                     /*!<Output Compare 6 Clear Enable */
7186 
7187 /*******************  Bit definition for TIM_CCER register  *******************/
7188 #define TIM_CCER_CC1E_Pos                   (0U)
7189 #define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)            /*!< 0x00000001 */
7190 #define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                       /*!<Capture/Compare 1 output enable */
7191 #define TIM_CCER_CC1P_Pos                   (1U)
7192 #define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)            /*!< 0x00000002 */
7193 #define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                       /*!<Capture/Compare 1 output Polarity */
7194 #define TIM_CCER_CC1NE_Pos                  (2U)
7195 #define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)           /*!< 0x00000004 */
7196 #define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                      /*!<Capture/Compare 1 Complementary output enable */
7197 #define TIM_CCER_CC1NP_Pos                  (3U)
7198 #define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)           /*!< 0x00000008 */
7199 #define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                      /*!<Capture/Compare 1 Complementary output Polarity */
7200 #define TIM_CCER_CC2E_Pos                   (4U)
7201 #define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)            /*!< 0x00000010 */
7202 #define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                       /*!<Capture/Compare 2 output enable */
7203 #define TIM_CCER_CC2P_Pos                   (5U)
7204 #define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)            /*!< 0x00000020 */
7205 #define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                       /*!<Capture/Compare 2 output Polarity */
7206 #define TIM_CCER_CC2NE_Pos                  (6U)
7207 #define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)           /*!< 0x00000040 */
7208 #define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                      /*!<Capture/Compare 2 Complementary output enable */
7209 #define TIM_CCER_CC2NP_Pos                  (7U)
7210 #define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)           /*!< 0x00000080 */
7211 #define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                      /*!<Capture/Compare 2 Complementary output Polarity */
7212 #define TIM_CCER_CC3E_Pos                   (8U)
7213 #define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)            /*!< 0x00000100 */
7214 #define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                       /*!<Capture/Compare 3 output enable */
7215 #define TIM_CCER_CC3P_Pos                   (9U)
7216 #define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)            /*!< 0x00000200 */
7217 #define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                       /*!<Capture/Compare 3 output Polarity */
7218 #define TIM_CCER_CC3NE_Pos                  (10U)
7219 #define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)           /*!< 0x00000400 */
7220 #define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                      /*!<Capture/Compare 3 Complementary output enable */
7221 #define TIM_CCER_CC3NP_Pos                  (11U)
7222 #define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)           /*!< 0x00000800 */
7223 #define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                      /*!<Capture/Compare 3 Complementary output Polarity */
7224 #define TIM_CCER_CC4E_Pos                   (12U)
7225 #define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)            /*!< 0x00001000 */
7226 #define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                       /*!<Capture/Compare 4 output enable */
7227 #define TIM_CCER_CC4P_Pos                   (13U)
7228 #define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)            /*!< 0x00002000 */
7229 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                       /*!<Capture/Compare 4 output Polarity */
7230 #define TIM_CCER_CC4NE_Pos                  (14U)
7231 #define TIM_CCER_CC4NE_Msk                  (0x1UL << TIM_CCER_CC4NE_Pos)           /*!< 0x00004000 */
7232 #define TIM_CCER_CC4NE                      TIM_CCER_CC4NE_Msk                      /*!<Capture/Compare 4 Complementary output enable */
7233 #define TIM_CCER_CC4NP_Pos                  (15U)
7234 #define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)           /*!< 0x00008000 */
7235 #define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                      /*!<Capture/Compare 4 Complementary output Polarity */
7236 #define TIM_CCER_CC5E_Pos                   (16U)
7237 #define TIM_CCER_CC5E_Msk                   (0x1UL << TIM_CCER_CC5E_Pos)            /*!< 0x00010000 */
7238 #define TIM_CCER_CC5E                       TIM_CCER_CC5E_Msk                       /*!<Capture/Compare 5 output enable */
7239 #define TIM_CCER_CC5P_Pos                   (17U)
7240 #define TIM_CCER_CC5P_Msk                   (0x1UL << TIM_CCER_CC5P_Pos)            /*!< 0x00020000 */
7241 #define TIM_CCER_CC5P                       TIM_CCER_CC5P_Msk                       /*!<Capture/Compare 5 output Polarity */
7242 #define TIM_CCER_CC6E_Pos                   (20U)
7243 #define TIM_CCER_CC6E_Msk                   (0x1UL << TIM_CCER_CC6E_Pos)            /*!< 0x00100000 */
7244 #define TIM_CCER_CC6E                       TIM_CCER_CC6E_Msk                       /*!<Capture/Compare 6 output enable */
7245 #define TIM_CCER_CC6P_Pos                   (21U)
7246 #define TIM_CCER_CC6P_Msk                   (0x1UL << TIM_CCER_CC6P_Pos)            /*!< 0x00200000 */
7247 #define TIM_CCER_CC6P                       TIM_CCER_CC6P_Msk                       /*!<Capture/Compare 6 output Polarity */
7248 
7249 /*******************  Bit definition for TIM_CNT register  ********************/
7250 #define TIM_CNT_CNT_Pos                     (0U)
7251 #define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)       /*!< 0xFFFFFFFF */
7252 #define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                         /*!<Counter Value */
7253 #define TIM_CNT_UIFCPY_Pos                  (31U)
7254 #define TIM_CNT_UIFCPY_Msk                  (0x1UL << TIM_CNT_UIFCPY_Pos)           /*!< 0x80000000 */
7255 #define TIM_CNT_UIFCPY                      TIM_CNT_UIFCPY_Msk                      /*!<Update interrupt flag copy (if UIFREMAP=1) */
7256 
7257 /*******************  Bit definition for TIM_PSC register  ********************/
7258 #define TIM_PSC_PSC_Pos                     (0U)
7259 #define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)           /*!< 0x0000FFFF */
7260 #define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                         /*!<Prescaler Value */
7261 
7262 /*******************  Bit definition for TIM_ARR register  ********************/
7263 #define TIM_ARR_ARR_Pos                     (0U)
7264 #define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)       /*!< 0xFFFFFFFF */
7265 #define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                         /*!<Actual auto-reload Value */
7266 
7267 /*******************  Bit definition for TIM_RCR register  ********************/
7268 #define TIM_RCR_REP_Pos                     (0U)
7269 #define TIM_RCR_REP_Msk                     (0xFFFFUL << TIM_RCR_REP_Pos)           /*!< 0x0000FFFF */
7270 #define TIM_RCR_REP                         TIM_RCR_REP_Msk                         /*!<Repetition Counter Value */
7271 
7272 /*******************  Bit definition for TIM_CCR1 register  *******************/
7273 #define TIM_CCR1_CCR1_Pos                   (0U)
7274 #define TIM_CCR1_CCR1_Msk                   (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0xFFFFFFFF */
7275 #define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                       /*!<Capture/Compare 1 Value */
7276 
7277 /*******************  Bit definition for TIM_CCR2 register  *******************/
7278 #define TIM_CCR2_CCR2_Pos                   (0U)
7279 #define TIM_CCR2_CCR2_Msk                   (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0xFFFFFFFF */
7280 #define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                       /*!<Capture/Compare 2 Value */
7281 
7282 /*******************  Bit definition for TIM_CCR3 register  *******************/
7283 #define TIM_CCR3_CCR3_Pos                   (0U)
7284 #define TIM_CCR3_CCR3_Msk                   (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0xFFFFFFFF */
7285 #define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                       /*!<Capture/Compare 3 Value */
7286 
7287 /*******************  Bit definition for TIM_CCR4 register  *******************/
7288 #define TIM_CCR4_CCR4_Pos                   (0U)
7289 #define TIM_CCR4_CCR4_Msk                   (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0xFFFFFFFF */
7290 #define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                       /*!<Capture/Compare 4 Value */
7291 
7292 /*******************  Bit definition for TIM_CCR5 register  *******************/
7293 #define TIM_CCR5_CCR5_Pos                   (0U)
7294 #define TIM_CCR5_CCR5_Msk                   (0xFFFFFUL << TIM_CCR5_CCR5_Pos)        /*!< 0x000FFFFF */
7295 #define TIM_CCR5_CCR5                       TIM_CCR5_CCR5_Msk                       /*!<Capture/Compare 5 Value */
7296 #define TIM_CCR5_GC5C1_Pos                  (29U)
7297 #define TIM_CCR5_GC5C1_Msk                  (0x1UL << TIM_CCR5_GC5C1_Pos)           /*!< 0x20000000 */
7298 #define TIM_CCR5_GC5C1                      TIM_CCR5_GC5C1_Msk                      /*!<Group Channel 5 and Channel 1 */
7299 #define TIM_CCR5_GC5C2_Pos                  (30U)
7300 #define TIM_CCR5_GC5C2_Msk                  (0x1UL << TIM_CCR5_GC5C2_Pos)           /*!< 0x40000000 */
7301 #define TIM_CCR5_GC5C2                      TIM_CCR5_GC5C2_Msk                      /*!<Group Channel 5 and Channel 2 */
7302 #define TIM_CCR5_GC5C3_Pos                  (31U)
7303 #define TIM_CCR5_GC5C3_Msk                  (0x1UL << TIM_CCR5_GC5C3_Pos)           /*!< 0x80000000 */
7304 #define TIM_CCR5_GC5C3                      TIM_CCR5_GC5C3_Msk                      /*!<Group Channel 5 and Channel 3 */
7305 
7306 /*******************  Bit definition for TIM_CCR6 register  *******************/
7307 #define TIM_CCR6_CCR6_Pos                   (0U)
7308 #define TIM_CCR6_CCR6_Msk                   (0xFFFFFUL << TIM_CCR6_CCR6_Pos)        /*!< 0x000FFFFF */
7309 #define TIM_CCR6_CCR6                       TIM_CCR6_CCR6_Msk                       /*!<Capture/Compare 6 Value */
7310 
7311 /*******************  Bit definition for TIM_BDTR register  *******************/
7312 #define TIM_BDTR_DTG_Pos                    (0U)
7313 #define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)            /*!< 0x000000FF */
7314 #define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                        /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7315 #define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000001 */
7316 #define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000002 */
7317 #define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000004 */
7318 #define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000008 */
7319 #define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000010 */
7320 #define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000020 */
7321 #define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000040 */
7322 #define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000080 */
7323 #define TIM_BDTR_LOCK_Pos                   (8U)
7324 #define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000300 */
7325 #define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                       /*!<LOCK[1:0] bits (Lock Configuration) */
7326 #define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000100 */
7327 #define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000200 */
7328 #define TIM_BDTR_OSSI_Pos                   (10U)
7329 #define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)            /*!< 0x00000400 */
7330 #define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                       /*!<Off-State Selection for Idle mode */
7331 #define TIM_BDTR_OSSR_Pos                   (11U)
7332 #define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)            /*!< 0x00000800 */
7333 #define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                       /*!<Off-State Selection for Run mode */
7334 #define TIM_BDTR_BKE_Pos                    (12U)
7335 #define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)             /*!< 0x00001000 */
7336 #define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                        /*!<Break enable for Break 1 */
7337 #define TIM_BDTR_BKP_Pos                    (13U)
7338 #define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)             /*!< 0x00002000 */
7339 #define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                        /*!<Break Polarity for Break 1 */
7340 #define TIM_BDTR_AOE_Pos                    (14U)
7341 #define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)             /*!< 0x00004000 */
7342 #define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                        /*!<Automatic Output enable */
7343 #define TIM_BDTR_MOE_Pos                    (15U)
7344 #define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)             /*!< 0x00008000 */
7345 #define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                        /*!<Main Output enable */
7346 #define TIM_BDTR_BKF_Pos                    (16U)
7347 #define TIM_BDTR_BKF_Msk                    (0xFUL << TIM_BDTR_BKF_Pos)             /*!< 0x000F0000 */
7348 #define TIM_BDTR_BKF                        TIM_BDTR_BKF_Msk                        /*!<Break Filter for Break 1 */
7349 #define TIM_BDTR_BK2F_Pos                   (20U)
7350 #define TIM_BDTR_BK2F_Msk                   (0xFUL << TIM_BDTR_BK2F_Pos)            /*!< 0x00F00000 */
7351 #define TIM_BDTR_BK2F                       TIM_BDTR_BK2F_Msk                       /*!<Break Filter for Break 2 */
7352 #define TIM_BDTR_BK2E_Pos                   (24U)
7353 #define TIM_BDTR_BK2E_Msk                   (0x1UL << TIM_BDTR_BK2E_Pos)            /*!< 0x01000000 */
7354 #define TIM_BDTR_BK2E                       TIM_BDTR_BK2E_Msk                       /*!<Break enable for Break 2 */
7355 #define TIM_BDTR_BK2P_Pos                   (25U)
7356 #define TIM_BDTR_BK2P_Msk                   (0x1UL << TIM_BDTR_BK2P_Pos)            /*!< 0x02000000 */
7357 #define TIM_BDTR_BK2P                       TIM_BDTR_BK2P_Msk                       /*!<Break Polarity for Break 2 */
7358 #define TIM_BDTR_BKDSRM_Pos                 (26U)
7359 #define TIM_BDTR_BKDSRM_Msk                 (0x1UL << TIM_BDTR_BKDSRM_Pos)          /*!< 0x04000000 */
7360 #define TIM_BDTR_BKDSRM                     TIM_BDTR_BKDSRM_Msk                     /*!<Break disarming/re-arming */
7361 #define TIM_BDTR_BK2DSRM_Pos                (27U)
7362 #define TIM_BDTR_BK2DSRM_Msk                (0x1UL << TIM_BDTR_BK2DSRM_Pos)         /*!< 0x08000000 */
7363 #define TIM_BDTR_BK2DSRM                    TIM_BDTR_BK2DSRM_Msk                    /*!<Break2 disarming/re-arming */
7364 #define TIM_BDTR_BKBID_Pos                  (28U)
7365 #define TIM_BDTR_BKBID_Msk                  (0x1UL << TIM_BDTR_BKBID_Pos)           /*!< 0x10000000 */
7366 #define TIM_BDTR_BKBID                      TIM_BDTR_BKBID_Msk                      /*!<Break BIDirectional */
7367 #define TIM_BDTR_BK2BID_Pos                 (29U)
7368 #define TIM_BDTR_BK2BID_Msk                 (0x1UL << TIM_BDTR_BK2BID_Pos)          /*!< 0x20000000 */
7369 #define TIM_BDTR_BK2BID                     TIM_BDTR_BK2BID_Msk                     /*!<Break2 BIDirectional */
7370 
7371 /*******************  Bit definition for TIM_DCR register  ********************/
7372 #define TIM_DCR_DBA_Pos                     (0U)
7373 #define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)             /*!< 0x0000001F */
7374 #define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                         /*!<DBA[4:0] bits (DMA Base Address) */
7375 #define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)             /*!< 0x00000001 */
7376 #define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)             /*!< 0x00000002 */
7377 #define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)             /*!< 0x00000004 */
7378 #define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)             /*!< 0x00000008 */
7379 #define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)             /*!< 0x00000010 */
7380 #define TIM_DCR_DBL_Pos                     (8U)
7381 #define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)             /*!< 0x00001F00 */
7382 #define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                         /*!<DBL[4:0] bits (DMA Burst Length) */
7383 #define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)             /*!< 0x00000100 */
7384 #define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)             /*!< 0x00000200 */
7385 #define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)             /*!< 0x00000400 */
7386 #define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)             /*!< 0x00000800 */
7387 #define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)             /*!< 0x00001000 */
7388 #define TIM_DCR_DBSS_Pos                    (16U)
7389 #define TIM_DCR_DBSS_Msk                    (0xFUL << TIM_DCR_DBSS_Pos)             /*!< 0x00000F00 */
7390 #define TIM_DCR_DBSS                        TIM_DCR_DBSS_Msk                        /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
7391 #define TIM_DCR_DBSS_0                      (0x01UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000100 */
7392 #define TIM_DCR_DBSS_1                      (0x02UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000200 */
7393 #define TIM_DCR_DBSS_2                      (0x04UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000400 */
7394 #define TIM_DCR_DBSS_3                      (0x08UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000800 */
7395 
7396 /*******************  Bit definition for TIM1_AF1 register  *******************/
7397 #define TIM1_AF1_BKINE_Pos                  (0U)
7398 #define TIM1_AF1_BKINE_Msk                  (0x1UL << TIM1_AF1_BKINE_Pos)           /*!< 0x00000001 */
7399 #define TIM1_AF1_BKINE                      TIM1_AF1_BKINE_Msk                      /*!<BRK BKIN input enable */
7400 #define TIM1_AF1_BKCMP1E_Pos                (1U)
7401 #define TIM1_AF1_BKCMP1E_Msk                (0x1UL << TIM1_AF1_BKCMP1E_Pos)         /*!< 0x00000002 */
7402 #define TIM1_AF1_BKCMP1E                    TIM1_AF1_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
7403 #define TIM1_AF1_BKCMP2E_Pos                (2U)
7404 #define TIM1_AF1_BKCMP2E_Msk                (0x1UL << TIM1_AF1_BKCMP2E_Pos)         /*!< 0x00000004 */
7405 #define TIM1_AF1_BKCMP2E                    TIM1_AF1_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
7406 #define TIM1_AF1_BKDF1BK0E_Pos              (8U)
7407 #define TIM1_AF1_BKDF1BK0E_Msk              (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)       /*!< 0x00000100 */
7408 #define TIM1_AF1_BKDF1BK0E                  TIM1_AF1_BKDF1BK0E_Msk                  /*!<BRK mdf1_break[0](TIM1) or mdf1_break[2](TIM2) enable */
7409 #define TIM1_AF1_BKINP_Pos                  (9U)
7410 #define TIM1_AF1_BKINP_Msk                  (0x1UL << TIM1_AF1_BKINP_Pos)           /*!< 0x00000200 */
7411 #define TIM1_AF1_BKINP                      TIM1_AF1_BKINP_Msk                      /*!<BRK BKIN input polarity */
7412 #define TIM1_AF1_BKCMP1P_Pos                (10U)
7413 #define TIM1_AF1_BKCMP1P_Msk                (0x1UL << TIM1_AF1_BKCMP1P_Pos)         /*!< 0x00000400 */
7414 #define TIM1_AF1_BKCMP1P                    TIM1_AF1_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
7415 #define TIM1_AF1_BKCMP2P_Pos                (11U)
7416 #define TIM1_AF1_BKCMP2P_Msk                (0x1UL << TIM1_AF1_BKCMP2P_Pos)         /*!< 0x00000800 */
7417 #define TIM1_AF1_BKCMP2P                    TIM1_AF1_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
7418 #define TIM1_AF1_ETRSEL_Pos                 (14U)
7419 #define TIM1_AF1_ETRSEL_Msk                 (0xFUL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x0003C000 */
7420 #define TIM1_AF1_ETRSEL                     TIM1_AF1_ETRSEL_Msk                     /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
7421 #define TIM1_AF1_ETRSEL_0                   (0x1UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00004000 */
7422 #define TIM1_AF1_ETRSEL_1                   (0x2UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00008000 */
7423 #define TIM1_AF1_ETRSEL_2                   (0x4UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00010000 */
7424 #define TIM1_AF1_ETRSEL_3                   (0x8UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00020000 */
7425 
7426 /*******************  Bit definition for TIM1_AF2 register  *********************/
7427 #define TIM1_AF2_BK2INE_Pos                 (0U)
7428 #define TIM1_AF2_BK2INE_Msk                 (0x1UL << TIM1_AF2_BK2INE_Pos)          /*!< 0x00000001 */
7429 #define TIM1_AF2_BK2INE                     TIM1_AF2_BK2INE_Msk                     /*!<BRK2 BKIN input enable */
7430 #define TIM1_AF2_BK2CMP1E_Pos               (1U)
7431 #define TIM1_AF2_BK2CMP1E_Msk               (0x1UL << TIM1_AF2_BK2CMP1E_Pos)        /*!< 0x00000002 */
7432 #define TIM1_AF2_BK2CMP1E                   TIM1_AF2_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
7433 #define TIM1_AF2_BK2CMP2E_Pos               (2U)
7434 #define TIM1_AF2_BK2CMP2E_Msk               (0x1UL << TIM1_AF2_BK2CMP2E_Pos)        /*!< 0x00000004 */
7435 #define TIM1_AF2_BK2CMP2E                   TIM1_AF2_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
7436 #define TIM1_AF2_BK2DF1BK1E_Pos             (8U)
7437 #define TIM1_AF2_BK2DF1BK1E_Msk             (0x1UL << TIM1_AF2_BK2DF1BK1E_Pos)      /*!< 0x00000100 */
7438 #define TIM1_AF2_BK2DF1BK1E                 TIM1_AF2_BK2DF1BK1E_Msk                 /*!<BRK2 mdf1_break[1](TIM1) or mdf1_break[3](TIM8) enable */
7439 #define TIM1_AF2_BK2INP_Pos                 (9U)
7440 #define TIM1_AF2_BK2INP_Msk                 (0x1UL << TIM1_AF2_BK2INP_Pos)          /*!< 0x00000200 */
7441 #define TIM1_AF2_BK2INP                     TIM1_AF2_BK2INP_Msk                     /*!<BRK2 BKIN input polarity */
7442 #define TIM1_AF2_BK2CMP1P_Pos               (10U)
7443 #define TIM1_AF2_BK2CMP1P_Msk               (0x1UL << TIM1_AF2_BK2CMP1P_Pos)        /*!< 0x00000400 */
7444 #define TIM1_AF2_BK2CMP1P                   TIM1_AF2_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
7445 #define TIM1_AF2_BK2CMP2P_Pos               (11U)
7446 #define TIM1_AF2_BK2CMP2P_Msk               (0x1UL << TIM1_AF2_BK2CMP2P_Pos)        /*!< 0x00000800 */
7447 #define TIM1_AF2_BK2CMP2P                   TIM1_AF2_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
7448 #define TIM1_AF2_OCRSEL_Pos                 (16U)
7449 #define TIM1_AF2_OCRSEL_Msk                 (0x1UL << TIM1_AF2_OCRSEL_Pos)          /*!< 0x00010000 */
7450 #define TIM1_AF2_OCRSEL                     TIM1_AF2_OCRSEL_Msk                     /*!<OCREF_CLR source selection */
7451 #define TIM1_AF2_OCRSEL_0                   (0x1UL << TIM1_AF2_OCRSEL_Pos)          /*!< 0x00010000 */
7452 
7453 /*******************  Bit definition for TIM_OR1 register  *********************/
7454 #define TIM_OR1_RTCPREEN_Pos                 (1U)
7455 #define TIM_OR1_RTCPREEN_Msk                 (0x1UL << TIM_OR1_RTCPREEN_Pos)           /*!< 0x00000002 */
7456 #define TIM_OR1_RTCPREEN                     TIM_OR1_RTCPREEN_Msk                      /*!< RTCPRE HSE divider enable */
7457 
7458 /*******************  Bit definition for TIM_TISEL register  *********************/
7459 #define TIM_TISEL_TI1SEL_Pos                (0U)
7460 #define TIM_TISEL_TI1SEL_Msk                (0xFUL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x0000000F */
7461 #define TIM_TISEL_TI1SEL                    TIM_TISEL_TI1SEL_Msk                    /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
7462 #define TIM_TISEL_TI1SEL_0                  (0x1UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000001 */
7463 #define TIM_TISEL_TI1SEL_1                  (0x2UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000002 */
7464 #define TIM_TISEL_TI1SEL_2                  (0x4UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000004 */
7465 #define TIM_TISEL_TI1SEL_3                  (0x8UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000008 */
7466 #define TIM_TISEL_TI2SEL_Pos                (8U)
7467 #define TIM_TISEL_TI2SEL_Msk                (0xFUL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000F00 */
7468 #define TIM_TISEL_TI2SEL                    TIM_TISEL_TI2SEL_Msk                    /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
7469 #define TIM_TISEL_TI2SEL_0                  (0x1UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000100 */
7470 #define TIM_TISEL_TI2SEL_1                  (0x2UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000200 */
7471 #define TIM_TISEL_TI2SEL_2                  (0x4UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000400 */
7472 #define TIM_TISEL_TI2SEL_3                  (0x8UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000800 */
7473 #define TIM_TISEL_TI3SEL_Pos                (16U)
7474 #define TIM_TISEL_TI3SEL_Msk                (0xFUL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x000F0000 */
7475 #define TIM_TISEL_TI3SEL                    TIM_TISEL_TI3SEL_Msk                    /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
7476 #define TIM_TISEL_TI3SEL_0                  (0x1UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00010000 */
7477 #define TIM_TISEL_TI3SEL_1                  (0x2UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00020000 */
7478 #define TIM_TISEL_TI3SEL_2                  (0x4UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00040000 */
7479 #define TIM_TISEL_TI3SEL_3                  (0x8UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00080000 */
7480 #define TIM_TISEL_TI4SEL_Pos                (24U)
7481 #define TIM_TISEL_TI4SEL_Msk                (0xFUL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x0F000000 */
7482 #define TIM_TISEL_TI4SEL                    TIM_TISEL_TI4SEL_Msk                    /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
7483 #define TIM_TISEL_TI4SEL_0                  (0x1UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x01000000 */
7484 #define TIM_TISEL_TI4SEL_1                  (0x2UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x02000000 */
7485 #define TIM_TISEL_TI4SEL_2                  (0x4UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x04000000 */
7486 #define TIM_TISEL_TI4SEL_3                  (0x8UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x08000000 */
7487 
7488 /*******************  Bit definition for TIM_DTR2 register  *********************/
7489 #define TIM_DTR2_DTGF_Pos                   (0U)
7490 #define TIM_DTR2_DTGF_Msk                   (0xFFUL << TIM_DTR2_DTGF_Pos)           /*!< 0x0000000F */
7491 #define TIM_DTR2_DTGF                       TIM_DTR2_DTGF_Msk                       /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
7492 #define TIM_DTR2_DTGF_0                     (0x01UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000001 */
7493 #define TIM_DTR2_DTGF_1                     (0x02UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000002 */
7494 #define TIM_DTR2_DTGF_2                     (0x04UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000004 */
7495 #define TIM_DTR2_DTGF_3                     (0x08UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000008 */
7496 #define TIM_DTR2_DTGF_4                     (0x10UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000010 */
7497 #define TIM_DTR2_DTGF_5                     (0x20UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000020 */
7498 #define TIM_DTR2_DTGF_6                     (0x40UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000040 */
7499 #define TIM_DTR2_DTGF_7                     (0x80UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000080 */
7500 #define TIM_DTR2_DTAE_Pos                   (16U)
7501 #define TIM_DTR2_DTAE_Msk                   (0x1UL << TIM_DTR2_DTAE_Pos)            /*!< 0x00004000 */
7502 #define TIM_DTR2_DTAE                       TIM_DTR2_DTAE_Msk                       /*!<Deadtime asymmetric enable */
7503 #define TIM_DTR2_DTPE_Pos                   (17U)
7504 #define TIM_DTR2_DTPE_Msk                   (0x1UL << TIM_DTR2_DTPE_Pos)            /*!< 0x00008000 */
7505 #define TIM_DTR2_DTPE                       TIM_DTR2_DTPE_Msk                       /*!<Deadtime prelaod enable */
7506 
7507 /*******************  Bit definition for TIM_ECR register  *********************/
7508 #define TIM_ECR_IE_Pos                      (0U)
7509 #define TIM_ECR_IE_Msk                      (0x1UL << TIM_ECR_IE_Pos)               /*!< 0x00000001 */
7510 #define TIM_ECR_IE                          TIM_ECR_IE_Msk                          /*!<Index enable */
7511 #define TIM_ECR_IDIR_Pos                    (1U)
7512 #define TIM_ECR_IDIR_Msk                    (0x3UL << TIM_ECR_IDIR_Pos)             /*!< 0x00000006 */
7513 #define TIM_ECR_IDIR                        TIM_ECR_IDIR_Msk                        /*!<IDIR[1:0] bits (Index direction)*/
7514 #define TIM_ECR_IDIR_0                      (0x01UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000001 */
7515 #define TIM_ECR_IDIR_1                      (0x02UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000002 */
7516 #define TIM_ECR_IBLK_Pos                    (3U)
7517 #define TIM_ECR_IBLK_Msk                    (0x5UL << TIM_ECR_IBLK_Pos)             /*!< 0x00000018 */
7518 #define TIM_ECR_IBLK                        TIM_ECR_IBLK_Msk                        /*!<IBLK[1:0] bits (Index blanking)*/
7519 #define TIM_ECR_IBLK_0                      (0x01UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000008 */
7520 #define TIM_ECR_IBLK_1                      (0x02UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000010 */
7521 #define TIM_ECR_FIDX_Pos                    (5U)
7522 #define TIM_ECR_FIDX_Msk                    (0x1UL << TIM_ECR_FIDX_Pos)             /*!< 0x00000020 */
7523 #define TIM_ECR_FIDX                        TIM_ECR_FIDX_Msk                        /*!<First index enable */
7524 #define TIM_ECR_IPOS_Pos                    (6U)
7525 #define TIM_ECR_IPOS_Msk                    (0x3UL << TIM_ECR_IPOS_Pos)             /*!< 0x0000000C0 */
7526 #define TIM_ECR_IPOS                        TIM_ECR_IPOS_Msk                        /*!<IPOS[1:0] bits (Index positioning)*/
7527 #define TIM_ECR_IPOS_0                      (0x01UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000001 */
7528 #define TIM_ECR_IPOS_1                      (0x02UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000002 */
7529 #define TIM_ECR_PW_Pos                      (16U)
7530 #define TIM_ECR_PW_Msk                      (0xFFUL << TIM_ECR_PW_Pos)              /*!< 0x00FF0000 */
7531 #define TIM_ECR_PW                          TIM_ECR_PW_Msk                          /*!<PW[7:0] bits (Pulse width)*/
7532 #define TIM_ECR_PW_0                        (0x01UL << TIM_ECR_PW_Pos)              /*!< 0x00010000 */
7533 #define TIM_ECR_PW_1                        (0x02UL << TIM_ECR_PW_Pos)              /*!< 0x00020000 */
7534 #define TIM_ECR_PW_2                        (0x04UL << TIM_ECR_PW_Pos)              /*!< 0x00040000 */
7535 #define TIM_ECR_PW_3                        (0x08UL << TIM_ECR_PW_Pos)              /*!< 0x00080000 */
7536 #define TIM_ECR_PW_4                        (0x10UL << TIM_ECR_PW_Pos)              /*!< 0x00100000 */
7537 #define TIM_ECR_PW_5                        (0x20UL << TIM_ECR_PW_Pos)              /*!< 0x00200000 */
7538 #define TIM_ECR_PW_6                        (0x40UL << TIM_ECR_PW_Pos)              /*!< 0x00400000 */
7539 #define TIM_ECR_PW_7                        (0x80UL << TIM_ECR_PW_Pos)              /*!< 0x00800000 */
7540 #define TIM_ECR_PWPRSC_Pos                  (24U)
7541 #define TIM_ECR_PWPRSC_Msk                  (0x7UL << TIM_ECR_PWPRSC_Pos)           /*!< 0x07000000 */
7542 #define TIM_ECR_PWPRSC                      TIM_ECR_PWPRSC_Msk                      /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
7543 #define TIM_ECR_PWPRSC_0                    (0x01UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x01000000 */
7544 #define TIM_ECR_PWPRSC_1                    (0x02UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x02000000 */
7545 #define TIM_ECR_PWPRSC_2                    (0x04UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x04000000 */
7546 
7547 /*******************  Bit definition for TIM_DMAR register  *******************/
7548 #define TIM_DMAR_DMAB_Pos                   (0U)
7549 #define TIM_DMAR_DMAB_Msk                   (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
7550 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
7551 
7552 
7553 /******************************************************************************/
7554 /*                                                                            */
7555 /*                         Low Power Timer (LPTIM)                            */
7556 /*                                                                            */
7557 /******************************************************************************/
7558 /******************  Bit definition for LPTIM_ISR register  *******************/
7559 #define LPTIM_ISR_CC1IF_Pos                 (0U)
7560 #define LPTIM_ISR_CC1IF_Msk                 (0x1UL << LPTIM_ISR_CC1IF_Pos)          /*!< 0x00000001 */
7561 #define LPTIM_ISR_CC1IF                     LPTIM_ISR_CC1IF_Msk                     /*!< Capture/Compare 1 interrupt flag */
7562 #define LPTIM_ISR_ARRM_Pos                  (1U)
7563 #define LPTIM_ISR_ARRM_Msk                  (0x1UL << LPTIM_ISR_ARRM_Pos)           /*!< 0x00000002 */
7564 #define LPTIM_ISR_ARRM                      LPTIM_ISR_ARRM_Msk                      /*!< Autoreload match */
7565 #define LPTIM_ISR_EXTTRIG_Pos               (2U)
7566 #define LPTIM_ISR_EXTTRIG_Msk               (0x1UL << LPTIM_ISR_EXTTRIG_Pos)        /*!< 0x00000004 */
7567 #define LPTIM_ISR_EXTTRIG                   LPTIM_ISR_EXTTRIG_Msk                   /*!< External trigger edge event */
7568 #define LPTIM_ISR_CMP1OK_Pos                (3U)
7569 #define LPTIM_ISR_CMP1OK_Msk                (0x1UL << LPTIM_ISR_CMP1OK_Pos)         /*!< 0x00000008 */
7570 #define LPTIM_ISR_CMP1OK                    LPTIM_ISR_CMP1OK_Msk                    /*!< Compare register 1 update OK */
7571 #define LPTIM_ISR_ARROK_Pos                 (4U)
7572 #define LPTIM_ISR_ARROK_Msk                 (0x1UL << LPTIM_ISR_ARROK_Pos)          /*!< 0x00000010 */
7573 #define LPTIM_ISR_ARROK                     LPTIM_ISR_ARROK_Msk                     /*!< Autoreload register update OK */
7574 #define LPTIM_ISR_UP_Pos                    (5U)
7575 #define LPTIM_ISR_UP_Msk                    (0x1UL << LPTIM_ISR_UP_Pos)             /*!< 0x00000020 */
7576 #define LPTIM_ISR_UP                        LPTIM_ISR_UP_Msk                        /*!< Counter direction change down to up */
7577 #define LPTIM_ISR_DOWN_Pos                  (6U)
7578 #define LPTIM_ISR_DOWN_Msk                  (0x1UL << LPTIM_ISR_DOWN_Pos)           /*!< 0x00000040 */
7579 #define LPTIM_ISR_DOWN                      LPTIM_ISR_DOWN_Msk                      /*!< Counter direction change up to down */
7580 #define LPTIM_ISR_UE_Pos                    (7U)
7581 #define LPTIM_ISR_UE_Msk                    (0x1UL << LPTIM_ISR_UE_Pos)             /*!< 0x00000080 */
7582 #define LPTIM_ISR_UE                        LPTIM_ISR_UE_Msk                        /*!< Update event */
7583 #define LPTIM_ISR_REPOK_Pos                 (8U)
7584 #define LPTIM_ISR_REPOK_Msk                 (0x1UL << LPTIM_ISR_REPOK_Pos)          /*!< 0x00000100 */
7585 #define LPTIM_ISR_REPOK                     LPTIM_ISR_REPOK_Msk                     /*!< Repetition register update OK */
7586 #define LPTIM_ISR_CC2IF_Pos                 (9U)
7587 #define LPTIM_ISR_CC2IF_Msk                 (0x1UL << LPTIM_ISR_CC2IF_Pos)          /*!< 0x00000200 */
7588 #define LPTIM_ISR_CC2IF                     LPTIM_ISR_CC2IF_Msk                     /*!< Capture/Compare 2 interrupt flag */
7589 #define LPTIM_ISR_CC1OF_Pos                 (12U)
7590 #define LPTIM_ISR_CC1OF_Msk                 (0x1UL << LPTIM_ISR_CC1OF_Pos)          /*!< 0x00001000 */
7591 #define LPTIM_ISR_CC1OF                     LPTIM_ISR_CC1OF_Msk                     /*!< Capture/Compare 1 over-capture flag */
7592 #define LPTIM_ISR_CC2OF_Pos                 (13U)
7593 #define LPTIM_ISR_CC2OF_Msk                 (0x1UL << LPTIM_ISR_CC2OF_Pos)          /*!< 0x00002000 */
7594 #define LPTIM_ISR_CC2OF                     LPTIM_ISR_CC2OF_Msk                     /*!< Capture/Compare 2 over-capture flag */
7595 #define LPTIM_ISR_CMP2OK_Pos                (19U)
7596 #define LPTIM_ISR_CMP2OK_Msk                (0x1UL << LPTIM_ISR_CMP2OK_Pos)         /*!< 0x00080000 */
7597 #define LPTIM_ISR_CMP2OK                    LPTIM_ISR_CMP2OK_Msk                    /*!< Compare register 2 update OK */
7598 #define LPTIM_ISR_DIEROK_Pos                (24U)
7599 #define LPTIM_ISR_DIEROK_Msk                (0x1UL << LPTIM_ISR_DIEROK_Pos)         /*!< 0x01000000 */
7600 #define LPTIM_ISR_DIEROK                    LPTIM_ISR_DIEROK_Msk                    /*!< DMA & interrupt enable update OK */
7601 
7602 /******************  Bit definition for LPTIM_ICR register  *******************/
7603 #define LPTIM_ICR_CC1CF_Pos                 (0U)
7604 #define LPTIM_ICR_CC1CF_Msk                 (0x1UL << LPTIM_ICR_CC1CF_Pos)          /*!< 0x00000001 */
7605 #define LPTIM_ICR_CC1CF                     LPTIM_ICR_CC1CF_Msk                     /*!< Capture/Compare 1 clear flag  */
7606 #define LPTIM_ICR_ARRMCF_Pos                (1U)
7607 #define LPTIM_ICR_ARRMCF_Msk                (0x1UL << LPTIM_ICR_ARRMCF_Pos)         /*!< 0x00000002 */
7608 #define LPTIM_ICR_ARRMCF                    LPTIM_ICR_ARRMCF_Msk                    /*!< Autoreload match clear flag */
7609 #define LPTIM_ICR_EXTTRIGCF_Pos             (2U)
7610 #define LPTIM_ICR_EXTTRIGCF_Msk             (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)      /*!< 0x00000004 */
7611 #define LPTIM_ICR_EXTTRIGCF                 LPTIM_ICR_EXTTRIGCF_Msk                 /*!< External trigger edge event clear flag */
7612 #define LPTIM_ICR_CMP1OKCF_Pos              (3U)
7613 #define LPTIM_ICR_CMP1OKCF_Msk              (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)       /*!< 0x00000008 */
7614 #define LPTIM_ICR_CMP1OKCF                  LPTIM_ICR_CMP1OKCF_Msk                  /*!< Compare register 1 update OK clear flag */
7615 #define LPTIM_ICR_ARROKCF_Pos               (4U)
7616 #define LPTIM_ICR_ARROKCF_Msk               (0x1UL << LPTIM_ICR_ARROKCF_Pos)        /*!< 0x00000010 */
7617 #define LPTIM_ICR_ARROKCF                   LPTIM_ICR_ARROKCF_Msk                   /*!< Autoreload register update OK clear flag */
7618 #define LPTIM_ICR_UPCF_Pos                  (5U)
7619 #define LPTIM_ICR_UPCF_Msk                  (0x1UL << LPTIM_ICR_UPCF_Pos)           /*!< 0x00000020 */
7620 #define LPTIM_ICR_UPCF                      LPTIM_ICR_UPCF_Msk                      /*!< Counter direction change down to up clear flag */
7621 #define LPTIM_ICR_DOWNCF_Pos                (6U)
7622 #define LPTIM_ICR_DOWNCF_Msk                (0x1UL << LPTIM_ICR_DOWNCF_Pos)         /*!< 0x00000040 */
7623 #define LPTIM_ICR_DOWNCF                    LPTIM_ICR_DOWNCF_Msk                    /*!< Counter direction change up to down clear flag */
7624 #define LPTIM_ICR_UECF_Pos                  (7U)
7625 #define LPTIM_ICR_UECF_Msk                  (0x1UL << LPTIM_ICR_UECF_Pos)           /*!< 0x00000080 */
7626 #define LPTIM_ICR_UECF                      LPTIM_ICR_UECF_Msk                      /*!< Update event clear flag */
7627 #define LPTIM_ICR_REPOKCF_Pos               (8U)
7628 #define LPTIM_ICR_REPOKCF_Msk               (0x1UL << LPTIM_ICR_REPOKCF_Pos)        /*!< 0x00000100 */
7629 #define LPTIM_ICR_REPOKCF                   LPTIM_ICR_REPOKCF_Msk                   /*!< Repetition register update OK clear flag */
7630 #define LPTIM_ICR_CC2CF_Pos                 (9U)
7631 #define LPTIM_ICR_CC2CF_Msk                 (0x1UL << LPTIM_ICR_CC2CF_Pos)          /*!< 0x00000200 */
7632 #define LPTIM_ICR_CC2CF                     LPTIM_ICR_CC2CF_Msk                     /*!< Capture/Compare 2 clear flag  */
7633 #define LPTIM_ICR_CC1OCF_Pos                (12U)
7634 #define LPTIM_ICR_CC1OCF_Msk                (0x1UL << LPTIM_ICR_CC1OCF_Pos)         /*!< 0x00001000 */
7635 #define LPTIM_ICR_CC1OCF                    LPTIM_ICR_CC1OCF_Msk                    /*!< Capture/Compare 1 over-capture clear flag */
7636 #define LPTIM_ICR_CC2OCF_Pos                (13U)
7637 #define LPTIM_ICR_CC2OCF_Msk                (0x1UL << LPTIM_ICR_CC2OCF_Pos)         /*!< 0x00002000 */
7638 #define LPTIM_ICR_CC2OCF                    LPTIM_ICR_CC2OCF_Msk                    /*!< Capture/Compare 2 over-capture clear flag */
7639 #define LPTIM_ICR_CMP2OKCF_Pos              (19U)
7640 #define LPTIM_ICR_CMP2OKCF_Msk              (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)       /*!< 0x00080000 */
7641 #define LPTIM_ICR_CMP2OKCF                  LPTIM_ICR_CMP2OKCF_Msk                  /*!< Compare register 2 update OK clear flag */
7642 #define LPTIM_ICR_DIEROKCF_Pos              (24U)
7643 #define LPTIM_ICR_DIEROKCF_Msk              (0x1UL << LPTIM_ICR_DIEROKCF_Pos)       /*!< 0x01000000 */
7644 #define LPTIM_ICR_DIEROKCF                  LPTIM_ICR_DIEROKCF_Msk                  /*!< Interrupt enable register update OK clear flag */
7645 
7646 /******************  Bit definition for LPTIM_DIER register *******************/
7647 #define LPTIM_DIER_CC1IE_Pos                (0U)
7648 #define LPTIM_DIER_CC1IE_Msk                (0x1UL << LPTIM_DIER_CC1IE_Pos)         /*!< 0x00000001 */
7649 #define LPTIM_DIER_CC1IE                    LPTIM_DIER_CC1IE_Msk                    /*!< Compare/Compare interrupt enable */
7650 #define LPTIM_DIER_ARRMIE_Pos               (1U)
7651 #define LPTIM_DIER_ARRMIE_Msk               (0x1UL << LPTIM_DIER_ARRMIE_Pos)        /*!< 0x00000002 */
7652 #define LPTIM_DIER_ARRMIE                   LPTIM_DIER_ARRMIE_Msk                   /*!< Autoreload match interrupt enable */
7653 #define LPTIM_DIER_EXTTRIGIE_Pos            (2U)
7654 #define LPTIM_DIER_EXTTRIGIE_Msk            (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)     /*!< 0x00000004 */
7655 #define LPTIM_DIER_EXTTRIGIE                LPTIM_DIER_EXTTRIGIE_Msk                /*!< External trigger edge event interrupt enable */
7656 #define LPTIM_DIER_CMP1OKIE_Pos             (3U)
7657 #define LPTIM_DIER_CMP1OKIE_Msk             (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)      /*!< 0x00000008 */
7658 #define LPTIM_DIER_CMP1OKIE                 LPTIM_DIER_CMP1OKIE_Msk                 /*!< Compare register 1 update OK interrupt enable */
7659 #define LPTIM_DIER_ARROKIE_Pos              (4U)
7660 #define LPTIM_DIER_ARROKIE_Msk              (0x1UL << LPTIM_DIER_ARROKIE_Pos)       /*!< 0x00000010 */
7661 #define LPTIM_DIER_ARROKIE                  LPTIM_DIER_ARROKIE_Msk                  /*!< Autoreload register update OK interrupt enable */
7662 #define LPTIM_DIER_UPIE_Pos                 (5U)
7663 #define LPTIM_DIER_UPIE_Msk                 (0x1UL << LPTIM_DIER_UPIE_Pos)          /*!< 0x00000020 */
7664 #define LPTIM_DIER_UPIE                     LPTIM_DIER_UPIE_Msk                     /*!< Counter direction change down to up interrupt enable */
7665 #define LPTIM_DIER_DOWNIE_Pos               (6U)
7666 #define LPTIM_DIER_DOWNIE_Msk               (0x1UL << LPTIM_DIER_DOWNIE_Pos)        /*!< 0x00000040 */
7667 #define LPTIM_DIER_DOWNIE                   LPTIM_DIER_DOWNIE_Msk                   /*!< Counter direction change up to down interrupt enable */
7668 #define LPTIM_DIER_UEIE_Pos                 (7U)
7669 #define LPTIM_DIER_UEIE_Msk                 (0x1UL << LPTIM_DIER_UEIE_Pos)          /*!< 0x00000080 */
7670 #define LPTIM_DIER_UEIE                     LPTIM_DIER_UEIE_Msk                     /*!< Update event interrupt enable */
7671 #define LPTIM_DIER_REPOKIE_Pos              (8U)
7672 #define LPTIM_DIER_REPOKIE_Msk              (0x1UL << LPTIM_DIER_REPOKIE_Pos)       /*!< 0x00000100 */
7673 #define LPTIM_DIER_REPOKIE                  LPTIM_DIER_REPOKIE_Msk                  /*!< Repetition register update OK interrupt enable */
7674 #define LPTIM_DIER_CC2IE_Pos                (9U)
7675 #define LPTIM_DIER_CC2IE_Msk                (0x1UL << LPTIM_DIER_CC2IE_Pos)         /*!< 0x00000200 */
7676 #define LPTIM_DIER_CC2IE                    LPTIM_DIER_CC2IE_Msk                    /*!< Capture/Compare 2 interrupt interrupt enable */
7677 #define LPTIM_DIER_CC1OIE_Pos               (12U)
7678 #define LPTIM_DIER_CC1OIE_Msk               (0x1UL << LPTIM_DIER_CC1OIE_Pos)        /*!< 0x00001000 */
7679 #define LPTIM_DIER_CC1OIE                   LPTIM_DIER_CC1OIE_Msk                   /*!< Capture/Compare 1 over-capture interrupt enable */
7680 #define LPTIM_DIER_CC2OIE_Pos               (13U)
7681 #define LPTIM_DIER_CC2OIE_Msk               (0x1UL << LPTIM_DIER_CC2OIE_Pos)        /*!< 0x00002000 */
7682 #define LPTIM_DIER_CC2OIE                   LPTIM_DIER_CC2OIE_Msk                   /*!< Capture/Compare 2 over-capture interrupt enable */
7683 #define LPTIM_DIER_CC1DE_Pos                (16U)
7684 #define LPTIM_DIER_CC1DE_Msk                (0x1UL << LPTIM_DIER_CC1DE_Pos)         /*!< 0x00010000 */
7685 #define LPTIM_DIER_CC1DE                    LPTIM_DIER_CC1DE_Msk                    /*!< Capture/Compare 1 DMA request enable */
7686 #define LPTIM_DIER_CMP2OKIE_Pos             (19U)
7687 #define LPTIM_DIER_CMP2OKIE_Msk             (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)      /*!< 0x00080000 */
7688 #define LPTIM_DIER_CMP2OKIE                 LPTIM_DIER_CMP2OKIE_Msk                 /*!< Compare register 2 update OK interrupt enable */
7689 #define LPTIM_DIER_UEDE_Pos                 (23U)
7690 #define LPTIM_DIER_UEDE_Msk                 (0x1UL << LPTIM_DIER_UEDE_Pos)          /*!< 0x00800000 */
7691 #define LPTIM_DIER_UEDE                     LPTIM_DIER_UEDE_Msk                     /*!< Update event DMA request enable */
7692 #define LPTIM_DIER_CC2DE_Pos                (25U)
7693 #define LPTIM_DIER_CC2DE_Msk                (0x1UL << LPTIM_DIER_CC2DE_Pos)         /*!< 0x02000000 */
7694 #define LPTIM_DIER_CC2DE                    LPTIM_DIER_CC2DE_Msk                    /*!< Capture/Compare 2 DMA request enable */
7695 
7696 /******************  Bit definition for LPTIM_CFGR register *******************/
7697 #define LPTIM_CFGR_CKSEL_Pos                (0U)
7698 #define LPTIM_CFGR_CKSEL_Msk                (0x1UL << LPTIM_CFGR_CKSEL_Pos)         /*!< 0x00000001 */
7699 #define LPTIM_CFGR_CKSEL                    LPTIM_CFGR_CKSEL_Msk                    /*!< Clock selector */
7700 #define LPTIM_CFGR_CKPOL_Pos                (1U)
7701 #define LPTIM_CFGR_CKPOL_Msk                (0x3UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000006 */
7702 #define LPTIM_CFGR_CKPOL                    LPTIM_CFGR_CKPOL_Msk                    /*!< CKPOL[1:0] bits (Clock polarity) */
7703 #define LPTIM_CFGR_CKPOL_0                  (0x1UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000002 */
7704 #define LPTIM_CFGR_CKPOL_1                  (0x2UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000004 */
7705 #define LPTIM_CFGR_CKFLT_Pos                (3U)
7706 #define LPTIM_CFGR_CKFLT_Msk                (0x3UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000018 */
7707 #define LPTIM_CFGR_CKFLT                    LPTIM_CFGR_CKFLT_Msk                    /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
7708 #define LPTIM_CFGR_CKFLT_0                  (0x1UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000008 */
7709 #define LPTIM_CFGR_CKFLT_1                  (0x2UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000010 */
7710 #define LPTIM_CFGR_TRGFLT_Pos               (6U)
7711 #define LPTIM_CFGR_TRGFLT_Msk               (0x3UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x000000C0 */
7712 #define LPTIM_CFGR_TRGFLT                   LPTIM_CFGR_TRGFLT_Msk                   /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
7713 #define LPTIM_CFGR_TRGFLT_0                 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000040 */
7714 #define LPTIM_CFGR_TRGFLT_1                 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000080 */
7715 #define LPTIM_CFGR_PRESC_Pos                (9U)
7716 #define LPTIM_CFGR_PRESC_Msk                (0x7UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000E00 */
7717 #define LPTIM_CFGR_PRESC                    LPTIM_CFGR_PRESC_Msk                    /*!< PRESC[2:0] bits (Clock prescaler) */
7718 #define LPTIM_CFGR_PRESC_0                  (0x1UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000200 */
7719 #define LPTIM_CFGR_PRESC_1                  (0x2UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000400 */
7720 #define LPTIM_CFGR_PRESC_2                  (0x4UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000800 */
7721 #define LPTIM_CFGR_TRIGSEL_Pos              (13U)
7722 #define LPTIM_CFGR_TRIGSEL_Msk              (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x0000E000 */
7723 #define LPTIM_CFGR_TRIGSEL                  LPTIM_CFGR_TRIGSEL_Msk                  /*!< TRIGSEL[2:0]] bits (Trigger selector) */
7724 #define LPTIM_CFGR_TRIGSEL_0                (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00002000 */
7725 #define LPTIM_CFGR_TRIGSEL_1                (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00004000 */
7726 #define LPTIM_CFGR_TRIGSEL_2                (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00008000 */
7727 #define LPTIM_CFGR_TRIGEN_Pos               (17U)
7728 #define LPTIM_CFGR_TRIGEN_Msk               (0x3UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00060000 */
7729 #define LPTIM_CFGR_TRIGEN                   LPTIM_CFGR_TRIGEN_Msk                   /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
7730 #define LPTIM_CFGR_TRIGEN_0                 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00020000 */
7731 #define LPTIM_CFGR_TRIGEN_1                 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00040000 */
7732 #define LPTIM_CFGR_TIMOUT_Pos               (19U)
7733 #define LPTIM_CFGR_TIMOUT_Msk               (0x1UL << LPTIM_CFGR_TIMOUT_Pos)        /*!< 0x00080000 */
7734 #define LPTIM_CFGR_TIMOUT                   LPTIM_CFGR_TIMOUT_Msk                   /*!< Timout enable */
7735 #define LPTIM_CFGR_WAVE_Pos                 (20U)
7736 #define LPTIM_CFGR_WAVE_Msk                 (0x1UL << LPTIM_CFGR_WAVE_Pos)          /*!< 0x00100000 */
7737 #define LPTIM_CFGR_WAVE                     LPTIM_CFGR_WAVE_Msk                     /*!< Waveform shape */
7738 #define LPTIM_CFGR_WAVPOL_Pos               (21U)
7739 #define LPTIM_CFGR_WAVPOL_Msk               (0x1UL << LPTIM_CFGR_WAVPOL_Pos)        /*!< 0x00200000 */
7740 #define LPTIM_CFGR_WAVPOL                   LPTIM_CFGR_WAVPOL_Msk                   /*!< Waveform shape */
7741 #define LPTIM_CFGR_PRELOAD_Pos              (22U)
7742 #define LPTIM_CFGR_PRELOAD_Msk              (0x1UL << LPTIM_CFGR_PRELOAD_Pos)       /*!< 0x00400000 */
7743 #define LPTIM_CFGR_PRELOAD                  LPTIM_CFGR_PRELOAD_Msk                  /*!< Reg update mode */
7744 #define LPTIM_CFGR_COUNTMODE_Pos            (23U)
7745 #define LPTIM_CFGR_COUNTMODE_Msk            (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)     /*!< 0x00800000 */
7746 #define LPTIM_CFGR_COUNTMODE                LPTIM_CFGR_COUNTMODE_Msk                /*!< Counter mode enable */
7747 #define LPTIM_CFGR_ENC_Pos                  (24U)
7748 #define LPTIM_CFGR_ENC_Msk                  (0x1UL << LPTIM_CFGR_ENC_Pos)           /*!< 0x01000000 */
7749 #define LPTIM_CFGR_ENC                      LPTIM_CFGR_ENC_Msk                      /*!< Encoder mode enable */
7750 
7751 /******************  Bit definition for LPTIM_CR register  ********************/
7752 #define LPTIM_CR_ENABLE_Pos                 (0U)
7753 #define LPTIM_CR_ENABLE_Msk                 (0x1UL << LPTIM_CR_ENABLE_Pos)          /*!< 0x00000001 */
7754 #define LPTIM_CR_ENABLE                     LPTIM_CR_ENABLE_Msk                     /*!< LPTIMer enable */
7755 #define LPTIM_CR_SNGSTRT_Pos                (1U)
7756 #define LPTIM_CR_SNGSTRT_Msk                (0x1UL << LPTIM_CR_SNGSTRT_Pos)         /*!< 0x00000002 */
7757 #define LPTIM_CR_SNGSTRT                    LPTIM_CR_SNGSTRT_Msk                    /*!< Timer start in single mode */
7758 #define LPTIM_CR_CNTSTRT_Pos                (2U)
7759 #define LPTIM_CR_CNTSTRT_Msk                (0x1UL << LPTIM_CR_CNTSTRT_Pos)         /*!< 0x00000004 */
7760 #define LPTIM_CR_CNTSTRT                    LPTIM_CR_CNTSTRT_Msk                    /*!< Timer start in continuous mode */
7761 #define LPTIM_CR_COUNTRST_Pos               (3U)
7762 #define LPTIM_CR_COUNTRST_Msk               (0x1UL << LPTIM_CR_COUNTRST_Pos)        /*!< 0x00000008 */
7763 #define LPTIM_CR_COUNTRST                   LPTIM_CR_COUNTRST_Msk                   /*!< Timer Counter reset in synchronous mode*/
7764 #define LPTIM_CR_RSTARE_Pos                 (4U)
7765 #define LPTIM_CR_RSTARE_Msk                 (0x1UL << LPTIM_CR_RSTARE_Pos)          /*!< 0x00000010 */
7766 #define LPTIM_CR_RSTARE                     LPTIM_CR_RSTARE_Msk                     /*!< Timer Counter reset after read enable (asynchronously)*/
7767 
7768 
7769 /******************  Bit definition for LPTIM_CCR1 register  ******************/
7770 #define LPTIM_CCR1_CCR1_Pos                 (0U)
7771 #define LPTIM_CCR1_CCR1_Msk                 (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)       /*!< 0x0000FFFF */
7772 #define LPTIM_CCR1_CCR1                     LPTIM_CCR1_CCR1_Msk                     /*!< Compare register 1 */
7773 
7774 /******************  Bit definition for LPTIM_ARR register  *******************/
7775 #define LPTIM_ARR_ARR_Pos                   (0U)
7776 #define LPTIM_ARR_ARR_Msk                   (0xFFFFUL << LPTIM_ARR_ARR_Pos)         /*!< 0x0000FFFF */
7777 #define LPTIM_ARR_ARR                       LPTIM_ARR_ARR_Msk                       /*!< Auto reload register */
7778 
7779 /******************  Bit definition for LPTIM_CNT register  *******************/
7780 #define LPTIM_CNT_CNT_Pos                   (0U)
7781 #define LPTIM_CNT_CNT_Msk                   (0xFFFFUL << LPTIM_CNT_CNT_Pos)         /*!< 0x0000FFFF */
7782 #define LPTIM_CNT_CNT                       LPTIM_CNT_CNT_Msk                       /*!< Counter register */
7783 
7784 /******************  Bit definition for LPTIM_CFGR2 register  *****************/
7785 #define LPTIM_CFGR2_IN1SEL_Pos              (0U)
7786 #define LPTIM_CFGR2_IN1SEL_Msk              (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000003 */
7787 #define LPTIM_CFGR2_IN1SEL                  LPTIM_CFGR2_IN1SEL_Msk                  /*!< IN1SEL[1:0] bits (Remap selection) */
7788 #define LPTIM_CFGR2_IN1SEL_0                (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000001 */
7789 #define LPTIM_CFGR2_IN1SEL_1                (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000002 */
7790 #define LPTIM_CFGR2_IN2SEL_Pos              (4U)
7791 #define LPTIM_CFGR2_IN2SEL_Msk              (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000030 */
7792 #define LPTIM_CFGR2_IN2SEL                  LPTIM_CFGR2_IN2SEL_Msk                  /*!< IN2SEL[5:4] bits (Remap selection) */
7793 #define LPTIM_CFGR2_IN2SEL_0                (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000010 */
7794 #define LPTIM_CFGR2_IN2SEL_1                (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000020 */
7795 #define LPTIM_CFGR2_IC1SEL_Pos              (16U)
7796 #define LPTIM_CFGR2_IC1SEL_Msk              (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00000003 */
7797 #define LPTIM_CFGR2_IC1SEL                  LPTIM_CFGR2_IC1SEL_Msk                  /*!< IC1SEL[17:16] bits */
7798 #define LPTIM_CFGR2_IC1SEL_0                (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00010000 */
7799 #define LPTIM_CFGR2_IC1SEL_1                (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00020000 */
7800 #define LPTIM_CFGR2_IC2SEL_Pos              (20U)
7801 #define LPTIM_CFGR2_IC2SEL_Msk              (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00000030 */
7802 #define LPTIM_CFGR2_IC2SEL                  LPTIM_CFGR2_IC2SEL_Msk                  /*!< IC2SEL[21:20] bits */
7803 #define LPTIM_CFGR2_IC2SEL_0                (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00100000 */
7804 #define LPTIM_CFGR2_IC2SEL_1                (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00200000 */
7805 
7806 /******************  Bit definition for LPTIM_RCR register  *******************/
7807 #define LPTIM_RCR_REP_Pos                   (0U)
7808 #define LPTIM_RCR_REP_Msk                   (0xFFUL << LPTIM_RCR_REP_Pos)           /*!< 0x000000FF */
7809 #define LPTIM_RCR_REP                       LPTIM_RCR_REP_Msk                       /*!< Repetition register value */
7810 
7811 /*****************  Bit definition for LPTIM_CCMR1 register  ******************/
7812 #define LPTIM_CCMR1_CC1SEL_Pos              (0U)
7813 #define LPTIM_CCMR1_CC1SEL_Msk              (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)       /*!< 0x00000001 */
7814 #define LPTIM_CCMR1_CC1SEL                  LPTIM_CCMR1_CC1SEL_Msk                  /*!< Capture/Compare 1 selection */
7815 #define LPTIM_CCMR1_CC1E_Pos                (1U)
7816 #define LPTIM_CCMR1_CC1E_Msk                (0x1UL << LPTIM_CCMR1_CC1E_Pos)         /*!< 0x00000002 */
7817 #define LPTIM_CCMR1_CC1E                    LPTIM_CCMR1_CC1E_Msk                    /*!< Capture/Compare 1 output enable */
7818 #define LPTIM_CCMR1_CC1P_Pos                (2U)
7819 #define LPTIM_CCMR1_CC1P_Msk                (0x3UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x0000000C */
7820 #define LPTIM_CCMR1_CC1P                    LPTIM_CCMR1_CC1P_Msk                    /*!< Capture/Compare 1 output polarity */
7821 #define LPTIM_CCMR1_CC1P_0                  (0x1UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000004 */
7822 #define LPTIM_CCMR1_CC1P_1                  (0x2UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000008 */
7823 #define LPTIM_CCMR1_IC1PSC_Pos              (8U)
7824 #define LPTIM_CCMR1_IC1PSC_Msk              (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000300 */
7825 #define LPTIM_CCMR1_IC1PSC                  LPTIM_CCMR1_IC1PSC_Msk                  /*!< Input capture 1 prescaler */
7826 #define LPTIM_CCMR1_IC1PSC_0                (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000100 */
7827 #define LPTIM_CCMR1_IC1PSC_1                (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000200 */
7828 #define LPTIM_CCMR1_IC1F_Pos                (12U)
7829 #define LPTIM_CCMR1_IC1F_Msk                (0x3UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00003000 */
7830 #define LPTIM_CCMR1_IC1F                    LPTIM_CCMR1_IC1F_Msk                    /*!< Input capture 1 filter */
7831 #define LPTIM_CCMR1_IC1F_0                  (0x1UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00001000 */
7832 #define LPTIM_CCMR1_IC1F_1                  (0x2UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00002000 */
7833 #define LPTIM_CCMR1_CC2SEL_Pos              (16U)
7834 #define LPTIM_CCMR1_CC2SEL_Msk              (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)       /*!< 0x00010000 */
7835 #define LPTIM_CCMR1_CC2SEL                  LPTIM_CCMR1_CC2SEL_Msk                  /*!< Capture/Compare 2 selection */
7836 #define LPTIM_CCMR1_CC2E_Pos                (17U)
7837 #define LPTIM_CCMR1_CC2E_Msk                (0x1UL << LPTIM_CCMR1_CC2E_Pos)         /*!< 0x00020000 */
7838 #define LPTIM_CCMR1_CC2E                    LPTIM_CCMR1_CC2E_Msk                    /*!< Capture/Compare 2 output enable */
7839 #define LPTIM_CCMR1_CC2P_Pos                (18U)
7840 #define LPTIM_CCMR1_CC2P_Msk                (0x3UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x000C0000 */
7841 #define LPTIM_CCMR1_CC2P                    LPTIM_CCMR1_CC2P_Msk                    /*!< Capture/Compare 2 output polarity */
7842 #define LPTIM_CCMR1_CC2P_0                  (0x1UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00040000 */
7843 #define LPTIM_CCMR1_CC2P_1                  (0x2UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00080000 */
7844 #define LPTIM_CCMR1_IC2PSC_Pos              (24U)
7845 #define LPTIM_CCMR1_IC2PSC_Msk              (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x03000000 */
7846 #define LPTIM_CCMR1_IC2PSC                  LPTIM_CCMR1_IC2PSC_Msk                  /*!< Input capture 2 prescaler */
7847 #define LPTIM_CCMR1_IC2PSC_0                (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x01000000 */
7848 #define LPTIM_CCMR1_IC2PSC_1                (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x02000000 */
7849 #define LPTIM_CCMR1_IC2F_Pos                (28U)
7850 #define LPTIM_CCMR1_IC2F_Msk                (0x3UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x30000000 */
7851 #define LPTIM_CCMR1_IC2F                    LPTIM_CCMR1_IC2F_Msk                    /*!< Input capture 2 filter */
7852 #define LPTIM_CCMR1_IC2F_0                  (0x1UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x10000000 */
7853 #define LPTIM_CCMR1_IC2F_1                  (0x2UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x20000000 */
7854 
7855 /******************  Bit definition for LPTIM_CCR2 register  ******************/
7856 #define LPTIM_CCR2_CCR2_Pos                 (0U)
7857 #define LPTIM_CCR2_CCR2_Msk                 (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)       /*!< 0x0000FFFF */
7858 #define LPTIM_CCR2_CCR2                     LPTIM_CCR2_CCR2_Msk                     /*!< Compare register 2 */
7859 
7860 /******************************************************************************/
7861 /*                                                                            */
7862 /*                             Power Control                                  */
7863 /*                                                                            */
7864 /******************************************************************************/
7865 /********************  Bit definition for PWR_PMCR register  ******************/
7866 #define PWR_PMCR_LPMS_Pos                    (0U)
7867 #define PWR_PMCR_LPMS_Msk                    (0x1UL << PWR_PMCR_LPMS_Pos)
7868 #define PWR_PMCR_LPMS                        PWR_PMCR_LPMS_Msk
7869 #define PWR_PMCR_SVOS_Pos                    (2U)
7870 #define PWR_PMCR_SVOS_Msk                    (0x3UL << PWR_PMCR_SVOS_Pos)
7871 #define PWR_PMCR_SVOS                        PWR_PMCR_SVOS_Msk
7872 #define PWR_PMCR_SVOS_0                      (0x1UL << PWR_PMCR_SVOS_Pos)
7873 #define PWR_PMCR_SVOS_1                      (0x2UL << PWR_PMCR_SVOS_Pos)
7874 #define PWR_PMCR_CSSF_Pos                    (7U)
7875 #define PWR_PMCR_CSSF_Msk                    (0x1UL << PWR_PMCR_CSSF_Pos)
7876 #define PWR_PMCR_CSSF                        PWR_PMCR_CSSF_Msk
7877 #define PWR_PMCR_FLPS_Pos                    (9U)
7878 #define PWR_PMCR_FLPS_Msk                    (0x1UL << PWR_PMCR_FLPS_Pos)
7879 #define PWR_PMCR_FLPS                        PWR_PMCR_FLPS_Msk
7880 #define PWR_PMCR_BOOSTE_Pos                  (12U)
7881 #define PWR_PMCR_BOOSTE_Msk                  (0x1UL << PWR_PMCR_BOOSTE_Pos)
7882 #define PWR_PMCR_BOOSTE                      PWR_PMCR_BOOSTE_Msk
7883 #define PWR_PMCR_AVD_READY_Pos               (13U)
7884 #define PWR_PMCR_AVD_READY_Msk               (0x1UL << PWR_PMCR_AVD_READY_Pos)
7885 #define PWR_PMCR_AVD_READY                   PWR_PMCR_AVD_READY_Msk
7886 #define PWR_PMCR_SRAM2SO_Pos                 (25U)
7887 #define PWR_PMCR_SRAM2SO_Msk                 (0x1UL << PWR_PMCR_SRAM2SO_Pos)
7888 #define PWR_PMCR_SRAM2SO                     PWR_PMCR_SRAM2SO_Msk
7889 #define PWR_PMCR_SRAM1SO_Pos                 (26U)
7890 #define PWR_PMCR_SRAM1SO_Msk                 (0x1UL << PWR_PMCR_SRAM1SO_Pos)
7891 #define PWR_PMCR_SRAM1SO                     PWR_PMCR_SRAM1SO_Msk
7892 
7893 /********************  Bit definition for PWR_PMSR register  *******************/
7894 #define PWR_PMSR_STOPF_Pos                   (5U)
7895 #define PWR_PMSR_STOPF_Msk                   (0x1UL << PWR_PMSR_STOPF_Pos)
7896 #define PWR_PMSR_STOPF                       PWR_PMSR_STOPF_Msk
7897 #define PWR_PMSR_SBF_Pos                     (6U)
7898 #define PWR_PMSR_SBF_Msk                     (0x1UL << PWR_PMSR_SBF_Pos)
7899 #define PWR_PMSR_SBF                         PWR_PMSR_SBF_Msk
7900 
7901 /********************  Bit definition for PWR_VOSCR register  ******************/
7902 #define PWR_VOSCR_VOS_Pos                    (4U)
7903 #define PWR_VOSCR_VOS_Msk                    (0x3UL << PWR_VOSCR_VOS_Pos)
7904 #define PWR_VOSCR_VOS                        PWR_VOSCR_VOS_Msk
7905 #define PWR_VOSCR_VOS_0                      (0x1UL << PWR_VOSCR_VOS_Pos)
7906 #define PWR_VOSCR_VOS_1                      (0x2UL << PWR_VOSCR_VOS_Pos)
7907 
7908 /********************  Bit definition for PWR_VOSSR register  *****************/
7909 #define PWR_VOSSR_VOSRDY_Pos                 (3U)
7910 #define PWR_VOSSR_VOSRDY_Msk                 (0x1UL << PWR_VOSSR_VOSRDY_Pos)
7911 #define PWR_VOSSR_VOSRDY                     PWR_VOSSR_VOSRDY_Msk
7912 #define PWR_VOSSR_ACTVOSRDY_Pos              (13U)
7913 #define PWR_VOSSR_ACTVOSRDY_Msk              (0x1UL << PWR_VOSSR_ACTVOSRDY_Pos)
7914 #define PWR_VOSSR_ACTVOSRDY                  PWR_VOSSR_ACTVOSRDY_Msk
7915 #define PWR_VOSSR_ACTVOS_Pos                 (14U)
7916 #define PWR_VOSSR_ACTVOS_Msk                 (0x3UL << PWR_VOSSR_ACTVOS_Pos)
7917 #define PWR_VOSSR_ACTVOS                     PWR_VOSSR_ACTVOS_Msk
7918 #define PWR_VOSSR_ACTVOS_0                   (0x1UL << PWR_VOSSR_ACTVOS_Pos)
7919 #define PWR_VOSSR_ACTVOS_1                   (0x2UL << PWR_VOSSR_ACTVOS_Pos)
7920 
7921 /********************  Bit definition for PWR_BDCR register  ******************/
7922 #define PWR_BDCR_BREN_Pos                    (0U)
7923 #define PWR_BDCR_BREN_Msk                    (0x1UL << PWR_BDCR_BREN_Pos)
7924 #define PWR_BDCR_BREN                        PWR_BDCR_BREN_Msk
7925 #define PWR_BDCR_MONEN_Pos                   (1U)
7926 #define PWR_BDCR_MONEN_Msk                   (0x1UL << PWR_BDCR_MONEN_Pos)
7927 #define PWR_BDCR_MONEN                       PWR_BDCR_MONEN_Msk
7928 #define PWR_BDCR_VBE_Pos                     (8U)
7929 #define PWR_BDCR_VBE_Msk                     (0x1UL << PWR_BDCR_VBE_Pos)
7930 #define PWR_BDCR_VBE                         PWR_BDCR_VBE_Msk
7931 #define PWR_BDCR_VBRS_Pos                    (9U)
7932 #define PWR_BDCR_VBRS_Msk                    (0x1UL << PWR_BDCR_VBRS_Pos)
7933 #define PWR_BDCR_VBRS                        PWR_BDCR_VBRS_Msk
7934 
7935 /********************  Bit definition for PWR_DBPCR register  *****************/
7936 #define PWR_DBPCR_DBP_Pos                    (0U)
7937 #define PWR_DBPCR_DBP_Msk                    (0x1UL << PWR_DBPCR_DBP_Pos)
7938 #define PWR_DBPCR_DBP                        PWR_DBPCR_DBP_Msk
7939 
7940 /********************  Bit definition for PWR_BDSR register  ******************/
7941 #define PWR_BDSR_BRRDY_Pos                   (16U)
7942 #define PWR_BDSR_BRRDY_Msk                   (0x1UL << PWR_BDSR_BRRDY_Pos)
7943 #define PWR_BDSR_BRRDY                       PWR_BDSR_BRRDY_Msk
7944 #define PWR_BDSR_VBATL_Pos                   (20U)
7945 #define PWR_BDSR_VBATL_Msk                   (0x1UL << PWR_BDSR_VBATL_Pos)
7946 #define PWR_BDSR_VBATL                       PWR_BDSR_VBATL_Msk
7947 #define PWR_BDSR_VBATH_Pos                   (21U)
7948 #define PWR_BDSR_VBATH_Msk                   (0x1UL << PWR_BDSR_VBATH_Pos)
7949 #define PWR_BDSR_VBATH                       PWR_BDSR_VBATH_Msk
7950 #define PWR_BDSR_TEMPL_Pos                   (22U)
7951 #define PWR_BDSR_TEMPL_Msk                   (0x1UL << PWR_BDSR_TEMPL_Pos)
7952 #define PWR_BDSR_TEMPL                       PWR_BDSR_TEMPL_Msk
7953 #define PWR_BDSR_TEMPH_Pos                   (23U)
7954 #define PWR_BDSR_TEMPH_Msk                   (0x1UL << PWR_BDSR_TEMPH_Pos)
7955 #define PWR_BDSR_TEMPH                       PWR_BDSR_TEMPH_Msk
7956 
7957 
7958 /********************  Bit definition for PWR_SCCR register  ******************/
7959 #define PWR_SCCR_BYPASS_Pos                  (0U)
7960 #define PWR_SCCR_BYPASS_Msk                  (0x1UL << PWR_SCCR_BYPASS_Pos)
7961 #define PWR_SCCR_BYPASS                      PWR_SCCR_BYPASS_Msk
7962 #define PWR_SCCR_LDOEN_Pos                   (8U)
7963 #define PWR_SCCR_LDOEN_Msk                   (0x1UL << PWR_SCCR_LDOEN_Pos)
7964 #define PWR_SCCR_LDOEN                       PWR_SCCR_LDOEN_Msk
7965 
7966 /********************  Bit definition for PWR_VMCR register  ******************/
7967 #define PWR_VMCR_PVDEN_Pos                   (0U)
7968 #define PWR_VMCR_PVDEN_Msk                   (0x1UL << PWR_VMCR_PVDEN_Pos)
7969 #define PWR_VMCR_PVDEN                       PWR_VMCR_PVDEN_Msk
7970 #define PWR_VMCR_PLS_Pos                     (1U)
7971 #define PWR_VMCR_PLS_Msk                     (0x7UL << PWR_VMCR_PLS_Pos)
7972 #define PWR_VMCR_PLS                         PWR_VMCR_PLS_Msk
7973 #define PWR_VMCR_PLS_0                       (0x1UL << PWR_VMCR_PLS_Pos)
7974 #define PWR_VMCR_PLS_1                       (0x2UL << PWR_VMCR_PLS_Pos)
7975 #define PWR_VMCR_PLS_2                       (0x4UL << PWR_VMCR_PLS_Pos)
7976 #define PWR_VMCR_AVDEN_Pos                   (8U)
7977 #define PWR_VMCR_AVDEN_Msk                   (0x1UL << PWR_VMCR_AVDEN_Pos)
7978 #define PWR_VMCR_AVDEN                       PWR_VMCR_AVDEN_Msk
7979 #define PWR_VMCR_ALS_Pos                     (9U)
7980 #define PWR_VMCR_ALS_Msk                     (0x3UL << PWR_VMCR_ALS_Pos)
7981 #define PWR_VMCR_ALS                         PWR_VMCR_ALS_Msk
7982 #define PWR_VMCR_ALS_0                       (0x1UL << PWR_VMCR_ALS_Pos)
7983 #define PWR_VMCR_ALS_1                       (0x2UL << PWR_VMCR_ALS_Pos)
7984 
7985 
7986 /********************  Bit definition for PWR_VMSR register  ******************/
7987 #define PWR_VMSR_AVDO_Pos                    (19U)
7988 #define PWR_VMSR_AVDO_Msk                    (0x1UL << PWR_VMSR_AVDO_Pos)
7989 #define PWR_VMSR_AVDO                        PWR_VMSR_AVDO_Msk
7990 #define PWR_VMSR_VDDIO2RDY_Pos               (20U)
7991 #define PWR_VMSR_VDDIO2RDY_Msk               (0x1UL << PWR_VMSR_VDDIO2RDY_Pos)
7992 #define PWR_VMSR_VDDIO2RDY                   PWR_VMSR_VDDIO2RDY_Msk
7993 #define PWR_VMSR_PVDO_Pos                    (22U)
7994 #define PWR_VMSR_PVDO_Msk                    (0x1UL << PWR_VMSR_PVDO_Pos)
7995 #define PWR_VMSR_PVDO                        PWR_VMSR_PVDO_Msk
7996 
7997 /********************  Bit definition for PWR_WUSCR register  ****************/
7998 #define PWR_WUSCR_CWUF1_Pos                (0U)
7999 #define PWR_WUSCR_CWUF1_Msk                (0x1UL << PWR_WUSCR_CWUF1_Pos)
8000 #define PWR_WUSCR_CWUF1                    PWR_WUSCR_CWUF1_Msk
8001 #define PWR_WUSCR_CWUF2_Pos                (1U)
8002 #define PWR_WUSCR_CWUF2_Msk                (0x1UL << PWR_WUSCR_CWUF2_Pos)
8003 #define PWR_WUSCR_CWUF2                    PWR_WUSCR_CWUF2_Msk
8004 #define PWR_WUSCR_CWUF3_Pos                (2U)
8005 #define PWR_WUSCR_CWUF3_Msk                (0x1UL << PWR_WUSCR_CWUF3_Pos)
8006 #define PWR_WUSCR_CWUF3                    PWR_WUSCR_CWUF3_Msk
8007 #define PWR_WUSCR_CWUF4_Pos                (3U)
8008 #define PWR_WUSCR_CWUF4_Msk                (0x1UL << PWR_WUSCR_CWUF4_Pos)
8009 #define PWR_WUSCR_CWUF4                    PWR_WUSCR_CWUF4_Msk
8010 #define PWR_WUSCR_CWUF5_Pos                (4U)
8011 #define PWR_WUSCR_CWUF5_Msk                (0x1UL << PWR_WUSCR_CWUF5_Pos)
8012 #define PWR_WUSCR_CWUF5                    PWR_WUSCR_CWUF5_Msk
8013 #define PWR_WUSCR_CWUF_Pos                 (0U)
8014 #define PWR_WUSCR_CWUF_Msk                 (0x1FUL << PWR_WUSCR_CWUF_Pos)
8015 #define PWR_WUSCR_CWUF                     PWR_WUSCR_CWUF_Msk
8016 
8017 /********************  Bit definition for PWR_WUSR register  ****************/
8018 #define PWR_WUSR_WUF1_Pos                (0U)
8019 #define PWR_WUSR_WUF1_Msk                (0x1UL << PWR_WUSR_WUF1_Pos)
8020 #define PWR_WUSR_WUF1                    PWR_WUSR_WUF1_Msk
8021 #define PWR_WUSR_WUF2_Pos                (1U)
8022 #define PWR_WUSR_WUF2_Msk                (0x1UL << PWR_WUSR_WUF2_Pos)
8023 #define PWR_WUSR_WUF2                    PWR_WUSR_WUF2_Msk
8024 #define PWR_WUSR_WUF3_Pos                (2U)
8025 #define PWR_WUSR_WUF3_Msk                (0x1UL << PWR_WUSR_WUF3_Pos)
8026 #define PWR_WUSR_WUF3                    PWR_WUSR_WUF3_Msk
8027 #define PWR_WUSR_WUF4_Pos                (3U)
8028 #define PWR_WUSR_WUF4_Msk                (0x1UL << PWR_WUSR_WUF4_Pos)
8029 #define PWR_WUSR_WUF4                    PWR_WUSR_WUF4_Msk
8030 #define PWR_WUSR_WUF5_Pos                (4U)
8031 #define PWR_WUSR_WUF5_Msk                (0x1UL << PWR_WUSR_WUF5_Pos)
8032 #define PWR_WUSR_WUF5                    PWR_WUSR_WUF5_Msk
8033 
8034 /********************  Bit definition for PWR_WUCR register  ***************/
8035 #define PWR_WUCR_WUPEN1_Pos              (0U)
8036 #define PWR_WUCR_WUPEN1_Msk              (0x1UL << PWR_WUCR_WUPEN1_Pos)
8037 #define PWR_WUCR_WUPEN1                  PWR_WUCR_WUPEN1_Msk
8038 #define PWR_WUCR_WUPEN2_Pos              (1U)
8039 #define PWR_WUCR_WUPEN2_Msk              (0x1UL << PWR_WUCR_WUPEN2_Pos)
8040 #define PWR_WUCR_WUPEN2                  PWR_WUCR_WUPEN2_Msk
8041 #define PWR_WUCR_WUPEN3_Pos              (2U)
8042 #define PWR_WUCR_WUPEN3_Msk              (0x1UL << PWR_WUCR_WUPEN3_Pos)
8043 #define PWR_WUCR_WUPEN3                  PWR_WUCR_WUPEN3_Msk
8044 #define PWR_WUCR_WUPEN4_Pos              (3U)
8045 #define PWR_WUCR_WUPEN4_Msk              (0x1UL << PWR_WUCR_WUPEN4_Pos)
8046 #define PWR_WUCR_WUPEN4                  PWR_WUCR_WUPEN4_Msk
8047 #define PWR_WUCR_WUPEN5_Pos              (4U)
8048 #define PWR_WUCR_WUPEN5_Msk              (0x1UL << PWR_WUCR_WUPEN5_Pos)
8049 #define PWR_WUCR_WUPEN5                  PWR_WUCR_WUPEN5_Msk
8050 #define PWR_WUCR_WUPEN_Pos               (0U)
8051 #define PWR_WUCR_WUPEN_Msk               (0x1FUL << PWR_WUCR_WUPEN_Pos)
8052 #define PWR_WUCR_WUPEN                   PWR_WUCR_WUPEN_Msk
8053 #define PWR_WUCR_WUPP1_Pos               (8U)
8054 #define PWR_WUCR_WUPP1_Msk               (0x1UL << PWR_WUCR_WUPP1_Pos)
8055 #define PWR_WUCR_WUPP1                   PWR_WUCR_WUPP1_Msk
8056 #define PWR_WUCR_WUPP2_Pos               (9U)
8057 #define PWR_WUCR_WUPP2_Msk               (0x1UL << PWR_WUCR_WUPP2_Pos)
8058 #define PWR_WUCR_WUPP2                   PWR_WUCR_WUPP2_Msk
8059 #define PWR_WUCR_WUPP3_Pos               (10U)
8060 #define PWR_WUCR_WUPP3_Msk               (0x1UL << PWR_WUCR_WUPP3_Pos)
8061 #define PWR_WUCR_WUPP3                   PWR_WUCR_WUPP3_Msk
8062 #define PWR_WUCR_WUPP4_Pos               (11U)
8063 #define PWR_WUCR_WUPP4_Msk               (0x1UL << PWR_WUCR_WUPP4_Pos)
8064 #define PWR_WUCR_WUPP4                   PWR_WUCR_WUPP4_Msk
8065 #define PWR_WUCR_WUPP5_Pos               (12U)
8066 #define PWR_WUCR_WUPP5_Msk               (0x1UL << PWR_WUCR_WUPP5_Pos)
8067 #define PWR_WUCR_WUPP5                   PWR_WUCR_WUPP5_Msk
8068 #define PWR_WUCR_WUPPUPD1_Pos            (16U)
8069 #define PWR_WUCR_WUPPUPD1_Msk            (0x3UL << PWR_WUCR_WUPPUPD1_Pos)
8070 #define PWR_WUCR_WUPPUPD1                PWR_WUCR_WUPPUPD1_Msk
8071 #define PWR_WUCR_WUPPUPD1_0              (0x1UL << PWR_WUCR_WUPPUPD1_Pos)
8072 #define PWR_WUCR_WUPPUPD1_1              (0x2UL << PWR_WUCR_WUPPUPD1_Pos)
8073 #define PWR_WUCR_WUPPUPD2_Pos            (18U)
8074 #define PWR_WUCR_WUPPUPD2_Msk            (0x3UL << PWR_WUCR_WUPPUPD2_Pos)
8075 #define PWR_WUCR_WUPPUPD2                PWR_WUCR_WUPPUPD2_Msk
8076 #define PWR_WUCR_WUPPUPD2_0              (0x1UL << PWR_WUCR_WUPPUPD2_Pos)
8077 #define PWR_WUCR_WUPPUPD2_1              (0x2UL << PWR_WUCR_WUPPUPD2_Pos)
8078 #define PWR_WUCR_WUPPUPD3_Pos            (20U)
8079 #define PWR_WUCR_WUPPUPD3_Msk            (0x3UL << PWR_WUCR_WUPPUPD3_Pos)
8080 #define PWR_WUCR_WUPPUPD3                PWR_WUCR_WUPPUPD3_Msk
8081 #define PWR_WUCR_WUPPUPD3_0              (0x1UL << PWR_WUCR_WUPPUPD3_Pos)
8082 #define PWR_WUCR_WUPPUPD3_1              (0x2UL << PWR_WUCR_WUPPUPD3_Pos)
8083 #define PWR_WUCR_WUPPUPD4_Pos            (22U)
8084 #define PWR_WUCR_WUPPUPD4_Msk            (0x3UL << PWR_WUCR_WUPPUPD4_Pos)
8085 #define PWR_WUCR_WUPPUPD4                PWR_WUCR_WUPPUPD4_Msk
8086 #define PWR_WUCR_WUPPUPD4_0              (0x1UL << PWR_WUCR_WUPPUPD4_Pos)
8087 #define PWR_WUCR_WUPPUPD4_1              (0x2UL << PWR_WUCR_WUPPUPD4_Pos)
8088 #define PWR_WUCR_WUPPUPD5_Pos            (24U)
8089 #define PWR_WUCR_WUPPUPD5_Msk            (0x3UL << PWR_WUCR_WUPPUPD5_Pos)
8090 #define PWR_WUCR_WUPPUPD5                PWR_WUCR_WUPPUPD5_Msk
8091 #define PWR_WUCR_WUPPUPD5_0              (0x1UL << PWR_WUCR_WUPPUPD5_Pos)
8092 #define PWR_WUCR_WUPPUPD5_1              (0x2UL << PWR_WUCR_WUPPUPD5_Pos)
8093 
8094 /********************  Bit definition for PWR_IORETR register  ****************/
8095 #define PWR_IORETR_IORETEN_Pos           (0U)
8096 #define PWR_IORETR_IORETEN_Msk           (0x1UL << PWR_IORETR_IORETEN_Pos)
8097 #define PWR_IORETR_IORETEN               PWR_IORETR_IORETEN_Msk
8098 #define PWR_IORETR_JTAGIORETEN_Pos       (16U)
8099 #define PWR_IORETR_JTAGIORETEN_Msk       (0x1UL << PWR_IORETR_JTAGIORETEN_Pos)
8100 #define PWR_IORETR_JTAGIORETEN           PWR_IORETR_JTAGIORETEN_Msk
8101 
8102 /********************  Bit definition for PWR_PRIVCFGR register  **************/
8103 #define PWR_PRIVCFGR_PRIV_Pos            (1U)
8104 #define PWR_PRIVCFGR_PRIV_Msk            (0x1UL << PWR_PRIVCFGR_PRIV_Pos)
8105 #define PWR_PRIVCFGR_PRIV                PWR_PRIVCFGR_PRIV_Msk
8106 
8107 /******************************************************************************/
8108 /*                                                                            */
8109 /*                      SRAMs configuration controller                        */
8110 /*                                                                            */
8111 /******************************************************************************/
8112 /*******************  Bit definition for RAMCFG_CR register  ******************/
8113 #define RAMCFG_CR_ECCE_Pos                  (0U)
8114 #define RAMCFG_CR_ECCE_Msk                  (0x1UL << RAMCFG_CR_ECCE_Pos)           /*!< 0x00000001 */
8115 #define RAMCFG_CR_ECCE                      RAMCFG_CR_ECCE_Msk                      /*!< ECC Enable */
8116 #define RAMCFG_CR_ALE_Pos                   (4U)
8117 #define RAMCFG_CR_ALE_Msk                   (0x1UL << RAMCFG_CR_ALE_Pos)            /*!< 0x00000010 */
8118 #define RAMCFG_CR_ALE                       RAMCFG_CR_ALE_Msk                       /*!< Address Latching Enable */
8119 #define RAMCFG_CR_SRAMER_Pos                (8U)
8120 #define RAMCFG_CR_SRAMER_Msk                (0x1UL << RAMCFG_CR_SRAMER_Pos)         /*!< 0x00000100 */
8121 #define RAMCFG_CR_SRAMER                    RAMCFG_CR_SRAMER_Msk                    /*!< Start Erase */
8122 
8123 /*******************  Bit definition for RAMCFG_IER register  *****************/
8124 #define RAMCFG_IER_SEIE_Pos                 (0U)
8125 #define RAMCFG_IER_SEIE_Msk                 (0x1UL << RAMCFG_IER_SEIE_Pos)          /*!< 0x00000001 */
8126 #define RAMCFG_IER_SEIE                     RAMCFG_IER_SEIE_Msk                     /*!< Single Error Interrupt Enable */
8127 #define RAMCFG_IER_DEIE_Pos                 (1U)
8128 #define RAMCFG_IER_DEIE_Msk                 (0x1UL << RAMCFG_IER_DEIE_Pos)          /*!< 0x00000002 */
8129 #define RAMCFG_IER_DEIE                     RAMCFG_IER_DEIE_Msk                     /*!< Double Error Interrupt Enable */
8130 #define RAMCFG_IER_ECCNMI_Pos               (3U)
8131 #define RAMCFG_IER_ECCNMI_Msk               (0x1UL << RAMCFG_IER_ECCNMI_Pos)        /*!< 0x00000008 */
8132 #define RAMCFG_IER_ECCNMI                   RAMCFG_IER_ECCNMI_Msk                   /*!< NMI redirection interrupt */
8133 
8134 /*******************  Bit definition for RAMCFG_ISR register  *****************/
8135 #define RAMCFG_ISR_SEDC_Pos                 (0U)
8136 #define RAMCFG_ISR_SEDC_Msk                 (0x1UL << RAMCFG_ISR_SEDC_Pos)          /*!< 0x00000001 */
8137 #define RAMCFG_ISR_SEDC                     RAMCFG_ISR_SEDC_Msk                     /*!< Single Error Detected and Corrected flag */
8138 #define RAMCFG_ISR_DED_Pos                  (1U)
8139 #define RAMCFG_ISR_DED_Msk                  (0x1UL << RAMCFG_ISR_DED_Pos)           /*!< 0x00000002 */
8140 #define RAMCFG_ISR_DED                      RAMCFG_ISR_DED_Msk                      /*!< Double Error Detected flag */
8141 #define RAMCFG_ISR_SRAMBUSY_Pos             (8U)
8142 #define RAMCFG_ISR_SRAMBUSY_Msk             (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)      /*!< 0x00000100 */
8143 #define RAMCFG_ISR_SRAMBUSY                 RAMCFG_ISR_SRAMBUSY_Msk                 /*!< SRAM busy flag */
8144 
8145 /*******************  Bit definition for RAMCFG_SEAR register  ****************/
8146 #define RAMCFG_SEAR_ESEA_Pos                (0U)
8147 #define RAMCFG_SEAR_ESEA_Msk                (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos)  /*!< 0xFFFFFFFF */
8148 #define RAMCFG_SEAR_ESEA                    RAMCFG_SEAR_ESEA_Msk                    /*!< ECC Single Error Address */
8149 
8150 /*******************  Bit definition for RAMCFG_DEAR register  ****************/
8151 #define RAMCFG_DEAR_EDEA_Pos                (0U)
8152 #define RAMCFG_DEAR_EDEA_Msk                (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos)  /*!< 0xFFFFFFFF */
8153 #define RAMCFG_DEAR_EDEA                    RAMCFG_DEAR_EDEA_Msk                    /*!< ECC Double Error Address */
8154 
8155 /*******************  Bit definition for RAMCFG_ICR register  *****************/
8156 #define RAMCFG_ICR_CSEDC_Pos                (0U)
8157 #define RAMCFG_ICR_CSEDC_Msk                (0x1UL << RAMCFG_ICR_CSEDC_Pos)         /*!< 0x00000001 */
8158 #define RAMCFG_ICR_CSEDC                    RAMCFG_ICR_CSEDC_Msk                    /*!< Clear ECC Single Error Detected and Corrected Flag */
8159 #define RAMCFG_ICR_CDED_Pos                 (1U)
8160 #define RAMCFG_ICR_CDED_Msk                 (0x1UL << RAMCFG_ICR_CDED_Pos)          /*!< 0x00000002 */
8161 #define RAMCFG_ICR_CDED                     RAMCFG_ICR_CDED_Msk                     /*!< Clear ECC Double Error Detected Flag*/
8162 
8163 /******************  Bit definition for RAMCFG_WPR1 register  *****************/
8164 #define RAMCFG_WPR1_P0WP_Pos                (0U)
8165 #define RAMCFG_WPR1_P0WP_Msk                (0x1UL << RAMCFG_WPR1_P0WP_Pos)         /*!< 0x00000001 */
8166 #define RAMCFG_WPR1_P0WP                    RAMCFG_WPR1_P0WP_Msk                    /*!< Write Protection Page 00 */
8167 #define RAMCFG_WPR1_P1WP_Pos                (1U)
8168 #define RAMCFG_WPR1_P1WP_Msk                (0x1UL << RAMCFG_WPR1_P1WP_Pos)         /*!< 0x00000002 */
8169 #define RAMCFG_WPR1_P1WP                    RAMCFG_WPR1_P1WP_Msk                    /*!< Write Protection Page 01 */
8170 #define RAMCFG_WPR1_P2WP_Pos                (2U)
8171 #define RAMCFG_WPR1_P2WP_Msk                (0x1UL << RAMCFG_WPR1_P2WP_Pos)         /*!< 0x00000004 */
8172 #define RAMCFG_WPR1_P2WP                    RAMCFG_WPR1_P2WP_Msk                    /*!< Write Protection Page 02 */
8173 #define RAMCFG_WPR1_P3WP_Pos                (3U)
8174 #define RAMCFG_WPR1_P3WP_Msk                (0x1UL << RAMCFG_WPR1_P3WP_Pos)         /*!< 0x00000008 */
8175 #define RAMCFG_WPR1_P3WP                    RAMCFG_WPR1_P3WP_Msk                    /*!< Write Protection Page 03 */
8176 #define RAMCFG_WPR1_P4WP_Pos                (4U)
8177 #define RAMCFG_WPR1_P4WP_Msk                (0x1UL << RAMCFG_WPR1_P4WP_Pos)         /*!< 0x00000010 */
8178 #define RAMCFG_WPR1_P4WP                    RAMCFG_WPR1_P4WP_Msk                    /*!< Write Protection Page 04 */
8179 #define RAMCFG_WPR1_P5WP_Pos                (5U)
8180 #define RAMCFG_WPR1_P5WP_Msk                (0x1UL << RAMCFG_WPR1_P5WP_Pos)         /*!< 0x00000020 */
8181 #define RAMCFG_WPR1_P5WP                    RAMCFG_WPR1_P5WP_Msk                    /*!< Write Protection Page 05 */
8182 #define RAMCFG_WPR1_P6WP_Pos                (6U)
8183 #define RAMCFG_WPR1_P6WP_Msk                (0x1UL << RAMCFG_WPR1_P6WP_Pos)         /*!< 0x00000040 */
8184 #define RAMCFG_WPR1_P6WP                    RAMCFG_WPR1_P6WP_Msk                    /*!< Write Protection Page 06 */
8185 #define RAMCFG_WPR1_P7WP_Pos                (7U)
8186 #define RAMCFG_WPR1_P7WP_Msk                (0x1UL << RAMCFG_WPR1_P7WP_Pos)         /*!< 0x00000080 */
8187 #define RAMCFG_WPR1_P7WP                    RAMCFG_WPR1_P7WP_Msk                    /*!< Write Protection Page 07 */
8188 #define RAMCFG_WPR1_P8WP_Pos                (8U)
8189 #define RAMCFG_WPR1_P8WP_Msk                (0x1UL << RAMCFG_WPR1_P8WP_Pos)         /*!< 0x00000100 */
8190 #define RAMCFG_WPR1_P8WP                    RAMCFG_WPR1_P8WP_Msk                    /*!< Write Protection Page 08 */
8191 #define RAMCFG_WPR1_P9WP_Pos                (9U)
8192 #define RAMCFG_WPR1_P9WP_Msk                (0x1UL << RAMCFG_WPR1_P9WP_Pos)         /*!< 0x00000200 */
8193 #define RAMCFG_WPR1_P9WP                    RAMCFG_WPR1_P9WP_Msk                    /*!< Write Protection Page 09 */
8194 #define RAMCFG_WPR1_P10WP_Pos               (10U)
8195 #define RAMCFG_WPR1_P10WP_Msk               (0x1UL << RAMCFG_WPR1_P10WP_Pos)        /*!< 0x00000400 */
8196 #define RAMCFG_WPR1_P10WP                   RAMCFG_WPR1_P10WP_Msk                   /*!< Write Protection Page 10 */
8197 #define RAMCFG_WPR1_P11WP_Pos               (11U)
8198 #define RAMCFG_WPR1_P11WP_Msk               (0x1UL << RAMCFG_WPR1_P11WP_Pos)        /*!< 0x00000800 */
8199 #define RAMCFG_WPR1_P11WP                   RAMCFG_WPR1_P11WP_Msk                   /*!< Write Protection Page 11 */
8200 #define RAMCFG_WPR1_P12WP_Pos               (12U)
8201 #define RAMCFG_WPR1_P12WP_Msk               (0x1UL << RAMCFG_WPR1_P12WP_Pos)        /*!< 0x00001000 */
8202 #define RAMCFG_WPR1_P12WP                   RAMCFG_WPR1_P12WP_Msk                   /*!< Write Protection Page 12 */
8203 #define RAMCFG_WPR1_P13WP_Pos               (13U)
8204 #define RAMCFG_WPR1_P13WP_Msk               (0x1UL << RAMCFG_WPR1_P13WP_Pos)        /*!< 0x00002000 */
8205 #define RAMCFG_WPR1_P13WP                   RAMCFG_WPR1_P13WP_Msk                   /*!< Write Protection Page 13 */
8206 #define RAMCFG_WPR1_P14WP_Pos               (14U)
8207 #define RAMCFG_WPR1_P14WP_Msk               (0x1UL << RAMCFG_WPR1_P14WP_Pos)        /*!< 0x00004000 */
8208 #define RAMCFG_WPR1_P14WP                   RAMCFG_WPR1_P14WP_Msk                   /*!< Write Protection Page 14 */
8209 #define RAMCFG_WPR1_P15WP_Pos               (15U)
8210 #define RAMCFG_WPR1_P15WP_Msk               (0x1UL << RAMCFG_WPR1_P15WP_Pos)        /*!< 0x00008000 */
8211 #define RAMCFG_WPR1_P15WP                   RAMCFG_WPR1_P15WP_Msk                   /*!< Write Protection Page 15 */
8212 #define RAMCFG_WPR1_P16WP_Pos               (16U)
8213 #define RAMCFG_WPR1_P16WP_Msk               (0x1UL << RAMCFG_WPR1_P16WP_Pos)        /*!< 0x00010000 */
8214 #define RAMCFG_WPR1_P16WP                   RAMCFG_WPR1_P16WP_Msk                   /*!< Write Protection Page 16 */
8215 
8216 /*****************  Bit definition for RAMCFG_ECCKEYR register  ***************/
8217 #define RAMCFG_ECCKEYR_ECCKEY_Pos           (0U)
8218 #define RAMCFG_ECCKEYR_ECCKEY_Msk           (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)   /*!< 0x000000FF */
8219 #define RAMCFG_ECCKEYR_ECCKEY               RAMCFG_ECCKEYR_ECCKEY_Msk               /*!< ECC Write Protection Key */
8220 
8221 /*****************  Bit definition for RAMCFG_ERKEYR register  ****************/
8222 #define RAMCFG_ERKEYR_ERASEKEY_Pos          (0U)
8223 #define RAMCFG_ERKEYR_ERASEKEY_Msk          (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos)  /*!< 0x000000FF */
8224 #define RAMCFG_ERKEYR_ERASEKEY              RAMCFG_ERKEYR_ERASEKEY_Msk              /*!< Erase Write Protection Key */
8225 
8226 
8227 /******************************************************************************/
8228 /*                                                                            */
8229 /*                         Reset and Clock Control                            */
8230 /*                                                                            */
8231 /******************************************************************************/
8232 /********************  Bit definition for RCC_CR register  ********************/
8233 #define RCC_CR_HSION_Pos                    (0U)
8234 #define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)             /*!< 0x00000001 */
8235 #define RCC_CR_HSION                        RCC_CR_HSION_Msk                        /*!< Internal High Speed oscillator (HSI) clock enable */
8236 #define RCC_CR_HSIRDY_Pos                   (1U)
8237 #define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)            /*!< 0x00000002 */
8238 #define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                       /*!< Internal High Speed oscillator (HSI) clock ready flag */
8239 #define RCC_CR_HSIKERON_Pos                 (2U)
8240 #define RCC_CR_HSIKERON_Msk                 (0x1UL << RCC_CR_HSIKERON_Pos)          /*!< 0x00000004 */
8241 #define RCC_CR_HSIKERON                     RCC_CR_HSIKERON_Msk                     /*!< Internal High Speed oscillator (HSI) clock enable for some IPs Kernel */
8242 #define RCC_CR_HSIDIV_Pos                   (3U)
8243 #define RCC_CR_HSIDIV_Msk                   (0x3UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000018 */
8244 #define RCC_CR_HSIDIV                       RCC_CR_HSIDIV_Msk                       /*!< Internal High Speed clock divider selection */
8245 #define RCC_CR_HSIDIV_0                     (0x1UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000008 */
8246 #define RCC_CR_HSIDIV_1                     (0x2UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000010 */
8247 #define RCC_CR_HSIDIVF_Pos                  (5U)
8248 #define RCC_CR_HSIDIVF_Msk                  (0x1UL << RCC_CR_HSIDIVF_Pos)           /*!< 0x00000020 */
8249 #define RCC_CR_HSIDIVF                      RCC_CR_HSIDIVF_Msk                      /*!< HSI Divider flag */
8250 #define RCC_CR_CSION_Pos                    (8U)
8251 #define RCC_CR_CSION_Msk                    (0x1UL << RCC_CR_CSION_Pos)             /*!< 0x00000100 */
8252 #define RCC_CR_CSION                        RCC_CR_CSION_Msk                        /*!< The Internal RC 4MHz oscillator (CSI) clock enable */
8253 #define RCC_CR_CSIRDY_Pos                   (9U)
8254 #define RCC_CR_CSIRDY_Msk                   (0x1UL << RCC_CR_CSIRDY_Pos)            /*!< 0x00000200 */
8255 #define RCC_CR_CSIRDY                       RCC_CR_CSIRDY_Msk                       /*!< The Internal RC 4MHz oscillator (CSI) clock ready */
8256 #define RCC_CR_CSIKERON_Pos                 (10U)
8257 #define RCC_CR_CSIKERON_Msk                 (0x1UL << RCC_CR_CSIKERON_Pos)          /*!< 0x00000400 */
8258 #define RCC_CR_CSIKERON                     RCC_CR_CSIKERON_Msk                     /*!< The Internal RC 4MHz oscillator (CSI) clock enable for some IPs Kernel */
8259 #define RCC_CR_HSI48ON_Pos                  (12U)
8260 #define RCC_CR_HSI48ON_Msk                  (0x1UL << RCC_CR_HSI48ON_Pos)           /*!< 0x00001000 */
8261 #define RCC_CR_HSI48ON                      RCC_CR_HSI48ON_Msk                      /*!< HSI48 clock enable */
8262 #define RCC_CR_HSI48RDY_Pos                 (13U)
8263 #define RCC_CR_HSI48RDY_Msk                 (0x1UL << RCC_CR_HSI48RDY_Pos)          /*!< 0x00002000 */
8264 #define RCC_CR_HSI48RDY                     RCC_CR_HSI48RDY_Msk                     /*!< HSI48 clock ready */
8265 #define RCC_CR_HSEON_Pos                    (16U)
8266 #define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)             /*!< 0x00010000 */
8267 #define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                        /*!< External High Speed oscillator (HSE) clock enable */
8268 #define RCC_CR_HSERDY_Pos                   (17U)
8269 #define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)            /*!< 0x00020000 */
8270 #define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                       /*!< External High Speed oscillator (HSE) clock ready */
8271 #define RCC_CR_HSEBYP_Pos                   (18U)
8272 #define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)            /*!< 0x00040000 */
8273 #define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                       /*!< External High Speed oscillator (HSE) clock bypass */
8274 #define RCC_CR_HSECSSON_Pos                 (19U)
8275 #define RCC_CR_HSECSSON_Msk                 (0x1UL << RCC_CR_HSECSSON_Pos)          /*!< 0x00080000 */
8276 #define RCC_CR_HSECSSON                     RCC_CR_HSECSSON_Msk                     /*!< HSE Clock Security System enable */
8277 #define RCC_CR_HSEEXT_Pos                   (20U)
8278 #define RCC_CR_HSEEXT_Msk                   (0x1UL << RCC_CR_HSEEXT_Pos)            /*!< 0x00100000 */
8279 #define RCC_CR_HSEEXT                       RCC_CR_HSEEXT_Msk                       /*!< External High Speed clock type in Bypass mode */
8280 #define RCC_CR_PLL1ON_Pos                   (24U)
8281 #define RCC_CR_PLL1ON_Msk                   (0x1UL << RCC_CR_PLL1ON_Pos)            /*!< 0x01000000 */
8282 #define RCC_CR_PLL1ON                       RCC_CR_PLL1ON_Msk                       /*!< System PLL clock enable */
8283 #define RCC_CR_PLL1RDY_Pos                  (25U)
8284 #define RCC_CR_PLL1RDY_Msk                  (0x1UL << RCC_CR_PLL1RDY_Pos)           /*!< 0x02000000 */
8285 #define RCC_CR_PLL1RDY                      RCC_CR_PLL1RDY_Msk                      /*!< System PLL clock ready */
8286 #define RCC_CR_PLL2ON_Pos                   (26U)
8287 #define RCC_CR_PLL2ON_Msk                   (0x1UL << RCC_CR_PLL2ON_Pos)            /*!< 0x04000000 */
8288 #define RCC_CR_PLL2ON                       RCC_CR_PLL2ON_Msk                       /*!< PLL2 enable */
8289 #define RCC_CR_PLL2RDY_Pos                  (27U)
8290 #define RCC_CR_PLL2RDY_Msk                  (0x1UL << RCC_CR_PLL2RDY_Pos)           /*!< 0x08000000 */
8291 #define RCC_CR_PLL2RDY                      RCC_CR_PLL2RDY_Msk                      /*!< PLL2 ready */
8292 
8293 /********************  Bit definition for RCC_HSICFGR register  ***************/
8294 /*!< HSICAL configuration */
8295 #define RCC_HSICFGR_HSICAL_Pos               (0U)
8296 #define RCC_HSICFGR_HSICAL_Msk               (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000FFF */
8297 #define RCC_HSICFGR_HSICAL                   RCC_HSICFGR_HSICAL_Msk                   /*!< HSICAL[11:0] bits */
8298 #define RCC_HSICFGR_HSICAL_0                 (0x01UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000001 */
8299 #define RCC_HSICFGR_HSICAL_1                 (0x02UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000002 */
8300 #define RCC_HSICFGR_HSICAL_2                 (0x04UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000004 */
8301 #define RCC_HSICFGR_HSICAL_3                 (0x08UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000008 */
8302 #define RCC_HSICFGR_HSICAL_4                 (0x10UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000010 */
8303 #define RCC_HSICFGR_HSICAL_5                 (0x20UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000020 */
8304 #define RCC_HSICFGR_HSICAL_6                 (0x40UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000040 */
8305 #define RCC_HSICFGR_HSICAL_7                 (0x80UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000080 */
8306 #define RCC_HSICFGR_HSICAL_8                 (0x100UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000100 */
8307 #define RCC_HSICFGR_HSICAL_9                 (0x200UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000200 */
8308 #define RCC_HSICFGR_HSICAL_10                (0x400UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000400 */
8309 #define RCC_HSICFGR_HSICAL_11                (0x800UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000800 */
8310 
8311 /*!< HSITRIM configuration */
8312 #define RCC_HSICFGR_HSITRIM_Pos              (16U)
8313 #define RCC_HSICFGR_HSITRIM_Msk              (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x007F0000 */
8314 #define RCC_HSICFGR_HSITRIM                  RCC_HSICFGR_HSITRIM_Msk                  /*!< HSITRIM[6:0] bits */
8315 #define RCC_HSICFGR_HSITRIM_0                (0x01UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00010000 */
8316 #define RCC_HSICFGR_HSITRIM_1                (0x02UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00020000 */
8317 #define RCC_HSICFGR_HSITRIM_2                (0x04UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00040000 */
8318 #define RCC_HSICFGR_HSITRIM_3                (0x08UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00080000 */
8319 #define RCC_HSICFGR_HSITRIM_4                (0x10UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00100000 */
8320 #define RCC_HSICFGR_HSITRIM_5                (0x20UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00200000 */
8321 #define RCC_HSICFGR_HSITRIM_6                (0x40UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00400000 */
8322 
8323 /********************  Bit definition for RCC_CRRCR register  *****************/
8324 /*!< HSI48CAL configuration */
8325 #define RCC_CRRCR_HSI48CAL_Pos              (0U)
8326 #define RCC_CRRCR_HSI48CAL_Msk              (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x000003FF */
8327 #define RCC_CRRCR_HSI48CAL                  RCC_CRRCR_HSI48CAL_Msk                  /*!< HSI48CAL[8:0] bits */
8328 #define RCC_CRRCR_HSI48CAL_0                (0x001UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000001 */
8329 #define RCC_CRRCR_HSI48CAL_1                (0x002UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000002 */
8330 #define RCC_CRRCR_HSI48CAL_2                (0x004UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000004 */
8331 #define RCC_CRRCR_HSI48CAL_3                (0x008UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000008 */
8332 #define RCC_CRRCR_HSI48CAL_4                (0x010UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000010 */
8333 #define RCC_CRRCR_HSI48CAL_5                (0x020UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000020 */
8334 #define RCC_CRRCR_HSI48CAL_6                (0x040UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000040 */
8335 #define RCC_CRRCR_HSI48CAL_7                (0x080UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000080 */
8336 #define RCC_CRRCR_HSI48CAL_8                (0x100UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000100 */
8337 #define RCC_CRRCR_HSI48CAL_9                (0x200UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000200 */
8338 
8339 /********************  Bit definition for RCC_CSICFGR register  ***************/
8340 /*!< CSICAL configuration */
8341 #define RCC_CSICFGR_CSICAL_Pos               (0U)
8342 #define RCC_CSICFGR_CSICAL_Msk               (0xFFUL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x000000FF */
8343 #define RCC_CSICFGR_CSICAL                   RCC_CSICFGR_CSICAL_Msk                   /*!< CSICAL[7:0] bits */
8344 #define RCC_CSICFGR_CSICAL_0                 (0x01UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000001 */
8345 #define RCC_CSICFGR_CSICAL_1                 (0x02UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000002 */
8346 #define RCC_CSICFGR_CSICAL_2                 (0x04UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000004 */
8347 #define RCC_CSICFGR_CSICAL_3                 (0x08UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000008 */
8348 #define RCC_CSICFGR_CSICAL_4                 (0x10UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000010 */
8349 #define RCC_CSICFGR_CSICAL_5                 (0x20UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000020 */
8350 #define RCC_CSICFGR_CSICAL_6                 (0x40UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000040 */
8351 #define RCC_CSICFGR_CSICAL_7                 (0x80UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000080 */
8352 
8353 /*!< CSITRIM configuration */
8354 #define RCC_CSICFGR_CSITRIM_Pos              (16U)
8355 #define RCC_CSICFGR_CSITRIM_Msk              (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x003F0000 */
8356 #define RCC_CSICFGR_CSITRIM                  RCC_CSICFGR_CSITRIM_Msk                  /*!< CSITRIM[5:0] bits */
8357 #define RCC_CSICFGR_CSITRIM_0                (0x01UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00010000 */
8358 #define RCC_CSICFGR_CSITRIM_1                (0x02UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00020000 */
8359 #define RCC_CSICFGR_CSITRIM_2                (0x04UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00040000 */
8360 #define RCC_CSICFGR_CSITRIM_3                (0x08UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00080000 */
8361 #define RCC_CSICFGR_CSITRIM_4                (0x10UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00100000 */
8362 #define RCC_CSICFGR_CSITRIM_5                (0x20UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00200000 */
8363 
8364 /********************  Bit definition for RCC_CFGR1 register  ******************/
8365 /*!< SW configuration */
8366 #define RCC_CFGR1_SW_Pos                    (0U)
8367 #define RCC_CFGR1_SW_Msk                    (0x3UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000003 */
8368 #define RCC_CFGR1_SW                        RCC_CFGR1_SW_Msk                        /*!< SW[1:0] bits (System clock Switch) */
8369 #define RCC_CFGR1_SW_0                      (0x1UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000001 */
8370 #define RCC_CFGR1_SW_1                      (0x2UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000002 */
8371 
8372 /*!< SWS configuration */
8373 #define RCC_CFGR1_SWS_Pos                   (3U)
8374 #define RCC_CFGR1_SWS_Msk                   (0x3UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000018 */
8375 #define RCC_CFGR1_SWS                       RCC_CFGR1_SWS_Msk                       /*!< SWS[1:0] bits (System Clock Switch Status) */
8376 #define RCC_CFGR1_SWS_0                     (0x1UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000008 */
8377 #define RCC_CFGR1_SWS_1                     (0x2UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000010 */
8378 
8379 #define RCC_CFGR1_STOPWUCK_Pos              (6U)
8380 #define RCC_CFGR1_STOPWUCK_Msk              (0x1UL << RCC_CFGR1_STOPWUCK_Pos)       /*!< 0x00000040 */
8381 #define RCC_CFGR1_STOPWUCK                  RCC_CFGR1_STOPWUCK_Msk                  /*!< Wake Up from stop and HSE CSS backup clock selection */
8382 #define RCC_CFGR1_STOPKERWUCK_Pos           (7U)
8383 #define RCC_CFGR1_STOPKERWUCK_Msk           (0x1UL << RCC_CFGR1_STOPKERWUCK_Pos)    /*!< 0x00000080 */
8384 #define RCC_CFGR1_STOPKERWUCK               RCC_CFGR1_STOPKERWUCK_Msk               /*!< Kernel Clock Selection after a Wake Up from STOP */
8385 
8386 /*!< RTCPRE configuration */
8387 #define RCC_CFGR1_RTCPRE_Pos                (8U)
8388 #define RCC_CFGR1_RTCPRE_Msk                (0x3FUL << RCC_CFGR1_RTCPRE_Pos)        /*!< 0x00003F00 */
8389 #define RCC_CFGR1_RTCPRE                    RCC_CFGR1_RTCPRE_Msk                    /*!< HSE division factor for RTC Clock */
8390 #define RCC_CFGR1_RTCPRE_0                  (0x1UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000100 */
8391 #define RCC_CFGR1_RTCPRE_1                  (0x2UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000200 */
8392 #define RCC_CFGR1_RTCPRE_2                  (0x4UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000400 */
8393 #define RCC_CFGR1_RTCPRE_3                  (0x8UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000800 */
8394 #define RCC_CFGR1_RTCPRE_4                  (0x10UL << RCC_CFGR1_RTCPRE_Pos)        /*!< 0x00001000 */
8395 #define RCC_CFGR1_RTCPRE_5                  (0x20UL << RCC_CFGR1_RTCPRE_Pos)        /*!< 0x00002000 */
8396 
8397 /*!< TIMPRE configuration */
8398 #define RCC_CFGR1_TIMPRE_Pos                (15U)
8399 #define RCC_CFGR1_TIMPRE_Msk                (0x1UL << RCC_CFGR1_TIMPRE_Pos)
8400 #define RCC_CFGR1_TIMPRE                    RCC_CFGR1_TIMPRE_Msk                    /*!< 0x00008000 */
8401 
8402 /*!< MCO1 configuration */
8403 #define RCC_CFGR1_MCO1PRE_Pos               (18U)
8404 #define RCC_CFGR1_MCO1PRE_Msk               (0xFUL << RCC_CFGR1_MCO1PRE_Pos)
8405 #define RCC_CFGR1_MCO1PRE                   RCC_CFGR1_MCO1PRE_Msk                   /*!< 0x003C0000 */
8406 #define RCC_CFGR1_MCO1PRE_0                 (0x1UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00040000 */
8407 #define RCC_CFGR1_MCO1PRE_1                 (0x2UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00080000 */
8408 #define RCC_CFGR1_MCO1PRE_2                 (0x4UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00100000 */
8409 #define RCC_CFGR1_MCO1PRE_3                 (0x8UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00200000 */
8410 
8411 #define RCC_CFGR1_MCO1SEL_Pos               (22U)
8412 #define RCC_CFGR1_MCO1SEL_Msk               (0x7UL << RCC_CFGR1_MCO1SEL_Pos)
8413 #define RCC_CFGR1_MCO1SEL                   RCC_CFGR1_MCO1SEL_Msk                   /*!< 0x01C00000 */
8414 #define RCC_CFGR1_MCO1SEL_0                 (0x1UL <<  RCC_CFGR1_MCO1SEL_Pos)       /*!< 0x00400000 */
8415 #define RCC_CFGR1_MCO1SEL_1                 (0x2UL <<  RCC_CFGR1_MCO1SEL_Pos)       /*!< 0x00800000 */
8416 #define RCC_CFGR1_MCO1SEL_2                 (0x4UL <<  RCC_CFGR1_MCO1SEL_Pos)       /*!< 0x01000000 */
8417 
8418 /*!< MCO2 configuration */
8419 #define RCC_CFGR1_MCO2PRE_Pos               (25U)
8420 #define RCC_CFGR1_MCO2PRE_Msk               (0xFUL << RCC_CFGR1_MCO2PRE_Pos)
8421 #define RCC_CFGR1_MCO2PRE                   RCC_CFGR1_MCO2PRE_Msk                   /*!< 0x1E000000 */
8422 #define RCC_CFGR1_MCO2PRE_0                 (0x1UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x02000000 */
8423 #define RCC_CFGR1_MCO2PRE_1                 (0x2UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x04000000 */
8424 #define RCC_CFGR1_MCO2PRE_2                 (0x4UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x08000000 */
8425 #define RCC_CFGR1_MCO2PRE_3                 (0x8UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x10000000 */
8426 
8427 #define RCC_CFGR1_MCO2SEL_Pos               (29U)
8428 #define RCC_CFGR1_MCO2SEL_Msk               (0x7UL << RCC_CFGR1_MCO2SEL_Pos)
8429 #define RCC_CFGR1_MCO2SEL                   RCC_CFGR1_MCO2SEL_Msk                   /*!< 0xE0000000 */
8430 #define RCC_CFGR1_MCO2SEL_0                 (0x1UL << RCC_CFGR1_MCO2SEL_Pos)        /*!< 0x20000000 */
8431 #define RCC_CFGR1_MCO2SEL_1                 (0x2UL << RCC_CFGR1_MCO2SEL_Pos)        /*!< 0x40000000 */
8432 #define RCC_CFGR1_MCO2SEL_2                 (0x4UL << RCC_CFGR1_MCO2SEL_Pos)        /*!< 0x80000000 */
8433 
8434 /********************  Bit definition for RCC_CFGR2 register  ******************/
8435 /*!< HPRE configuration */
8436 #define RCC_CFGR2_HPRE_Pos                  (0U)
8437 #define RCC_CFGR2_HPRE_Msk                  (0xFUL << RCC_CFGR2_HPRE_Pos)           /*!< 0x0000000F */
8438 #define RCC_CFGR2_HPRE                      RCC_CFGR2_HPRE_Msk                      /*!< HPRE[3:0] bits (AHB prescaler) */
8439 #define RCC_CFGR2_HPRE_0                    (0x1UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000001 */
8440 #define RCC_CFGR2_HPRE_1                    (0x2UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000002 */
8441 #define RCC_CFGR2_HPRE_2                    (0x4UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000004 */
8442 #define RCC_CFGR2_HPRE_3                    (0x8UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000008 */
8443 
8444 /*!< PPRE1 configuration */
8445 #define RCC_CFGR2_PPRE1_Pos                 (4U)
8446 #define RCC_CFGR2_PPRE1_Msk                 (0x7UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000070 */
8447 #define RCC_CFGR2_PPRE1                     RCC_CFGR2_PPRE1_Msk                     /*!< PPRE1[2:0] bits (APB1 prescaler) */
8448 #define RCC_CFGR2_PPRE1_0                   (0x1UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000010 */
8449 #define RCC_CFGR2_PPRE1_1                   (0x2UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000020 */
8450 #define RCC_CFGR2_PPRE1_2                   (0x4UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000040 */
8451 
8452 /*!< PPRE2 configuration */
8453 #define RCC_CFGR2_PPRE2_Pos                 (8U)
8454 #define RCC_CFGR2_PPRE2_Msk                 (0x7UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000700 */
8455 #define RCC_CFGR2_PPRE2                     RCC_CFGR2_PPRE2_Msk                     /*!< PPRE2[2:0] bits (APB2 prescaler) */
8456 #define RCC_CFGR2_PPRE2_0                   (0x1UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000100 */
8457 #define RCC_CFGR2_PPRE2_1                   (0x2UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000200 */
8458 #define RCC_CFGR2_PPRE2_2                   (0x4UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000400 */
8459 
8460 /*!< PPRE3 configuration */
8461 #define RCC_CFGR2_PPRE3_Pos                 (12U)
8462 #define RCC_CFGR2_PPRE3_Msk                 (0x7UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00007000 */
8463 #define RCC_CFGR2_PPRE3                     RCC_CFGR2_PPRE3_Msk                     /*!< PPRE3[2:0] bits (APB3 prescaler) */
8464 #define RCC_CFGR2_PPRE3_0                   (0x1UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00001000 */
8465 #define RCC_CFGR2_PPRE3_1                   (0x2UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00002000 */
8466 #define RCC_CFGR2_PPRE3_2                   (0x4UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00004000 */
8467 
8468 #define RCC_CFGR2_AHB1DIS_Pos               (16U)
8469 #define RCC_CFGR2_AHB1DIS_Msk               (0x1UL << RCC_CFGR2_AHB1DIS_Pos)        /*!< 0x00010000 */
8470 #define RCC_CFGR2_AHB1DIS                   RCC_CFGR2_AHB1DIS_Msk                   /*!< AHB1 clock disable */
8471 #define RCC_CFGR2_AHB2DIS_Pos               (17U)
8472 #define RCC_CFGR2_AHB2DIS_Msk               (0x1UL << RCC_CFGR2_AHB2DIS_Pos)        /*!< 0x00020000 */
8473 #define RCC_CFGR2_AHB2DIS                   RCC_CFGR2_AHB2DIS_Msk                   /*!< AHB2 clock disable */
8474 #define RCC_CFGR2_APB1DIS_Pos               (20U)
8475 #define RCC_CFGR2_APB1DIS_Msk               (0x1UL << RCC_CFGR2_APB1DIS_Pos)        /*!< 0x00100000 */
8476 #define RCC_CFGR2_APB1DIS                   RCC_CFGR2_APB1DIS_Msk                   /*!< APB1 clock disable */
8477 #define RCC_CFGR2_APB2DIS_Pos               (21U)
8478 #define RCC_CFGR2_APB2DIS_Msk               (0x1UL << RCC_CFGR2_APB2DIS_Pos)        /*!< 0x00200000 */
8479 #define RCC_CFGR2_APB2DIS                   RCC_CFGR2_APB2DIS_Msk                   /*!< APB2 clock disable */
8480 #define RCC_CFGR2_APB3DIS_Pos               (22U)
8481 #define RCC_CFGR2_APB3DIS_Msk               (0x1UL << RCC_CFGR2_APB3DIS_Pos)        /*!< 0x00400000 */
8482 #define RCC_CFGR2_APB3DIS                   RCC_CFGR2_APB3DIS_Msk                   /*!< APB3 clock disable */
8483 
8484 /********************  Bit definition for RCC_PLL1CFGR register  ***************/
8485 #define RCC_PLL1CFGR_PLL1SRC_Pos            (0U)
8486 #define RCC_PLL1CFGR_PLL1SRC_Msk            (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000003 */
8487 #define RCC_PLL1CFGR_PLL1SRC                RCC_PLL1CFGR_PLL1SRC_Msk
8488 #define RCC_PLL1CFGR_PLL1SRC_0              (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000001 */
8489 #define RCC_PLL1CFGR_PLL1SRC_1              (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000002 */
8490 #define RCC_PLL1CFGR_PLL1RGE_Pos            (2U)
8491 #define RCC_PLL1CFGR_PLL1RGE_Msk            (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x0000000C */
8492 #define RCC_PLL1CFGR_PLL1RGE                RCC_PLL1CFGR_PLL1RGE_Msk
8493 #define RCC_PLL1CFGR_PLL1RGE_0              (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x00000004 */
8494 #define RCC_PLL1CFGR_PLL1RGE_1              (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x00000008 */
8495 #define RCC_PLL1CFGR_PLL1FRACEN_Pos         (4U)
8496 #define RCC_PLL1CFGR_PLL1FRACEN_Msk         (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos)  /*!< 0x00000010 */
8497 #define RCC_PLL1CFGR_PLL1FRACEN             RCC_PLL1CFGR_PLL1FRACEN_Msk
8498 #define RCC_PLL1CFGR_PLL1VCOSEL_Pos         (5U)
8499 #define RCC_PLL1CFGR_PLL1VCOSEL_Msk         (0x1UL << RCC_PLL1CFGR_PLL1VCOSEL_Pos) /*!< 0x00000020 */
8500 #define RCC_PLL1CFGR_PLL1VCOSEL             RCC_PLL1CFGR_PLL1VCOSEL_Msk
8501 #define RCC_PLL1CFGR_PLL1M_Pos              (8U)
8502 #define RCC_PLL1CFGR_PLL1M_Msk              (0x3FUL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00003F00 */
8503 #define RCC_PLL1CFGR_PLL1M                  RCC_PLL1CFGR_PLL1M_Msk
8504 #define RCC_PLL1CFGR_PLL1M_0                (0x01UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000100 */
8505 #define RCC_PLL1CFGR_PLL1M_1                (0x02UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000200 */
8506 #define RCC_PLL1CFGR_PLL1M_2                (0x04UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000400 */
8507 #define RCC_PLL1CFGR_PLL1M_3                (0x08UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000800 */
8508 #define RCC_PLL1CFGR_PLL1M_4                (0x10UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00001000 */
8509 #define RCC_PLL1CFGR_PLL1M_5                (0x20UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00002000 */
8510 #define RCC_PLL1CFGR_PLL1PEN_Pos            (16U)
8511 #define RCC_PLL1CFGR_PLL1PEN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos)     /*!< 0x00010000 */
8512 #define RCC_PLL1CFGR_PLL1PEN                RCC_PLL1CFGR_PLL1PEN_Msk
8513 #define RCC_PLL1CFGR_PLL1QEN_Pos            (17U)
8514 #define RCC_PLL1CFGR_PLL1QEN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos)     /*!< 0x00020000 */
8515 #define RCC_PLL1CFGR_PLL1QEN                RCC_PLL1CFGR_PLL1QEN_Msk
8516 #define RCC_PLL1CFGR_PLL1REN_Pos            (18U)
8517 #define RCC_PLL1CFGR_PLL1REN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos)     /*!< 0x00040000 */
8518 #define RCC_PLL1CFGR_PLL1REN                RCC_PLL1CFGR_PLL1REN_Msk
8519 
8520 /********************  Bit definition for RCC_PLL2CFGR register  ***************/
8521 #define RCC_PLL2CFGR_PLL2SRC_Pos            (0U)
8522 #define RCC_PLL2CFGR_PLL2SRC_Msk            (0x3UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000003 */
8523 #define RCC_PLL2CFGR_PLL2SRC                RCC_PLL2CFGR_PLL2SRC_Msk
8524 #define RCC_PLL2CFGR_PLL2SRC_0              (0x1UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000001 */
8525 #define RCC_PLL2CFGR_PLL2SRC_1              (0x2UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000002 */
8526 #define RCC_PLL2CFGR_PLL2RGE_Pos            (2U)
8527 #define RCC_PLL2CFGR_PLL2RGE_Msk            (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x0000000C */
8528 #define RCC_PLL2CFGR_PLL2RGE                RCC_PLL2CFGR_PLL2RGE_Msk
8529 #define RCC_PLL2CFGR_PLL2RGE_0              (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x00000004 */
8530 #define RCC_PLL2CFGR_PLL2RGE_1              (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x00000008 */
8531 #define RCC_PLL2CFGR_PLL2FRACEN_Pos         (4U)
8532 #define RCC_PLL2CFGR_PLL2FRACEN_Msk         (0x1UL << RCC_PLL2CFGR_PLL2FRACEN_Pos)  /*!< 0x00000010 */
8533 #define RCC_PLL2CFGR_PLL2FRACEN             RCC_PLL2CFGR_PLL2FRACEN_Msk
8534 #define RCC_PLL2CFGR_PLL2VCOSEL_Pos         (5U)
8535 #define RCC_PLL2CFGR_PLL2VCOSEL_Msk         (0x1UL << RCC_PLL2CFGR_PLL2VCOSEL_Pos)  /*!< 0x00000020 */
8536 #define RCC_PLL2CFGR_PLL2VCOSEL             RCC_PLL2CFGR_PLL2VCOSEL_Msk
8537 #define RCC_PLL2CFGR_PLL2M_Pos              (8U)
8538 #define RCC_PLL2CFGR_PLL2M_Msk              (0x3FUL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00003F00 */
8539 #define RCC_PLL2CFGR_PLL2M                  RCC_PLL2CFGR_PLL2M_Msk
8540 #define RCC_PLL2CFGR_PLL2M_0                (0x01UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000100 */
8541 #define RCC_PLL2CFGR_PLL2M_1                (0x02UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000200 */
8542 #define RCC_PLL2CFGR_PLL2M_2                (0x04UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000400 */
8543 #define RCC_PLL2CFGR_PLL2M_3                (0x08UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000800 */
8544 #define RCC_PLL2CFGR_PLL2M_4                (0x10UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00001000 */
8545 #define RCC_PLL2CFGR_PLL2M_5                (0x20UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00002000 */
8546 #define RCC_PLL2CFGR_PLL2PEN_Pos            (16U)
8547 #define RCC_PLL2CFGR_PLL2PEN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2PEN_Pos)     /*!< 0x00010000 */
8548 #define RCC_PLL2CFGR_PLL2PEN                RCC_PLL2CFGR_PLL2PEN_Msk
8549 #define RCC_PLL2CFGR_PLL2QEN_Pos            (17U)
8550 #define RCC_PLL2CFGR_PLL2QEN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2QEN_Pos)     /*!< 0x00020000 */
8551 #define RCC_PLL2CFGR_PLL2QEN                RCC_PLL2CFGR_PLL2QEN_Msk
8552 #define RCC_PLL2CFGR_PLL2REN_Pos            (18U)
8553 #define RCC_PLL2CFGR_PLL2REN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2REN_Pos)     /*!< 0x00040000 */
8554 #define RCC_PLL2CFGR_PLL2REN                RCC_PLL2CFGR_PLL2REN_Msk
8555 
8556 /********************  Bit definition for RCC_PLL1DIVR register  ***************/
8557 #define RCC_PLL1DIVR_PLL1N_Pos              (0U)
8558 #define RCC_PLL1DIVR_PLL1N_Msk              (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x000001FF */
8559 #define RCC_PLL1DIVR_PLL1N                  RCC_PLL1DIVR_PLL1N_Msk
8560 #define RCC_PLL1DIVR_PLL1N_0                (0x001UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000001 */
8561 #define RCC_PLL1DIVR_PLL1N_1                (0x002UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000002 */
8562 #define RCC_PLL1DIVR_PLL1N_2                (0x004UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000004 */
8563 #define RCC_PLL1DIVR_PLL1N_3                (0x008UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000008 */
8564 #define RCC_PLL1DIVR_PLL1N_4                (0x010UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000010 */
8565 #define RCC_PLL1DIVR_PLL1N_5                (0x020UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000020 */
8566 #define RCC_PLL1DIVR_PLL1N_6                (0x040UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000040 */
8567 #define RCC_PLL1DIVR_PLL1N_7                (0x080UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000080 */
8568 #define RCC_PLL1DIVR_PLL1N_8                (0x100UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000100 */
8569 #define RCC_PLL1DIVR_PLL1P_Pos              (9U)
8570 #define RCC_PLL1DIVR_PLL1P_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos)      /*!< 0x0000FE00 */
8571 #define RCC_PLL1DIVR_PLL1P                  RCC_PLL1DIVR_PLL1P_Msk
8572 #define RCC_PLL1DIVR_PLL1P_0                (0x001UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000200 */
8573 #define RCC_PLL1DIVR_PLL1P_1                (0x002UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000400 */
8574 #define RCC_PLL1DIVR_PLL1P_2                (0x004UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000800 */
8575 #define RCC_PLL1DIVR_PLL1P_3                (0x008UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00001000 */
8576 #define RCC_PLL1DIVR_PLL1P_4                (0x010UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00002000 */
8577 #define RCC_PLL1DIVR_PLL1P_5                (0x020UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00004000 */
8578 #define RCC_PLL1DIVR_PLL1P_6                (0x040UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00008000 */
8579 #define RCC_PLL1DIVR_PLL1Q_Pos              (16U)
8580 #define RCC_PLL1DIVR_PLL1Q_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos)      /*!< 0x007F0000 */
8581 #define RCC_PLL1DIVR_PLL1Q                  RCC_PLL1DIVR_PLL1Q_Msk
8582 #define RCC_PLL1DIVR_PLL1Q_0                (0x001UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00010000 */
8583 #define RCC_PLL1DIVR_PLL1Q_1                (0x002UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00020000 */
8584 #define RCC_PLL1DIVR_PLL1Q_2                (0x004UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00040000 */
8585 #define RCC_PLL1DIVR_PLL1Q_3                (0x008UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00080000 */
8586 #define RCC_PLL1DIVR_PLL1Q_4                (0x010UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00100000 */
8587 #define RCC_PLL1DIVR_PLL1Q_5                (0x020UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00200020 */
8588 #define RCC_PLL1DIVR_PLL1Q_6                (0x040UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00400000 */
8589 #define RCC_PLL1DIVR_PLL1R_Pos              (24U)
8590 #define RCC_PLL1DIVR_PLL1R_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos)      /*!< 0x7F000000 */
8591 #define RCC_PLL1DIVR_PLL1R                  RCC_PLL1DIVR_PLL1R_Msk
8592 #define RCC_PLL1DIVR_PLL1R_0                (0x001UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x01000000 */
8593 #define RCC_PLL1DIVR_PLL1R_1                (0x002UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x02000000 */
8594 #define RCC_PLL1DIVR_PLL1R_2                (0x004UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x04000000 */
8595 #define RCC_PLL1DIVR_PLL1R_3                (0x008UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x08000000 */
8596 #define RCC_PLL1DIVR_PLL1R_4                (0x010UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x10000000 */
8597 #define RCC_PLL1DIVR_PLL1R_5                (0x020UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x20000000 */
8598 #define RCC_PLL1DIVR_PLL1R_6                (0x040UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x40000000 */
8599 
8600 /********************  Bit definition for RCC_PLL1FRACR register  ***************/
8601 #define RCC_PLL1FRACR_PLL1FRACN_Pos         (3U)
8602 #define RCC_PLL1FRACR_PLL1FRACN_Msk         (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */
8603 #define RCC_PLL1FRACR_PLL1FRACN             RCC_PLL1FRACR_PLL1FRACN_Msk
8604 #define RCC_PLL1FRACR_PLL1FRACN_0           (0x0001UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000008 */
8605 #define RCC_PLL1FRACR_PLL1FRACN_1           (0x0002UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000010 */
8606 #define RCC_PLL1FRACR_PLL1FRACN_2           (0x0004UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000020 */
8607 #define RCC_PLL1FRACR_PLL1FRACN_3           (0x0008UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000040 */
8608 #define RCC_PLL1FRACR_PLL1FRACN_4           (0x0010UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000080 */
8609 #define RCC_PLL1FRACR_PLL1FRACN_5           (0x0020UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000100 */
8610 #define RCC_PLL1FRACR_PLL1FRACN_6           (0x0040UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000200 */
8611 #define RCC_PLL1FRACR_PLL1FRACN_7           (0x0080UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000400 */
8612 #define RCC_PLL1FRACR_PLL1FRACN_8           (0x0100UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000800 */
8613 #define RCC_PLL1FRACR_PLL1FRACN_9           (0x0200UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00001000 */
8614 #define RCC_PLL1FRACR_PLL1FRACN_10          (0x0400UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00002000 */
8615 #define RCC_PLL1FRACR_PLL1FRACN_11          (0x0800UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00004000 */
8616 #define RCC_PLL1FRACR_PLL1FRACN_12          (0x1000UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00008000 */
8617 
8618 /********************  Bit definition for RCC_PLL2DIVR register  ***************/
8619 #define RCC_PLL2DIVR_PLL2N_Pos              (0U)
8620 #define RCC_PLL2DIVR_PLL2N_Msk              (0x1FFUL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x000001FF */
8621 #define RCC_PLL2DIVR_PLL2N                  RCC_PLL2DIVR_PLL2N_Msk
8622 #define RCC_PLL2DIVR_PLL2N_0                (0x001UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000001 */
8623 #define RCC_PLL2DIVR_PLL2N_1                (0x002UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000002 */
8624 #define RCC_PLL2DIVR_PLL2N_2                (0x004UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000004 */
8625 #define RCC_PLL2DIVR_PLL2N_3                (0x008UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000008 */
8626 #define RCC_PLL2DIVR_PLL2N_4                (0x010UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000010 */
8627 #define RCC_PLL2DIVR_PLL2N_5                (0x020UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000020 */
8628 #define RCC_PLL2DIVR_PLL2N_6                (0x040UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000040 */
8629 #define RCC_PLL2DIVR_PLL2N_7                (0x080UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000080 */
8630 #define RCC_PLL2DIVR_PLL2N_8                (0x100UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000100 */
8631 #define RCC_PLL2DIVR_PLL2P_Pos              (9U)
8632 #define RCC_PLL2DIVR_PLL2P_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2P_Pos)      /*!< 0x0000FE00 */
8633 #define RCC_PLL2DIVR_PLL2P                  RCC_PLL2DIVR_PLL2P_Msk
8634 #define RCC_PLL2DIVR_PLL2P_0                (0x001UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000200 */
8635 #define RCC_PLL2DIVR_PLL2P_1                (0x002UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000400 */
8636 #define RCC_PLL2DIVR_PLL2P_2                (0x004UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000800 */
8637 #define RCC_PLL2DIVR_PLL2P_3                (0x008UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00001000 */
8638 #define RCC_PLL2DIVR_PLL2P_4                (0x010UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00002000 */
8639 #define RCC_PLL2DIVR_PLL2P_5                (0x020UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00004000 */
8640 #define RCC_PLL2DIVR_PLL2P_6                (0x040UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00008000 */
8641 #define RCC_PLL2DIVR_PLL2Q_Pos              (16U)
8642 #define RCC_PLL2DIVR_PLL2Q_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2Q_Pos)      /*!< 0x007F0000 */
8643 #define RCC_PLL2DIVR_PLL2Q                  RCC_PLL2DIVR_PLL2Q_Msk
8644 #define RCC_PLL2DIVR_PLL2Q_0                (0x001UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00010000 */
8645 #define RCC_PLL2DIVR_PLL2Q_1                (0x002UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00020000 */
8646 #define RCC_PLL2DIVR_PLL2Q_2                (0x004UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00040000 */
8647 #define RCC_PLL2DIVR_PLL2Q_3                (0x008UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00080000 */
8648 #define RCC_PLL2DIVR_PLL2Q_4                (0x010UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00100000 */
8649 #define RCC_PLL2DIVR_PLL2Q_5                (0x020UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00200020 */
8650 #define RCC_PLL2DIVR_PLL2Q_6                (0x040UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00400000 */
8651 #define RCC_PLL2DIVR_PLL2R_Pos              (24U)
8652 #define RCC_PLL2DIVR_PLL2R_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2R_Pos)      /*!< 0x7F000000 */
8653 #define RCC_PLL2DIVR_PLL2R                  RCC_PLL2DIVR_PLL2R_Msk
8654 #define RCC_PLL2DIVR_PLL2R_0                (0x001UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x01000000 */
8655 #define RCC_PLL2DIVR_PLL2R_1                (0x002UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x02000000 */
8656 #define RCC_PLL2DIVR_PLL2R_2                (0x004UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x04000000 */
8657 #define RCC_PLL2DIVR_PLL2R_3                (0x008UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x08000000 */
8658 #define RCC_PLL2DIVR_PLL2R_4                (0x010UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x10000000 */
8659 #define RCC_PLL2DIVR_PLL2R_5                (0x020UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x20000000 */
8660 #define RCC_PLL2DIVR_PLL2R_6                (0x040UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x40000000 */
8661 
8662 /********************  Bit definition for RCC_PLL2FRACR register  ***************/
8663 #define RCC_PLL2FRACR_PLL2FRACN_Pos         (3U)
8664 #define RCC_PLL2FRACR_PLL2FRACN_Msk         (0x1FFFUL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x0000FFF8 */
8665 #define RCC_PLL2FRACR_PLL2FRACN             RCC_PLL2FRACR_PLL2FRACN_Msk
8666 #define RCC_PLL2FRACR_PLL2FRACN_0           (0x0001UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000008 */
8667 #define RCC_PLL2FRACR_PLL2FRACN_1           (0x0002UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000010 */
8668 #define RCC_PLL2FRACR_PLL2FRACN_2           (0x0004UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000020 */
8669 #define RCC_PLL2FRACR_PLL2FRACN_3           (0x0008UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000040 */
8670 #define RCC_PLL2FRACR_PLL2FRACN_4           (0x0010UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000080 */
8671 #define RCC_PLL2FRACR_PLL2FRACN_5           (0x0020UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000100 */
8672 #define RCC_PLL2FRACR_PLL2FRACN_6           (0x0040UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000200 */
8673 #define RCC_PLL2FRACR_PLL2FRACN_7           (0x0080UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000400 */
8674 #define RCC_PLL2FRACR_PLL2FRACN_8           (0x0100UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000800 */
8675 #define RCC_PLL2FRACR_PLL2FRACN_9           (0x0200UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00001000 */
8676 #define RCC_PLL2FRACR_PLL2FRACN_10          (0x0400UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00002000 */
8677 #define RCC_PLL2FRACR_PLL2FRACN_11          (0x0800UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00004000 */
8678 #define RCC_PLL2FRACR_PLL2FRACN_12          (0x1000UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00008000 */
8679 
8680 /********************  Bit definition for RCC_CIER register  ******************/
8681 #define RCC_CIER_LSIRDYIE_Pos               (0U)
8682 #define RCC_CIER_LSIRDYIE_Msk               (0x1UL << RCC_CIER_LSIRDYIE_Pos)        /*!< 0x00000001 */
8683 #define RCC_CIER_LSIRDYIE                   RCC_CIER_LSIRDYIE_Msk
8684 #define RCC_CIER_LSERDYIE_Pos               (1U)
8685 #define RCC_CIER_LSERDYIE_Msk               (0x1UL << RCC_CIER_LSERDYIE_Pos)        /*!< 0x00000002 */
8686 #define RCC_CIER_LSERDYIE                   RCC_CIER_LSERDYIE_Msk
8687 #define RCC_CIER_CSIRDYIE_Pos               (2U)
8688 #define RCC_CIER_CSIRDYIE_Msk               (0x1UL << RCC_CIER_CSIRDYIE_Pos)        /*!< 0x00000004 */
8689 #define RCC_CIER_CSIRDYIE                   RCC_CIER_CSIRDYIE_Msk
8690 #define RCC_CIER_HSIRDYIE_Pos               (3U)
8691 #define RCC_CIER_HSIRDYIE_Msk               (0x1UL << RCC_CIER_HSIRDYIE_Pos)        /*!< 0x00000008 */
8692 #define RCC_CIER_HSIRDYIE                   RCC_CIER_HSIRDYIE_Msk
8693 #define RCC_CIER_HSERDYIE_Pos               (4U)
8694 #define RCC_CIER_HSERDYIE_Msk               (0x1UL << RCC_CIER_HSERDYIE_Pos)        /*!< 0x00000010 */
8695 #define RCC_CIER_HSERDYIE                   RCC_CIER_HSERDYIE_Msk
8696 #define RCC_CIER_HSI48RDYIE_Pos             (5U)
8697 #define RCC_CIER_HSI48RDYIE_Msk             (0x1UL << RCC_CIER_HSI48RDYIE_Pos)      /*!< 0x00000020 */
8698 #define RCC_CIER_HSI48RDYIE                 RCC_CIER_HSI48RDYIE_Msk
8699 #define RCC_CIER_PLL1RDYIE_Pos              (6U)
8700 #define RCC_CIER_PLL1RDYIE_Msk              (0x1UL << RCC_CIER_PLL1RDYIE_Pos)       /*!< 0x00000040 */
8701 #define RCC_CIER_PLL1RDYIE                  RCC_CIER_PLL1RDYIE_Msk
8702 #define RCC_CIER_PLL2RDYIE_Pos              (7U)
8703 #define RCC_CIER_PLL2RDYIE_Msk              (0x1UL << RCC_CIER_PLL2RDYIE_Pos)       /*!< 0x00000080 */
8704 #define RCC_CIER_PLL2RDYIE                  RCC_CIER_PLL2RDYIE_Msk
8705 
8706 /********************  Bit definition for RCC_CIFR register  ****************/
8707 #define RCC_CIFR_LSIRDYF_Pos                (0U)
8708 #define RCC_CIFR_LSIRDYF_Msk                (0x1UL << RCC_CIFR_LSIRDYF_Pos)         /*!< 0x00000001 */
8709 #define RCC_CIFR_LSIRDYF                    RCC_CIFR_LSIRDYF_Msk
8710 #define RCC_CIFR_LSERDYF_Pos                (1U)
8711 #define RCC_CIFR_LSERDYF_Msk                (0x1UL << RCC_CIFR_LSERDYF_Pos)         /*!< 0x00000002 */
8712 #define RCC_CIFR_LSERDYF                    RCC_CIFR_LSERDYF_Msk
8713 #define RCC_CIFR_CSIRDYF_Pos                (2U)
8714 #define RCC_CIFR_CSIRDYF_Msk                (0x1UL << RCC_CIFR_CSIRDYF_Pos)         /*!< 0x00000004 */
8715 #define RCC_CIFR_CSIRDYF                    RCC_CIFR_CSIRDYF_Msk
8716 #define RCC_CIFR_HSIRDYF_Pos                (3U)
8717 #define RCC_CIFR_HSIRDYF_Msk                (0x1UL << RCC_CIFR_HSIRDYF_Pos)         /*!< 0x00000008 */
8718 #define RCC_CIFR_HSIRDYF                    RCC_CIFR_HSIRDYF_Msk
8719 #define RCC_CIFR_HSERDYF_Pos                (4U)
8720 #define RCC_CIFR_HSERDYF_Msk                (0x1UL << RCC_CIFR_HSERDYF_Pos)         /*!< 0x00000010 */
8721 #define RCC_CIFR_HSERDYF                    RCC_CIFR_HSERDYF_Msk
8722 #define RCC_CIFR_HSI48RDYF_Pos              (5U)
8723 #define RCC_CIFR_HSI48RDYF_Msk              (0x1UL << RCC_CIFR_HSI48RDYF_Pos)       /*!< 0x00000020 */
8724 #define RCC_CIFR_HSI48RDYF                  RCC_CIFR_HSI48RDYF_Msk
8725 #define RCC_CIFR_PLL1RDYF_Pos               (6U)
8726 #define RCC_CIFR_PLL1RDYF_Msk               (0x1UL << RCC_CIFR_PLL1RDYF_Pos)        /*!< 0x00000040 */
8727 #define RCC_CIFR_PLL1RDYF                   RCC_CIFR_PLL1RDYF_Msk
8728 #define RCC_CIFR_PLL2RDYF_Pos               (7U)
8729 #define RCC_CIFR_PLL2RDYF_Msk               (0x1UL << RCC_CIFR_PLL2RDYF_Pos)        /*!< 0x00000080 */
8730 #define RCC_CIFR_PLL2RDYF                   RCC_CIFR_PLL2RDYF_Msk
8731 #define RCC_CIFR_HSECSSF_Pos                (10U)
8732 #define RCC_CIFR_HSECSSF_Msk                (0x1UL << RCC_CIFR_HSECSSF_Pos)         /*!< 0x00000400 */
8733 #define RCC_CIFR_HSECSSF                    RCC_CIFR_HSECSSF_Msk
8734 
8735 /********************  Bit definition for RCC_CICR register  ****************/
8736 #define RCC_CICR_LSIRDYC_Pos                (0U)
8737 #define RCC_CICR_LSIRDYC_Msk                (0x1UL << RCC_CICR_LSIRDYC_Pos)         /*!< 0x00000001 */
8738 #define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk
8739 #define RCC_CICR_LSERDYC_Pos                (1U)
8740 #define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)         /*!< 0x00000002 */
8741 #define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk
8742 #define RCC_CICR_CSIRDYC_Pos                (2U)
8743 #define RCC_CICR_CSIRDYC_Msk                (0x1UL << RCC_CICR_CSIRDYC_Pos)         /*!< 0x00000004 */
8744 #define RCC_CICR_CSIRDYC                    RCC_CICR_CSIRDYC_Msk
8745 #define RCC_CICR_HSIRDYC_Pos                (3U)
8746 #define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)         /*!< 0x00000008 */
8747 #define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk
8748 #define RCC_CICR_HSERDYC_Pos                (4U)
8749 #define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)         /*!< 0x00000010 */
8750 #define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk
8751 #define RCC_CICR_HSI48RDYC_Pos              (5U)
8752 #define RCC_CICR_HSI48RDYC_Msk              (0x1UL << RCC_CICR_HSI48RDYC_Pos)       /*!< 0x00000020 */
8753 #define RCC_CICR_HSI48RDYC                  RCC_CICR_HSI48RDYC_Msk
8754 #define RCC_CICR_PLL1RDYC_Pos               (6U)
8755 #define RCC_CICR_PLL1RDYC_Msk               (0x1UL << RCC_CICR_PLL1RDYC_Pos)        /*!< 0x00000040 */
8756 #define RCC_CICR_PLL1RDYC                   RCC_CICR_PLL1RDYC_Msk
8757 #define RCC_CICR_PLL2RDYC_Pos               (7U)
8758 #define RCC_CICR_PLL2RDYC_Msk               (0x1UL << RCC_CICR_PLL2RDYC_Pos)        /*!< 0x00000080 */
8759 #define RCC_CICR_PLL2RDYC                   RCC_CICR_PLL2RDYC_Msk
8760 #define RCC_CICR_HSECSSC_Pos                (10U)
8761 #define RCC_CICR_HSECSSC_Msk                (0x1UL << RCC_CICR_HSECSSC_Pos)         /*!< 0x00000400 */
8762 #define RCC_CICR_HSECSSC                    RCC_CICR_HSECSSC_Msk
8763 
8764 /********************  Bit definition for RCC_AHB1RSTR register  **************/
8765 #define RCC_AHB1RSTR_GPDMA1RST_Pos          (0U)
8766 #define RCC_AHB1RSTR_GPDMA1RST_Msk          (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos)   /*!< 0x00000001 */
8767 #define RCC_AHB1RSTR_GPDMA1RST              RCC_AHB1RSTR_GPDMA1RST_Msk
8768 #define RCC_AHB1RSTR_GPDMA2RST_Pos          (1U)
8769 #define RCC_AHB1RSTR_GPDMA2RST_Msk          (0x1UL << RCC_AHB1RSTR_GPDMA2RST_Pos)   /*!< 0x00000002 */
8770 #define RCC_AHB1RSTR_GPDMA2RST              RCC_AHB1RSTR_GPDMA2RST_Msk
8771 #define RCC_AHB1RSTR_CRCRST_Pos             (12U)
8772 #define RCC_AHB1RSTR_CRCRST_Msk             (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)      /*!< 0x00001000 */
8773 #define RCC_AHB1RSTR_CRCRST                 RCC_AHB1RSTR_CRCRST_Msk
8774 #define RCC_AHB1RSTR_RAMCFGRST_Pos          (17U)
8775 #define RCC_AHB1RSTR_RAMCFGRST_Msk          (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos)   /*!< 0x00020000 */
8776 #define RCC_AHB1RSTR_RAMCFGRST              RCC_AHB1RSTR_RAMCFGRST_Msk
8777 #define RCC_AHB1RSTR_TZSC1RST_Pos           (24U)
8778 #define RCC_AHB1RSTR_TZSC1RST_Msk           (0x1UL << RCC_AHB1RSTR_TZSC1RST_Pos)    /*!< 0x01000000 */
8779 #define RCC_AHB1RSTR_TZSC1RST               RCC_AHB1RSTR_TZSC1RST_Msk
8780 
8781 /********************  Bit definition for RCC_AHB2RSTR register  **************/
8782 #define RCC_AHB2RSTR_GPIOARST_Pos           (0U)
8783 #define RCC_AHB2RSTR_GPIOARST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)    /*!< 0x00000001 */
8784 #define RCC_AHB2RSTR_GPIOARST               RCC_AHB2RSTR_GPIOARST_Msk
8785 #define RCC_AHB2RSTR_GPIOBRST_Pos           (1U)
8786 #define RCC_AHB2RSTR_GPIOBRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)    /*!< 0x00000002 */
8787 #define RCC_AHB2RSTR_GPIOBRST               RCC_AHB2RSTR_GPIOBRST_Msk
8788 #define RCC_AHB2RSTR_GPIOCRST_Pos           (2U)
8789 #define RCC_AHB2RSTR_GPIOCRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)    /*!< 0x00000004 */
8790 #define RCC_AHB2RSTR_GPIOCRST               RCC_AHB2RSTR_GPIOCRST_Msk
8791 #define RCC_AHB2RSTR_GPIODRST_Pos           (3U)
8792 #define RCC_AHB2RSTR_GPIODRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)    /*!< 0x00000008 */
8793 #define RCC_AHB2RSTR_GPIODRST               RCC_AHB2RSTR_GPIODRST_Msk
8794 #define RCC_AHB2RSTR_GPIOHRST_Pos           (7U)
8795 #define RCC_AHB2RSTR_GPIOHRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)    /*!< 0x00000080 */
8796 #define RCC_AHB2RSTR_GPIOHRST               RCC_AHB2RSTR_GPIOHRST_Msk
8797 #define RCC_AHB2RSTR_ADCRST_Pos             (10U)
8798 #define RCC_AHB2RSTR_ADCRST_Msk             (0x1UL << RCC_AHB2RSTR_ADCRST_Pos)      /*!< 0x00000400 */
8799 #define RCC_AHB2RSTR_ADCRST                 RCC_AHB2RSTR_ADCRST_Msk
8800 #define RCC_AHB2RSTR_DAC1RST_Pos            (11U)
8801 #define RCC_AHB2RSTR_DAC1RST_Msk            (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)     /*!< 0x00000800 */
8802 #define RCC_AHB2RSTR_DAC1RST                RCC_AHB2RSTR_DAC1RST_Msk
8803 #define RCC_AHB2RSTR_HASHRST_Pos            (17U)
8804 #define RCC_AHB2RSTR_HASHRST_Msk            (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)     /*!< 0x00020000 */
8805 #define RCC_AHB2RSTR_HASHRST                RCC_AHB2RSTR_HASHRST_Msk
8806 #define RCC_AHB2RSTR_RNGRST_Pos             (18U)
8807 #define RCC_AHB2RSTR_RNGRST_Msk             (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)      /*!< 0x00040000 */
8808 #define RCC_AHB2RSTR_RNGRST                 RCC_AHB2RSTR_RNGRST_Msk
8809 #define RCC_AHB2RSTR_PKARST_Pos             (19U)
8810 #define RCC_AHB2RSTR_PKARST_Msk             (0x1UL << RCC_AHB2RSTR_PKARST_Pos)      /*!< 0x00080000 */
8811 #define RCC_AHB2RSTR_PKARST                 RCC_AHB2RSTR_PKARST_Msk
8812 
8813 /********************  Bit definition for RCC_APB1LRSTR register  **************/
8814 #define RCC_APB1LRSTR_TIM2RST_Pos           (0U)
8815 #define RCC_APB1LRSTR_TIM2RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)    /*!< 0x00000001 */
8816 #define RCC_APB1LRSTR_TIM2RST               RCC_APB1LRSTR_TIM2RST_Msk
8817 #define RCC_APB1LRSTR_TIM3RST_Pos           (1U)
8818 #define RCC_APB1LRSTR_TIM3RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)    /*!< 0x00000002 */
8819 #define RCC_APB1LRSTR_TIM3RST               RCC_APB1LRSTR_TIM3RST_Msk
8820 #define RCC_APB1LRSTR_TIM6RST_Pos           (4U)
8821 #define RCC_APB1LRSTR_TIM6RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)    /*!< 0x00000010 */
8822 #define RCC_APB1LRSTR_TIM6RST               RCC_APB1LRSTR_TIM6RST_Msk
8823 #define RCC_APB1LRSTR_TIM7RST_Pos           (5U)
8824 #define RCC_APB1LRSTR_TIM7RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)    /*!< 0x00000020 */
8825 #define RCC_APB1LRSTR_TIM7RST               RCC_APB1LRSTR_TIM7RST_Msk
8826 #define RCC_APB1LRSTR_OPAMPRST_Pos          (13U)
8827 #define RCC_APB1LRSTR_OPAMPRST_Msk          (0x1UL << RCC_APB1LRSTR_OPAMPRST_Pos)  /*!< 0x00002000 */
8828 #define RCC_APB1LRSTR_OPAMPRST              RCC_APB1LRSTR_OPAMPRST_Msk
8829 #define RCC_APB1LRSTR_SPI2RST_Pos           (14U)
8830 #define RCC_APB1LRSTR_SPI2RST_Msk           (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)    /*!< 0x00004000 */
8831 #define RCC_APB1LRSTR_SPI2RST               RCC_APB1LRSTR_SPI2RST_Msk
8832 #define RCC_APB1LRSTR_SPI3RST_Pos           (15U)
8833 #define RCC_APB1LRSTR_SPI3RST_Msk           (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)    /*!< 0x00008000 */
8834 #define RCC_APB1LRSTR_SPI3RST               RCC_APB1LRSTR_SPI3RST_Msk
8835 #define RCC_APB1LRSTR_COMPRST_Pos           (16U)
8836 #define RCC_APB1LRSTR_COMPRST_Msk           (0x1UL << RCC_APB1LRSTR_COMPRST_Pos)    /*!< 0x00010000 */
8837 #define RCC_APB1LRSTR_COMPRST               RCC_APB1LRSTR_COMPRST_Msk
8838 #define RCC_APB1LRSTR_USART2RST_Pos         (17U)
8839 #define RCC_APB1LRSTR_USART2RST_Msk         (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)  /*!< 0x00020000 */
8840 #define RCC_APB1LRSTR_USART2RST             RCC_APB1LRSTR_USART2RST_Msk
8841 #define RCC_APB1LRSTR_USART3RST_Pos         (18U)
8842 #define RCC_APB1LRSTR_USART3RST_Msk         (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)  /*!< 0x00040000 */
8843 #define RCC_APB1LRSTR_USART3RST             RCC_APB1LRSTR_USART3RST_Msk
8844 #define RCC_APB1LRSTR_I2C1RST_Pos           (21U)
8845 #define RCC_APB1LRSTR_I2C1RST_Msk           (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)    /*!< 0x00200000 */
8846 #define RCC_APB1LRSTR_I2C1RST               RCC_APB1LRSTR_I2C1RST_Msk
8847 #define RCC_APB1LRSTR_I2C2RST_Pos           (22U)
8848 #define RCC_APB1LRSTR_I2C2RST_Msk           (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)    /*!< 0x00400000 */
8849 #define RCC_APB1LRSTR_I2C2RST               RCC_APB1LRSTR_I2C2RST_Msk
8850 #define RCC_APB1LRSTR_I3C1RST_Pos           (23U)
8851 #define RCC_APB1LRSTR_I3C1RST_Msk           (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos)    /*!< 0x00800000 */
8852 #define RCC_APB1LRSTR_I3C1RST               RCC_APB1LRSTR_I3C1RST_Msk
8853 #define RCC_APB1LRSTR_CRSRST_Pos            (24U)
8854 #define RCC_APB1LRSTR_CRSRST_Msk            (0x1UL << RCC_APB1LRSTR_CRSRST_Pos)     /*!< 0x01000000 */
8855 #define RCC_APB1LRSTR_CRSRST                RCC_APB1LRSTR_CRSRST_Msk
8856 
8857 /********************  Bit definition for RCC_APB1HRSTR register  **************/
8858 #define RCC_APB1HRSTR_DTSRST_Pos            (3U)
8859 #define RCC_APB1HRSTR_DTSRST_Msk            (0x1UL << RCC_APB1HRSTR_DTSRST_Pos)     /*!< 0x00000008 */
8860 #define RCC_APB1HRSTR_DTSRST                RCC_APB1HRSTR_DTSRST_Msk
8861 #define RCC_APB1HRSTR_LPTIM2RST_Pos         (5U)
8862 #define RCC_APB1HRSTR_LPTIM2RST_Msk         (0x1UL << RCC_APB1HRSTR_LPTIM2RST_Pos)  /*!< 0x00000020 */
8863 #define RCC_APB1HRSTR_LPTIM2RST             RCC_APB1HRSTR_LPTIM2RST_Msk
8864 #define RCC_APB1HRSTR_FDCANRST_Pos          (9U)
8865 #define RCC_APB1HRSTR_FDCANRST_Msk          (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)   /*!< 0x00000200 */
8866 #define RCC_APB1HRSTR_FDCANRST              RCC_APB1HRSTR_FDCANRST_Msk
8867 
8868 /********************  Bit definition for RCC_APB2RSTR register  **************/
8869 #define RCC_APB2RSTR_TIM1RST_Pos            (11U)
8870 #define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)     /*!< 0x00000800 */
8871 #define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk
8872 #define RCC_APB2RSTR_SPI1RST_Pos            (12U)
8873 #define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)     /*!< 0x00001000 */
8874 #define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk
8875 #define RCC_APB2RSTR_USART1RST_Pos          (14U)
8876 #define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos)   /*!< 0x00004000 */
8877 #define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk
8878 #define RCC_APB2RSTR_USBRST_Pos             (24U)
8879 #define RCC_APB2RSTR_USBRST_Msk             (0x1UL << RCC_APB2RSTR_USBRST_Pos)      /*!< 0x01000000 */
8880 #define RCC_APB2RSTR_USBRST                 RCC_APB2RSTR_USBRST_Msk
8881 
8882 /********************  Bit definition for RCC_APB3RSTR register  **************/
8883 #define RCC_APB3RSTR_LPUART1RST_Pos         (6U)
8884 #define RCC_APB3RSTR_LPUART1RST_Msk         (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos)  /*!< 0x00000040 */
8885 #define RCC_APB3RSTR_LPUART1RST             RCC_APB3RSTR_LPUART1RST_Msk
8886 #define RCC_APB3RSTR_I3C2RST_Pos            (9U)
8887 #define RCC_APB3RSTR_I3C2RST_Msk            (0x1UL << RCC_APB3RSTR_I3C2RST_Pos)     /*!< 0x00000200 */
8888 #define RCC_APB3RSTR_I3C2RST                RCC_APB3RSTR_I3C2RST_Msk
8889 #define RCC_APB3RSTR_LPTIM1RST_Pos          (11U)
8890 #define RCC_APB3RSTR_LPTIM1RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos)   /*!< 0x00000800 */
8891 #define RCC_APB3RSTR_LPTIM1RST              RCC_APB3RSTR_LPTIM1RST_Msk
8892 
8893 /********************  Bit definition for RCC_AHB1ENR register  **************/
8894 #define RCC_AHB1ENR_GPDMA1EN_Pos            (0U)
8895 #define RCC_AHB1ENR_GPDMA1EN_Msk            (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)     /*!< 0x00000001 */
8896 #define RCC_AHB1ENR_GPDMA1EN                RCC_AHB1ENR_GPDMA1EN_Msk
8897 #define RCC_AHB1ENR_GPDMA2EN_Pos            (1U)
8898 #define RCC_AHB1ENR_GPDMA2EN_Msk            (0x1UL << RCC_AHB1ENR_GPDMA2EN_Pos)     /*!< 0x00000002 */
8899 #define RCC_AHB1ENR_GPDMA2EN                RCC_AHB1ENR_GPDMA2EN_Msk
8900 #define RCC_AHB1ENR_FLITFEN_Pos             (8U)
8901 #define RCC_AHB1ENR_FLITFEN_Msk             (0x1UL << RCC_AHB1ENR_FLITFEN_Pos)      /*!< 0x00000100 */
8902 #define RCC_AHB1ENR_FLITFEN                 RCC_AHB1ENR_FLITFEN_Msk
8903 #define RCC_AHB1ENR_CRCEN_Pos               (12U)
8904 #define RCC_AHB1ENR_CRCEN_Msk               (0x1UL << RCC_AHB1ENR_CRCEN_Pos)        /*!< 0x00001000 */
8905 #define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk
8906 #define RCC_AHB1ENR_RAMCFGEN_Pos            (17U)
8907 #define RCC_AHB1ENR_RAMCFGEN_Msk            (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos)     /*!< 0x00020000 */
8908 #define RCC_AHB1ENR_RAMCFGEN                RCC_AHB1ENR_RAMCFGEN_Msk
8909 #define RCC_AHB1ENR_TZSC1EN_Pos             (24U)
8910 #define RCC_AHB1ENR_TZSC1EN_Msk             (0x1UL << RCC_AHB1ENR_TZSC1EN_Pos)      /*!< 0x01000000 */
8911 #define RCC_AHB1ENR_TZSC1EN                 RCC_AHB1ENR_TZSC1EN_Msk
8912 #define RCC_AHB1ENR_BKPRAMEN_Pos            (28U)
8913 #define RCC_AHB1ENR_BKPRAMEN_Msk            (0x1UL << RCC_AHB1ENR_BKPRAMEN_Pos)     /*!< 0x10000000 */
8914 #define RCC_AHB1ENR_BKPRAMEN                RCC_AHB1ENR_BKPRAMEN_Msk
8915 #define RCC_AHB1ENR_SRAM1EN_Pos             (31U)
8916 #define RCC_AHB1ENR_SRAM1EN_Msk             (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos)      /*!< 0x80000000 */
8917 #define RCC_AHB1ENR_SRAM1EN                 RCC_AHB1ENR_SRAM1EN_Msk
8918 
8919 /********************  Bit definition for RCC_AHB2ENR register  **************/
8920 #define RCC_AHB2ENR_GPIOAEN_Pos             (0U)
8921 #define RCC_AHB2ENR_GPIOAEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)      /*!< 0x00000001 */
8922 #define RCC_AHB2ENR_GPIOAEN                 RCC_AHB2ENR_GPIOAEN_Msk
8923 #define RCC_AHB2ENR_GPIOBEN_Pos             (1U)
8924 #define RCC_AHB2ENR_GPIOBEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)      /*!< 0x00000002 */
8925 #define RCC_AHB2ENR_GPIOBEN                 RCC_AHB2ENR_GPIOBEN_Msk
8926 #define RCC_AHB2ENR_GPIOCEN_Pos             (2U)
8927 #define RCC_AHB2ENR_GPIOCEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)      /*!< 0x00000004 */
8928 #define RCC_AHB2ENR_GPIOCEN                 RCC_AHB2ENR_GPIOCEN_Msk
8929 #define RCC_AHB2ENR_GPIODEN_Pos             (3U)
8930 #define RCC_AHB2ENR_GPIODEN_Msk             (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)      /*!< 0x00000008 */
8931 #define RCC_AHB2ENR_GPIODEN                 RCC_AHB2ENR_GPIODEN_Msk
8932 #define RCC_AHB2ENR_GPIOHEN_Pos             (7U)
8933 #define RCC_AHB2ENR_GPIOHEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)      /*!< 0x00000080 */
8934 #define RCC_AHB2ENR_GPIOHEN                 RCC_AHB2ENR_GPIOHEN_Msk
8935 #define RCC_AHB2ENR_ADCEN_Pos               (10U)
8936 #define RCC_AHB2ENR_ADCEN_Msk               (0x1UL << RCC_AHB2ENR_ADCEN_Pos)        /*!< 0x00000400 */
8937 #define RCC_AHB2ENR_ADCEN                   RCC_AHB2ENR_ADCEN_Msk
8938 #define RCC_AHB2ENR_DAC1EN_Pos              (11U)
8939 #define RCC_AHB2ENR_DAC1EN_Msk              (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)       /*!< 0x00000800 */
8940 #define RCC_AHB2ENR_DAC1EN                  RCC_AHB2ENR_DAC1EN_Msk
8941 #define RCC_AHB2ENR_HASHEN_Pos              (17U)
8942 #define RCC_AHB2ENR_HASHEN_Msk              (0x1UL << RCC_AHB2ENR_HASHEN_Pos)       /*!< 0x00020000 */
8943 #define RCC_AHB2ENR_HASHEN                  RCC_AHB2ENR_HASHEN_Msk
8944 #define RCC_AHB2ENR_RNGEN_Pos               (18U)
8945 #define RCC_AHB2ENR_RNGEN_Msk               (0x1UL << RCC_AHB2ENR_RNGEN_Pos)        /*!< 0x00040000 */
8946 #define RCC_AHB2ENR_RNGEN                   RCC_AHB2ENR_RNGEN_Msk
8947 #define RCC_AHB2ENR_PKAEN_Pos               (19U)
8948 #define RCC_AHB2ENR_PKAEN_Msk               (0x1UL << RCC_AHB2ENR_PKAEN_Pos)        /*!< 0x00080000 */
8949 #define RCC_AHB2ENR_PKAEN                   RCC_AHB2ENR_PKAEN_Msk
8950 #define RCC_AHB2ENR_SRAM2EN_Pos             (30U)
8951 #define RCC_AHB2ENR_SRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)      /*!< 0x40000000 */
8952 #define RCC_AHB2ENR_SRAM2EN                 RCC_AHB2ENR_SRAM2EN_Msk
8953 
8954 /********************  Bit definition for RCC_APB1LENR register  **************/
8955 #define RCC_APB1LENR_TIM2EN_Pos             (0U)
8956 #define RCC_APB1LENR_TIM2EN_Msk             (0x1UL << RCC_APB1LENR_TIM2EN_Pos)      /*!< 0x00000001 */
8957 #define RCC_APB1LENR_TIM2EN                 RCC_APB1LENR_TIM2EN_Msk
8958 #define RCC_APB1LENR_TIM3EN_Pos             (1U)
8959 #define RCC_APB1LENR_TIM3EN_Msk             (0x1UL << RCC_APB1LENR_TIM3EN_Pos)      /*!< 0x00000002 */
8960 #define RCC_APB1LENR_TIM3EN                 RCC_APB1LENR_TIM3EN_Msk
8961 #define RCC_APB1LENR_TIM6EN_Pos             (4U)
8962 #define RCC_APB1LENR_TIM6EN_Msk             (0x1UL << RCC_APB1LENR_TIM6EN_Pos)      /*!< 0x00000010 */
8963 #define RCC_APB1LENR_TIM6EN                 RCC_APB1LENR_TIM6EN_Msk
8964 #define RCC_APB1LENR_TIM7EN_Pos             (5U)
8965 #define RCC_APB1LENR_TIM7EN_Msk             (0x1UL << RCC_APB1LENR_TIM7EN_Pos)      /*!< 0x00000020 */
8966 #define RCC_APB1LENR_TIM7EN                 RCC_APB1LENR_TIM7EN_Msk
8967 #define RCC_APB1LENR_WWDGEN_Pos             (11U)
8968 #define RCC_APB1LENR_WWDGEN_Msk             (0x1UL << RCC_APB1LENR_WWDGEN_Pos)      /*!< 0x00000800 */
8969 #define RCC_APB1LENR_WWDGEN                 RCC_APB1LENR_WWDGEN_Msk
8970 #define RCC_APB1LENR_OPAMPEN_Pos            (13U)
8971 #define RCC_APB1LENR_OPAMPEN_Msk            (0x1UL << RCC_APB1LENR_OPAMPEN_Pos)     /*!< 0x00002000 */
8972 #define RCC_APB1LENR_OPAMPEN                 RCC_APB1LENR_OPAMPEN_Msk
8973 #define RCC_APB1LENR_SPI2EN_Pos             (14U)
8974 #define RCC_APB1LENR_SPI2EN_Msk             (0x1UL << RCC_APB1LENR_SPI2EN_Pos)      /*!< 0x00004000 */
8975 #define RCC_APB1LENR_SPI2EN                 RCC_APB1LENR_SPI2EN_Msk
8976 #define RCC_APB1LENR_SPI3EN_Pos             (15U)
8977 #define RCC_APB1LENR_SPI3EN_Msk             (0x1UL << RCC_APB1LENR_SPI3EN_Pos)      /*!< 0x00008000 */
8978 #define RCC_APB1LENR_SPI3EN                 RCC_APB1LENR_SPI3EN_Msk
8979 #define RCC_APB1LENR_COMPEN_Pos             (16U)
8980 #define RCC_APB1LENR_COMPEN_Msk             (0x1UL << RCC_APB1LENR_COMPEN_Pos)      /*!< 0x00010000 */
8981 #define RCC_APB1LENR_COMPEN                 RCC_APB1LENR_COMPEN_Msk
8982 #define RCC_APB1LENR_USART2EN_Pos           (17U)
8983 #define RCC_APB1LENR_USART2EN_Msk           (0x1UL << RCC_APB1LENR_USART2EN_Pos)    /*!< 0x00020000 */
8984 #define RCC_APB1LENR_USART2EN               RCC_APB1LENR_USART2EN_Msk
8985 #define RCC_APB1LENR_USART3EN_Pos           (18U)
8986 #define RCC_APB1LENR_USART3EN_Msk           (0x1UL << RCC_APB1LENR_USART3EN_Pos)    /*!< 0x00040000 */
8987 #define RCC_APB1LENR_USART3EN               RCC_APB1LENR_USART3EN_Msk
8988 #define RCC_APB1LENR_I2C1EN_Pos             (21U)
8989 #define RCC_APB1LENR_I2C1EN_Msk             (0x1UL << RCC_APB1LENR_I2C1EN_Pos)      /*!< 0x00200000 */
8990 #define RCC_APB1LENR_I2C1EN                 RCC_APB1LENR_I2C1EN_Msk
8991 #define RCC_APB1LENR_I2C2EN_Pos             (22U)
8992 #define RCC_APB1LENR_I2C2EN_Msk             (0x1UL << RCC_APB1LENR_I2C2EN_Pos)      /*!< 0x00400000 */
8993 #define RCC_APB1LENR_I2C2EN                 RCC_APB1LENR_I2C2EN_Msk
8994 #define RCC_APB1LENR_I3C1EN_Pos             (23U)
8995 #define RCC_APB1LENR_I3C1EN_Msk             (0x1UL << RCC_APB1LENR_I3C1EN_Pos)      /*!< 0x00800000 */
8996 #define RCC_APB1LENR_I3C1EN                 RCC_APB1LENR_I3C1EN_Msk
8997 #define RCC_APB1LENR_CRSEN_Pos              (24U)
8998 #define RCC_APB1LENR_CRSEN_Msk              (0x1UL << RCC_APB1LENR_CRSEN_Pos)       /*!< 0x01000000 */
8999 #define RCC_APB1LENR_CRSEN                   RCC_APB1LENR_CRSEN_Msk
9000 
9001 /********************  Bit definition for RCC_APB1HENR register  **************/
9002 #define RCC_APB1HENR_DTSEN_Pos              (3U)
9003 #define RCC_APB1HENR_DTSEN_Msk              (0x1UL << RCC_APB1HENR_DTSEN_Pos)       /*!< 0x00000008 */
9004 #define RCC_APB1HENR_DTSEN                  RCC_APB1HENR_DTSEN_Msk
9005 #define RCC_APB1HENR_LPTIM2EN_Pos           (5U)
9006 #define RCC_APB1HENR_LPTIM2EN_Msk           (0x1UL << RCC_APB1HENR_LPTIM2EN_Pos)    /*!< 0x00000020 */
9007 #define RCC_APB1HENR_LPTIM2EN               RCC_APB1HENR_LPTIM2EN_Msk
9008 #define RCC_APB1HENR_FDCANEN_Pos            (9U)
9009 #define RCC_APB1HENR_FDCANEN_Msk            (0x1UL << RCC_APB1HENR_FDCANEN_Pos)     /*!< 0x00000200 */
9010 #define RCC_APB1HENR_FDCANEN                 RCC_APB1HENR_FDCANEN_Msk
9011 
9012 /********************  Bit definition for RCC_APB2ENR register  **************/
9013 #define RCC_APB2ENR_TIM1EN_Pos              (11U)
9014 #define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)       /*!< 0x00000800 */
9015 #define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk
9016 #define RCC_APB2ENR_SPI1EN_Pos              (12U)
9017 #define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)       /*!< 0x00001000 */
9018 #define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk
9019 #define RCC_APB2ENR_USART1EN_Pos            (14U)
9020 #define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos)     /*!< 0x00004000 */
9021 #define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk
9022 #define RCC_APB2ENR_USBEN_Pos               (24U)
9023 #define RCC_APB2ENR_USBEN_Msk               (0x1UL << RCC_APB2ENR_USBEN_Pos)        /*!< 0x01000000 */
9024 #define RCC_APB2ENR_USBEN                   RCC_APB2ENR_USBEN_Msk
9025 
9026 /********************  Bit definition for RCC_APB3ENR register  **************/
9027 #define RCC_APB3ENR_SBSEN_Pos               (1U)
9028 #define RCC_APB3ENR_SBSEN_Msk               (0x1UL << RCC_APB3ENR_SBSEN_Pos)        /*!< 0x00000002 */
9029 #define RCC_APB3ENR_SBSEN                   RCC_APB3ENR_SBSEN_Msk
9030 #define RCC_APB3ENR_LPUART1EN_Pos           (6U)
9031 #define RCC_APB3ENR_LPUART1EN_Msk           (0x1UL << RCC_APB3ENR_LPUART1EN_Pos)    /*!< 0x00000040 */
9032 #define RCC_APB3ENR_LPUART1EN               RCC_APB3ENR_LPUART1EN_Msk
9033 #define RCC_APB3ENR_I3C2EN_Pos              (9U)
9034 #define RCC_APB3ENR_I3C2EN_Msk              (0x1UL << RCC_APB3ENR_I3C2EN_Pos)       /*!< 0x00000200 */
9035 #define RCC_APB3ENR_I3C2EN                  RCC_APB3ENR_I3C2EN_Msk
9036 #define RCC_APB3ENR_LPTIM1EN_Pos            (11U)
9037 #define RCC_APB3ENR_LPTIM1EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos)     /*!< 0x00000800 */
9038 #define RCC_APB3ENR_LPTIM1EN                RCC_APB3ENR_LPTIM1EN_Msk
9039 #define RCC_APB3ENR_RTCAPBEN_Pos            (21U)
9040 #define RCC_APB3ENR_RTCAPBEN_Msk            (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos)     /*!< 0x00200000 */
9041 #define RCC_APB3ENR_RTCAPBEN                RCC_APB3ENR_RTCAPBEN_Msk
9042 
9043 /********************  Bit definition for RCC_AHB1LPENR register  **************/
9044 #define RCC_AHB1LPENR_GPDMA1LPEN_Pos        (0U)
9045 #define RCC_AHB1LPENR_GPDMA1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000000*/
9046 #define RCC_AHB1LPENR_GPDMA1LPEN            RCC_AHB1LPENR_GPDMA1LPEN_Msk
9047 #define RCC_AHB1LPENR_GPDMA2LPEN_Pos        (1U)
9048 #define RCC_AHB1LPENR_GPDMA2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPDMA2LPEN_Pos) /*!< 0x00000000*/
9049 #define RCC_AHB1LPENR_GPDMA2LPEN            RCC_AHB1LPENR_GPDMA2LPEN_Msk
9050 #define RCC_AHB1LPENR_FLITFLPEN_Pos         (8U)
9051 #define RCC_AHB1LPENR_FLITFLPEN_Msk         (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)   /*!< 0x00000100*/
9052 #define RCC_AHB1LPENR_FLITFLPEN             RCC_AHB1LPENR_FLITFLPEN_Msk
9053 #define RCC_AHB1LPENR_CRCLPEN_Pos           (12U)
9054 #define RCC_AHB1LPENR_CRCLPEN_Msk           (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)    /*!< 0x00001000 */
9055 #define RCC_AHB1LPENR_CRCLPEN               RCC_AHB1LPENR_CRCLPEN_Msk
9056 #define RCC_AHB1LPENR_RAMCFGLPEN_Pos        (17U)
9057 #define RCC_AHB1LPENR_RAMCFGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */
9058 #define RCC_AHB1LPENR_RAMCFGLPEN            RCC_AHB1LPENR_RAMCFGLPEN_Msk
9059 #define RCC_AHB1LPENR_TZSC1LPEN_Pos         (24U)
9060 #define RCC_AHB1LPENR_TZSC1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_TZSC1LPEN_Pos)  /*!< 0x01000000 */
9061 #define RCC_AHB1LPENR_TZSC1LPEN             RCC_AHB1LPENR_TZSC1LPEN_Msk
9062 #define RCC_AHB1LPENR_BKPRAMLPEN_Pos        (28U)
9063 #define RCC_AHB1LPENR_BKPRAMLPEN_Msk        (0x1UL << RCC_AHB1LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
9064 #define RCC_AHB1LPENR_BKPRAMLPEN            RCC_AHB1LPENR_BKPRAMLPEN_Msk
9065 #define RCC_AHB1LPENR_ICACHELPEN_Pos        (29U)
9066 #define RCC_AHB1LPENR_ICACHELPEN_Msk        (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x20000000 */
9067 #define RCC_AHB1LPENR_ICACHELPEN            RCC_AHB1LPENR_ICACHELPEN_Msk
9068 #define RCC_AHB1LPENR_SRAM1LPEN_Pos         (31U)
9069 #define RCC_AHB1LPENR_SRAM1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)  /*!< 0x80000000 */
9070 #define RCC_AHB1LPENR_SRAM1LPEN             RCC_AHB1LPENR_SRAM1LPEN_Msk
9071 
9072 /********************  Bit definition for RCC_AHB2LPENR register  **************/
9073 #define RCC_AHB2LPENR_GPIOALPEN_Pos         (0U)
9074 #define RCC_AHB2LPENR_GPIOALPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos)  /*!< 0x00000001 */
9075 #define RCC_AHB2LPENR_GPIOALPEN             RCC_AHB2LPENR_GPIOALPEN_Msk
9076 #define RCC_AHB2LPENR_GPIOBLPEN_Pos         (1U)
9077 #define RCC_AHB2LPENR_GPIOBLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos)  /*!< 0x00000002 */
9078 #define RCC_AHB2LPENR_GPIOBLPEN             RCC_AHB2LPENR_GPIOBLPEN_Msk
9079 #define RCC_AHB2LPENR_GPIOCLPEN_Pos         (2U)
9080 #define RCC_AHB2LPENR_GPIOCLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos)  /*!< 0x00000004 */
9081 #define RCC_AHB2LPENR_GPIOCLPEN             RCC_AHB2LPENR_GPIOCLPEN_Msk
9082 #define RCC_AHB2LPENR_GPIODLPEN_Pos         (3U)
9083 #define RCC_AHB2LPENR_GPIODLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos)  /*!< 0x00000008 */
9084 #define RCC_AHB2LPENR_GPIODLPEN             RCC_AHB2LPENR_GPIODLPEN_Msk
9085 #define RCC_AHB2LPENR_GPIOHLPEN_Pos         (7U)
9086 #define RCC_AHB2LPENR_GPIOHLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos)  /*!< 0x00000080 */
9087 #define RCC_AHB2LPENR_GPIOHLPEN             RCC_AHB2LPENR_GPIOHLPEN_Msk
9088 #define RCC_AHB2LPENR_ADCLPEN_Pos           (10U)
9089 #define RCC_AHB2LPENR_ADCLPEN_Msk           (0x1UL << RCC_AHB2LPENR_ADCLPEN_Pos)    /*!< 0x00000400 */
9090 #define RCC_AHB2LPENR_ADCLPEN               RCC_AHB2LPENR_ADCLPEN_Msk
9091 #define RCC_AHB2LPENR_DAC1LPEN_Pos          (11U)
9092 #define RCC_AHB2LPENR_DAC1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos)   /*!< 0x00000800 */
9093 #define RCC_AHB2LPENR_DAC1LPEN              RCC_AHB2LPENR_DAC1LPEN_Msk
9094 #define RCC_AHB2LPENR_HASHLPEN_Pos          (17U)
9095 #define RCC_AHB2LPENR_HASHLPEN_Msk          (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)   /*!< 0x00020000 */
9096 #define RCC_AHB2LPENR_HASHLPEN              RCC_AHB2LPENR_HASHLPEN_Msk
9097 #define RCC_AHB2LPENR_RNGLPEN_Pos           (18U)
9098 #define RCC_AHB2LPENR_RNGLPEN_Msk           (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)    /*!< 0x00040000 */
9099 #define RCC_AHB2LPENR_RNGLPEN               RCC_AHB2LPENR_RNGLPEN_Msk
9100 #define RCC_AHB2LPENR_SRAM2LPEN_Pos         (30U)
9101 #define RCC_AHB2LPENR_SRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)  /*!< 0x40000000 */
9102 #define RCC_AHB2LPENR_SRAM2LPEN             RCC_AHB2LPENR_SRAM2LPEN_Msk
9103 
9104 /********************  Bit definition for RCC_APB1LLPENR register  **************/
9105 #define RCC_APB1LLPENR_TIM2LPEN_Pos         (0U)
9106 #define RCC_APB1LLPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)  /*!< 0x00000001 */
9107 #define RCC_APB1LLPENR_TIM2LPEN             RCC_APB1LLPENR_TIM2LPEN_Msk
9108 #define RCC_APB1LLPENR_TIM3LPEN_Pos         (1U)
9109 #define RCC_APB1LLPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)  /*!< 0x00000002 */
9110 #define RCC_APB1LLPENR_TIM3LPEN             RCC_APB1LLPENR_TIM3LPEN_Msk
9111 #define RCC_APB1LLPENR_TIM6LPEN_Pos         (4U)
9112 #define RCC_APB1LLPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)  /*!< 0x00000010 */
9113 #define RCC_APB1LLPENR_TIM6LPEN             RCC_APB1LLPENR_TIM6LPEN_Msk
9114 #define RCC_APB1LLPENR_TIM7LPEN_Pos         (5U)
9115 #define RCC_APB1LLPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)  /*!< 0x00000020 */
9116 #define RCC_APB1LLPENR_TIM7LPEN             RCC_APB1LLPENR_TIM7LPEN_Msk
9117 #define RCC_APB1LLPENR_WWDGLPEN_Pos         (11U)
9118 #define RCC_APB1LLPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos)  /*!< 0x00000800 */
9119 #define RCC_APB1LLPENR_WWDGLPEN             RCC_APB1LLPENR_WWDGLPEN_Msk
9120 #define RCC_APB1LLPENR_OPAMPLPEN_Pos        (13U)
9121 #define RCC_APB1LLPENR_OPAMPLPEN_Msk        (0x1UL << RCC_APB1LLPENR_OPAMPLPEN_Pos) /*!< 0x00002000 */
9122 #define RCC_APB1LLPENR_OPAMPLPEN            RCC_APB1LLPENR_OPAMPLPEN_Msk
9123 #define RCC_APB1LLPENR_SPI2LPEN_Pos         (14U)
9124 #define RCC_APB1LLPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)  /*!< 0x00004000 */
9125 #define RCC_APB1LLPENR_SPI2LPEN             RCC_APB1LLPENR_SPI2LPEN_Msk
9126 #define RCC_APB1LLPENR_SPI3LPEN_Pos         (15U)
9127 #define RCC_APB1LLPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)  /*!< 0x00008000 */
9128 #define RCC_APB1LLPENR_SPI3LPEN             RCC_APB1LLPENR_SPI3LPEN_Msk
9129 #define RCC_APB1LLPENR_COMPLPEN_Pos         (16U)
9130 #define RCC_APB1LLPENR_COMPLPEN_Msk         (0x1UL << RCC_APB1LLPENR_COMPLPEN_Pos)  /*!< 0x00010000 */
9131 #define RCC_APB1LLPENR_COMPLPEN             RCC_APB1LLPENR_COMPLPEN_Msk
9132 #define RCC_APB1LLPENR_USART2LPEN_Pos       (17U)
9133 #define RCC_APB1LLPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
9134 #define RCC_APB1LLPENR_USART2LPEN           RCC_APB1LLPENR_USART2LPEN_Msk
9135 #define RCC_APB1LLPENR_USART3LPEN_Pos       (18U)
9136 #define RCC_APB1LLPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
9137 #define RCC_APB1LLPENR_USART3LPEN           RCC_APB1LLPENR_USART3LPEN_Msk
9138 #define RCC_APB1LLPENR_I2C1LPEN_Pos         (21U)
9139 #define RCC_APB1LLPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)  /*!< 0x00200000 */
9140 #define RCC_APB1LLPENR_I2C1LPEN             RCC_APB1LLPENR_I2C1LPEN_Msk
9141 #define RCC_APB1LLPENR_I2C2LPEN_Pos         (22U)
9142 #define RCC_APB1LLPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)  /*!< 0x00400000 */
9143 #define RCC_APB1LLPENR_I2C2LPEN             RCC_APB1LLPENR_I2C2LPEN_Msk
9144 #define RCC_APB1LLPENR_I3C1LPEN_Pos         (23U)
9145 #define RCC_APB1LLPENR_I3C1LPEN_Msk         (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos)  /*!< 0x00800000 */
9146 #define RCC_APB1LLPENR_I3C1LPEN             RCC_APB1LLPENR_I3C1LPEN_Msk
9147 #define RCC_APB1LLPENR_CRSLPEN_Pos          (24U)
9148 #define RCC_APB1LLPENR_CRSLPEN_Msk          (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos)   /*!< 0x01000000 */
9149 #define RCC_APB1LLPENR_CRSLPEN              RCC_APB1LLPENR_CRSLPEN_Msk
9150 
9151 /********************  Bit definition for RCC_APB1HLPENR register  **************/
9152 #define RCC_APB1HLPENR_DTSLPEN_Pos          (3U)
9153 #define RCC_APB1HLPENR_DTSLPEN_Msk          (0x1UL << RCC_APB1HLPENR_DTSLPEN_Pos)    /*!< 0x00000008 */
9154 #define RCC_APB1HLPENR_DTSLPEN              RCC_APB1HLPENR_DTSLPEN_Msk
9155 #define RCC_APB1HLPENR_LPTIM2LPEN_Pos       (5U)
9156 #define RCC_APB1HLPENR_LPTIM2LPEN_Msk       (0x1UL << RCC_APB1HLPENR_LPTIM2LPEN_Pos) /*!< 0x00000020 */
9157 #define RCC_APB1HLPENR_LPTIM2LPEN           RCC_APB1HLPENR_LPTIM2LPEN_Msk
9158 #define RCC_APB1HLPENR_FDCANLPEN_Pos        (9U)
9159 #define RCC_APB1HLPENR_FDCANLPEN_Msk        (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)  /*!< 0x00000200 */
9160 #define RCC_APB1HLPENR_FDCANLPEN            RCC_APB1HLPENR_FDCANLPEN_Msk
9161 
9162 /********************  Bit definition for RCC_APB2LPENR register  **************/
9163 #define RCC_APB2LPENR_TIM1LPEN_Pos          (11U)
9164 #define RCC_APB2LPENR_TIM1LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)   /*!< 0x00000800 */
9165 #define RCC_APB2LPENR_TIM1LPEN              RCC_APB2LPENR_TIM1LPEN_Msk
9166 #define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)
9167 #define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)   /*!< 0x00001000 */
9168 #define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk
9169 #define RCC_APB2LPENR_USART1LPEN_Pos        (14U)
9170 #define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
9171 #define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk
9172 #define RCC_APB2LPENR_USBLPEN_Pos           (24U)
9173 #define RCC_APB2LPENR_USBLPEN_Msk           (0x1UL << RCC_APB2LPENR_USBLPEN_Pos)    /*!< 0x01000000 */
9174 #define RCC_APB2LPENR_USBLPEN               RCC_APB2LPENR_USBLPEN_Msk
9175 
9176 /********************  Bit definition for RCC_APB3LPENR register  **************/
9177 #define RCC_APB3LPENR_SBSLPEN_Pos           (1U)
9178 #define RCC_APB3LPENR_SBSLPEN_Msk           (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos)    /*!< 0x00000001 */
9179 #define RCC_APB3LPENR_SBSLPEN               RCC_APB3LPENR_SBSLPEN_Msk
9180 #define RCC_APB3LPENR_LPUART1LPEN_Pos       (6U)
9181 #define RCC_APB3LPENR_LPUART1LPEN_Msk       (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */
9182 #define RCC_APB3LPENR_LPUART1LPEN           RCC_APB3LPENR_LPUART1LPEN_Msk
9183 #define RCC_APB3LPENR_I3C2LPEN_Pos          (9U)
9184 #define RCC_APB3LPENR_I3C2LPEN_Msk          (0x1UL << RCC_APB3LPENR_I3C2LPEN_Pos)   /*!< 0x00000100 */
9185 #define RCC_APB3LPENR_I3C2LPEN              RCC_APB3LPENR_I3C2LPEN_Msk
9186 #define RCC_APB3LPENR_LPTIM1LPEN_Pos        (11U)
9187 #define RCC_APB3LPENR_LPTIM1LPEN_Msk        (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */
9188 #define RCC_APB3LPENR_LPTIM1LPEN            RCC_APB3LPENR_LPTIM1LPEN_Msk
9189 #define RCC_APB3LPENR_RTCAPBLPEN_Pos        (21U)
9190 #define RCC_APB3LPENR_RTCAPBLPEN_Msk        (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */
9191 #define RCC_APB3LPENR_RTCAPBLPEN            RCC_APB3LPENR_RTCAPBLPEN_Msk
9192 
9193 /********************  Bit definition for RCC_CCIPR1 register  ******************/
9194 #define RCC_CCIPR1_USART1SEL_Pos            (0U)
9195 #define RCC_CCIPR1_USART1SEL_Msk            (0x7UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000007 */
9196 #define RCC_CCIPR1_USART1SEL                RCC_CCIPR1_USART1SEL_Msk
9197 #define RCC_CCIPR1_USART1SEL_0              (0x1UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000001 */
9198 #define RCC_CCIPR1_USART1SEL_1              (0x2UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000002 */
9199 #define RCC_CCIPR1_USART1SEL_2              (0x4UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000004 */
9200 
9201 #define RCC_CCIPR1_USART2SEL_Pos            (3U)
9202 #define RCC_CCIPR1_USART2SEL_Msk            (0x7UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000038 */
9203 #define RCC_CCIPR1_USART2SEL                RCC_CCIPR1_USART2SEL_Msk
9204 #define RCC_CCIPR1_USART2SEL_0              (0x1UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000008 */
9205 #define RCC_CCIPR1_USART2SEL_1              (0x2UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000010 */
9206 #define RCC_CCIPR1_USART2SEL_2              (0x4UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000020 */
9207 
9208 #define RCC_CCIPR1_USART3SEL_Pos            (6U)
9209 #define RCC_CCIPR1_USART3SEL_Msk            (0x7UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x000001C0 */
9210 #define RCC_CCIPR1_USART3SEL                RCC_CCIPR1_USART3SEL_Msk
9211 #define RCC_CCIPR1_USART3SEL_0              (0x1UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000040 */
9212 #define RCC_CCIPR1_USART3SEL_1              (0x2UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000080 */
9213 #define RCC_CCIPR1_USART3SEL_2              (0x4UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000100 */
9214 
9215 #define RCC_CCIPR1_TIMICSEL_Pos             (31U)
9216 #define RCC_CCIPR1_TIMICSEL_Msk             (0x1UL << RCC_CCIPR1_TIMICSEL_Pos)      /*!< 0x10000000 */
9217 #define RCC_CCIPR1_TIMICSEL                 RCC_CCIPR1_TIMICSEL_Msk
9218 
9219 /********************  Bit definition for RCC_CCIPR2 register  ******************/
9220 #define RCC_CCIPR2_LPTIM1SEL_Pos            (8U)
9221 #define RCC_CCIPR2_LPTIM1SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000700 */
9222 #define RCC_CCIPR2_LPTIM1SEL                RCC_CCIPR2_LPTIM1SEL_Msk
9223 #define RCC_CCIPR2_LPTIM1SEL_0              (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000100 */
9224 #define RCC_CCIPR2_LPTIM1SEL_1              (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000200 */
9225 #define RCC_CCIPR2_LPTIM1SEL_2              (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000400 */
9226 
9227 #define RCC_CCIPR2_LPTIM2SEL_Pos            (12U)
9228 #define RCC_CCIPR2_LPTIM2SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00007000 */
9229 #define RCC_CCIPR2_LPTIM2SEL                RCC_CCIPR2_LPTIM2SEL_Msk
9230 #define RCC_CCIPR2_LPTIM2SEL_0              (0x1UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00001000 */
9231 #define RCC_CCIPR2_LPTIM2SEL_1              (0x2UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00002000 */
9232 #define RCC_CCIPR2_LPTIM2SEL_2              (0x4UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00004000 */
9233 
9234 /********************  Bit definition for RCC_CCIPR3 register  ***************/
9235 #define RCC_CCIPR3_SPI1SEL_Pos              (0U)
9236 #define RCC_CCIPR3_SPI1SEL_Msk              (0x7UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000007 */
9237 #define RCC_CCIPR3_SPI1SEL                  RCC_CCIPR3_SPI1SEL_Msk
9238 #define RCC_CCIPR3_SPI1SEL_0                (0x1UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000001 */
9239 #define RCC_CCIPR3_SPI1SEL_1                (0x2UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000002 */
9240 #define RCC_CCIPR3_SPI1SEL_2                (0x4UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000004 */
9241 
9242 #define RCC_CCIPR3_SPI2SEL_Pos              (3U)
9243 #define RCC_CCIPR3_SPI2SEL_Msk              (0x7UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000038 */
9244 #define RCC_CCIPR3_SPI2SEL                  RCC_CCIPR3_SPI2SEL_Msk
9245 #define RCC_CCIPR3_SPI2SEL_0                (0x1UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000008 */
9246 #define RCC_CCIPR3_SPI2SEL_1                (0x2UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000010 */
9247 #define RCC_CCIPR3_SPI2SEL_2                (0x4UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000020 */
9248 
9249 #define RCC_CCIPR3_SPI3SEL_Pos              (6U)
9250 #define RCC_CCIPR3_SPI3SEL_Msk              (0x7UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x000001C0 */
9251 #define RCC_CCIPR3_SPI3SEL                  RCC_CCIPR3_SPI3SEL_Msk
9252 #define RCC_CCIPR3_SPI3SEL_0                (0x1UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x00000040 */
9253 #define RCC_CCIPR3_SPI3SEL_1                (0x2UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x00000080 */
9254 #define RCC_CCIPR3_SPI3SEL_2                (0x4UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x00000100 */
9255 
9256 #define RCC_CCIPR3_LPUART1SEL_Pos           (24U)
9257 #define RCC_CCIPR3_LPUART1SEL_Msk           (0x7UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x07000000 */
9258 #define RCC_CCIPR3_LPUART1SEL               RCC_CCIPR3_LPUART1SEL_Msk
9259 #define RCC_CCIPR3_LPUART1SEL_0             (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x01000000 */
9260 #define RCC_CCIPR3_LPUART1SEL_1             (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x02000000 */
9261 #define RCC_CCIPR3_LPUART1SEL_2             (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x04000000 */
9262 
9263 /********************  Bit definition for RCC_CCIPR4 register  ***************/
9264 
9265 #define RCC_CCIPR4_SYSTICKSEL_Pos           (2U)
9266 #define RCC_CCIPR4_SYSTICKSEL_Msk           (0x3UL << RCC_CCIPR4_SYSTICKSEL_Pos)    /*!< 0x0000000C */
9267 #define RCC_CCIPR4_SYSTICKSEL               RCC_CCIPR4_SYSTICKSEL_Msk
9268 #define RCC_CCIPR4_SYSTICKSEL_0             (0x1UL << RCC_CCIPR4_SYSTICKSEL_Pos)    /*!< 0x00000004 */
9269 #define RCC_CCIPR4_SYSTICKSEL_1             (0x2UL << RCC_CCIPR4_SYSTICKSEL_Pos)    /*!< 0x00000008 */
9270 
9271 #define RCC_CCIPR4_USBSEL_Pos               (4U)
9272 #define RCC_CCIPR4_USBSEL_Msk               (0x3UL << RCC_CCIPR4_USBSEL_Pos)        /*!< 0x00000030 */
9273 #define RCC_CCIPR4_USBSEL                   RCC_CCIPR4_USBSEL_Msk
9274 #define RCC_CCIPR4_USBSEL_0                 (0x1UL << RCC_CCIPR4_USBSEL_Pos)        /*!< 0x00000010 */
9275 #define RCC_CCIPR4_USBSEL_1                 (0x2UL << RCC_CCIPR4_USBSEL_Pos)        /*!< 0x00000020 */
9276 
9277 #define RCC_CCIPR4_I2C1SEL_Pos             (16U)
9278 #define RCC_CCIPR4_I2C1SEL_Msk             (0x3UL << RCC_CCIPR4_I2C1SEL_Pos)      /*!< 0x00030000 */
9279 #define RCC_CCIPR4_I2C1SEL                 RCC_CCIPR4_I2C1SEL_Msk
9280 #define RCC_CCIPR4_I2C1SEL_0               (0x1UL << RCC_CCIPR4_I2C1SEL_Pos)      /*!< 0x00010000 */
9281 #define RCC_CCIPR4_I2C1SEL_1               (0x2UL << RCC_CCIPR4_I2C1SEL_Pos)      /*!< 0x00020000 */
9282 
9283 #define RCC_CCIPR4_I2C2SEL_Pos             (18U)
9284 #define RCC_CCIPR4_I2C2SEL_Msk             (0x3UL << RCC_CCIPR4_I2C2SEL_Pos)      /*!< 0x000C0000 */
9285 #define RCC_CCIPR4_I2C2SEL                 RCC_CCIPR4_I2C2SEL_Msk
9286 #define RCC_CCIPR4_I2C2SEL_0               (0x1UL << RCC_CCIPR4_I2C2SEL_Pos)      /*!< 0x00040000 */
9287 #define RCC_CCIPR4_I2C2SEL_1               (0x2UL << RCC_CCIPR4_I2C2SEL_Pos)      /*!< 0x00080000 */
9288 
9289 #define RCC_CCIPR4_I3C1SEL_Pos             (24U)
9290 #define RCC_CCIPR4_I3C1SEL_Msk             (0x3UL << RCC_CCIPR4_I3C1SEL_Pos)      /*!< 0x03000000 */
9291 #define RCC_CCIPR4_I3C1SEL                 RCC_CCIPR4_I3C1SEL_Msk
9292 #define RCC_CCIPR4_I3C1SEL_0               (0x1UL << RCC_CCIPR4_I3C1SEL_Pos)      /*!< 0x01000000 */
9293 #define RCC_CCIPR4_I3C1SEL_1               (0x2UL << RCC_CCIPR4_I3C1SEL_Pos)      /*!< 0x02000000 */
9294 
9295 #define RCC_CCIPR4_I3C2SEL_Pos             (26U)
9296 #define RCC_CCIPR4_I3C2SEL_Msk             (0x3UL << RCC_CCIPR4_I3C2SEL_Pos)      /*!< 0x0C000000 */
9297 #define RCC_CCIPR4_I3C2SEL                 RCC_CCIPR4_I3C2SEL_Msk
9298 #define RCC_CCIPR4_I3C2SEL_0               (0x1UL << RCC_CCIPR4_I3C2SEL_Pos)      /*!< 0x04000000 */
9299 #define RCC_CCIPR4_I3C2SEL_1               (0x2UL << RCC_CCIPR4_I3C2SEL_Pos)      /*!< 0x08000000 */
9300 
9301 /********************  Bit definition for RCC_CCIPR5 register  ***************/
9302 
9303 #define RCC_CCIPR5_ADCDACSEL_Pos           (0U)
9304 #define RCC_CCIPR5_ADCDACSEL_Msk           (0x7UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000007 */
9305 #define RCC_CCIPR5_ADCDACSEL               RCC_CCIPR5_ADCDACSEL_Msk
9306 #define RCC_CCIPR5_ADCDACSEL_0             (0x1UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000001 */
9307 #define RCC_CCIPR5_ADCDACSEL_1             (0x2UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000002 */
9308 #define RCC_CCIPR5_ADCDACSEL_2             (0x4UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000004 */
9309 
9310 #define RCC_CCIPR5_DACSEL_Pos              (3U)
9311 #define RCC_CCIPR5_DACSEL_Msk              (0x1UL << RCC_CCIPR5_DACSEL_Pos)       /*!< 0x00000008 */
9312 #define RCC_CCIPR5_DACSEL                  RCC_CCIPR5_DACSEL_Msk
9313 
9314 #define RCC_CCIPR5_RNGSEL_Pos              (4U)
9315 #define RCC_CCIPR5_RNGSEL_Msk              (0x3UL << RCC_CCIPR5_RNGSEL_Pos)       /*!< 0x00000030 */
9316 #define RCC_CCIPR5_RNGSEL                  RCC_CCIPR5_RNGSEL_Msk
9317 #define RCC_CCIPR5_RNGSEL_0                (0x1UL << RCC_CCIPR5_RNGSEL_Pos)       /*!< 0x00000010 */
9318 #define RCC_CCIPR5_RNGSEL_1                (0x2UL << RCC_CCIPR5_RNGSEL_Pos)       /*!< 0x00000020 */
9319 
9320 #define RCC_CCIPR5_FDCANSEL_Pos            (8U)
9321 #define RCC_CCIPR5_FDCANSEL_Msk            (0x3UL << RCC_CCIPR5_FDCANSEL_Pos)     /*!< 0x00000300 */
9322 #define RCC_CCIPR5_FDCANSEL                RCC_CCIPR5_FDCANSEL_Msk
9323 #define RCC_CCIPR5_FDCANSEL_0              (0x1UL << RCC_CCIPR5_FDCANSEL_Pos)     /*!< 0x00000100 */
9324 #define RCC_CCIPR5_FDCANSEL_1              (0x2UL << RCC_CCIPR5_FDCANSEL_Pos)     /*!< 0x00000200 */
9325 
9326 #define RCC_CCIPR5_CKERPSEL_Pos            (30U)
9327 #define RCC_CCIPR5_CKERPSEL_Msk            (0x3UL << RCC_CCIPR5_CKERPSEL_Pos)     /*!< 0xC0000000 */
9328 #define RCC_CCIPR5_CKERPSEL                RCC_CCIPR5_CKERPSEL_Msk
9329 #define RCC_CCIPR5_CKERPSEL_0              (0x1UL << RCC_CCIPR5_CKERPSEL_Pos)     /*!< 0x40000000 */
9330 #define RCC_CCIPR5_CKERPSEL_1              (0x2UL << RCC_CCIPR5_CKERPSEL_Pos)     /*!< 0x80000000 */
9331 
9332 /********************  Bit definition for RCC_BDCR register  ******************/
9333 #define RCC_BDCR_LSEON_Pos                  (0U)
9334 #define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)           /*!< 0x00000001 */
9335 #define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk
9336 #define RCC_BDCR_LSERDY_Pos                 (1U)
9337 #define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)          /*!< 0x00000002 */
9338 #define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk
9339 #define RCC_BDCR_LSEBYP_Pos                 (2U)
9340 #define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)          /*!< 0x00000004 */
9341 #define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk
9342 #define RCC_BDCR_LSEDRV_Pos                 (3U)
9343 #define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000018 */
9344 #define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk
9345 #define RCC_BDCR_LSEDRV_0                   (0x1UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000008 */
9346 #define RCC_BDCR_LSEDRV_1                   (0x2UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000010 */
9347 #define RCC_BDCR_LSECSSON_Pos               (5U)
9348 #define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)        /*!< 0x00000020 */
9349 #define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk
9350 #define RCC_BDCR_LSECSSD_Pos                (6U)
9351 #define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)         /*!< 0x00000040 */
9352 #define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk
9353 #define RCC_BDCR_LSEEXT_Pos                 (7U)
9354 #define RCC_BDCR_LSEEXT_Msk                 (0x1UL << RCC_BDCR_LSEEXT_Pos)          /*!< 0x00000080 */
9355 #define RCC_BDCR_LSEEXT                     RCC_BDCR_LSEEXT_Msk
9356 #define RCC_BDCR_RTCSEL_Pos                 (8U)
9357 #define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000300 */
9358 #define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk
9359 #define RCC_BDCR_RTCSEL_0                   (0x1UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000100 */
9360 #define RCC_BDCR_RTCSEL_1                   (0x2UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000200 */
9361 #define RCC_BDCR_RTCEN_Pos                  (15U)
9362 #define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)           /*!< 0x00008000 */
9363 #define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk
9364 #define RCC_BDCR_VSWRST_Pos                 (16U)
9365 #define RCC_BDCR_VSWRST_Msk                 (0x1UL << RCC_BDCR_VSWRST_Pos)          /*!< 0x00010000 */
9366 #define RCC_BDCR_VSWRST                     RCC_BDCR_VSWRST_Msk
9367 #define RCC_BDCR_LSCOEN_Pos                 (24U)
9368 #define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)          /*!< 0x01000000 */
9369 #define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk
9370 #define RCC_BDCR_LSCOSEL_Pos                (25U)
9371 #define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)         /*!< 0x02000000 */
9372 #define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk
9373 #define RCC_BDCR_LSION_Pos                  (26U)
9374 #define RCC_BDCR_LSION_Msk                  (0x1UL << RCC_BDCR_LSION_Pos)           /*!< 0x04000000 */
9375 #define RCC_BDCR_LSION                      RCC_BDCR_LSION_Msk
9376 #define RCC_BDCR_LSIRDY_Pos                 (27U)
9377 #define RCC_BDCR_LSIRDY_Msk                 (0x1UL << RCC_BDCR_LSIRDY_Pos)          /*!< 0x08000000 */
9378 #define RCC_BDCR_LSIRDY                     RCC_BDCR_LSIRDY_Msk
9379 
9380 /********************  Bit definition for RCC_RSR register  *******************/
9381 #define RCC_RSR_RMVF_Pos                    (23U)
9382 #define RCC_RSR_RMVF_Msk                    (0x1UL << RCC_RSR_RMVF_Pos)             /*!< 0x00800000 */
9383 #define RCC_RSR_RMVF                        RCC_RSR_RMVF_Msk
9384 #define RCC_RSR_PINRSTF_Pos                 (26U)
9385 #define RCC_RSR_PINRSTF_Msk                 (0x1UL << RCC_RSR_PINRSTF_Pos)          /*!< 0x04000000 */
9386 #define RCC_RSR_PINRSTF                     RCC_RSR_PINRSTF_Msk
9387 #define RCC_RSR_BORRSTF_Pos                 (27U)
9388 #define RCC_RSR_BORRSTF_Msk                 (0x1UL << RCC_RSR_BORRSTF_Pos)          /*!< 0x08000000 */
9389 #define RCC_RSR_BORRSTF                     RCC_RSR_BORRSTF_Msk
9390 #define RCC_RSR_SFTRSTF_Pos                 (28U)
9391 #define RCC_RSR_SFTRSTF_Msk                 (0x1UL << RCC_RSR_SFTRSTF_Pos)          /*!< 0x10000000 */
9392 #define RCC_RSR_SFTRSTF                     RCC_RSR_SFTRSTF_Msk
9393 #define RCC_RSR_IWDGRSTF_Pos                (29U)
9394 #define RCC_RSR_IWDGRSTF_Msk                (0x1UL << RCC_RSR_IWDGRSTF_Pos)         /*!< 0x20000000 */
9395 #define RCC_RSR_IWDGRSTF                    RCC_RSR_IWDGRSTF_Msk
9396 #define RCC_RSR_WWDGRSTF_Pos                (30U)
9397 #define RCC_RSR_WWDGRSTF_Msk                (0x1UL << RCC_RSR_WWDGRSTF_Pos)         /*!< 0x40000000 */
9398 #define RCC_RSR_WWDGRSTF                    RCC_RSR_WWDGRSTF_Msk
9399 #define RCC_RSR_LPWRRSTF_Pos                (31U)
9400 #define RCC_RSR_LPWRRSTF_Msk                (0x1UL << RCC_RSR_LPWRRSTF_Pos)         /*!< 0x80000000 */
9401 #define RCC_RSR_LPWRRSTF                    RCC_RSR_LPWRRSTF_Msk
9402 
9403 /********************  Bit definition for RCC_PRIVCFGR register  **************/
9404 #define RCC_PRIVCFGR_PRIV_Pos               (1U)
9405 #define RCC_PRIVCFGR_PRIV_Msk               (0x1UL << RCC_PRIVCFGR_PRIV_Pos)        /*!< 0x00000002 */
9406 #define RCC_PRIVCFGR_PRIV                   RCC_PRIVCFGR_PRIV_Msk
9407 
9408 /******************************************************************************/
9409 /*                                                                            */
9410 /*                           Real-Time Clock (RTC)                            */
9411 /*                                                                            */
9412 /******************************************************************************/
9413 /********************  Bits definition for RTC_TR register  *******************/
9414 #define RTC_TR_SU_Pos                       (0U)
9415 #define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
9416 #define RTC_TR_SU                           RTC_TR_SU_Msk
9417 #define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
9418 #define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
9419 #define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
9420 #define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
9421 #define RTC_TR_ST_Pos                       (4U)
9422 #define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
9423 #define RTC_TR_ST                           RTC_TR_ST_Msk
9424 #define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
9425 #define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
9426 #define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
9427 #define RTC_TR_MNU_Pos                      (8U)
9428 #define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
9429 #define RTC_TR_MNU                          RTC_TR_MNU_Msk
9430 #define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
9431 #define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
9432 #define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
9433 #define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
9434 #define RTC_TR_MNT_Pos                      (12U)
9435 #define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
9436 #define RTC_TR_MNT                          RTC_TR_MNT_Msk
9437 #define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
9438 #define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
9439 #define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
9440 #define RTC_TR_HU_Pos                       (16U)
9441 #define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
9442 #define RTC_TR_HU                           RTC_TR_HU_Msk
9443 #define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
9444 #define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
9445 #define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
9446 #define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
9447 #define RTC_TR_HT_Pos                       (20U)
9448 #define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
9449 #define RTC_TR_HT                           RTC_TR_HT_Msk
9450 #define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
9451 #define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
9452 #define RTC_TR_PM_Pos                       (22U)
9453 #define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
9454 #define RTC_TR_PM                           RTC_TR_PM_Msk
9455 
9456 /********************  Bits definition for RTC_DR register  *******************/
9457 #define RTC_DR_DU_Pos                       (0U)
9458 #define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
9459 #define RTC_DR_DU                           RTC_DR_DU_Msk
9460 #define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
9461 #define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
9462 #define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
9463 #define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
9464 #define RTC_DR_DT_Pos                       (4U)
9465 #define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
9466 #define RTC_DR_DT                           RTC_DR_DT_Msk
9467 #define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
9468 #define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
9469 #define RTC_DR_MU_Pos                       (8U)
9470 #define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
9471 #define RTC_DR_MU                           RTC_DR_MU_Msk
9472 #define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
9473 #define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
9474 #define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
9475 #define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
9476 #define RTC_DR_MT_Pos                       (12U)
9477 #define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
9478 #define RTC_DR_MT                           RTC_DR_MT_Msk
9479 #define RTC_DR_WDU_Pos                      (13U)
9480 #define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
9481 #define RTC_DR_WDU                          RTC_DR_WDU_Msk
9482 #define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
9483 #define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
9484 #define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
9485 #define RTC_DR_YU_Pos                       (16U)
9486 #define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
9487 #define RTC_DR_YU                           RTC_DR_YU_Msk
9488 #define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
9489 #define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
9490 #define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
9491 #define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
9492 #define RTC_DR_YT_Pos                       (20U)
9493 #define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
9494 #define RTC_DR_YT                           RTC_DR_YT_Msk
9495 #define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
9496 #define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
9497 #define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
9498 #define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
9499 
9500 /********************  Bits definition for RTC_SSR register  ******************/
9501 #define RTC_SSR_SS_Pos                      (0U)
9502 #define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
9503 #define RTC_SSR_SS                          RTC_SSR_SS_Msk
9504 
9505 /********************  Bits definition for RTC_ICSR register  ******************/
9506 #define RTC_ICSR_ALRAWF_Pos                 (0U)
9507 #define RTC_ICSR_ALRAWF_Msk                 (0x1UL << RTC_ICSR_ALRAWF_Pos)          /*!< 0x00000001 */
9508 #define RTC_ICSR_ALRAWF                     RTC_ICSR_ALRAWF_Msk
9509 #define RTC_ICSR_ALRBWF_Pos                 (1U)
9510 #define RTC_ICSR_ALRBWF_Msk                 (0x1UL << RTC_ICSR_ALRBWF_Pos)          /*!< 0x00000002 */
9511 #define RTC_ICSR_ALRBWF                     RTC_ICSR_ALRBWF_Msk
9512 #define RTC_ICSR_WUTWF_Pos                  (2U)
9513 #define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
9514 #define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
9515 #define RTC_ICSR_SHPF_Pos                   (3U)
9516 #define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
9517 #define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
9518 #define RTC_ICSR_INITS_Pos                  (4U)
9519 #define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
9520 #define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
9521 #define RTC_ICSR_RSF_Pos                    (5U)
9522 #define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
9523 #define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
9524 #define RTC_ICSR_INITF_Pos                  (6U)
9525 #define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
9526 #define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
9527 #define RTC_ICSR_INIT_Pos                   (7U)
9528 #define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
9529 #define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
9530 #define RTC_ICSR_BIN_Pos                    (8U)
9531 #define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
9532 #define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
9533 #define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
9534 #define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
9535 #define RTC_ICSR_BCDU_Pos                   (10U)
9536 #define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
9537 #define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
9538 #define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
9539 #define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
9540 #define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
9541 #define RTC_ICSR_RECALPF_Pos                (16U)
9542 #define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
9543 #define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
9544 
9545 /********************  Bits definition for RTC_PRER register  *****************/
9546 #define RTC_PRER_PREDIV_S_Pos               (0U)
9547 #define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
9548 #define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
9549 #define RTC_PRER_PREDIV_A_Pos               (16U)
9550 #define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
9551 #define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
9552 
9553 /********************  Bits definition for RTC_WUTR register  *****************/
9554 #define RTC_WUTR_WUT_Pos                    (0U)
9555 #define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
9556 #define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
9557 #define RTC_WUTR_WUTOCLR_Pos                (16U)
9558 #define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
9559 #define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
9560 
9561 /********************  Bits definition for RTC_CR register  *******************/
9562 #define RTC_CR_WUCKSEL_Pos                  (0U)
9563 #define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
9564 #define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
9565 #define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
9566 #define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
9567 #define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
9568 #define RTC_CR_TSEDGE_Pos                   (3U)
9569 #define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
9570 #define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
9571 #define RTC_CR_REFCKON_Pos                  (4U)
9572 #define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
9573 #define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
9574 #define RTC_CR_BYPSHAD_Pos                  (5U)
9575 #define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
9576 #define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
9577 #define RTC_CR_FMT_Pos                      (6U)
9578 #define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
9579 #define RTC_CR_FMT                          RTC_CR_FMT_Msk
9580 #define RTC_CR_SSRUIE_Pos                   (7U)
9581 #define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
9582 #define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
9583 #define RTC_CR_ALRAE_Pos                    (8U)
9584 #define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
9585 #define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
9586 #define RTC_CR_ALRBE_Pos                    (9U)
9587 #define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
9588 #define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
9589 #define RTC_CR_WUTE_Pos                     (10U)
9590 #define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
9591 #define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
9592 #define RTC_CR_TSE_Pos                      (11U)
9593 #define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
9594 #define RTC_CR_TSE                          RTC_CR_TSE_Msk
9595 #define RTC_CR_ALRAIE_Pos                   (12U)
9596 #define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
9597 #define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
9598 #define RTC_CR_ALRBIE_Pos                   (13U)
9599 #define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
9600 #define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
9601 #define RTC_CR_WUTIE_Pos                    (14U)
9602 #define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
9603 #define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
9604 #define RTC_CR_TSIE_Pos                     (15U)
9605 #define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
9606 #define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
9607 #define RTC_CR_ADD1H_Pos                    (16U)
9608 #define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
9609 #define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
9610 #define RTC_CR_SUB1H_Pos                    (17U)
9611 #define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
9612 #define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
9613 #define RTC_CR_BKP_Pos                      (18U)
9614 #define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
9615 #define RTC_CR_BKP                          RTC_CR_BKP_Msk
9616 #define RTC_CR_COSEL_Pos                    (19U)
9617 #define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
9618 #define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
9619 #define RTC_CR_POL_Pos                      (20U)
9620 #define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
9621 #define RTC_CR_POL                          RTC_CR_POL_Msk
9622 #define RTC_CR_OSEL_Pos                     (21U)
9623 #define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
9624 #define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
9625 #define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
9626 #define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
9627 #define RTC_CR_COE_Pos                      (23U)
9628 #define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
9629 #define RTC_CR_COE                          RTC_CR_COE_Msk
9630 #define RTC_CR_ITSE_Pos                     (24U)
9631 #define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
9632 #define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
9633 #define RTC_CR_TAMPTS_Pos                   (25U)
9634 #define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
9635 #define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
9636 #define RTC_CR_TAMPOE_Pos                   (26U)
9637 #define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
9638 #define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
9639 #define RTC_CR_ALRAFCLR_Pos                 (27U)
9640 #define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
9641 #define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
9642 #define RTC_CR_ALRBFCLR_Pos                 (28U)
9643 #define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
9644 #define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
9645 #define RTC_CR_TAMPALRM_PU_Pos              (29U)
9646 #define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
9647 #define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
9648 #define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
9649 #define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
9650 #define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
9651 #define RTC_CR_OUT2EN_Pos                   (31U)
9652 #define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
9653 #define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
9654 
9655 /********************  Bits definition for RTC_PRIVCFGR register  *****************/
9656 #define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
9657 #define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
9658 #define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
9659 #define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
9660 #define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
9661 #define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
9662 #define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
9663 #define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
9664 #define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
9665 #define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
9666 #define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
9667 #define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
9668 #define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
9669 #define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
9670 #define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
9671 #define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
9672 #define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
9673 #define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
9674 #define RTC_PRIVCFGR_PRIV_Pos               (15U)
9675 #define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
9676 #define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk
9677 
9678 
9679 /********************  Bits definition for RTC_WPR register  ******************/
9680 #define RTC_WPR_KEY_Pos                     (0U)
9681 #define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
9682 #define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
9683 
9684 /********************  Bits definition for RTC_CALR register  *****************/
9685 #define RTC_CALR_CALM_Pos                   (0U)
9686 #define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
9687 #define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
9688 #define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
9689 #define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
9690 #define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
9691 #define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
9692 #define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
9693 #define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
9694 #define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
9695 #define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
9696 #define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
9697 #define RTC_CALR_LPCAL_Pos                  (12U)
9698 #define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
9699 #define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
9700 #define RTC_CALR_CALW16_Pos                 (13U)
9701 #define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
9702 #define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
9703 #define RTC_CALR_CALW8_Pos                  (14U)
9704 #define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
9705 #define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
9706 #define RTC_CALR_CALP_Pos                   (15U)
9707 #define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
9708 #define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
9709 
9710 /********************  Bits definition for RTC_SHIFTR register  ***************/
9711 #define RTC_SHIFTR_SUBFS_Pos                (0U)
9712 #define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
9713 #define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
9714 #define RTC_SHIFTR_ADD1S_Pos                (31U)
9715 #define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
9716 #define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
9717 
9718 /********************  Bits definition for RTC_TSTR register  *****************/
9719 #define RTC_TSTR_SU_Pos                     (0U)
9720 #define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
9721 #define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
9722 #define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
9723 #define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
9724 #define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
9725 #define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
9726 #define RTC_TSTR_ST_Pos                     (4U)
9727 #define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
9728 #define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
9729 #define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
9730 #define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
9731 #define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
9732 #define RTC_TSTR_MNU_Pos                    (8U)
9733 #define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
9734 #define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
9735 #define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
9736 #define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
9737 #define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
9738 #define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
9739 #define RTC_TSTR_MNT_Pos                    (12U)
9740 #define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
9741 #define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
9742 #define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
9743 #define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
9744 #define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
9745 #define RTC_TSTR_HU_Pos                     (16U)
9746 #define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
9747 #define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
9748 #define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
9749 #define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
9750 #define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
9751 #define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
9752 #define RTC_TSTR_HT_Pos                     (20U)
9753 #define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
9754 #define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
9755 #define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
9756 #define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
9757 #define RTC_TSTR_PM_Pos                     (22U)
9758 #define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
9759 #define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
9760 
9761 /********************  Bits definition for RTC_TSDR register  *****************/
9762 #define RTC_TSDR_DU_Pos                     (0U)
9763 #define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
9764 #define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
9765 #define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
9766 #define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
9767 #define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
9768 #define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
9769 #define RTC_TSDR_DT_Pos                     (4U)
9770 #define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
9771 #define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
9772 #define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
9773 #define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
9774 #define RTC_TSDR_MU_Pos                     (8U)
9775 #define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
9776 #define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
9777 #define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
9778 #define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
9779 #define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
9780 #define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
9781 #define RTC_TSDR_MT_Pos                     (12U)
9782 #define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
9783 #define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
9784 #define RTC_TSDR_WDU_Pos                    (13U)
9785 #define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
9786 #define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
9787 #define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
9788 #define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
9789 #define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
9790 
9791 /********************  Bits definition for RTC_TSSSR register  ****************/
9792 #define RTC_TSSSR_SS_Pos                    (0U)
9793 #define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
9794 #define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
9795 
9796 /********************  Bits definition for RTC_ALRMAR register  ***************/
9797 #define RTC_ALRMAR_SU_Pos                   (0U)
9798 #define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
9799 #define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
9800 #define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
9801 #define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
9802 #define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
9803 #define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
9804 #define RTC_ALRMAR_ST_Pos                   (4U)
9805 #define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
9806 #define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
9807 #define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
9808 #define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
9809 #define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
9810 #define RTC_ALRMAR_MSK1_Pos                 (7U)
9811 #define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
9812 #define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
9813 #define RTC_ALRMAR_MNU_Pos                  (8U)
9814 #define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
9815 #define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
9816 #define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
9817 #define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
9818 #define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
9819 #define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
9820 #define RTC_ALRMAR_MNT_Pos                  (12U)
9821 #define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
9822 #define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
9823 #define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
9824 #define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
9825 #define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
9826 #define RTC_ALRMAR_MSK2_Pos                 (15U)
9827 #define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
9828 #define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
9829 #define RTC_ALRMAR_HU_Pos                   (16U)
9830 #define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
9831 #define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
9832 #define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
9833 #define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
9834 #define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
9835 #define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
9836 #define RTC_ALRMAR_HT_Pos                   (20U)
9837 #define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
9838 #define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
9839 #define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
9840 #define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
9841 #define RTC_ALRMAR_PM_Pos                   (22U)
9842 #define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
9843 #define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
9844 #define RTC_ALRMAR_MSK3_Pos                 (23U)
9845 #define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
9846 #define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
9847 #define RTC_ALRMAR_DU_Pos                   (24U)
9848 #define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
9849 #define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
9850 #define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
9851 #define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
9852 #define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
9853 #define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
9854 #define RTC_ALRMAR_DT_Pos                   (28U)
9855 #define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
9856 #define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
9857 #define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
9858 #define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
9859 #define RTC_ALRMAR_WDSEL_Pos                (30U)
9860 #define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
9861 #define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
9862 #define RTC_ALRMAR_MSK4_Pos                 (31U)
9863 #define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
9864 #define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
9865 
9866 /********************  Bits definition for RTC_ALRMASSR register  *************/
9867 #define RTC_ALRMASSR_SS_Pos                 (0U)
9868 #define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
9869 #define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
9870 #define RTC_ALRMASSR_MASKSS_Pos             (24U)
9871 #define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
9872 #define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
9873 #define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
9874 #define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
9875 #define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
9876 #define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
9877 #define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
9878 #define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
9879 #define RTC_ALRMASSR_SSCLR_Pos              (31U)
9880 #define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
9881 #define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
9882 
9883 /********************  Bits definition for RTC_ALRMBR register  ***************/
9884 #define RTC_ALRMBR_SU_Pos                   (0U)
9885 #define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
9886 #define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
9887 #define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
9888 #define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
9889 #define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
9890 #define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
9891 #define RTC_ALRMBR_ST_Pos                   (4U)
9892 #define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
9893 #define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
9894 #define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
9895 #define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
9896 #define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
9897 #define RTC_ALRMBR_MSK1_Pos                 (7U)
9898 #define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
9899 #define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
9900 #define RTC_ALRMBR_MNU_Pos                  (8U)
9901 #define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
9902 #define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
9903 #define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
9904 #define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
9905 #define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
9906 #define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
9907 #define RTC_ALRMBR_MNT_Pos                  (12U)
9908 #define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
9909 #define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
9910 #define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
9911 #define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
9912 #define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
9913 #define RTC_ALRMBR_MSK2_Pos                 (15U)
9914 #define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
9915 #define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
9916 #define RTC_ALRMBR_HU_Pos                   (16U)
9917 #define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
9918 #define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
9919 #define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
9920 #define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
9921 #define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
9922 #define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
9923 #define RTC_ALRMBR_HT_Pos                   (20U)
9924 #define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
9925 #define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
9926 #define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
9927 #define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
9928 #define RTC_ALRMBR_PM_Pos                   (22U)
9929 #define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
9930 #define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
9931 #define RTC_ALRMBR_MSK3_Pos                 (23U)
9932 #define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
9933 #define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
9934 #define RTC_ALRMBR_DU_Pos                   (24U)
9935 #define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
9936 #define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
9937 #define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
9938 #define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
9939 #define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
9940 #define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
9941 #define RTC_ALRMBR_DT_Pos                   (28U)
9942 #define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
9943 #define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
9944 #define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
9945 #define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
9946 #define RTC_ALRMBR_WDSEL_Pos                (30U)
9947 #define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
9948 #define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
9949 #define RTC_ALRMBR_MSK4_Pos                 (31U)
9950 #define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
9951 #define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
9952 
9953 /********************  Bits definition for RTC_ALRMBSSR register  *************/
9954 #define RTC_ALRMBSSR_SS_Pos                 (0U)
9955 #define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
9956 #define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
9957 #define RTC_ALRMBSSR_MASKSS_Pos             (24U)
9958 #define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
9959 #define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
9960 #define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
9961 #define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
9962 #define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
9963 #define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
9964 #define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
9965 #define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
9966 #define RTC_ALRMBSSR_SSCLR_Pos              (31U)
9967 #define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
9968 #define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
9969 
9970 /********************  Bits definition for RTC_SR register  *******************/
9971 #define RTC_SR_ALRAF_Pos                    (0U)
9972 #define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
9973 #define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
9974 #define RTC_SR_ALRBF_Pos                    (1U)
9975 #define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
9976 #define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
9977 #define RTC_SR_WUTF_Pos                     (2U)
9978 #define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
9979 #define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
9980 #define RTC_SR_TSF_Pos                      (3U)
9981 #define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
9982 #define RTC_SR_TSF                          RTC_SR_TSF_Msk
9983 #define RTC_SR_TSOVF_Pos                    (4U)
9984 #define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
9985 #define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
9986 #define RTC_SR_ITSF_Pos                     (5U)
9987 #define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
9988 #define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
9989 #define RTC_SR_SSRUF_Pos                    (6U)
9990 #define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
9991 #define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
9992 
9993 /********************  Bits definition for RTC_MISR register  *****************/
9994 #define RTC_MISR_ALRAMF_Pos                 (0U)
9995 #define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
9996 #define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
9997 #define RTC_MISR_ALRBMF_Pos                 (1U)
9998 #define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
9999 #define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
10000 #define RTC_MISR_WUTMF_Pos                  (2U)
10001 #define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
10002 #define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
10003 #define RTC_MISR_TSMF_Pos                   (3U)
10004 #define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
10005 #define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
10006 #define RTC_MISR_TSOVMF_Pos                 (4U)
10007 #define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
10008 #define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
10009 #define RTC_MISR_ITSMF_Pos                  (5U)
10010 #define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
10011 #define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
10012 #define RTC_MISR_SSRUMF_Pos                 (6U)
10013 #define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
10014 #define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
10015 
10016 
10017 /********************  Bits definition for RTC_SCR register  ******************/
10018 #define RTC_SCR_CALRAF_Pos                  (0U)
10019 #define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
10020 #define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
10021 #define RTC_SCR_CALRBF_Pos                  (1U)
10022 #define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
10023 #define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
10024 #define RTC_SCR_CWUTF_Pos                   (2U)
10025 #define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
10026 #define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
10027 #define RTC_SCR_CTSF_Pos                    (3U)
10028 #define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
10029 #define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
10030 #define RTC_SCR_CTSOVF_Pos                  (4U)
10031 #define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
10032 #define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
10033 #define RTC_SCR_CITSF_Pos                   (5U)
10034 #define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
10035 #define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
10036 #define RTC_SCR_CSSRUF_Pos                  (6U)
10037 #define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
10038 #define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
10039 
10040 
10041 /********************  Bits definition for RTC_ALRABINR register  ******************/
10042 #define RTC_ALRABINR_SS_Pos                 (0U)
10043 #define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
10044 #define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
10045 
10046 /********************  Bits definition for RTC_ALRBBINR register  ******************/
10047 #define RTC_ALRBBINR_SS_Pos                 (0U)
10048 #define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
10049 #define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
10050 
10051 /******************************************************************************/
10052 /*                                                                            */
10053 /*                     Tamper and backup register (TAMP)                      */
10054 /*                                                                            */
10055 /******************************************************************************/
10056 /********************  Bits definition for TAMP_CR1 register  *****************/
10057 #define TAMP_CR1_TAMP1E_Pos                 (0U)
10058 #define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
10059 #define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
10060 #define TAMP_CR1_TAMP2E_Pos                 (1U)
10061 #define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
10062 #define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
10063 #define TAMP_CR1_ITAMP1E_Pos                (16U)
10064 #define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
10065 #define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
10066 #define TAMP_CR1_ITAMP2E_Pos                (17U)
10067 #define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00020000 */
10068 #define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
10069 #define TAMP_CR1_ITAMP3E_Pos                (18U)
10070 #define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
10071 #define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
10072 #define TAMP_CR1_ITAMP4E_Pos                (19U)
10073 #define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
10074 #define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
10075 #define TAMP_CR1_ITAMP5E_Pos                (20U)
10076 #define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
10077 #define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
10078 #define TAMP_CR1_ITAMP6E_Pos                (21U)
10079 #define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
10080 #define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
10081 #define TAMP_CR1_ITAMP7E_Pos                (22U)
10082 #define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
10083 #define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
10084 #define TAMP_CR1_ITAMP8E_Pos                (23U)
10085 #define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
10086 #define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
10087 #define TAMP_CR1_ITAMP9E_Pos                (24U)
10088 #define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
10089 #define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
10090 #define TAMP_CR1_ITAMP11E_Pos               (26U)
10091 #define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
10092 #define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
10093 #define TAMP_CR1_ITAMP12E_Pos               (27U)
10094 #define TAMP_CR1_ITAMP12E_Msk               (0x1UL << TAMP_CR1_ITAMP12E_Pos)        /*!< 0x08000000 */
10095 #define TAMP_CR1_ITAMP12E                   TAMP_CR1_ITAMP12E_Msk
10096 #define TAMP_CR1_ITAMP13E_Pos               (28U)
10097 #define TAMP_CR1_ITAMP13E_Msk               (0x1UL << TAMP_CR1_ITAMP13E_Pos)        /*!< 0x10000000 */
10098 #define TAMP_CR1_ITAMP13E                   TAMP_CR1_ITAMP13E_Msk
10099 #define TAMP_CR1_ITAMP15E_Pos               (30U)
10100 #define TAMP_CR1_ITAMP15E_Msk               (0x1UL << TAMP_CR1_ITAMP15E_Pos)        /*!< 0x40000000 */
10101 #define TAMP_CR1_ITAMP15E                   TAMP_CR1_ITAMP15E_Msk
10102 
10103 /********************  Bits definition for TAMP_CR2 register  *****************/
10104 #define TAMP_CR2_TAMP1NOERASE_Pos           (0U)
10105 #define TAMP_CR2_TAMP1NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)    /*!< 0x00000001 */
10106 #define TAMP_CR2_TAMP1NOERASE               TAMP_CR2_TAMP1NOERASE_Msk
10107 #define TAMP_CR2_TAMP2NOERASE_Pos           (1U)
10108 #define TAMP_CR2_TAMP2NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)    /*!< 0x00000002 */
10109 #define TAMP_CR2_TAMP2NOERASE               TAMP_CR2_TAMP2NOERASE_Msk
10110 #define TAMP_CR2_TAMP1MSK_Pos               (16U)
10111 #define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
10112 #define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
10113 #define TAMP_CR2_TAMP2MSK_Pos               (17U)
10114 #define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
10115 #define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
10116 #define TAMP_CR2_BKBLOCK_Pos                (22U)
10117 #define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
10118 #define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
10119 #define TAMP_CR2_BKERASE_Pos                (23U)
10120 #define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
10121 #define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
10122 #define TAMP_CR2_TAMP1TRG_Pos               (24U)
10123 #define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
10124 #define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
10125 #define TAMP_CR2_TAMP2TRG_Pos               (25U)
10126 #define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
10127 #define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
10128 
10129 /********************  Bits definition for TAMP_CR3 register  *****************/
10130 #define TAMP_CR3_ITAMP1NOER_Pos             (0U)
10131 #define TAMP_CR3_ITAMP1NOER_Msk             (0x1UL << TAMP_CR3_ITAMP1NOER_Pos)      /*!< 0x00000001 */
10132 #define TAMP_CR3_ITAMP1NOER                 TAMP_CR3_ITAMP1NOER_Msk
10133 #define TAMP_CR3_ITAMP2NOER_Pos             (1U)
10134 #define TAMP_CR3_ITAMP2NOER_Msk             (0x1UL << TAMP_CR3_ITAMP2NOER_Pos)      /*!< 0x00000002 */
10135 #define TAMP_CR3_ITAMP2NOER                 TAMP_CR3_ITAMP2NOER_Msk
10136 #define TAMP_CR3_ITAMP3NOER_Pos             (2U)
10137 #define TAMP_CR3_ITAMP3NOER_Msk             (0x1UL << TAMP_CR3_ITAMP3NOER_Pos)      /*!< 0x00000004 */
10138 #define TAMP_CR3_ITAMP3NOER                 TAMP_CR3_ITAMP3NOER_Msk
10139 #define TAMP_CR3_ITAMP4NOER_Pos             (3U)
10140 #define TAMP_CR3_ITAMP4NOER_Msk             (0x1UL << TAMP_CR3_ITAMP4NOER_Pos)      /*!< 0x00000008 */
10141 #define TAMP_CR3_ITAMP4NOER                 TAMP_CR3_ITAMP4NOER_Msk
10142 #define TAMP_CR3_ITAMP5NOER_Pos             (4U)
10143 #define TAMP_CR3_ITAMP5NOER_Msk             (0x1UL << TAMP_CR3_ITAMP5NOER_Pos)      /*!< 0x00000010 */
10144 #define TAMP_CR3_ITAMP5NOER                 TAMP_CR3_ITAMP5NOER_Msk
10145 #define TAMP_CR3_ITAMP6NOER_Pos             (5U)
10146 #define TAMP_CR3_ITAMP6NOER_Msk             (0x1UL << TAMP_CR3_ITAMP6NOER_Pos)      /*!< 0x00000020 */
10147 #define TAMP_CR3_ITAMP6NOER                 TAMP_CR3_ITAMP6NOER_Msk
10148 #define TAMP_CR3_ITAMP7NOER_Pos             (6U)
10149 #define TAMP_CR3_ITAMP7NOER_Msk             (0x1UL << TAMP_CR3_ITAMP7NOER_Pos)      /*!< 0x00000040 */
10150 #define TAMP_CR3_ITAMP7NOER                 TAMP_CR3_ITAMP7NOER_Msk
10151 #define TAMP_CR3_ITAMP8NOER_Pos             (7U)
10152 #define TAMP_CR3_ITAMP8NOER_Msk             (0x1UL << TAMP_CR3_ITAMP8NOER_Pos)      /*!< 0x00000080 */
10153 #define TAMP_CR3_ITAMP8NOER                 TAMP_CR3_ITAMP8NOER_Msk
10154 #define TAMP_CR3_ITAMP9NOER_Pos             (8U)
10155 #define TAMP_CR3_ITAMP9NOER_Msk             (0x1UL << TAMP_CR3_ITAMP9NOER_Pos)      /*!< 0x00000100 */
10156 #define TAMP_CR3_ITAMP9NOER                 TAMP_CR3_ITAMP9NOER_Msk
10157 #define TAMP_CR3_ITAMP11NOER_Pos            (10U)
10158 #define TAMP_CR3_ITAMP11NOER_Msk            (0x1UL << TAMP_CR3_ITAMP11NOER_Pos)     /*!< 0x00000400 */
10159 #define TAMP_CR3_ITAMP11NOER                TAMP_CR3_ITAMP11NOER_Msk
10160 #define TAMP_CR3_ITAMP12NOER_Pos            (11U)
10161 #define TAMP_CR3_ITAMP12NOER_Msk            (0x1UL << TAMP_CR3_ITAMP12NOER_Pos)     /*!< 0x00000800 */
10162 #define TAMP_CR3_ITAMP12NOER                TAMP_CR3_ITAMP12NOER_Msk
10163 #define TAMP_CR3_ITAMP13NOER_Pos            (12U)
10164 #define TAMP_CR3_ITAMP13NOER_Msk            (0x1UL << TAMP_CR3_ITAMP13NOER_Pos)     /*!< 0x00001000 */
10165 #define TAMP_CR3_ITAMP13NOER                TAMP_CR3_ITAMP13NOER_Msk
10166 #define TAMP_CR3_ITAMP15NOER_Pos            (14U)
10167 #define TAMP_CR3_ITAMP15NOER_Msk            (0x1UL << TAMP_CR3_ITAMP15NOER_Pos)     /*!< 0x00004000 */
10168 #define TAMP_CR3_ITAMP15NOER                TAMP_CR3_ITAMP15NOER_Msk
10169 
10170 /********************  Bits definition for TAMP_FLTCR register  ***************/
10171 #define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
10172 #define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
10173 #define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
10174 #define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
10175 #define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
10176 #define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
10177 #define TAMP_FLTCR_TAMPFLT_Pos              (3U)
10178 #define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
10179 #define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
10180 #define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
10181 #define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
10182 #define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
10183 #define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
10184 #define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
10185 #define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
10186 #define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
10187 #define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
10188 #define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
10189 #define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
10190 
10191 /********************  Bits definition for TAMP_ATCR1 register  ***************/
10192 #define TAMP_ATCR1_TAMP1AM_Pos              (0U)
10193 #define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
10194 #define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
10195 #define TAMP_ATCR1_TAMP2AM_Pos              (1U)
10196 #define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
10197 #define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
10198 #define TAMP_ATCR1_ATOSEL1_Pos              (8U)
10199 #define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
10200 #define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
10201 #define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
10202 #define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
10203 #define TAMP_ATCR1_ATOSEL2_Pos              (10U)
10204 #define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
10205 #define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
10206 #define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
10207 #define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
10208 #define TAMP_ATCR1_ATCKSEL_Pos              (16U)
10209 #define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
10210 #define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
10211 #define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
10212 #define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
10213 #define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
10214 #define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
10215 #define TAMP_ATCR1_ATPER_Pos                (24U)
10216 #define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
10217 #define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
10218 #define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
10219 #define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
10220 #define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
10221 #define TAMP_ATCR1_ATOSHARE_Pos             (30U)
10222 #define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
10223 #define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
10224 #define TAMP_ATCR1_FLTEN_Pos                (31U)
10225 #define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
10226 #define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk
10227 
10228 /********************  Bits definition for TAMP_ATSEEDR register  ******************/
10229 #define TAMP_ATSEEDR_SEED_Pos               (0U)
10230 #define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
10231 #define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
10232 
10233 /********************  Bits definition for TAMP_ATOR register  ******************/
10234 #define TAMP_ATOR_PRNG_Pos                  (0U)
10235 #define TAMP_ATOR_PRNG_Msk                  (0xFFUL << TAMP_ATOR_PRNG_Pos)            /*!< 0x000000FF */
10236 #define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
10237 #define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
10238 #define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
10239 #define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
10240 #define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
10241 #define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
10242 #define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
10243 #define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
10244 #define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
10245 #define TAMP_ATOR_SEEDF_Pos                 (14U)
10246 #define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
10247 #define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
10248 #define TAMP_ATOR_INITS_Pos                 (15U)
10249 #define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
10250 #define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
10251 
10252 /********************  Bits definition for TAMP_ATCR2 register  ***************/
10253 #define TAMP_ATCR2_ATOSEL1_Pos              (8U)
10254 #define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
10255 #define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
10256 #define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
10257 #define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
10258 #define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
10259 #define TAMP_ATCR2_ATOSEL2_Pos              (11U)
10260 #define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
10261 #define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
10262 #define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
10263 #define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
10264 #define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
10265 
10266 /********************  Bits definition for TAMP_SECCFGR register  *************/
10267 /* Keep SEC acronym  name as following devices (STM32H562xx, STM32H563xx, STM32H573xx) with secure
10268    acronym to avoid duplicated bits definitions */
10269 #define TAMP_SECCFGR_BKPRWSEC_Pos           (0U)
10270 #define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x000000FF */
10271 #define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
10272 #define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
10273 #define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
10274 #define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
10275 #define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
10276 #define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
10277 #define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
10278 #define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
10279 #define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
10280 #define TAMP_SECCFGR_BKPWSEC_Pos            (16U)
10281 #define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00FF0000 */
10282 #define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
10283 #define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
10284 #define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
10285 #define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
10286 #define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
10287 #define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
10288 #define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
10289 #define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
10290 #define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
10291 
10292 /********************  Bits definition for TAMP_PRIVCFGR register  ************/
10293 #define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
10294 #define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)     /*!< 0x20000000 */
10295 #define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
10296 #define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
10297 #define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)    /*!< 0x20000000 */
10298 #define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
10299 #define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
10300 #define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)     /*!< 0x40000000 */
10301 #define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
10302 #define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
10303 #define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
10304 #define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk
10305 
10306 /********************  Bits definition for TAMP_IER register  *****************/
10307 #define TAMP_IER_TAMP1IE_Pos                (0U)
10308 #define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
10309 #define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
10310 #define TAMP_IER_TAMP2IE_Pos                (1U)
10311 #define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
10312 #define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
10313 #define TAMP_IER_ITAMP1IE_Pos               (16U)
10314 #define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
10315 #define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
10316 #define TAMP_IER_ITAMP2IE_Pos               (17U)
10317 #define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
10318 #define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
10319 #define TAMP_IER_ITAMP3IE_Pos               (18U)
10320 #define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
10321 #define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
10322 #define TAMP_IER_ITAMP4IE_Pos               (19U)
10323 #define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
10324 #define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
10325 #define TAMP_IER_ITAMP5IE_Pos               (20U)
10326 #define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
10327 #define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
10328 #define TAMP_IER_ITAMP6IE_Pos               (21U)
10329 #define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
10330 #define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
10331 #define TAMP_IER_ITAMP7IE_Pos               (22U)
10332 #define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
10333 #define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
10334 #define TAMP_IER_ITAMP8IE_Pos               (23U)
10335 #define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
10336 #define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
10337 #define TAMP_IER_ITAMP9IE_Pos               (24U)
10338 #define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
10339 #define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
10340 #define TAMP_IER_ITAMP11IE_Pos              (26U)
10341 #define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
10342 #define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
10343 #define TAMP_IER_ITAMP12IE_Pos              (27U)
10344 #define TAMP_IER_ITAMP12IE_Msk              (0x1UL << TAMP_IER_ITAMP12IE_Pos)       /*!< 0x08000000 */
10345 #define TAMP_IER_ITAMP12IE                  TAMP_IER_ITAMP12IE_Msk
10346 #define TAMP_IER_ITAMP13IE_Pos              (28U)
10347 #define TAMP_IER_ITAMP13IE_Msk              (0x1UL << TAMP_IER_ITAMP13IE_Pos)       /*!< 0x10000000 */
10348 #define TAMP_IER_ITAMP13IE                  TAMP_IER_ITAMP13IE_Msk
10349 #define TAMP_IER_ITAMP15IE_Pos              (30U)
10350 #define TAMP_IER_ITAMP15IE_Msk              (0x1UL << TAMP_IER_ITAMP15IE_Pos)       /*!< 0x40000000 */
10351 #define TAMP_IER_ITAMP15IE                  TAMP_IER_ITAMP15IE_Msk
10352 
10353 /********************  Bits definition for TAMP_SR register  *****************/
10354 #define TAMP_SR_TAMP1F_Pos                  (0U)
10355 #define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
10356 #define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
10357 #define TAMP_SR_TAMP2F_Pos                  (1U)
10358 #define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
10359 #define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
10360 #define TAMP_SR_ITAMP1F_Pos                 (16U)
10361 #define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
10362 #define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
10363 #define TAMP_SR_ITAMP2F_Pos                 (17U)
10364 #define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00020000 */
10365 #define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
10366 #define TAMP_SR_ITAMP3F_Pos                 (18U)
10367 #define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
10368 #define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
10369 #define TAMP_SR_ITAMP4F_Pos                 (19U)
10370 #define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
10371 #define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
10372 #define TAMP_SR_ITAMP5F_Pos                 (20U)
10373 #define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
10374 #define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
10375 #define TAMP_SR_ITAMP6F_Pos                 (21U)
10376 #define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
10377 #define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
10378 #define TAMP_SR_ITAMP7F_Pos                 (22U)
10379 #define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
10380 #define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
10381 #define TAMP_SR_ITAMP8F_Pos                 (23U)
10382 #define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
10383 #define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
10384 #define TAMP_SR_ITAMP9F_Pos                 (24U)
10385 #define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
10386 #define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
10387 #define TAMP_SR_ITAMP11F_Pos                (26U)
10388 #define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
10389 #define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
10390 #define TAMP_SR_ITAMP12F_Pos                (27U)
10391 #define TAMP_SR_ITAMP12F_Msk                (0x1UL << TAMP_SR_ITAMP12F_Pos)         /*!< 0x08000000 */
10392 #define TAMP_SR_ITAMP12F                    TAMP_SR_ITAMP12F_Msk
10393 #define TAMP_SR_ITAMP13F_Pos                (28U)
10394 #define TAMP_SR_ITAMP13F_Msk                (0x1UL << TAMP_SR_ITAMP13F_Pos)         /*!< 0x10000000 */
10395 #define TAMP_SR_ITAMP13F                    TAMP_SR_ITAMP13F_Msk
10396 #define TAMP_SR_ITAMP15F_Pos                (30U)
10397 #define TAMP_SR_ITAMP15F_Msk                (0x1UL << TAMP_SR_ITAMP15F_Pos)         /*!< 0x40000000 */
10398 #define TAMP_SR_ITAMP15F                    TAMP_SR_ITAMP15F_Msk
10399 
10400 /********************  Bits definition for TAMP_MISR register  ****************/
10401 #define TAMP_MISR_TAMP1MF_Pos               (0U)
10402 #define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
10403 #define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
10404 #define TAMP_MISR_TAMP2MF_Pos               (1U)
10405 #define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
10406 #define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
10407 #define TAMP_MISR_ITAMP1MF_Pos              (16U)
10408 #define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
10409 #define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
10410 #define TAMP_MISR_ITAMP2MF_Pos              (17U)
10411 #define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00020000 */
10412 #define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
10413 #define TAMP_MISR_ITAMP3MF_Pos              (18U)
10414 #define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
10415 #define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
10416 #define TAMP_MISR_ITAMP4MF_Pos              (19U)
10417 #define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
10418 #define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
10419 #define TAMP_MISR_ITAMP5MF_Pos              (20U)
10420 #define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
10421 #define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
10422 #define TAMP_MISR_ITAMP6MF_Pos              (21U)
10423 #define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
10424 #define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
10425 #define TAMP_MISR_ITAMP7MF_Pos              (22U)
10426 #define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
10427 #define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
10428 #define TAMP_MISR_ITAMP8MF_Pos              (23U)
10429 #define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
10430 #define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
10431 #define TAMP_MISR_ITAMP9MF_Pos              (24U)
10432 #define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
10433 #define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
10434 #define TAMP_MISR_ITAMP11MF_Pos             (26U)
10435 #define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
10436 #define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
10437 #define TAMP_MISR_ITAMP12MF_Pos             (27U)
10438 #define TAMP_MISR_ITAMP12MF_Msk             (0x1UL << TAMP_MISR_ITAMP12MF_Pos)       /*!< 0x08000000 */
10439 #define TAMP_MISR_ITAMP12MF                 TAMP_MISR_ITAMP12MF_Msk
10440 #define TAMP_MISR_ITAMP13MF_Pos             (28U)
10441 #define TAMP_MISR_ITAMP13MF_Msk             (0x1UL << TAMP_MISR_ITAMP13MF_Pos)       /*!< 0x10000000 */
10442 #define TAMP_MISR_ITAMP13MF                 TAMP_MISR_ITAMP13MF_Msk
10443 #define TAMP_MISR_ITAMP15MF_Pos             (30U)
10444 #define TAMP_MISR_ITAMP15MF_Msk             (0x1UL << TAMP_MISR_ITAMP15MF_Pos)      /*!< 0x40000000 */
10445 #define TAMP_MISR_ITAMP15MF                 TAMP_MISR_ITAMP15MF_Msk
10446 
10447 
10448 /********************  Bits definition for TAMP_SCR register  *****************/
10449 #define TAMP_SCR_CTAMP1F_Pos                (0U)
10450 #define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
10451 #define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
10452 #define TAMP_SCR_CTAMP2F_Pos                (1U)
10453 #define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
10454 #define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
10455 #define TAMP_SCR_CITAMP1F_Pos               (16U)
10456 #define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
10457 #define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
10458 #define TAMP_SCR_CITAMP2F_Pos               (17U)
10459 #define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00020000 */
10460 #define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
10461 #define TAMP_SCR_CITAMP3F_Pos               (18U)
10462 #define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
10463 #define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
10464 #define TAMP_SCR_CITAMP4F_Pos               (19U)
10465 #define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
10466 #define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
10467 #define TAMP_SCR_CITAMP5F_Pos               (20U)
10468 #define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
10469 #define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
10470 #define TAMP_SCR_CITAMP6F_Pos               (21U)
10471 #define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
10472 #define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
10473 #define TAMP_SCR_CITAMP7F_Pos               (22U)
10474 #define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
10475 #define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
10476 #define TAMP_SCR_CITAMP8F_Pos               (23U)
10477 #define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
10478 #define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
10479 #define TAMP_SCR_CITAMP9F_Pos               (24U)
10480 #define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x00100000 */
10481 #define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
10482 #define TAMP_SCR_CITAMP11F_Pos              (26U)
10483 #define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x00400000 */
10484 #define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
10485 #define TAMP_SCR_CITAMP12F_Pos              (27U)
10486 #define TAMP_SCR_CITAMP12F_Msk              (0x1UL << TAMP_SCR_CITAMP12F_Pos)       /*!< 0x08000000 */
10487 #define TAMP_SCR_CITAMP12F                  TAMP_SCR_CITAMP12F_Msk
10488 #define TAMP_SCR_CITAMP13F_Pos              (28U)
10489 #define TAMP_SCR_CITAMP13F_Msk              (0x1UL << TAMP_SCR_CITAMP13F_Pos)       /*!< 0x10000000 */
10490 #define TAMP_SCR_CITAMP13F                  TAMP_SCR_CITAMP13F_Msk
10491 #define TAMP_SCR_CITAMP15F_Pos              (30U)
10492 #define TAMP_SCR_CITAMP15F_Msk              (0x1UL << TAMP_SCR_CITAMP15F_Pos)       /*!< 0x40000000 */
10493 #define TAMP_SCR_CITAMP15F                  TAMP_SCR_CITAMP15F_Msk
10494 /********************  Bits definition for TAMP_COUNT1R register  ***************/
10495 #define TAMP_COUNT1R_COUNT_Pos              (0U)
10496 #define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
10497 #define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk
10498 
10499 
10500 /********************  Bits definition for TAMP_ERCFG register  ***************/
10501 #define TAMP_ERCFGR_ERCFG0_Pos              (0U)
10502 #define TAMP_ERCFGR_ERCFG0_Msk              (0x1UL << TAMP_ERCFGR_ERCFG0_Pos)         /*!< 0x00000001 */
10503 #define TAMP_ERCFGR_ERCFG0                  TAMP_ERCFGR_ERCFG0_Msk
10504 
10505 /********************  Bits definition for TAMP_BKP0R register  ***************/
10506 #define TAMP_BKP0R_Pos                      (0U)
10507 #define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
10508 #define TAMP_BKP0R                          TAMP_BKP0R_Msk
10509 
10510 /********************  Bits definition for TAMP_BKP1R register  ****************/
10511 #define TAMP_BKP1R_Pos                      (0U)
10512 #define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
10513 #define TAMP_BKP1R                          TAMP_BKP1R_Msk
10514 
10515 /********************  Bits definition for TAMP_BKP2R register  ****************/
10516 #define TAMP_BKP2R_Pos                      (0U)
10517 #define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
10518 #define TAMP_BKP2R                          TAMP_BKP2R_Msk
10519 
10520 /********************  Bits definition for TAMP_BKP3R register  ****************/
10521 #define TAMP_BKP3R_Pos                      (0U)
10522 #define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
10523 #define TAMP_BKP3R                          TAMP_BKP3R_Msk
10524 
10525 /********************  Bits definition for TAMP_BKP4R register  ****************/
10526 #define TAMP_BKP4R_Pos                      (0U)
10527 #define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
10528 #define TAMP_BKP4R                          TAMP_BKP4R_Msk
10529 
10530 /********************  Bits definition for TAMP_BKP5R register  ****************/
10531 #define TAMP_BKP5R_Pos                      (0U)
10532 #define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
10533 #define TAMP_BKP5R                          TAMP_BKP5R_Msk
10534 
10535 /********************  Bits definition for TAMP_BKP6R register  ****************/
10536 #define TAMP_BKP6R_Pos                      (0U)
10537 #define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
10538 #define TAMP_BKP6R                          TAMP_BKP6R_Msk
10539 
10540 /********************  Bits definition for TAMP_BKP7R register  ****************/
10541 #define TAMP_BKP7R_Pos                      (0U)
10542 #define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
10543 #define TAMP_BKP7R                          TAMP_BKP7R_Msk
10544 
10545 /********************  Bits definition for TAMP_BKP8R register  ****************/
10546 #define TAMP_BKP8R_Pos                      (0U)
10547 #define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
10548 #define TAMP_BKP8R                          TAMP_BKP8R_Msk
10549 
10550 /********************  Bits definition for TAMP_BKP9R register  ****************/
10551 #define TAMP_BKP9R_Pos                      (0U)
10552 #define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
10553 #define TAMP_BKP9R                          TAMP_BKP9R_Msk
10554 
10555 /********************  Bits definition for TAMP_BKP10R register  ***************/
10556 #define TAMP_BKP10R_Pos                     (0U)
10557 #define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
10558 #define TAMP_BKP10R                         TAMP_BKP10R_Msk
10559 
10560 /********************  Bits definition for TAMP_BKP11R register  ***************/
10561 #define TAMP_BKP11R_Pos                     (0U)
10562 #define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
10563 #define TAMP_BKP11R                         TAMP_BKP11R_Msk
10564 
10565 /********************  Bits definition for TAMP_BKP12R register  ***************/
10566 #define TAMP_BKP12R_Pos                     (0U)
10567 #define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
10568 #define TAMP_BKP12R                         TAMP_BKP12R_Msk
10569 
10570 /********************  Bits definition for TAMP_BKP13R register  ***************/
10571 #define TAMP_BKP13R_Pos                     (0U)
10572 #define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
10573 #define TAMP_BKP13R                         TAMP_BKP13R_Msk
10574 
10575 /********************  Bits definition for TAMP_BKP14R register  ***************/
10576 #define TAMP_BKP14R_Pos                     (0U)
10577 #define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
10578 #define TAMP_BKP14R                         TAMP_BKP14R_Msk
10579 
10580 /********************  Bits definition for TAMP_BKP15R register  ***************/
10581 #define TAMP_BKP15R_Pos                     (0U)
10582 #define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
10583 #define TAMP_BKP15R                         TAMP_BKP15R_Msk
10584 
10585 /********************  Bits definition for TAMP_BKP16R register  ***************/
10586 #define TAMP_BKP16R_Pos                     (0U)
10587 #define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
10588 #define TAMP_BKP16R                         TAMP_BKP16R_Msk
10589 
10590 /********************  Bits definition for TAMP_BKP17R register  ***************/
10591 #define TAMP_BKP17R_Pos                     (0U)
10592 #define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
10593 #define TAMP_BKP17R                         TAMP_BKP17R_Msk
10594 
10595 /********************  Bits definition for TAMP_BKP18R register  ***************/
10596 #define TAMP_BKP18R_Pos                     (0U)
10597 #define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
10598 #define TAMP_BKP18R                         TAMP_BKP18R_Msk
10599 
10600 /********************  Bits definition for TAMP_BKP19R register  ***************/
10601 #define TAMP_BKP19R_Pos                     (0U)
10602 #define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
10603 #define TAMP_BKP19R                         TAMP_BKP19R_Msk
10604 
10605 /********************  Bits definition for TAMP_BKP20R register  ***************/
10606 #define TAMP_BKP20R_Pos                     (0U)
10607 #define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
10608 #define TAMP_BKP20R                         TAMP_BKP20R_Msk
10609 
10610 /********************  Bits definition for TAMP_BKP21R register  ***************/
10611 #define TAMP_BKP21R_Pos                     (0U)
10612 #define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
10613 #define TAMP_BKP21R                         TAMP_BKP21R_Msk
10614 
10615 /********************  Bits definition for TAMP_BKP22R register  ***************/
10616 #define TAMP_BKP22R_Pos                     (0U)
10617 #define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
10618 #define TAMP_BKP22R                         TAMP_BKP22R_Msk
10619 
10620 /********************  Bits definition for TAMP_BKP23R register  ***************/
10621 #define TAMP_BKP23R_Pos                     (0U)
10622 #define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
10623 #define TAMP_BKP23R                         TAMP_BKP23R_Msk
10624 
10625 /********************  Bits definition for TAMP_BKP24R register  ***************/
10626 #define TAMP_BKP24R_Pos                     (0U)
10627 #define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
10628 #define TAMP_BKP24R                         TAMP_BKP24R_Msk
10629 
10630 /********************  Bits definition for TAMP_BKP25R register  ***************/
10631 #define TAMP_BKP25R_Pos                     (0U)
10632 #define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
10633 #define TAMP_BKP25R                         TAMP_BKP25R_Msk
10634 
10635 /********************  Bits definition for TAMP_BKP26R register  ***************/
10636 #define TAMP_BKP26R_Pos                     (0U)
10637 #define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
10638 #define TAMP_BKP26R                         TAMP_BKP26R_Msk
10639 
10640 /********************  Bits definition for TAMP_BKP27R register  ***************/
10641 #define TAMP_BKP27R_Pos                     (0U)
10642 #define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
10643 #define TAMP_BKP27R                         TAMP_BKP27R_Msk
10644 
10645 /********************  Bits definition for TAMP_BKP28R register  ***************/
10646 #define TAMP_BKP28R_Pos                     (0U)
10647 #define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
10648 #define TAMP_BKP28R                         TAMP_BKP28R_Msk
10649 
10650 /********************  Bits definition for TAMP_BKP29R register  ***************/
10651 #define TAMP_BKP29R_Pos                     (0U)
10652 #define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
10653 #define TAMP_BKP29R                         TAMP_BKP29R_Msk
10654 
10655 /********************  Bits definition for TAMP_BKP30R register  ***************/
10656 #define TAMP_BKP30R_Pos                     (0U)
10657 #define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
10658 #define TAMP_BKP30R                         TAMP_BKP30R_Msk
10659 
10660 /********************  Bits definition for TAMP_BKP31R register  ***************/
10661 #define TAMP_BKP31R_Pos                     (0U)
10662 #define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
10663 #define TAMP_BKP31R                         TAMP_BKP31R_Msk
10664 
10665 /******************************************************************************/
10666 /*                                                                            */
10667 /*                                 SBS                                        */
10668 /*                                                                            */
10669 /******************************************************************************/
10670 /********************  Bit definition for SBS_HDPLCR register  *****************/
10671 #define SBS_HDPLCR_INCR_HDPL_Pos            (0U)
10672 #define SBS_HDPLCR_INCR_HDPL_Msk            (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos)     /*!< 0x000000FF */
10673 #define SBS_HDPLCR_INCR_HDPL                SBS_HDPLCR_INCR_HDPL_Msk                 /*!< Increment HDPL value. */
10674 
10675 /********************  Bit definition for SBS_HDPLSR register  *****************/
10676 #define SBS_HDPLSR_HDPL_Pos                 (0U)
10677 #define SBS_HDPLSR_HDPL_Msk                 (0xFFUL << SBS_HDPLSR_HDPL_Pos)          /*!< 0x000000FF */
10678 #define SBS_HDPLSR_HDPL                     SBS_HDPLSR_HDPL_Msk                      /*!< HDPL value. */
10679 
10680 /********************  Bit definition for SBS_DBGCR register  *****************/
10681 #define SBS_DBGCR_AP_UNLOCK_Pos           (0U)
10682 #define SBS_DBGCR_AP_UNLOCK_Msk           (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos)    /*!< 0x000000FF */
10683 #define SBS_DBGCR_AP_UNLOCK               SBS_DBGCR_AP_UNLOCK_Msk                /*!< Open the Access Port. */
10684 
10685 #define SBS_DBGCR_DBG_UNLOCK_Pos          (8U)
10686 #define SBS_DBGCR_DBG_UNLOCK_Msk          (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos)   /*!< 0x0000FF00 */
10687 #define SBS_DBGCR_DBG_UNLOCK              SBS_DBGCR_DBG_UNLOCK_Msk               /*!< Open the debug when DBG_AUTH_HDPL is reached. */
10688 
10689 #define SBS_DBGCR_DBG_AUTH_HDPL_Pos       (16U)
10690 #define SBS_DBGCR_DBG_AUTH_HDPL_Msk       (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */
10691 #define SBS_DBGCR_DBG_AUTH_HDPL           SBS_DBGCR_DBG_AUTH_HDPL_Msk             /*!< HDPL value when the debug should be effectively opened. */
10692 
10693 /********************  Bit definition for SBS_DBGLCKR register  *****************/
10694 #define SBS_DBGLOCKR_DBGCFG_LOCK_Pos      (0U)
10695 #define SBS_DBGLOCKR_DBGCFG_LOCK_Msk      (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */
10696 #define SBS_DBGLOCKR_DBGCFG_LOCK          SBS_DBGLOCKR_DBGCFG_LOCK_Msk             /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */
10697 
10698 /******************  Bit definition for SBS_PMCR register  ****************/
10699 #define SBS_PMCR_PB6_FMP_Pos              (16U)
10700 #define SBS_PMCR_PB6_FMP_Msk              (0x1UL << SBS_PMCR_PB6_FMP_Pos)            /*!< 0x00010000 */
10701 #define SBS_PMCR_PB6_FMP                  SBS_PMCR_PB6_FMP_Msk                       /*!< Fast-mode Plus command on PB(6) */
10702 #define SBS_PMCR_PB7_FMP_Pos              (17U)
10703 #define SBS_PMCR_PB7_FMP_Msk              (0x1UL << SBS_PMCR_PB7_FMP_Pos)            /*!< 0x00020000 */
10704 #define SBS_PMCR_PB7_FMP                  SBS_PMCR_PB7_FMP_Msk                       /*!< Fast-mode Plus command on PB(7) */
10705 #define SBS_PMCR_PB8_FMP_Pos              (18U)
10706 #define SBS_PMCR_PB8_FMP_Msk              (0x1UL << SBS_PMCR_PB8_FMP_Pos)            /*!< 0x00040000 */
10707 #define SBS_PMCR_PB8_FMP                  SBS_PMCR_PB8_FMP_Msk                       /*!< Fast-mode Plus command on PB(8) */
10708 
10709 /******************  Bit definition for SBS_FPUIMR register  ***************/
10710 #define SBS_FPUIMR_FPU_IE_Pos            (0U)
10711 #define SBS_FPUIMR_FPU_IE_Msk            (0x3FUL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x0000003F - */
10712 #define SBS_FPUIMR_FPU_IE                SBS_FPUIMR_FPU_IE_Msk                       /*!<  All FPU interrupts enable */
10713 #define SBS_FPUIMR_FPU_IE_0              (0x1UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000001 - Invalid operation Interrupt enable */
10714 #define SBS_FPUIMR_FPU_IE_1              (0x2UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000002 - Divide-by-zero Interrupt enable */
10715 #define SBS_FPUIMR_FPU_IE_2              (0x4UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000004 - Underflow Interrupt enable */
10716 #define SBS_FPUIMR_FPU_IE_3              (0x8UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000008 - Overflow Interrupt enable */
10717 #define SBS_FPUIMR_FPU_IE_4              (0x10UL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x00000010 - Input denormal Interrupt enable */
10718 #define SBS_FPUIMR_FPU_IE_5              (0x20UL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */
10719 
10720 /******************  Bit definition for SBS_MESR register  ****************/
10721 #define SBS_MESR_MCLR_Pos                (0U)
10722 #define SBS_MESR_MCLR_Msk                (0x1UL << SBS_MESR_MCLR_Pos)         /*!< 0x00000001 */
10723 #define SBS_MESR_MCLR                    SBS_MESR_MCLR_Msk                    /*!< Status of Erase after Reset */
10724 #define SBS_MESR_IPMEE_Pos               (16U)
10725 #define SBS_MESR_IPMEE_Msk               (0x1UL << SBS_MESR_IPMEE_Pos)        /*!< 0x00010000 */
10726 #define SBS_MESR_IPMEE                   SBS_MESR_IPMEE_Msk                   /*!< Status of End of Erase for ICache and PKA RAMs */
10727 
10728 /******************  Bit definition for SBS_CCCSR register  ****************/
10729 #define SBS_CCCSR_EN1_Pos                (0U)
10730 #define SBS_CCCSR_EN1_Msk                (0x1UL << SBS_CCCSR_EN1_Pos)         /*!< 0x00000001 */
10731 #define SBS_CCCSR_EN1                    SBS_CCCSR_EN1_Msk                    /*!< Enable compensation cell for VDD power rail */
10732 #define SBS_CCCSR_CS1_Pos                (1U)
10733 #define SBS_CCCSR_CS1_Msk                (0x1UL << SBS_CCCSR_CS1_Pos)         /*!< 0x00000002 */
10734 #define SBS_CCCSR_CS1                    SBS_CCCSR_CS1_Msk                    /*!< Code selection for VDD power rail */
10735 #define SBS_CCCSR_EN2_Pos                (2U)
10736 #define SBS_CCCSR_EN2_Msk                (0x1UL << SBS_CCCSR_EN2_Pos)         /*!< 0x00000004 */
10737 #define SBS_CCCSR_EN2                    SBS_CCCSR_EN2_Msk                    /*!< Enable compensation cell for VDDIO power rail */
10738 #define SBS_CCCSR_CS2_Pos                (3U)
10739 #define SBS_CCCSR_CS2_Msk                (0x1UL << SBS_CCCSR_CS2_Pos)         /*!< 0x00000008 */
10740 #define SBS_CCCSR_CS2                    SBS_CCCSR_CS2_Msk                    /*!< Code selection for VDDIO power rail */
10741 #define SBS_CCCSR_RDY1_Pos               (8U)
10742 #define SBS_CCCSR_RDY1_Msk               (0x1UL << SBS_CCCSR_RDY1_Pos)        /*!< 0x00000100 */
10743 #define SBS_CCCSR_RDY1                   SBS_CCCSR_RDY1_Msk                   /*!< VDD compensation cell ready flag */
10744 #define SBS_CCCSR_RDY2_Pos               (9U)
10745 #define SBS_CCCSR_RDY2_Msk               (0x1UL << SBS_CCCSR_RDY2_Pos)        /*!< 0x00000200 */
10746 #define SBS_CCCSR_RDY2                   SBS_CCCSR_RDY2_Msk                   /*!< VDDIO compensation cell ready flag */
10747 
10748 /******************  Bit definition for SBS_CCVALR register  ****************/
10749 #define SBS_CCVALR_ANSRC1_Pos            (0U)
10750 #define SBS_CCVALR_ANSRC1_Msk            (0xFUL << SBS_CCVALR_ANSRC1_Pos)     /*!< 0x0000000F */
10751 #define SBS_CCVALR_ANSRC1                SBS_CCVALR_ANSRC1_Msk                /*!< NMOS compensation value */
10752 #define SBS_CCVALR_APSRC1_Pos            (4U)
10753 #define SBS_CCVALR_APSRC1_Msk            (0xFUL << SBS_CCVALR_APSRC1_Pos)     /*!< 0x000000F0 */
10754 #define SBS_CCVALR_APSRC1                SBS_CCVALR_APSRC1_Msk                /*!< PMOS compensation value */
10755 #define SBS_CCVALR_ANSRC2_Pos            (8U)
10756 #define SBS_CCVALR_ANSRC2_Msk            (0xFUL << SBS_CCVALR_ANSRC2_Pos)     /*!< 0x00000F00 */
10757 #define SBS_CCVALR_ANSRC2                SBS_CCVALR_ANSRC2_Msk                /*!< NMOS compensation value */
10758 #define SBS_CCVALR_APSRC2_Pos            (12U)
10759 #define SBS_CCVALR_APSRC2_Msk            (0xFUL << SBS_CCVALR_APSRC2_Pos)     /*!< 0x0000F000 */
10760 #define SBS_CCVALR_APSRC2                SBS_CCVALR_APSRC2_Msk                /*!< PMOS compensation value */
10761 
10762 /******************  Bit definition for SBS_CCSWCR register  ****************/
10763 #define SBS_CCSWCR_SW_ANSRC1_Pos         (0U)
10764 #define SBS_CCSWCR_SW_ANSRC1_Msk         (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos)  /*!< 0x0000000F */
10765 #define SBS_CCSWCR_SW_ANSRC1             SBS_CCSWCR_SW_ANSRC1_Msk             /*!< NMOS compensation code for VDD Power Rail */
10766 #define SBS_CCSWCR_SW_APSRC1_Pos         (4U)
10767 #define SBS_CCSWCR_SW_APSRC1_Msk         (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos)  /*!< 0x000000F0 */
10768 #define SBS_CCSWCR_SW_APSRC1             SBS_CCSWCR_SW_APSRC1_Msk             /*!< PMOS compensation code for VDD Power Rail */
10769 #define SBS_CCSWCR_SW_ANSRC2_Pos         (8U)
10770 #define SBS_CCSWCR_SW_ANSRC2_Msk         (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos)  /*!< 0x00000F00 */
10771 #define SBS_CCSWCR_SW_ANSRC2             SBS_CCSWCR_SW_ANSRC2_Msk             /*!< NMOS compensation code for VDDIO Power Rail */
10772 #define SBS_CCSWCR_SW_APSRC2_Pos         (12U)
10773 #define SBS_CCSWCR_SW_APSRC2_Msk         (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos)  /*!< 0x0000F000 */
10774 #define SBS_CCSWCR_SW_APSRC2             SBS_CCSWCR_SW_APSRC2_Msk             /*!< PMOS compensation code for VDDIO Power Rail */
10775 
10776 /******************  Bit definition for SBS_CFGR2 register  ****************/
10777 #define SBS_CFGR2_CLL_Pos                (0U)
10778 #define SBS_CFGR2_CLL_Msk                (0x1UL << SBS_CFGR2_CLL_Pos)   /*!< 0x00000001 */
10779 #define SBS_CFGR2_CLL                    SBS_CFGR2_CLL_Msk              /*!< Core Lockup Lock */
10780 #define SBS_CFGR2_SEL_Pos                (1U)
10781 #define SBS_CFGR2_SEL_Msk                (0x1UL << SBS_CFGR2_SEL_Pos)   /*!< 0x00000002 */
10782 #define SBS_CFGR2_SEL                    SBS_CFGR2_SEL_Msk              /*!< SRAM ECC Lock */
10783 #define SBS_CFGR2_PVDL_Pos               (2U)
10784 #define SBS_CFGR2_PVDL_Msk               (0x1UL << SBS_CFGR2_PVDL_Pos)  /*!< 0x00000004 */
10785 #define SBS_CFGR2_PVDL                   SBS_CFGR2_PVDL_Msk             /*!<  PVD Lock */
10786 #define SBS_CFGR2_ECCL_Pos               (3U)
10787 #define SBS_CFGR2_ECCL_Msk               (0x1UL << SBS_CFGR2_ECCL_Pos)  /*!< 0x00000008 */
10788 #define SBS_CFGR2_ECCL                   SBS_CFGR2_ECCL_Msk             /*!< Flash ECC Lock*/
10789 
10790 /******************  Bit definition for SBS_CNSLCKR register  **************/
10791 #define SBS_CNSLCKR_LOCKNSVTOR_Pos       (0U)
10792 #define SBS_CNSLCKR_LOCKNSVTOR_Msk       (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */
10793 #define SBS_CNSLCKR_LOCKNSVTOR           SBS_CNSLCKR_LOCKNSVTOR_Msk            /*!< Disable VTOR_NS register writes by SW or debug agent */
10794 #define SBS_CNSLCKR_LOCKNSMPU_Pos        (1U)
10795 #define SBS_CNSLCKR_LOCKNSMPU_Msk        (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos)  /*!< 0x00000002 */
10796 #define SBS_CNSLCKR_LOCKNSMPU            SBS_CNSLCKR_LOCKNSMPU_Msk             /*!< Disable Non-Secure MPU registers writes by SW or debug agent */
10797 
10798 /******************  Bit definition for SBS_ECCNMIR register  ***************/
10799 #define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos   (0U)
10800 #define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk   (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos)   /*!< 0x00000001 */
10801 #define SBS_ECCNMIR_ECCNMI_MASK_EN       SBS_ECCNMIR_ECCNMI_MASK_EN_Msk              /*!< Disable NMI in case of double ECC error in flash interface */
10802 
10803 /*****************************************************************************/
10804 /*                                                                           */
10805 /*                        Global TrustZone Control                           */
10806 /*                                                                           */
10807 /*****************************************************************************/
10808 
10809 /*******************  Bits definition for GTZC_TZSC_MPCWM_CFGR register  **********/
10810 #define GTZC_TZSC_MPCWM_CFGR_SREN_Pos       (0U)
10811 #define GTZC_TZSC_MPCWM_CFGR_SREN_Msk       (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos)
10812 #define GTZC_TZSC_MPCWM_CFGR_SREN           GTZC_TZSC_MPCWM_CFGR_SREN_Msk
10813 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos     (1U)
10814 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk     (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos)
10815 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK         GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk
10816 #define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos       (9U)
10817 #define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk       (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos)
10818 #define GTZC_TZSC_MPCWM_CFGR_PRIV           GTZC_TZSC_MPCWM_CFGR_PRIV_Msk
10819 
10820 /*******************  Bits definition for GTZC_TZSC_MPCWMR register  **************/
10821 #define GTZC_TZSC_MPCWMR_SUBZ_START_Pos     (0U)
10822 #define GTZC_TZSC_MPCWMR_SUBZ_START_Msk     (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos)
10823 #define GTZC_TZSC_MPCWMR_SUBZ_START         GTZC_TZSC_MPCWMR_SUBZ_START_Msk
10824 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos    (16U)
10825 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk    (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos)
10826 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH        GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk
10827 
10828 /*******  Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers  *****/
10829 
10830 /***************  Bits definition for register x=1 (TZSC1) *************/
10831 #define GTZC_CFGR1_TIM2_Pos                 (0U)
10832 #define GTZC_CFGR1_TIM2_Msk                 (0x01UL << GTZC_CFGR1_TIM2_Pos)
10833 #define GTZC_CFGR1_TIM3_Pos                 (1U)
10834 #define GTZC_CFGR1_TIM3_Msk                 (0x01UL << GTZC_CFGR1_TIM3_Pos)
10835 #define GTZC_CFGR1_TIM6_Pos                 (4U)
10836 #define GTZC_CFGR1_TIM6_Msk                 (0x01UL << GTZC_CFGR1_TIM6_Pos)
10837 #define GTZC_CFGR1_TIM7_Pos                 (5U)
10838 #define GTZC_CFGR1_TIM7_Msk                 (0x01UL << GTZC_CFGR1_TIM7_Pos)
10839 #define GTZC_CFGR1_WWDG_Pos                 (9U)
10840 #define GTZC_CFGR1_WWDG_Msk                 (0x01UL << GTZC_CFGR1_WWDG_Pos)
10841 #define GTZC_CFGR1_IWDG_Pos                 (10U)
10842 #define GTZC_CFGR1_IWDG_Msk                 (0x01UL << GTZC_CFGR1_IWDG_Pos)
10843 #define GTZC_CFGR1_SPI2_Pos                 (11U)
10844 #define GTZC_CFGR1_SPI2_Msk                 (0x01UL << GTZC_CFGR1_SPI2_Pos)
10845 #define GTZC_CFGR1_SPI3_Pos                 (12U)
10846 #define GTZC_CFGR1_SPI3_Msk                 (0x01UL << GTZC_CFGR1_SPI3_Pos)
10847 #define GTZC_CFGR1_USART2_Pos               (13U)
10848 #define GTZC_CFGR1_USART2_Msk               (0x01UL << GTZC_CFGR1_USART2_Pos)
10849 #define GTZC_CFGR1_USART3_Pos               (14U)
10850 #define GTZC_CFGR1_USART3_Msk               (0x01UL << GTZC_CFGR1_USART3_Pos)
10851 #define GTZC_CFGR1_I2C1_Pos                 (17U)
10852 #define GTZC_CFGR1_I2C1_Msk                 (0x01UL << GTZC_CFGR1_I2C1_Pos)
10853 #define GTZC_CFGR1_I2C2_Pos                 (18U)
10854 #define GTZC_CFGR1_I2C2_Msk                 (0x01UL << GTZC_CFGR1_I2C2_Pos)
10855 #define GTZC_CFGR1_I3C1_Pos                 (19U)
10856 #define GTZC_CFGR1_I3C1_Msk                 (0x01UL << GTZC_CFGR1_I3C1_Pos)
10857 #define GTZC_CFGR1_CRS_Pos                  (20U)
10858 #define GTZC_CFGR1_CRS_Msk                  (0x01UL << GTZC_CFGR1_CRS_Pos)
10859 #define GTZC_CFGR1_DAC1_Pos                 (25U)
10860 #define GTZC_CFGR1_DAC1_Msk                 (0x01UL << GTZC_CFGR1_DAC1_Pos)
10861 #define GTZC_CFGR1_DTS_Pos                  (30U)
10862 #define GTZC_CFGR1_DTS_Msk                  (0x01UL << GTZC_CFGR1_DTS_Pos)
10863 #define GTZC_CFGR1_LPTIM2_Pos               (31U)
10864 #define GTZC_CFGR1_LPTIM2_Msk               (0x01UL << GTZC_CFGR1_LPTIM2_Pos)
10865 
10866 /***************  Bits definition for register x=2 (TZSC1) *************/
10867 #define GTZC_CFGR2_FDCAN1_Pos               (0U)
10868 #define GTZC_CFGR2_FDCAN1_Msk               (0x01UL << GTZC_CFGR2_FDCAN1_Pos)
10869 #define GTZC_CFGR2_OPAMP_Pos                (3U)
10870 #define GTZC_CFGR2_OPAMP_Msk                (0x01UL << GTZC_CFGR2_OPAMP_Pos)
10871 #define GTZC_CFGR2_COMP_Pos                 (4U)
10872 #define GTZC_CFGR2_COMP_Msk                 (0x01UL << GTZC_CFGR2_COMP_Pos)
10873 #define GTZC_CFGR2_TIM1_Pos                 (8U)
10874 #define GTZC_CFGR2_TIM1_Msk                 (0x01UL << GTZC_CFGR2_TIM1_Pos)
10875 #define GTZC_CFGR2_SPI1_Pos                 (9U)
10876 #define GTZC_CFGR2_SPI1_Msk                 (0x01UL << GTZC_CFGR2_SPI1_Pos)
10877 #define GTZC_CFGR2_USART1_Pos               (11U)
10878 #define GTZC_CFGR2_USART1_Msk               (0x01UL << GTZC_CFGR2_USART1_Pos)
10879 #define GTZC_CFGR2_USB_Pos                  (19U)
10880 #define GTZC_CFGR2_USB_Msk                  (0x01UL << GTZC_CFGR2_USB_Pos)
10881 #define GTZC_CFGR2_LPUART1_Pos              (25U)
10882 #define GTZC_CFGR2_LPUART1_Msk              (0x01UL << GTZC_CFGR2_LPUART1_Pos)
10883 #define GTZC_CFGR2_LPTIM1_Pos               (28U)
10884 #define GTZC_CFGR2_LPTIM1_Msk               (0x01UL << GTZC_CFGR2_LPTIM1_Pos)
10885 
10886 /***************  Bits definition for register x=3 (TZSC1) *************/
10887 #define GTZC_CFGR3_I3C2_Pos                 (2U)
10888 #define GTZC_CFGR3_I3C2_Msk                 (0x01UL << GTZC_CFGR3_I3C2_Pos)
10889 #define GTZC_CFGR3_CRC_Pos                  (8U)
10890 #define GTZC_CFGR3_CRC_Msk                  (0x01UL << GTZC_CFGR3_CRC_Pos)
10891 #define GTZC_CFGR3_ICACHE_REG_Pos           (12U)
10892 #define GTZC_CFGR3_ICACHE_REG_Msk           (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos)
10893 #define GTZC_CFGR3_ADC_Pos                  (14U)
10894 #define GTZC_CFGR3_ADC_Msk                  (0x01UL << GTZC_CFGR3_ADC_Pos)
10895 #define GTZC_CFGR3_HASH_Pos                 (17U)
10896 #define GTZC_CFGR3_HASH_Msk                 (0x01UL << GTZC_CFGR3_HASH_Pos)
10897 #define GTZC_CFGR3_RNG_Pos                  (18U)
10898 #define GTZC_CFGR3_RNG_Msk                  (0x01UL << GTZC_CFGR3_RNG_Pos)
10899 #define GTZC_CFGR3_RAMCFG_Pos               (26U)
10900 #define GTZC_CFGR3_RAMCFG_Msk               (0x01UL << GTZC_CFGR3_RAMCFG_Pos)
10901 
10902 /***************  Bits definition for register x=4 (TZSC1) *************/
10903 #define GTZC_CFGR4_GPDMA1_Pos               (0U)
10904 #define GTZC_CFGR4_GPDMA1_Msk               (0x01UL << GTZC_CFGR4_GPDMA1_Pos)
10905 #define GTZC_CFGR4_GPDMA2_Pos               (1U)
10906 #define GTZC_CFGR4_GPDMA2_Msk               (0x01UL << GTZC_CFGR4_GPDMA2_Pos)
10907 #define GTZC_CFGR4_FLASH_Pos                (2U)
10908 #define GTZC_CFGR4_FLASH_Msk                (0x01UL << GTZC_CFGR4_FLASH_Pos)
10909 #define GTZC_CFGR4_FLASH_REG_Pos            (3U)
10910 #define GTZC_CFGR4_FLASH_REG_Msk            (0x01UL << GTZC_CFGR4_FLASH_REG_Pos)
10911 
10912 #define GTZC_CFGR4_SBS_Pos                  (6U)
10913 #define GTZC_CFGR4_SBS_Msk                  (0x01UL << GTZC_CFGR4_SBS_Pos)
10914 #define GTZC_CFGR4_RTC_Pos                  (7U)
10915 #define GTZC_CFGR4_RTC_Msk                  (0x01UL << GTZC_CFGR4_RTC_Pos)
10916 #define GTZC_CFGR4_TAMP_Pos                 (8U)
10917 #define GTZC_CFGR4_TAMP_Msk                 (0x01UL << GTZC_CFGR4_TAMP_Pos)
10918 #define GTZC_CFGR4_PWR_Pos                  (9U)
10919 #define GTZC_CFGR4_PWR_Msk                  (0x01UL << GTZC_CFGR4_PWR_Pos)
10920 #define GTZC_CFGR4_RCC_Pos                  (10U)
10921 #define GTZC_CFGR4_RCC_Msk                  (0x01UL << GTZC_CFGR4_RCC_Pos)
10922 #define GTZC_CFGR4_EXTI_Pos                 (11U)
10923 #define GTZC_CFGR4_EXTI_Msk                 (0x01UL << GTZC_CFGR4_EXTI_Pos)
10924 #define GTZC_CFGR4_TZSC_Pos                 (16U)
10925 #define GTZC_CFGR4_TZSC_Msk                 (0x01UL << GTZC_CFGR4_TZSC_Pos)
10926 #define GTZC_CFGR4_BKPSRAM_Pos              (20U)
10927 #define GTZC_CFGR4_BKPSRAM_Msk              (0x01UL << GTZC_CFGR4_BKPSRAM_Pos)
10928 #define GTZC_CFGR4_SRAM1_Pos                (24U)
10929 #define GTZC_CFGR4_SRAM1_Msk                (0x01UL << GTZC_CFGR4_SRAM1_Pos)
10930 #define GTZC_CFGR4_MPCBB1_REG_Pos           (25U)
10931 #define GTZC_CFGR4_MPCBB1_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
10932 #define GTZC_CFGR4_SRAM2_Pos                (26U)
10933 #define GTZC_CFGR4_SRAM2_Msk                (0x01UL << GTZC_CFGR4_SRAM2_Pos)
10934 #define GTZC_CFGR4_MPCBB2_REG_Pos           (27U)
10935 #define GTZC_CFGR4_MPCBB2_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos)
10936 
10937 
10938 
10939 /*******************  Bits definition for GTZC_TZSC_PRIVCFGR1 register  ***************/
10940 #define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos           GTZC_CFGR1_TIM2_Pos
10941 #define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk           GTZC_CFGR1_TIM2_Msk
10942 #define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos           GTZC_CFGR1_TIM3_Pos
10943 #define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk           GTZC_CFGR1_TIM3_Msk
10944 #define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos           GTZC_CFGR1_TIM6_Pos
10945 #define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk           GTZC_CFGR1_TIM6_Msk
10946 #define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos           GTZC_CFGR1_TIM7_Pos
10947 #define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk           GTZC_CFGR1_TIM7_Msk
10948 #define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos           GTZC_CFGR1_WWDG_Pos
10949 #define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk           GTZC_CFGR1_WWDG_Msk
10950 #define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos           GTZC_CFGR1_IWDG_Pos
10951 #define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk           GTZC_CFGR1_IWDG_Msk
10952 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos           GTZC_CFGR1_SPI2_Pos
10953 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk           GTZC_CFGR1_SPI2_Msk
10954 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos           GTZC_CFGR1_SPI3_Pos
10955 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk           GTZC_CFGR1_SPI3_Msk
10956 #define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos           GTZC_CFGR1_I2C1_Pos
10957 #define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk           GTZC_CFGR1_I2C1_Msk
10958 #define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos           GTZC_CFGR1_I2C2_Pos
10959 #define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk           GTZC_CFGR1_I2C2_Msk
10960 #define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos           GTZC_CFGR1_I3C1_Pos
10961 #define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk           GTZC_CFGR1_I3C1_Msk
10962 #define GTZC_TZSC1_PRIVCFGR1_CRS_Pos            GTZC_CFGR1_CRS_Pos
10963 #define GTZC_TZSC1_PRIVCFGR1_CRS_Msk            GTZC_CFGR1_CRS_Msk
10964 #define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos           GTZC_CFGR1_DAC1_Pos
10965 #define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk           GTZC_CFGR1_DAC1_Msk
10966 #define GTZC_TZSC1_PRIVCFGR1_DTS_Pos            GTZC_CFGR1_DTS_Pos
10967 #define GTZC_TZSC1_PRIVCFGR1_DTS_Msk            GTZC_CFGR1_DTS_Msk
10968 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos         GTZC_CFGR1_LPTIM2_Pos
10969 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk         GTZC_CFGR1_LPTIM2_Msk
10970 
10971 /*******************  Bits definition for GTZC_TZSC_PRIVCFGR2 register  ***************/
10972 #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos         GTZC_CFGR2_FDCAN1_Pos
10973 #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk         GTZC_CFGR2_FDCAN1_Msk
10974 #define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos           GTZC_CFGR2_TIM1_Pos
10975 #define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk           GTZC_CFGR2_TIM1_Msk
10976 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos           GTZC_CFGR2_SPI1_Pos
10977 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk           GTZC_CFGR2_SPI1_Msk
10978 #define GTZC_TZSC1_PRIVCFGR2_USART1_Pos         GTZC_CFGR2_USART1_Pos
10979 #define GTZC_TZSC1_PRIVCFGR2_USART1_Msk         GTZC_CFGR2_USART1_Msk
10980 #define GTZC_TZSC1_PRIVCFGR2_USB_Pos            GTZC_CFGR2_USB_Pos
10981 #define GTZC_TZSC1_PRIVCFGR2_USB_Msk            GTZC_CFGR2_USB_Msk
10982 #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos        GTZC_CFGR2_LPUART1_Pos
10983 #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk        GTZC_CFGR2_LPUART1_Msk
10984 #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos         GTZC_CFGR2_LPTIM1_Pos
10985 #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk         GTZC_CFGR2_LPTIM1_Msk
10986 
10987 /*******************  Bits definition for GTZC_TZSC_PRIVCFGR3 register  ***************/
10988 #define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos           GTZC_CFGR3_I3C2_Pos
10989 #define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk           GTZC_CFGR3_I3C2_Msk
10990 #define GTZC_TZSC1_PRIVCFGR3_CRC_Pos            GTZC_CFGR3_CRC_Pos
10991 #define GTZC_TZSC1_PRIVCFGR3_CRC_Msk            GTZC_CFGR3_CRC_Msk
10992 #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos     GTZC_CFGR3_ICACHE_REG_Pos
10993 #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk     GTZC_CFGR3_ICACHE_REG_Msk
10994 #define GTZC_TZSC1_PRIVCFGR3_ADC_Pos            GTZC_CFGR3_ADC_Pos
10995 #define GTZC_TZSC1_PRIVCFGR3_ADC_Msk            GTZC_CFGR3_ADC_Msk
10996 #define GTZC_TZSC1_PRIVCFGR3_HASH_Pos           GTZC_CFGR3_HASH_Pos
10997 #define GTZC_TZSC1_PRIVCFGR3_HASH_Msk           GTZC_CFGR3_HASH_Msk
10998 #define GTZC_TZSC1_PRIVCFGR3_RNG_Pos            GTZC_CFGR3_RNG_Pos
10999 #define GTZC_TZSC1_PRIVCFGR3_RNG_Msk            GTZC_CFGR3_RNG_Msk
11000 #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos         GTZC_CFGR3_RAMCFG_Pos
11001 #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk         GTZC_CFGR3_RAMCFG_Msk
11002 
11003 
11004 
11005 
11006 
11007 /******************************************************************************/
11008 /*                                                                            */
11009 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
11010 /*                                                                            */
11011 /******************************************************************************/
11012 #define USART_DMAREQUESTS_SW_WA
11013 /******************  Bit definition for USART_CR1 register  *******************/
11014 #define USART_CR1_UE_Pos                    (0U)
11015 #define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
11016 #define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
11017 #define USART_CR1_UESM_Pos                  (1U)
11018 #define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
11019 #define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
11020 #define USART_CR1_RE_Pos                    (2U)
11021 #define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
11022 #define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
11023 #define USART_CR1_TE_Pos                    (3U)
11024 #define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
11025 #define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
11026 #define USART_CR1_IDLEIE_Pos                (4U)
11027 #define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
11028 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
11029 #define USART_CR1_RXNEIE_Pos                (5U)
11030 #define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
11031 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
11032 #define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
11033 #define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
11034 #define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
11035 #define USART_CR1_TCIE_Pos                  (6U)
11036 #define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
11037 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
11038 #define USART_CR1_TXEIE_Pos                 (7U)
11039 #define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
11040 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
11041 #define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
11042 #define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
11043 #define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
11044 #define USART_CR1_PEIE_Pos                  (8U)
11045 #define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
11046 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
11047 #define USART_CR1_PS_Pos                    (9U)
11048 #define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
11049 #define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
11050 #define USART_CR1_PCE_Pos                   (10U)
11051 #define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
11052 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
11053 #define USART_CR1_WAKE_Pos                  (11U)
11054 #define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
11055 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
11056 #define USART_CR1_M_Pos                     (12U)
11057 #define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)          /*!< 0x10001000 */
11058 #define USART_CR1_M                         USART_CR1_M_Msk                         /*!< Word length */
11059 #define USART_CR1_M0_Pos                    (12U)
11060 #define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
11061 #define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
11062 #define USART_CR1_MME_Pos                   (13U)
11063 #define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
11064 #define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
11065 #define USART_CR1_CMIE_Pos                  (14U)
11066 #define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
11067 #define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match interrupt enable */
11068 #define USART_CR1_OVER8_Pos                 (15U)
11069 #define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
11070 #define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
11071 #define USART_CR1_DEDT_Pos                  (16U)
11072 #define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
11073 #define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
11074 #define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
11075 #define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
11076 #define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
11077 #define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
11078 #define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
11079 #define USART_CR1_DEAT_Pos                  (21U)
11080 #define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
11081 #define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
11082 #define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
11083 #define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
11084 #define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
11085 #define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
11086 #define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
11087 #define USART_CR1_RTOIE_Pos                 (26U)
11088 #define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
11089 #define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out interrupt enable */
11090 #define USART_CR1_EOBIE_Pos                 (27U)
11091 #define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
11092 #define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block interrupt enable */
11093 #define USART_CR1_M1_Pos                    (28U)
11094 #define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
11095 #define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
11096 #define USART_CR1_FIFOEN_Pos                (29U)
11097 #define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
11098 #define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
11099 #define USART_CR1_TXFEIE_Pos                (30U)
11100 #define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
11101 #define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TXFIFO empty interrupt enable */
11102 #define USART_CR1_RXFFIE_Pos                (31U)
11103 #define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
11104 #define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RXFIFO Full interrupt enable */
11105 
11106 /******************  Bit definition for USART_CR2 register  *******************/
11107 #define USART_CR2_SLVEN_Pos                 (0U)
11108 #define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
11109 #define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
11110 #define USART_CR2_DIS_NSS_Pos               (3U)
11111 #define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
11112 #define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
11113 #define USART_CR2_ADDM7_Pos                 (4U)
11114 #define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
11115 #define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
11116 #define USART_CR2_LBDL_Pos                  (5U)
11117 #define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
11118 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
11119 #define USART_CR2_LBDIE_Pos                 (6U)
11120 #define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
11121 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
11122 #define USART_CR2_LBCL_Pos                  (8U)
11123 #define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
11124 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
11125 #define USART_CR2_CPHA_Pos                  (9U)
11126 #define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
11127 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
11128 #define USART_CR2_CPOL_Pos                  (10U)
11129 #define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
11130 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
11131 #define USART_CR2_CLKEN_Pos                 (11U)
11132 #define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
11133 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
11134 #define USART_CR2_STOP_Pos                  (12U)
11135 #define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
11136 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
11137 #define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
11138 #define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
11139 #define USART_CR2_LINEN_Pos                 (14U)
11140 #define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
11141 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
11142 #define USART_CR2_SWAP_Pos                  (15U)
11143 #define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
11144 #define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
11145 #define USART_CR2_RXINV_Pos                 (16U)
11146 #define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
11147 #define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
11148 #define USART_CR2_TXINV_Pos                 (17U)
11149 #define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
11150 #define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
11151 #define USART_CR2_DATAINV_Pos               (18U)
11152 #define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
11153 #define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
11154 #define USART_CR2_MSBFIRST_Pos              (19U)
11155 #define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
11156 #define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
11157 #define USART_CR2_ABREN_Pos                 (20U)
11158 #define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
11159 #define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
11160 #define USART_CR2_ABRMODE_Pos               (21U)
11161 #define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
11162 #define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
11163 #define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
11164 #define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
11165 #define USART_CR2_RTOEN_Pos                 (23U)
11166 #define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
11167 #define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
11168 #define USART_CR2_ADD_Pos                   (24U)
11169 #define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
11170 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */
11171 
11172 /******************  Bit definition for USART_CR3 register  *******************/
11173 #define USART_CR3_EIE_Pos                   (0U)
11174 #define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
11175 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
11176 #define USART_CR3_IREN_Pos                  (1U)
11177 #define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
11178 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
11179 #define USART_CR3_IRLP_Pos                  (2U)
11180 #define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
11181 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
11182 #define USART_CR3_HDSEL_Pos                 (3U)
11183 #define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
11184 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
11185 #define USART_CR3_NACK_Pos                  (4U)
11186 #define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
11187 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
11188 #define USART_CR3_SCEN_Pos                  (5U)
11189 #define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
11190 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
11191 #define USART_CR3_DMAR_Pos                  (6U)
11192 #define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
11193 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
11194 #define USART_CR3_DMAT_Pos                  (7U)
11195 #define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
11196 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
11197 #define USART_CR3_RTSE_Pos                  (8U)
11198 #define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
11199 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
11200 #define USART_CR3_CTSE_Pos                  (9U)
11201 #define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
11202 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
11203 #define USART_CR3_CTSIE_Pos                 (10U)
11204 #define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
11205 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
11206 #define USART_CR3_ONEBIT_Pos                (11U)
11207 #define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
11208 #define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
11209 #define USART_CR3_OVRDIS_Pos                (12U)
11210 #define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
11211 #define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
11212 #define USART_CR3_DDRE_Pos                  (13U)
11213 #define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
11214 #define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
11215 #define USART_CR3_DEM_Pos                   (14U)
11216 #define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
11217 #define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
11218 #define USART_CR3_DEP_Pos                   (15U)
11219 #define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
11220 #define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
11221 #define USART_CR3_SCARCNT_Pos               (17U)
11222 #define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
11223 #define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
11224 #define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
11225 #define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
11226 #define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
11227 #define USART_CR3_WUS_Pos                   (20U)
11228 #define USART_CR3_WUS_Msk                   (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
11229 #define USART_CR3_WUS                       USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
11230 #define USART_CR3_WUS_0                     (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
11231 #define USART_CR3_WUS_1                     (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
11232 #define USART_CR3_WUFIE_Pos                 (22U)
11233 #define USART_CR3_WUFIE_Msk                 (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
11234 #define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
11235 #define USART_CR3_TXFTIE_Pos                (23U)
11236 #define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
11237 #define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TXFIFO threshold interrupt enable */
11238 #define USART_CR3_TCBGTIE_Pos               (24U)
11239 #define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
11240 #define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
11241 #define USART_CR3_RXFTCFG_Pos               (25U)
11242 #define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
11243 #define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RXFIFO FIFO threshold configuration */
11244 #define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
11245 #define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
11246 #define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
11247 #define USART_CR3_RXFTIE_Pos                (28U)
11248 #define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
11249 #define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RXFIFO threshold interrupt enable */
11250 #define USART_CR3_TXFTCFG_Pos               (29U)
11251 #define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
11252 #define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TXFIFO threshold configuration */
11253 #define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
11254 #define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
11255 #define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
11256 
11257 /******************  Bit definition for USART_BRR register  *******************/
11258 #define USART_BRR_LPUART_Pos                (0U)
11259 #define USART_BRR_LPUART_Msk                (0xFFFFFUL << USART_BRR_LPUART_Pos)     /*!< 0x000FFFFF */
11260 #define USART_BRR_LPUART                    USART_BRR_LPUART_Msk                    /*!< LPUART Baud rate register [19:0] */
11261 #define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
11262 
11263 /******************  Bit definition for USART_GTPR register  ******************/
11264 #define USART_GTPR_PSC_Pos                  (0U)
11265 #define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
11266 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
11267 #define USART_GTPR_GT_Pos                   (8U)
11268 #define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
11269 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
11270 
11271 /*******************  Bit definition for USART_RTOR register  *****************/
11272 #define USART_RTOR_RTO_Pos                  (0U)
11273 #define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
11274 #define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Time Out Value */
11275 #define USART_RTOR_BLEN_Pos                 (24U)
11276 #define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
11277 #define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */
11278 
11279 /*******************  Bit definition for USART_RQR register  ******************/
11280 #define USART_RQR_ABRRQ                     ((uint16_t)0x0001)                      /*!< Auto-Baud Rate Request */
11281 #define USART_RQR_SBKRQ                     ((uint16_t)0x0002)                      /*!< Send Break Request */
11282 #define USART_RQR_MMRQ                      ((uint16_t)0x0004)                      /*!< Mute Mode Request */
11283 #define USART_RQR_RXFRQ                     ((uint16_t)0x0008)                      /*!< Receive Data flush Request */
11284 #define USART_RQR_TXFRQ                     ((uint16_t)0x0010)                      /*!< Transmit data flush Request */
11285 
11286 /*******************  Bit definition for USART_ISR register  ******************/
11287 #define USART_ISR_PE_Pos                    (0U)
11288 #define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
11289 #define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
11290 #define USART_ISR_FE_Pos                    (1U)
11291 #define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
11292 #define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
11293 #define USART_ISR_NE_Pos                    (2U)
11294 #define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
11295 #define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise detected Flag */
11296 #define USART_ISR_ORE_Pos                   (3U)
11297 #define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
11298 #define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
11299 #define USART_ISR_IDLE_Pos                  (4U)
11300 #define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
11301 #define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
11302 #define USART_ISR_RXNE_Pos                  (5U)
11303 #define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
11304 #define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
11305 #define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
11306 #define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
11307 #define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
11308 #define USART_ISR_TC_Pos                    (6U)
11309 #define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
11310 #define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
11311 #define USART_ISR_TXE_Pos                   (7U)
11312 #define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
11313 #define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
11314 #define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
11315 #define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
11316 #define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
11317 #define USART_ISR_LBDF_Pos                  (8U)
11318 #define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
11319 #define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
11320 #define USART_ISR_CTSIF_Pos                 (9U)
11321 #define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
11322 #define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt flag */
11323 #define USART_ISR_CTS_Pos                   (10U)
11324 #define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
11325 #define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS flag */
11326 #define USART_ISR_RTOF_Pos                  (11U)
11327 #define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
11328 #define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Time Out */
11329 #define USART_ISR_EOBF_Pos                  (12U)
11330 #define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
11331 #define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
11332 #define USART_ISR_UDR_Pos                   (13U)
11333 #define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
11334 #define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI slave underrun error flag */
11335 #define USART_ISR_ABRE_Pos                  (14U)
11336 #define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
11337 #define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
11338 #define USART_ISR_ABRF_Pos                  (15U)
11339 #define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
11340 #define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
11341 #define USART_ISR_BUSY_Pos                  (16U)
11342 #define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
11343 #define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
11344 #define USART_ISR_CMF_Pos                   (17U)
11345 #define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
11346 #define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
11347 #define USART_ISR_SBKF_Pos                  (18U)
11348 #define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
11349 #define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
11350 #define USART_ISR_RWU_Pos                   (19U)
11351 #define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
11352 #define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
11353 #define USART_ISR_WUF_Pos                   (20U)
11354 #define USART_ISR_WUF_Msk                   (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
11355 #define USART_ISR_WUF                       USART_ISR_WUF_Msk                       /*!< Wake Up from low power mode Flag */
11356 #define USART_ISR_TEACK_Pos                 (21U)
11357 #define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
11358 #define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
11359 #define USART_ISR_REACK_Pos                 (22U)
11360 #define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
11361 #define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
11362 #define USART_ISR_TXFE_Pos                  (23U)
11363 #define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
11364 #define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TXFIFO Empty */
11365 #define USART_ISR_RXFF_Pos                  (24U)
11366 #define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
11367 #define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RXFIFO Full */
11368 #define USART_ISR_TCBGT_Pos                 (25U)
11369 #define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
11370 #define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
11371 #define USART_ISR_RXFT_Pos                  (26U)
11372 #define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
11373 #define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RXFIFO threshold flag */
11374 #define USART_ISR_TXFT_Pos                  (27U)
11375 #define USART_ISR_TXFT_Msk                  (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
11376 #define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TXFIFO threshold flag */
11377 
11378 /*******************  Bit definition for USART_ICR register  ******************/
11379 #define USART_ICR_PECF_Pos                  (0U)
11380 #define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
11381 #define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
11382 #define USART_ICR_FECF_Pos                  (1U)
11383 #define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
11384 #define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
11385 #define USART_ICR_NECF_Pos                  (2U)
11386 #define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
11387 #define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise detected Clear Flag */
11388 #define USART_ICR_ORECF_Pos                 (3U)
11389 #define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
11390 #define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
11391 #define USART_ICR_IDLECF_Pos                (4U)
11392 #define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
11393 #define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
11394 #define USART_ICR_TXFECF_Pos                (5U)
11395 #define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
11396 #define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TXFIFO empty Clear flag */
11397 #define USART_ICR_TCCF_Pos                  (6U)
11398 #define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
11399 #define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
11400 #define USART_ICR_TCBGTCF_Pos               (7U)
11401 #define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
11402 #define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
11403 #define USART_ICR_LBDCF_Pos                 (8U)
11404 #define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
11405 #define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
11406 #define USART_ICR_CTSCF_Pos                 (9U)
11407 #define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
11408 #define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
11409 #define USART_ICR_RTOCF_Pos                 (11U)
11410 #define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
11411 #define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
11412 #define USART_ICR_EOBCF_Pos                 (12U)
11413 #define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
11414 #define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
11415 #define USART_ICR_UDRCF_Pos                 (13U)
11416 #define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
11417 #define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
11418 #define USART_ICR_CMCF_Pos                  (17U)
11419 #define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
11420 #define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
11421 #define USART_ICR_WUCF_Pos                  (20U)
11422 #define USART_ICR_WUCF_Msk                  (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
11423 #define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */
11424 
11425 /*******************  Bit definition for USART_RDR register  ******************/
11426 #define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */
11427 
11428 /*******************  Bit definition for USART_TDR register  ******************/
11429 #define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */
11430 
11431 /*******************  Bit definition for USART_PRESC register  ****************/
11432 #define USART_PRESC_PRESCALER_Pos           (0U)
11433 #define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
11434 #define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
11435 #define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
11436 #define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
11437 #define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
11438 #define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
11439 
11440 /*******************  Bit definition for USART_HWCFGR2 register  **************/
11441 #define USART_HWCFGR2_CFG1_Pos              (0U)
11442 #define USART_HWCFGR2_CFG1_Msk              (0xFUL << USART_HWCFGR2_CFG1_Pos)       /*!< 0x0000000F */
11443 #define USART_HWCFGR2_CFG1                  USART_HWCFGR2_CFG1_Msk                  /*!< CFG1[3:0] bits (USART hardware configuration 1) */
11444 #define USART_HWCFGR2_CFG2_Pos              (4U)
11445 #define USART_HWCFGR2_CFG2_Msk              (0xFUL << USART_HWCFGR2_CFG2_Pos)       /*!< 0x000000F0 */
11446 #define USART_HWCFGR2_CFG2                  USART_HWCFGR2_CFG2_Msk                  /*!< CFG2[7:4] bits (USART hardware configuration 2) */
11447 
11448 /*******************  Bit definition for USART_HWCFGR1 register  **************/
11449 #define USART_HWCFGR1_CFG1_Pos              (0U)
11450 #define USART_HWCFGR1_CFG1_Msk              (0xFUL << USART_HWCFGR1_CFG1_Pos)       /*!< 0x0000000F */
11451 #define USART_HWCFGR1_CFG1                  USART_HWCFGR1_CFG1_Msk                  /*!< CFG1[3:0] bits (USART hardware configuration 1) */
11452 #define USART_HWCFGR1_CFG2_Pos              (4U)
11453 #define USART_HWCFGR1_CFG2_Msk              (0xFUL << USART_HWCFGR1_CFG2_Pos)       /*!< 0x000000F0 */
11454 #define USART_HWCFGR1_CFG2                  USART_HWCFGR1_CFG2_Msk                  /*!< CFG2[7:4] bits (USART hardware configuration 2) */
11455 #define USART_HWCFGR1_CFG3_Pos              (8U)
11456 #define USART_HWCFGR1_CFG3_Msk              (0xFUL << USART_HWCFGR1_CFG3_Pos)       /*!< 0x00000F00 */
11457 #define USART_HWCFGR1_CFG3                  USART_HWCFGR1_CFG3_Msk                  /*!< CFG3[11:8] bits (USART hardware configuration 3) */
11458 #define USART_HWCFGR1_CFG4_Pos              (12U)
11459 #define USART_HWCFGR1_CFG4_Msk              (0xFUL << USART_HWCFGR1_CFG4_Pos)       /*!< 0x0000F000 */
11460 #define USART_HWCFGR1_CFG4                  USART_HWCFGR1_CFG4_Msk                  /*!< CFG4[15:12] bits (USART hardware configuration 4) */
11461 #define USART_HWCFGR1_CFG5_Pos              (16U)
11462 #define USART_HWCFGR1_CFG5_Msk              (0xFUL << USART_HWCFGR1_CFG5_Pos)       /*!< 0x000F0000 */
11463 #define USART_HWCFGR1_CFG5                  USART_HWCFGR1_CFG5_Msk                  /*!< CFG5[19:16] bits (USART hardware configuration 5) */
11464 #define USART_HWCFGR1_CFG6_Pos              (20U)
11465 #define USART_HWCFGR1_CFG6_Msk              (0xFUL << USART_HWCFGR1_CFG6_Pos)       /*!< 0x00F00000 */
11466 #define USART_HWCFGR1_CFG6                  USART_HWCFGR1_CFG6_Msk                  /*!< CFG6[23:20] bits (USART hardware configuration 6) */
11467 #define USART_HWCFGR1_CFG7_Pos              (24U)
11468 #define USART_HWCFGR1_CFG7_Msk              (0xFUL << USART_HWCFGR1_CFG7_Pos)       /*!< 0x0F000000 */
11469 #define USART_HWCFGR1_CFG7                  USART_HWCFGR1_CFG7_Msk                  /*!< CFG7[27:24] bits (USART hardware configuration 7) */
11470 #define USART_HWCFGR1_CFG8_Pos              (28U)
11471 #define USART_HWCFGR1_CFG8_Msk              (0xFUL << USART_HWCFGR1_CFG8_Pos)       /*!< 0xF0000000 */
11472 #define USART_HWCFGR1_CFG8                  USART_HWCFGR1_CFG8_Msk                  /*!< CFG8[31:28] bits (USART hardware configuration 8) */
11473 
11474 /*******************  Bit definition for USART_VERR register  *****************/
11475 #define USART_VERR_MINREV_Pos               (0U)
11476 #define USART_VERR_MINREV_Msk               (0xFUL << USART_VERR_MINREV_Pos)        /*!< 0x0000000F */
11477 #define USART_VERR_MINREV                   USART_VERR_MINREV_Msk                   /*!< MAJREV[3:0] bits (Minor revision) */
11478 #define USART_VERR_MAJREV_Pos               (4U)
11479 #define USART_VERR_MAJREV_Msk               (0xFUL << USART_VERR_MAJREV_Pos)        /*!< 0x000000F0 */
11480 #define USART_VERR_MAJREV                   USART_VERR_MAJREV_Msk                   /*!< MINREV[3:0] bits (Major revision) */
11481 
11482 /*******************  Bit definition for USART_IPIDR register  ****************/
11483 #define USART_IPIDR_ID_Pos                  (0U)
11484 #define USART_IPIDR_ID_Msk                  (0xFFFFFFFFUL << USART_IPIDR_ID_Pos)    /*!< 0xFFFFFFFF */
11485 #define USART_IPIDR_ID                      USART_IPIDR_ID_Msk                      /*!< ID[31:0] bits (Peripheral identifier) */
11486 
11487 /*******************  Bit definition for USART_SIDR register  ****************/
11488 #define USART_SIDR_ID_Pos                   (0U)
11489 #define USART_SIDR_ID_Msk                   (0xFFFFFFFFUL << USART_SIDR_ID_Pos)     /*!< 0xFFFFFFFF */
11490 #define USART_SIDR_ID                       USART_SIDR_ID_Msk                       /*!< SID[31:0] bits (Size identification) */
11491 
11492 
11493 /******************************************************************************/
11494 /*                                                                            */
11495 /*                      Inter-integrated Circuit Interface (I2C)              */
11496 /*                                                                            */
11497 /******************************************************************************/
11498 /*******************  Bit definition for I2C_CR1 register  *******************/
11499 #define I2C_CR1_PE_Pos                      (0U)
11500 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
11501 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
11502 #define I2C_CR1_TXIE_Pos                    (1U)
11503 #define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
11504 #define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
11505 #define I2C_CR1_RXIE_Pos                    (2U)
11506 #define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
11507 #define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
11508 #define I2C_CR1_ADDRIE_Pos                  (3U)
11509 #define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
11510 #define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
11511 #define I2C_CR1_NACKIE_Pos                  (4U)
11512 #define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
11513 #define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
11514 #define I2C_CR1_STOPIE_Pos                  (5U)
11515 #define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
11516 #define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
11517 #define I2C_CR1_TCIE_Pos                    (6U)
11518 #define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
11519 #define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
11520 #define I2C_CR1_ERRIE_Pos                   (7U)
11521 #define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
11522 #define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
11523 #define I2C_CR1_DNF_Pos                     (8U)
11524 #define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
11525 #define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
11526 #define I2C_CR1_ANFOFF_Pos                  (12U)
11527 #define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
11528 #define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
11529 #define I2C_CR1_SWRST_Pos                   (13U)
11530 #define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
11531 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
11532 #define I2C_CR1_TXDMAEN_Pos                 (14U)
11533 #define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
11534 #define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
11535 #define I2C_CR1_RXDMAEN_Pos                 (15U)
11536 #define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
11537 #define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
11538 #define I2C_CR1_SBC_Pos                     (16U)
11539 #define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
11540 #define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
11541 #define I2C_CR1_NOSTRETCH_Pos               (17U)
11542 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
11543 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
11544 #define I2C_CR1_WUPEN_Pos                   (18U)
11545 #define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
11546 #define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
11547 #define I2C_CR1_GCEN_Pos                    (19U)
11548 #define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
11549 #define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
11550 #define I2C_CR1_SMBHEN_Pos                  (20U)
11551 #define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
11552 #define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
11553 #define I2C_CR1_SMBDEN_Pos                  (21U)
11554 #define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
11555 #define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
11556 #define I2C_CR1_ALERTEN_Pos                 (22U)
11557 #define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
11558 #define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
11559 #define I2C_CR1_PECEN_Pos                   (23U)
11560 #define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
11561 #define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
11562 #define I2C_CR1_FMP_Pos                     (24U)
11563 #define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
11564 #define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
11565 #define I2C_CR1_ADDRACLR_Pos                (30U)
11566 #define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
11567 #define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
11568 #define I2C_CR1_STOPFACLR_Pos               (31U)
11569 #define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
11570 #define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
11571 
11572 /******************  Bit definition for I2C_CR2 register  ********************/
11573 #define I2C_CR2_SADD_Pos                    (0U)
11574 #define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
11575 #define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
11576 #define I2C_CR2_RD_WRN_Pos                  (10U)
11577 #define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
11578 #define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
11579 #define I2C_CR2_ADD10_Pos                   (11U)
11580 #define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
11581 #define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
11582 #define I2C_CR2_HEAD10R_Pos                 (12U)
11583 #define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
11584 #define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
11585 #define I2C_CR2_START_Pos                   (13U)
11586 #define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
11587 #define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
11588 #define I2C_CR2_STOP_Pos                    (14U)
11589 #define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
11590 #define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
11591 #define I2C_CR2_NACK_Pos                    (15U)
11592 #define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
11593 #define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
11594 #define I2C_CR2_NBYTES_Pos                  (16U)
11595 #define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
11596 #define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
11597 #define I2C_CR2_RELOAD_Pos                  (24U)
11598 #define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
11599 #define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
11600 #define I2C_CR2_AUTOEND_Pos                 (25U)
11601 #define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
11602 #define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
11603 #define I2C_CR2_PECBYTE_Pos                 (26U)
11604 #define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
11605 #define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */
11606 
11607 /*******************  Bit definition for I2C_OAR1 register  ******************/
11608 #define I2C_OAR1_OA1_Pos                    (0U)
11609 #define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
11610 #define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
11611 #define I2C_OAR1_OA1MODE_Pos                (10U)
11612 #define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
11613 #define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
11614 #define I2C_OAR1_OA1EN_Pos                  (15U)
11615 #define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
11616 #define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
11617 
11618 /*******************  Bit definition for I2C_OAR2 register  ******************/
11619 #define I2C_OAR2_OA2_Pos                    (1U)
11620 #define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
11621 #define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
11622 #define I2C_OAR2_OA2MSK_Pos                 (8U)
11623 #define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
11624 #define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
11625 #define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
11626 #define I2C_OAR2_OA2MASK01_Pos              (8U)
11627 #define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
11628 #define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
11629 #define I2C_OAR2_OA2MASK02_Pos              (9U)
11630 #define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
11631 #define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
11632 #define I2C_OAR2_OA2MASK03_Pos              (8U)
11633 #define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
11634 #define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
11635 #define I2C_OAR2_OA2MASK04_Pos              (10U)
11636 #define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
11637 #define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
11638 #define I2C_OAR2_OA2MASK05_Pos              (8U)
11639 #define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
11640 #define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
11641 #define I2C_OAR2_OA2MASK06_Pos              (9U)
11642 #define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
11643 #define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
11644 #define I2C_OAR2_OA2MASK07_Pos              (8U)
11645 #define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
11646 #define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
11647 #define I2C_OAR2_OA2EN_Pos                  (15U)
11648 #define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
11649 #define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
11650 
11651 /*******************  Bit definition for I2C_TIMINGR register *******************/
11652 #define I2C_TIMINGR_SCLL_Pos                (0U)
11653 #define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
11654 #define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
11655 #define I2C_TIMINGR_SCLH_Pos                (8U)
11656 #define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
11657 #define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
11658 #define I2C_TIMINGR_SDADEL_Pos              (16U)
11659 #define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
11660 #define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
11661 #define I2C_TIMINGR_SCLDEL_Pos              (20U)
11662 #define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
11663 #define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
11664 #define I2C_TIMINGR_PRESC_Pos               (28U)
11665 #define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
11666 #define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
11667 
11668 /******************* Bit definition for I2C_TIMEOUTR register *******************/
11669 #define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
11670 #define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
11671 #define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
11672 #define I2C_TIMEOUTR_TIDLE_Pos              (12U)
11673 #define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
11674 #define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
11675 #define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
11676 #define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
11677 #define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
11678 #define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
11679 #define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
11680 #define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
11681 #define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
11682 #define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
11683 #define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */
11684 
11685 /******************  Bit definition for I2C_ISR register  *********************/
11686 #define I2C_ISR_TXE_Pos                     (0U)
11687 #define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
11688 #define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
11689 #define I2C_ISR_TXIS_Pos                    (1U)
11690 #define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
11691 #define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
11692 #define I2C_ISR_RXNE_Pos                    (2U)
11693 #define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
11694 #define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
11695 #define I2C_ISR_ADDR_Pos                    (3U)
11696 #define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
11697 #define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
11698 #define I2C_ISR_NACKF_Pos                   (4U)
11699 #define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
11700 #define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
11701 #define I2C_ISR_STOPF_Pos                   (5U)
11702 #define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
11703 #define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
11704 #define I2C_ISR_TC_Pos                      (6U)
11705 #define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
11706 #define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
11707 #define I2C_ISR_TCR_Pos                     (7U)
11708 #define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
11709 #define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
11710 #define I2C_ISR_BERR_Pos                    (8U)
11711 #define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
11712 #define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
11713 #define I2C_ISR_ARLO_Pos                    (9U)
11714 #define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
11715 #define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
11716 #define I2C_ISR_OVR_Pos                     (10U)
11717 #define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
11718 #define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
11719 #define I2C_ISR_PECERR_Pos                  (11U)
11720 #define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
11721 #define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
11722 #define I2C_ISR_TIMEOUT_Pos                 (12U)
11723 #define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
11724 #define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
11725 #define I2C_ISR_ALERT_Pos                   (13U)
11726 #define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
11727 #define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
11728 #define I2C_ISR_BUSY_Pos                    (15U)
11729 #define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
11730 #define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
11731 #define I2C_ISR_DIR_Pos                     (16U)
11732 #define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
11733 #define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
11734 #define I2C_ISR_ADDCODE_Pos                 (17U)
11735 #define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
11736 #define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
11737 
11738 /******************  Bit definition for I2C_ICR register  *********************/
11739 #define I2C_ICR_ADDRCF_Pos                  (3U)
11740 #define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
11741 #define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
11742 #define I2C_ICR_NACKCF_Pos                  (4U)
11743 #define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
11744 #define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
11745 #define I2C_ICR_STOPCF_Pos                  (5U)
11746 #define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
11747 #define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
11748 #define I2C_ICR_BERRCF_Pos                  (8U)
11749 #define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
11750 #define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
11751 #define I2C_ICR_ARLOCF_Pos                  (9U)
11752 #define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
11753 #define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
11754 #define I2C_ICR_OVRCF_Pos                   (10U)
11755 #define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
11756 #define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
11757 #define I2C_ICR_PECCF_Pos                   (11U)
11758 #define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
11759 #define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
11760 #define I2C_ICR_TIMOUTCF_Pos                (12U)
11761 #define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
11762 #define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
11763 #define I2C_ICR_ALERTCF_Pos                 (13U)
11764 #define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
11765 #define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */
11766 
11767 /******************  Bit definition for I2C_PECR register  *********************/
11768 #define I2C_PECR_PEC_Pos                    (0U)
11769 #define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
11770 #define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */
11771 
11772 /******************  Bit definition for I2C_RXDR register  *********************/
11773 #define I2C_RXDR_RXDATA_Pos                 (0U)
11774 #define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
11775 #define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
11776 
11777 /******************  Bit definition for I2C_TXDR register  *********************/
11778 #define I2C_TXDR_TXDATA_Pos                 (0U)
11779 #define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
11780 #define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
11781 
11782 
11783 /******************************************************************************/
11784 /*                                                                            */
11785 /*             Improved Inter-integrated Circuit Interface (I3C)              */
11786 /*                                                                            */
11787 /******************************************************************************/
11788 /*******************  Bit definition for I3C_CR register  *********************/
11789 #define I3C_CR_DCNT_Pos                     (0U)
11790 #define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
11791 #define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
11792 #define I3C_CR_RNW_Pos                      (16U)
11793 #define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
11794 #define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
11795 #define I3C_CR_CCC_Pos                      (16U)
11796 #define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
11797 #define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
11798 #define I3C_CR_ADD_Pos                      (17U)
11799 #define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
11800 #define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
11801 #define I3C_CR_MTYPE_Pos                    (27U)
11802 #define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
11803 #define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
11804 #define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
11805 #define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
11806 #define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
11807 #define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
11808 #define I3C_CR_MEND_Pos                     (31U)
11809 #define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
11810 #define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */
11811 
11812 /*******************  Bit definition for I3C_CFGR register  *******************/
11813 #define I3C_CFGR_EN_Pos                     (0U)
11814 #define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
11815 #define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
11816 #define I3C_CFGR_CRINIT_Pos                 (1U)
11817 #define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
11818 #define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
11819 #define I3C_CFGR_NOARBH_Pos                 (2U)
11820 #define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
11821 #define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
11822 #define I3C_CFGR_RSTPTRN_Pos                (3U)
11823 #define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
11824 #define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
11825 #define I3C_CFGR_EXITPTRN_Pos               (4U)
11826 #define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
11827 #define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
11828 #define I3C_CFGR_HKSDAEN_Pos                (5U)
11829 #define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
11830 #define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
11831 #define I3C_CFGR_HJACK_Pos                  (7U)
11832 #define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
11833 #define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
11834 #define I3C_CFGR_RXDMAEN_Pos                (8U)
11835 #define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
11836 #define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
11837 #define I3C_CFGR_RXFLUSH_Pos                (9U)
11838 #define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
11839 #define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
11840 #define I3C_CFGR_RXTHRES_Pos                (10U)
11841 #define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
11842 #define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
11843 #define I3C_CFGR_TXDMAEN_Pos                (12U)
11844 #define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
11845 #define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
11846 #define I3C_CFGR_TXFLUSH_Pos                (13U)
11847 #define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
11848 #define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
11849 #define I3C_CFGR_TXTHRES_Pos                (14U)
11850 #define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
11851 #define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
11852 #define I3C_CFGR_SDMAEN_Pos                 (16U)
11853 #define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
11854 #define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
11855 #define I3C_CFGR_SFLUSH_Pos                 (17U)
11856 #define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
11857 #define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
11858 #define I3C_CFGR_SMODE_Pos                  (18U)
11859 #define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
11860 #define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
11861 #define I3C_CFGR_TMODE_Pos                  (19U)
11862 #define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
11863 #define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
11864 #define I3C_CFGR_CDMAEN_Pos                 (20U)
11865 #define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
11866 #define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
11867 #define I3C_CFGR_CFLUSH_Pos                 (21U)
11868 #define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
11869 #define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
11870 #define I3C_CFGR_TSFSET_Pos                 (30U)
11871 #define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
11872 #define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */
11873 
11874 /*******************  Bit definition for I3C_RDR register  ********************/
11875 #define I3C_RDR_RDB0_Pos                    (0U)
11876 #define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
11877 #define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */
11878 
11879 /******************  Bit definition for I3C_RDWR register  ********************/
11880 #define I3C_RDWR_RDBx_Pos                   (0U)
11881 #define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
11882 #define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
11883 #define I3C_RDWR_RDB0_Pos                   (0U)
11884 #define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
11885 #define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
11886 #define I3C_RDWR_RDB1_Pos                   (8U)
11887 #define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
11888 #define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
11889 #define I3C_RDWR_RDB2_Pos                   (16U)
11890 #define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
11891 #define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
11892 #define I3C_RDWR_RDB3_Pos                   (24U)
11893 #define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
11894 #define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */
11895 
11896 /*******************  Bit definition for I3C_TDR register  ********************/
11897 #define I3C_TDR_TDB0_Pos                    (0U)
11898 #define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
11899 #define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */
11900 
11901 /******************  Bit definition for I3C_TDWR register  ********************/
11902 #define I3C_TDWR_TDBx_Pos                   (0U)
11903 #define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
11904 #define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
11905 #define I3C_TDWR_TDB0_Pos                   (0U)
11906 #define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
11907 #define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
11908 #define I3C_TDWR_TDB1_Pos                   (8U)
11909 #define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
11910 #define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
11911 #define I3C_TDWR_TDB2_Pos                   (16U)
11912 #define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
11913 #define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
11914 #define I3C_TDWR_TDB3_Pos                   (24U)
11915 #define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
11916 #define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */
11917 
11918 /*******************  Bit definition for I3C_IBIDR register  ******************/
11919 #define I3C_IBIDR_IBIDBx_Pos                (0U)
11920 #define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
11921 #define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
11922 #define I3C_IBIDR_IBIDB0_Pos                (0U)
11923 #define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
11924 #define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
11925 #define I3C_IBIDR_IBIDB1_Pos                (8U)
11926 #define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
11927 #define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
11928 #define I3C_IBIDR_IBIDB2_Pos                (16U)
11929 #define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
11930 #define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
11931 #define I3C_IBIDR_IBIDB3_Pos                (24U)
11932 #define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
11933 #define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */
11934 
11935 /******************  Bit definition for I3C_TGTTDR register  ******************/
11936 #define I3C_TGTTDR_TGTTDCNT_Pos             (0U)
11937 #define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
11938 #define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
11939 #define I3C_TGTTDR_PRELOAD_Pos              (16U)
11940 #define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
11941 #define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */
11942 
11943 /*******************  Bit definition for I3C_SR register  *********************/
11944 #define I3C_SR_XDCNT_Pos                    (0U)
11945 #define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
11946 #define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
11947 #define I3C_SR_ABT_Pos                      (17U)
11948 #define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
11949 #define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
11950 #define I3C_SR_DIR_Pos                      (18U)
11951 #define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
11952 #define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
11953 #define I3C_SR_MID_Pos                      (24U)
11954 #define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
11955 #define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */
11956 
11957 /*******************  Bit definition for I3C_SER register  ********************/
11958 #define I3C_SER_CODERR_Pos                  (0U)
11959 #define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
11960 #define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
11961 #define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
11962 #define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
11963 #define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
11964 #define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
11965 #define I3C_SER_PERR_Pos                    (4U)
11966 #define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
11967 #define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
11968 #define I3C_SER_STALL_Pos                   (5U)
11969 #define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
11970 #define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
11971 #define I3C_SER_DOVR_Pos                    (6U)
11972 #define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
11973 #define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
11974 #define I3C_SER_COVR_Pos                    (7U)
11975 #define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
11976 #define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
11977 #define I3C_SER_ANACK_Pos                   (8U)
11978 #define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
11979 #define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
11980 #define I3C_SER_DNACK_Pos                   (9U)
11981 #define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
11982 #define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
11983 #define I3C_SER_DERR_Pos                    (10U)
11984 #define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
11985 #define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */
11986 
11987 /*******************  Bit definition for I3C_RMR register  ********************/
11988 #define I3C_RMR_IBIRDCNT_Pos                (0U)
11989 #define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
11990 #define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
11991 #define I3C_RMR_RCODE_Pos                   (8U)
11992 #define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
11993 #define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
11994 #define I3C_RMR_RADD_Pos                    (17U)
11995 #define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
11996 #define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */
11997 
11998 /*******************  Bit definition for I3C_EVR register  ********************/
11999 #define I3C_EVR_CFEF_Pos                    (0U)
12000 #define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
12001 #define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
12002 #define I3C_EVR_TXFEF_Pos                   (1U)
12003 #define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
12004 #define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
12005 #define I3C_EVR_CFNFF_Pos                   (2U)
12006 #define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
12007 #define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
12008 #define I3C_EVR_SFNEF_Pos                   (3U)
12009 #define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
12010 #define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
12011 #define I3C_EVR_TXFNFF_Pos                  (4U)
12012 #define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
12013 #define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
12014 #define I3C_EVR_RXFNEF_Pos                  (5U)
12015 #define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
12016 #define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
12017 #define I3C_EVR_TXLASTF_Pos                 (6U)
12018 #define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
12019 #define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
12020 #define I3C_EVR_RXLASTF_Pos                 (7U)
12021 #define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
12022 #define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
12023 #define I3C_EVR_FCF_Pos                     (9U)
12024 #define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
12025 #define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
12026 #define I3C_EVR_RXTGTENDF_Pos               (10U)
12027 #define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
12028 #define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
12029 #define I3C_EVR_ERRF_Pos                    (11U)
12030 #define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
12031 #define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
12032 #define I3C_EVR_IBIF_Pos                    (15U)
12033 #define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
12034 #define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
12035 #define I3C_EVR_IBIENDF_Pos                 (16U)
12036 #define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
12037 #define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
12038 #define I3C_EVR_CRF_Pos                     (17U)
12039 #define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
12040 #define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
12041 #define I3C_EVR_CRUPDF_Pos                  (18U)
12042 #define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
12043 #define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
12044 #define I3C_EVR_HJF_Pos                     (19U)
12045 #define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
12046 #define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
12047 #define I3C_EVR_WKPF_Pos                    (21U)
12048 #define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
12049 #define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
12050 #define I3C_EVR_GETF_Pos                    (22U)
12051 #define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
12052 #define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
12053 #define I3C_EVR_STAF_Pos                    (23U)
12054 #define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
12055 #define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
12056 #define I3C_EVR_DAUPDF_Pos                  (24U)
12057 #define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
12058 #define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
12059 #define I3C_EVR_MWLUPDF_Pos                 (25U)
12060 #define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
12061 #define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
12062 #define I3C_EVR_MRLUPDF_Pos                 (26U)
12063 #define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
12064 #define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
12065 #define I3C_EVR_RSTF_Pos                    (27U)
12066 #define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
12067 #define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
12068 #define I3C_EVR_ASUPDF_Pos                  (28U)
12069 #define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
12070 #define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
12071 #define I3C_EVR_INTUPDF_Pos                 (29U)
12072 #define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
12073 #define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
12074 #define I3C_EVR_DEFF_Pos                    (30U)
12075 #define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
12076 #define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
12077 #define I3C_EVR_GRPF_Pos                    (31U)
12078 #define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
12079 #define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */
12080 
12081 /*******************  Bit definition for I3C_IER register  ********************/
12082 #define I3C_IER_CFNFIE_Pos                  (2U)
12083 #define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
12084 #define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
12085 #define I3C_IER_SFNEIE_Pos                  (3U)
12086 #define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
12087 #define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
12088 #define I3C_IER_TXFNFIE_Pos                 (4U)
12089 #define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
12090 #define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
12091 #define I3C_IER_RXFNEIE_Pos                 (5U)
12092 #define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
12093 #define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
12094 #define I3C_IER_FCIE_Pos                    (9U)
12095 #define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
12096 #define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
12097 #define I3C_IER_RXTGTENDIE_Pos              (10U)
12098 #define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
12099 #define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
12100 #define I3C_IER_ERRIE_Pos                   (11U)
12101 #define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
12102 #define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
12103 #define I3C_IER_IBIIE_Pos                   (15U)
12104 #define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
12105 #define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
12106 #define I3C_IER_IBIENDIE_Pos                (16U)
12107 #define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
12108 #define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
12109 #define I3C_IER_CRIE_Pos                    (17U)
12110 #define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
12111 #define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
12112 #define I3C_IER_CRUPDIE_Pos                 (18U)
12113 #define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
12114 #define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
12115 #define I3C_IER_HJIE_Pos                    (19U)
12116 #define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
12117 #define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
12118 #define I3C_IER_WKPIE_Pos                   (21U)
12119 #define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
12120 #define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
12121 #define I3C_IER_GETIE_Pos                   (22U)
12122 #define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
12123 #define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
12124 #define I3C_IER_STAIE_Pos                   (23U)
12125 #define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
12126 #define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
12127 #define I3C_IER_DAUPDIE_Pos                 (24U)
12128 #define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
12129 #define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
12130 #define I3C_IER_MWLUPDIE_Pos                (25U)
12131 #define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
12132 #define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
12133 #define I3C_IER_MRLUPDIE_Pos                (26U)
12134 #define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
12135 #define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
12136 #define I3C_IER_RSTIE_Pos                   (27U)
12137 #define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
12138 #define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
12139 #define I3C_IER_ASUPDIE_Pos                 (28U)
12140 #define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
12141 #define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
12142 #define I3C_IER_INTUPDIE_Pos                (29U)
12143 #define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
12144 #define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
12145 #define I3C_IER_DEFIE_Pos                   (30U)
12146 #define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
12147 #define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
12148 #define I3C_IER_GRPIE_Pos                   (31U)
12149 #define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
12150 #define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */
12151 
12152 /*******************  Bit definition for I3C_CEVR register  *******************/
12153 #define I3C_CEVR_CFCF_Pos                   (9U)
12154 #define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
12155 #define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
12156 #define I3C_CEVR_CRXTGTENDF_Pos             (10U)
12157 #define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
12158 #define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
12159 #define I3C_CEVR_CERRF_Pos                  (11U)
12160 #define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
12161 #define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
12162 #define I3C_CEVR_CIBIF_Pos                  (15U)
12163 #define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
12164 #define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
12165 #define I3C_CEVR_CIBIENDF_Pos               (16U)
12166 #define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
12167 #define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
12168 #define I3C_CEVR_CCRF_Pos                   (17U)
12169 #define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
12170 #define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
12171 #define I3C_CEVR_CCRUPDF_Pos                (18U)
12172 #define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
12173 #define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
12174 #define I3C_CEVR_CHJF_Pos                   (19U)
12175 #define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
12176 #define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
12177 #define I3C_CEVR_CWKPF_Pos                  (21U)
12178 #define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
12179 #define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
12180 #define I3C_CEVR_CGETF_Pos                  (22U)
12181 #define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
12182 #define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
12183 #define I3C_CEVR_CSTAF_Pos                  (23U)
12184 #define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
12185 #define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
12186 #define I3C_CEVR_CDAUPDF_Pos                (24U)
12187 #define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
12188 #define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
12189 #define I3C_CEVR_CMWLUPDF_Pos               (25U)
12190 #define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
12191 #define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
12192 #define I3C_CEVR_CMRLUPDF_Pos               (26U)
12193 #define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
12194 #define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
12195 #define I3C_CEVR_CRSTF_Pos                  (27U)
12196 #define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
12197 #define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
12198 #define I3C_CEVR_CASUPDF_Pos                (28U)
12199 #define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
12200 #define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
12201 #define I3C_CEVR_CINTUPDF_Pos               (29U)
12202 #define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
12203 #define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
12204 #define I3C_CEVR_CDEFF_Pos                  (30U)
12205 #define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
12206 #define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
12207 #define I3C_CEVR_CGRPF_Pos                  (31U)
12208 #define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
12209 #define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */
12210 
12211 /******************  Bit definition for I3C_DEVR0 register  *******************/
12212 #define I3C_DEVR0_DAVAL_Pos                 (0U)
12213 #define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
12214 #define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
12215 #define I3C_DEVR0_DA_Pos                    (1U)
12216 #define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
12217 #define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
12218 #define I3C_DEVR0_IBIEN_Pos                 (16U)
12219 #define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
12220 #define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
12221 #define I3C_DEVR0_CREN_Pos                  (17U)
12222 #define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
12223 #define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
12224 #define I3C_DEVR0_HJEN_Pos                  (19U)
12225 #define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
12226 #define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
12227 #define I3C_DEVR0_AS_Pos                    (20U)
12228 #define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
12229 #define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
12230 #define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
12231 #define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
12232 #define I3C_DEVR0_RSTACT_Pos                (22U)
12233 #define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
12234 #define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
12235 #define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
12236 #define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
12237 #define I3C_DEVR0_RSTVAL_Pos                (24U)
12238 #define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
12239 #define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */
12240 
12241 /******************  Bit definition for I3C_DEVRX register  *******************/
12242 #define I3C_DEVRX_DA_Pos                    (1U)
12243 #define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
12244 #define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
12245 #define I3C_DEVRX_IBIACK_Pos                (16U)
12246 #define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
12247 #define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
12248 #define I3C_DEVRX_CRACK_Pos                 (17U)
12249 #define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
12250 #define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
12251 #define I3C_DEVRX_IBIDEN_Pos                (18U)
12252 #define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
12253 #define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
12254 #define I3C_DEVRX_SUSP_Pos                  (19U)
12255 #define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
12256 #define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
12257 #define I3C_DEVRX_DIS_Pos                   (31U)
12258 #define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
12259 #define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */
12260 
12261 /******************  Bit definition for I3C_MAXRLR register  ******************/
12262 #define I3C_MAXRLR_MRL_Pos                  (0U)
12263 #define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
12264 #define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
12265 #define I3C_MAXRLR_IBIP_Pos                 (16U)
12266 #define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
12267 #define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
12268 #define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
12269 #define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
12270 #define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */
12271 
12272 /******************  Bit definition for I3C_MAXWLR register  ******************/
12273 #define I3C_MAXWLR_MWL_Pos                  (0U)
12274 #define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
12275 #define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */
12276 
12277 /****************  Bit definition for I3C_TIMINGR0 register  ******************/
12278 #define I3C_TIMINGR0_SCLL_PP_Pos            (0U)
12279 #define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
12280 #define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
12281 #define I3C_TIMINGR0_SCLH_I3C_Pos           (8U)
12282 #define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
12283 #define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
12284 #define I3C_TIMINGR0_SCLL_OD_Pos            (16U)
12285 #define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
12286 #define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
12287 #define I3C_TIMINGR0_SCLH_I2C_Pos           (24U)
12288 #define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
12289 #define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */
12290 
12291 /****************  Bit definition for I3C_TIMINGR1 register  ******************/
12292 #define I3C_TIMINGR1_AVAL_Pos               (0U)
12293 #define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
12294 #define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
12295 #define I3C_TIMINGR1_ASNCR_Pos              (8U)
12296 #define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
12297 #define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
12298 #define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
12299 #define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
12300 #define I3C_TIMINGR1_FREE_Pos               (16U)
12301 #define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
12302 #define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
12303 #define I3C_TIMINGR1_SDA_HD_Pos             (28U)
12304 #define I3C_TIMINGR1_SDA_HD_Msk             (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x00010000 */
12305 #define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */
12306 
12307 /****************  Bit definition for I3C_TIMINGR2 register  ******************/
12308 #define I3C_TIMINGR2_STALLT_Pos             (0U)
12309 #define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x00000001 */
12310 #define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
12311 #define I3C_TIMINGR2_STALLD_Pos             (1U)
12312 #define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x00000002 */
12313 #define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
12314 #define I3C_TIMINGR2_STALLC_Pos             (2U)
12315 #define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x00000004 */
12316 #define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
12317 #define I3C_TIMINGR2_STALLA_Pos             (3U)
12318 #define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x00000008 */
12319 #define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
12320 #define I3C_TIMINGR2_STALL_Pos              (8U)
12321 #define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x0000FF00 */
12322 #define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */
12323 
12324 /*******************  Bit definition for I3C_BCR register  ********************/
12325 #define I3C_BCR_BCR_Pos                     (0U)
12326 #define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
12327 #define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
12328 #define I3C_BCR_BCR0_Pos                    (0U)
12329 #define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
12330 #define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
12331 #define I3C_BCR_BCR1_Pos                    (1U)
12332 #define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
12333 #define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
12334 #define I3C_BCR_BCR2_Pos                    (2U)
12335 #define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
12336 #define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
12337 #define I3C_BCR_BCR3_Pos                    (3U)
12338 #define I3C_BCR_BCR3_Msk                    (0x1UL << I3C_BCR_BCR3_Pos)             /*!< 0x00000008 */
12339 #define I3C_BCR_BCR3                        I3C_BCR_BCR3_Msk                        /*!< Offline capable */
12340 #define I3C_BCR_BCR4_Pos                    (4U)
12341 #define I3C_BCR_BCR4_Msk                    (0x1UL << I3C_BCR_BCR4_Pos)             /*!< 0x00000010 */
12342 #define I3C_BCR_BCR4                        I3C_BCR_BCR4_Msk                        /*!< Virtual target support */
12343 #define I3C_BCR_BCR5_Pos                    (5U)
12344 #define I3C_BCR_BCR5_Msk                    (0x1UL << I3C_BCR_BCR5_Pos)             /*!< 0x00000020 */
12345 #define I3C_BCR_BCR5                        I3C_BCR_BCR5_Msk                        /*!< Advanced capabilities */
12346 #define I3C_BCR_BCR6_Pos                    (6U)
12347 #define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
12348 #define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */
12349 
12350 /*******************  Bit definition for I3C_DCR register  ********************/
12351 #define I3C_DCR_DCR_Pos                     (0U)
12352 #define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x000000FF */
12353 #define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */
12354 
12355 /*****************  Bit definition for I3C_GETCAPR register  ******************/
12356 #define I3C_GETCAPR_CAPPEND_Pos             (14U)
12357 #define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
12358 #define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */
12359 
12360 /*****************  Bit definition for I3C_CRCAPR register  *******************/
12361 #define I3C_CRCAPR_CAPDHOFF_Pos             (3U)
12362 #define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
12363 #define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
12364 #define I3C_CRCAPR_CAPGRP_Pos               (9U)
12365 #define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
12366 #define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */
12367 
12368 /****************  Bit definition for I3C_GETMXDSR register  ******************/
12369 #define I3C_GETMXDSR_HOFFAS_Pos             (0U)
12370 #define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
12371 #define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
12372 #define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
12373 #define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
12374 #define I3C_GETMXDSR_FMT_Pos                (8U)
12375 #define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
12376 #define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
12377 #define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
12378 #define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
12379 #define I3C_GETMXDSR_RDTURN_Pos             (16U)
12380 #define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
12381 #define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
12382 #define I3C_GETMXDSR_TSCO_Pos               (24U)
12383 #define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
12384 #define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */
12385 
12386 /******************  Bit definition for I3C_EPIDR register  *******************/
12387 #define I3C_EPIDR_MIPIID_Pos                (12U)
12388 #define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
12389 #define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
12390 #define I3C_EPIDR_IDTSEL_Pos                (16U)
12391 #define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
12392 #define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
12393 #define I3C_EPIDR_MIPIMID_Pos               (17U)
12394 #define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
12395 #define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */
12396 
12397 /******************************************************************************/
12398 /*                                                                            */
12399 /*                           Independent WATCHDOG                             */
12400 /*                                                                            */
12401 /******************************************************************************/
12402 /*******************  Bit definition for IWDG_KR register  ********************/
12403 #define IWDG_KR_KEY_Pos                     (0U)
12404 #define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)           /*!< 0x0000FFFF */
12405 #define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                         /*!<Key value (write only, read 0000h)  */
12406 
12407 /*******************  Bit definition for IWDG_PR register  ********************/
12408 #define IWDG_PR_PR_Pos                      (0U)
12409 #define IWDG_PR_PR_Msk                      (0xFUL << IWDG_PR_PR_Pos)               /*!< 0x0000000F */
12410 #define IWDG_PR_PR                          IWDG_PR_PR_Msk                          /*!<PR[3:0] (Prescaler divider)         */
12411 #define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)               /*!< 0x00000001 */
12412 #define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)               /*!< 0x00000002 */
12413 #define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)               /*!< 0x00000004 */
12414 #define IWDG_PR_PR_3                        (0x8UL << IWDG_PR_PR_Pos)               /*!< 0x00000008 */
12415 
12416 /*******************  Bit definition for IWDG_RLR register  *******************/
12417 #define IWDG_RLR_RL_Pos                     (0U)
12418 #define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)            /*!< 0x00000FFF */
12419 #define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                         /*!<Watchdog counter reload value        */
12420 
12421 /*******************  Bit definition for IWDG_SR register  ********************/
12422 #define IWDG_SR_PVU_Pos                     (0U)
12423 #define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)              /*!< 0x00000001 */
12424 #define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                         /*!< Watchdog prescaler value update */
12425 #define IWDG_SR_RVU_Pos                     (1U)
12426 #define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)              /*!< 0x00000002 */
12427 #define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                         /*!< Watchdog counter reload value update */
12428 #define IWDG_SR_WVU_Pos                     (2U)
12429 #define IWDG_SR_WVU_Msk                     (0x1UL << IWDG_SR_WVU_Pos)              /*!< 0x00000004 */
12430 #define IWDG_SR_WVU                         IWDG_SR_WVU_Msk                         /*!< Watchdog counter window value update */
12431 #define IWDG_SR_EWU_Pos                     (3U)
12432 #define IWDG_SR_EWU_Msk                     (0x1UL << IWDG_SR_EWU_Pos)              /*!< 0x00000008 */
12433 #define IWDG_SR_EWU                         IWDG_SR_EWU_Msk                         /*!< Watchdog interrupt comparator value update */
12434 #define IWDG_SR_ONF_Pos                     (8U)
12435 #define IWDG_SR_ONF_Msk                     (0x1UL << IWDG_SR_ONF_Pos)              /*!< 0x00000100 */
12436 #define IWDG_SR_ONF                         IWDG_SR_ONF_Msk                         /*!< Watchdog Enable status bit */
12437 #define IWDG_SR_EWIF_Pos                    (14U)
12438 #define IWDG_SR_EWIF_Msk                    (0x1UL << IWDG_SR_EWIF_Pos)             /*!< 0x00004000 */
12439 #define IWDG_SR_EWIF                        IWDG_SR_EWIF_Msk                        /*!< Watchdog early interrupt flag */
12440 
12441 /******************  Bit definition for IWDG_WINR register  *******************/
12442 #define IWDG_WINR_WIN_Pos                   (0U)
12443 #define IWDG_WINR_WIN_Msk                   (0xFFFUL << IWDG_WINR_WIN_Pos)          /*!< 0x00000FFF */
12444 #define IWDG_WINR_WIN                       IWDG_WINR_WIN_Msk                       /*!< Watchdog counter window value */
12445 
12446 /******************  Bit definition for IWDG_EWCR register  *******************/
12447 #define IWDG_EWCR_EWIT_Pos                  (0U)
12448 #define IWDG_EWCR_EWIT_Msk                  (0xFFFUL << IWDG_EWCR_EWIT_Pos)         /*!< 0x00000FFF */
12449 #define IWDG_EWCR_EWIT                      IWDG_EWCR_EWIT_Msk                      /*!< Watchdog early wakeup comparator value */
12450 #define IWDG_EWCR_EWIC_Pos                  (14U)
12451 #define IWDG_EWCR_EWIC_Msk                  (0x1UL << IWDG_EWCR_EWIC_Pos)           /*!< 0x00000FFF */
12452 #define IWDG_EWCR_EWIC                      IWDG_EWCR_EWIC_Msk                      /*!< Watchdog early wakeup comparator value */
12453 #define IWDG_EWCR_EWIE_Pos                  (15U)
12454 #define IWDG_EWCR_EWIE_Msk                  (0x1UL << IWDG_EWCR_EWIE_Pos)           /*!< 0x00000FFF */
12455 #define IWDG_EWCR_EWIE                      IWDG_EWCR_EWIE_Msk                      /*!< Watchdog early wakeup comparator value */
12456 
12457 
12458 /******************************************************************************/
12459 /*                                                                            */
12460 /*                   Serial Peripheral Interface (SPI/I2S)                    */
12461 /*                                                                            */
12462 /******************************************************************************/
12463 /*******************  Bit definition for SPI_CR1 register  ********************/
12464 #define SPI_CR1_SPE_Pos                     (0U)
12465 #define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
12466 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
12467 #define SPI_CR1_MASRX_Pos                   (8U)
12468 #define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
12469 #define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
12470 #define SPI_CR1_CSTART_Pos                  (9U)
12471 #define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
12472 #define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
12473 #define SPI_CR1_CSUSP_Pos                   (10U)
12474 #define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
12475 #define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
12476 #define SPI_CR1_HDDIR_Pos                   (11U)
12477 #define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
12478 #define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
12479 #define SPI_CR1_SSI_Pos                     (12U)
12480 #define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
12481 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
12482 #define SPI_CR1_CRC33_17_Pos                (13U)
12483 #define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
12484 #define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
12485 #define SPI_CR1_RCRCINI_Pos                 (14U)
12486 #define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
12487 #define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
12488 #define SPI_CR1_TCRCINI_Pos                 (15U)
12489 #define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
12490 #define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
12491 #define SPI_CR1_IOLOCK_Pos                  (16U)
12492 #define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
12493 #define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */
12494 
12495 /*******************  Bit definition for SPI_CR2 register  ********************/
12496 #define SPI_CR2_TSIZE_Pos                   (0U)
12497 #define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
12498 #define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */
12499 
12500 /*******************  Bit definition for SPI_CFG1 register  ********************/
12501 #define SPI_CFG1_DSIZE_Pos                  (0U)
12502 #define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
12503 #define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
12504 #define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
12505 #define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
12506 #define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
12507 #define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
12508 #define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
12509 #define SPI_CFG1_FTHLV_Pos                  (5U)
12510 #define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
12511 #define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
12512 #define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
12513 #define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
12514 #define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
12515 #define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
12516 #define SPI_CFG1_UDRCFG_Pos                 (9U)
12517 #define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
12518 #define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
12519 #define SPI_CFG1_RXDMAEN_Pos                (14U)
12520 #define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
12521 #define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
12522 #define SPI_CFG1_TXDMAEN_Pos                (15U)
12523 #define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
12524 #define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
12525 #define SPI_CFG1_CRCSIZE_Pos                (16U)
12526 #define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
12527 #define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
12528 #define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
12529 #define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
12530 #define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
12531 #define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
12532 #define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
12533 #define SPI_CFG1_CRCEN_Pos                  (22U)
12534 #define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
12535 #define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
12536 #define SPI_CFG1_MBR_Pos                    (28U)
12537 #define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
12538 #define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
12539 #define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
12540 #define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
12541 #define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
12542 #define SPI_CFG1_BPASS_Pos                  (31U)
12543 #define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
12544 #define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */
12545 
12546 /*******************  Bit definition for SPI_CFG2 register  ********************/
12547 #define SPI_CFG2_MSSI_Pos                   (0U)
12548 #define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
12549 #define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
12550 #define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
12551 #define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
12552 #define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
12553 #define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
12554 #define SPI_CFG2_MIDI_Pos                   (4U)
12555 #define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
12556 #define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
12557 #define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
12558 #define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
12559 #define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
12560 #define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
12561 #define SPI_CFG2_RDIOM_Pos                  (13U)
12562 #define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
12563 #define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
12564 #define SPI_CFG2_RDIOP_Pos                  (14U)
12565 #define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
12566 #define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
12567 #define SPI_CFG2_IOSWP_Pos                  (15U)
12568 #define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
12569 #define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
12570 #define SPI_CFG2_COMM_Pos                   (17U)
12571 #define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
12572 #define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
12573 #define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
12574 #define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
12575 #define SPI_CFG2_SP_Pos                     (19U)
12576 #define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
12577 #define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
12578 #define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
12579 #define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
12580 #define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
12581 #define SPI_CFG2_MASTER_Pos                 (22U)
12582 #define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
12583 #define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
12584 #define SPI_CFG2_LSBFRST_Pos                (23U)
12585 #define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
12586 #define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
12587 #define SPI_CFG2_CPHA_Pos                   (24U)
12588 #define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
12589 #define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
12590 #define SPI_CFG2_CPOL_Pos                   (25U)
12591 #define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
12592 #define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
12593 #define SPI_CFG2_SSM_Pos                    (26U)
12594 #define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
12595 #define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
12596 #define SPI_CFG2_SSIOP_Pos                  (28U)
12597 #define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
12598 #define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
12599 #define SPI_CFG2_SSOE_Pos                   (29U)
12600 #define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
12601 #define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
12602 #define SPI_CFG2_SSOM_Pos                   (30U)
12603 #define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
12604 #define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
12605 #define SPI_CFG2_AFCNTR_Pos                 (31U)
12606 #define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
12607 #define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */
12608 
12609 /*******************  Bit definition for SPI_IER register  ********************/
12610 #define SPI_IER_RXPIE_Pos                   (0U)
12611 #define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
12612 #define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
12613 #define SPI_IER_TXPIE_Pos                   (1U)
12614 #define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
12615 #define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
12616 #define SPI_IER_DXPIE_Pos                   (2U)
12617 #define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
12618 #define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
12619 #define SPI_IER_EOTIE_Pos                   (3U)
12620 #define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
12621 #define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
12622 #define SPI_IER_TXTFIE_Pos                  (4U)
12623 #define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
12624 #define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
12625 #define SPI_IER_UDRIE_Pos                   (5U)
12626 #define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
12627 #define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
12628 #define SPI_IER_OVRIE_Pos                   (6U)
12629 #define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
12630 #define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
12631 #define SPI_IER_CRCEIE_Pos                  (7U)
12632 #define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
12633 #define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
12634 #define SPI_IER_TIFREIE_Pos                 (8U)
12635 #define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
12636 #define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
12637 #define SPI_IER_MODFIE_Pos                  (9U)
12638 #define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
12639 #define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */
12640 
12641 /*******************  Bit definition for SPI_SR register  ********************/
12642 #define SPI_SR_RXP_Pos                      (0U)
12643 #define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
12644 #define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
12645 #define SPI_SR_TXP_Pos                      (1U)
12646 #define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
12647 #define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
12648 #define SPI_SR_DXP_Pos                      (2U)
12649 #define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
12650 #define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
12651 #define SPI_SR_EOT_Pos                      (3U)
12652 #define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
12653 #define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
12654 #define SPI_SR_TXTF_Pos                     (4U)
12655 #define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
12656 #define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
12657 #define SPI_SR_UDR_Pos                      (5U)
12658 #define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
12659 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
12660 #define SPI_SR_OVR_Pos                      (6U)
12661 #define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
12662 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
12663 #define SPI_SR_CRCE_Pos                     (7U)
12664 #define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
12665 #define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
12666 #define SPI_SR_TIFRE_Pos                    (8U)
12667 #define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
12668 #define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
12669 #define SPI_SR_MODF_Pos                     (9U)
12670 #define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
12671 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
12672 #define SPI_SR_SUSP_Pos                     (11U)
12673 #define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
12674 #define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
12675 #define SPI_SR_TXC_Pos                      (12U)
12676 #define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
12677 #define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
12678 #define SPI_SR_RXPLVL_Pos                   (13U)
12679 #define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
12680 #define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
12681 #define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
12682 #define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
12683 #define SPI_SR_RXWNE_Pos                    (15U)
12684 #define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
12685 #define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
12686 #define SPI_SR_CTSIZE_Pos                   (16U)
12687 #define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
12688 #define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */
12689 
12690 /*******************  Bit definition for SPI_IFCR register  ********************/
12691 #define SPI_IFCR_EOTC_Pos                   (3U)
12692 #define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
12693 #define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
12694 #define SPI_IFCR_TXTFC_Pos                  (4U)
12695 #define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
12696 #define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
12697 #define SPI_IFCR_UDRC_Pos                   (5U)
12698 #define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
12699 #define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
12700 #define SPI_IFCR_OVRC_Pos                   (6U)
12701 #define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
12702 #define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
12703 #define SPI_IFCR_CRCEC_Pos                  (7U)
12704 #define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
12705 #define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
12706 #define SPI_IFCR_TIFREC_Pos                 (8U)
12707 #define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
12708 #define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
12709 #define SPI_IFCR_MODFC_Pos                  (9U)
12710 #define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
12711 #define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
12712 #define SPI_IFCR_SUSPC_Pos                  (11U)
12713 #define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
12714 #define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */
12715 
12716 /*******************  Bit definition for SPI_TXDR register  ********************/
12717 #define SPI_TXDR_TXDR_Pos                   (0U)
12718 #define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
12719 #define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /*!<Transmit Data Register */
12720 
12721 /*******************  Bit definition for SPI_RXDR register  ********************/
12722 #define SPI_RXDR_RXDR_Pos                   (0U)
12723 #define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
12724 #define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /*!<Receive Data Register */
12725 
12726 /*******************  Bit definition for SPI_CRCPOLY register  ********************/
12727 #define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
12728 #define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
12729 #define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                   /*!<CRC Polynomial register */
12730 
12731 /*******************  Bit definition for SPI_TXCRC register  ********************/
12732 #define SPI_TXCRC_TXCRC_Pos                 (0U)
12733 #define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
12734 #define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /*!<CRCRegister for transmitter */
12735 
12736 /*******************  Bit definition for SPI_RXCRC register  ********************/
12737 #define SPI_RXCRC_RXCRC_Pos                 (0U)
12738 #define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
12739 #define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /*!<CRCRegister for receiver */
12740 
12741 /*******************  Bit definition for SPI_UDRDR register  ********************/
12742 #define SPI_UDRDR_UDRDR_Pos                 (0U)
12743 #define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
12744 #define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /*!<Data at slave underrun condition */
12745 
12746 /******************  Bit definition for SPI_I2SCFGR register  *****************/
12747 #define SPI_I2SCFGR_I2SMOD_Pos      (0U)
12748 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
12749 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
12750 #define SPI_I2SCFGR_I2SCFG_Pos      (1U)
12751 #define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
12752 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
12753 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
12754 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
12755 #define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
12756 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
12757 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
12758 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
12759 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
12760 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
12761 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
12762 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
12763 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
12764 #define SPI_I2SCFGR_DATLEN_Pos      (8U)
12765 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
12766 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
12767 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
12768 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
12769 #define SPI_I2SCFGR_CHLEN_Pos       (10U)
12770 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
12771 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
12772 #define SPI_I2SCFGR_CKPOL_Pos       (11U)
12773 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
12774 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
12775 #define SPI_I2SCFGR_FIXCH_Pos       (12U)
12776 #define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
12777 #define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
12778 #define SPI_I2SCFGR_WSINV_Pos       (13U)
12779 #define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
12780 #define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
12781 #define SPI_I2SCFGR_DATFMT_Pos      (14U)
12782 #define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
12783 #define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
12784 #define SPI_I2SCFGR_I2SDIV_Pos      (16U)
12785 #define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
12786 #define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
12787 #define SPI_I2SCFGR_ODD_Pos         (24U)
12788 #define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
12789 #define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
12790 #define SPI_I2SCFGR_MCKOE_Pos       (25U)
12791 #define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
12792 #define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
12793 
12794 
12795 /******************************************************************************/
12796 /*                                                                            */
12797 /*                            Window WATCHDOG                                 */
12798 /*                                                                            */
12799 /******************************************************************************/
12800 /*******************  Bit definition for WWDG_CR register  ********************/
12801 #define WWDG_CR_T_Pos                       (0U)
12802 #define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
12803 #define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
12804 #define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
12805 #define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
12806 #define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
12807 #define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
12808 #define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
12809 #define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
12810 #define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
12811 #define WWDG_CR_WDGA_Pos                    (7U)
12812 #define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
12813 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */
12814 
12815 /*******************  Bit definition for WWDG_CFR register  *******************/
12816 #define WWDG_CFR_W_Pos                      (0U)
12817 #define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
12818 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
12819 #define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
12820 #define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
12821 #define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
12822 #define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
12823 #define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
12824 #define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
12825 #define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
12826 #define WWDG_CFR_EWI_Pos                    (9U)
12827 #define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
12828 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */
12829 #define WWDG_CFR_WDGTB_Pos                  (11U)
12830 #define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
12831 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
12832 #define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
12833 #define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
12834 #define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
12835 
12836 /*******************  Bit definition for WWDG_SR register  ********************/
12837 #define WWDG_SR_EWIF_Pos                    (0U)
12838 #define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
12839 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */
12840 
12841 
12842 /******************************************************************************/
12843 /*                                                                            */
12844 /*                         USB Dual Role Device FS Endpoint registers         */
12845 /*                                                                            */
12846 /******************************************************************************/
12847 
12848 /******************  Bits definition for USB_DRD_CNTR register  *******************/
12849 #define USB_CNTR_HOST_Pos               (31U)
12850 #define USB_CNTR_HOST_Msk               (0x1UL << USB_CNTR_HOST_Pos)    /*!< 0x80000000 */
12851 #define USB_CNTR_HOST                   USB_CNTR_HOST_Msk               /*!< Host Mode  */
12852 #define USB_CNTR_THR512M_Pos            (16U)
12853 #define USB_CNTR_THR512M_Msk            (0x1UL << USB_CNTR_THR512M_Pos)  /*!< 0x00010000 */
12854 #define USB_CNTR_THR512M                USB_CNTR_THR512M_Msk             /*!< 512byte Threshold interrupt mask */
12855 #define USB_CNTR_CTRM_Pos               (15U)
12856 #define USB_CNTR_CTRM_Msk               (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
12857 #define USB_CNTR_CTRM                   USB_CNTR_CTRM_Msk               /*!< Correct Transfer Mask */
12858 #define USB_CNTR_PMAOVRM_Pos            (14U)
12859 #define USB_CNTR_PMAOVRM_Msk            (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
12860 #define USB_CNTR_PMAOVRM                USB_CNTR_PMAOVRM_Msk            /*!< DMA OVeR/underrun Mask */
12861 #define USB_CNTR_ERRM_Pos               (13U)
12862 #define USB_CNTR_ERRM_Msk               (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
12863 #define USB_CNTR_ERRM                   USB_CNTR_ERRM_Msk               /*!< ERRor Mask */
12864 #define USB_CNTR_WKUPM_Pos              (12U)
12865 #define USB_CNTR_WKUPM_Msk              (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
12866 #define USB_CNTR_WKUPM                  USB_CNTR_WKUPM_Msk              /*!< WaKe UP Mask */
12867 #define USB_CNTR_SUSPM_Pos              (11U)
12868 #define USB_CNTR_SUSPM_Msk              (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
12869 #define USB_CNTR_SUSPM                  USB_CNTR_SUSPM_Msk              /*!< SUSPend Mask */
12870 #define USB_CNTR_RESETM_Pos             (10U)
12871 #define USB_CNTR_RESETM_Msk             (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
12872 #define USB_CNTR_RESETM                 USB_CNTR_RESETM_Msk             /*!< RESET Mask */
12873 #define USB_CNTR_DCON                   USB_CNTR_RESETM_Msk             /*!< Disconnection Connection Mask */
12874 #define USB_CNTR_SOFM_Pos               (9U)
12875 #define USB_CNTR_SOFM_Msk               (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
12876 #define USB_CNTR_SOFM                   USB_CNTR_SOFM_Msk               /*!< Start Of Frame Mask */
12877 #define USB_CNTR_ESOFM_Pos              (8U)
12878 #define USB_CNTR_ESOFM_Msk              (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
12879 #define USB_CNTR_ESOFM                  USB_CNTR_ESOFM_Msk              /*!< Expected Start Of Frame Mask */
12880 #define USB_CNTR_L1REQM_Pos             (7U)
12881 #define USB_CNTR_L1REQM_Msk             (0x1UL << USB_CNTR_L1REQM_Pos)  /*!< 0x00000080 */
12882 #define USB_CNTR_L1REQM                 USB_CNTR_L1REQM_Msk             /*!< LPM L1 state request interrupt Mask */
12883 #define USB_CNTR_L1XACT_Pos             (6U)
12884 #define USB_CNTR_L1XACT_Msk             (0x1UL << USB_CNTR_L1XACT_Pos)  /*!< 0x00000040 */
12885 #define USB_CNTR_L1XACT                 USB_CNTR_L1XACT_Msk             /*!< Host LPM L1 transaction request Mask */
12886 #define USB_CNTR_L1RES_Pos              (5U)
12887 #define USB_CNTR_L1RES_Msk              (0x1UL << USB_CNTR_L1RES_Pos)   /*!< 0x00000020 */
12888 #define USB_CNTR_L1RES                  USB_CNTR_L1RES_Msk              /*!< LPM L1 Resume request/ Remote Wakeup Mask */
12889 #define USB_CNTR_L2RES_Pos              (4U)
12890 #define USB_CNTR_L2RES_Msk              (0x1UL << USB_CNTR_L2RES_Pos)   /*!< 0x00000010 */
12891 #define USB_CNTR_L2RES                  USB_CNTR_L2RES_Msk              /*!< L2 Remote Wakeup / Resume driver Mask */
12892 #define USB_CNTR_SUSPEN_Pos             (3U)
12893 #define USB_CNTR_SUSPEN_Msk             (0x1UL << USB_CNTR_SUSPEN_Pos)  /*!< 0x00000008 */
12894 #define USB_CNTR_SUSPEN                 USB_CNTR_SUSPEN_Msk             /*!< Suspend state enable Mask */
12895 #define USB_CNTR_SUSPRDY_Pos            (2U)
12896 #define USB_CNTR_SUSPRDY_Msk            (0x1UL << USB_CNTR_SUSPRDY_Pos) /*!< 0x00000004 */
12897 #define USB_CNTR_SUSPRDY                USB_CNTR_SUSPRDY_Msk            /*!< Suspend state effective Mask */
12898 #define USB_CNTR_PDWN_Pos               (1U)
12899 #define USB_CNTR_PDWN_Msk               (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
12900 #define USB_CNTR_PDWN                   USB_CNTR_PDWN_Msk               /*!< Power DoWN Mask */
12901 #define USB_CNTR_USBRST_Pos             (0U)
12902 #define USB_CNTR_USBRST_Msk             (0x1UL << USB_CNTR_USBRST_Pos)  /*!< 0x00000001 */
12903 #define USB_CNTR_USBRST                 USB_CNTR_USBRST_Msk             /*!< USB Reset Mask */
12904 
12905 /******************  Bits definition for USB_DRD_ISTR register  *******************/
12906 #define USB_ISTR_IDN_Pos                (0U)
12907 #define USB_ISTR_IDN_Msk                (0xFUL << USB_ISTR_IDN_Pos)     /*!< 0x0000000F */
12908 #define USB_ISTR_IDN                    USB_ISTR_IDN_Msk                /*!< EndPoint IDentifier (read-only bit) Mask */
12909 #define USB_ISTR_DIR_Pos                (4U)
12910 #define USB_ISTR_DIR_Msk                (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
12911 #define USB_ISTR_DIR                    USB_ISTR_DIR_Msk                /*!< DIRection of transaction (read-only bit) Mask */
12912 #define USB_ISTR_L1REQ_Pos              (7U)
12913 #define USB_ISTR_L1REQ_Msk              (0x1UL << USB_ISTR_L1REQ_Pos)   /*!< 0x00000080 */
12914 #define USB_ISTR_L1REQ                  USB_ISTR_L1REQ_Msk              /*!< LPM L1 state request Mask */
12915 #define USB_ISTR_ESOF_Pos               (8U)
12916 #define USB_ISTR_ESOF_Msk               (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
12917 #define USB_ISTR_ESOF                   USB_ISTR_ESOF_Msk               /*!< Expected Start Of Frame (clear-only bit) Mask */
12918 #define USB_ISTR_SOF_Pos                (9U)
12919 #define USB_ISTR_SOF_Msk                (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
12920 #define USB_ISTR_SOF                    USB_ISTR_SOF_Msk                /*!< Start Of Frame (clear-only bit) Mask */
12921 #define USB_ISTR_RESET_Pos              (10U)
12922 #define USB_ISTR_RESET_Msk              (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
12923 #define USB_ISTR_RESET                  USB_ISTR_RESET_Msk              /*!< RESET Mask */
12924 #define USB_ISTR_DCON_Pos               (10U)
12925 #define USB_ISTR_DCON_Msk               (0x1UL << USB_ISTR_DCON_Pos)    /*!< 0x00000400 */
12926 #define USB_ISTR_DCON                   USB_ISTR_DCON_Msk               /*!< HOST MODE-Device Connection or disconnection Mask */
12927 #define USB_ISTR_SUSP_Pos               (11U)
12928 #define USB_ISTR_SUSP_Msk               (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
12929 #define USB_ISTR_SUSP                   USB_ISTR_SUSP_Msk               /*!< SUSPend (clear-only bit) Mask */
12930 #define USB_ISTR_WKUP_Pos               (12U)
12931 #define USB_ISTR_WKUP_Msk               (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
12932 #define USB_ISTR_WKUP                   USB_ISTR_WKUP_Msk               /*!< WaKe UP (clear-only bit) Mask */
12933 #define USB_ISTR_ERR_Pos                (13U)
12934 #define USB_ISTR_ERR_Msk                (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
12935 #define USB_ISTR_ERR                    USB_ISTR_ERR_Msk                /*!< ERRor (clear-only bit) Mask */
12936 #define USB_ISTR_PMAOVR_Pos             (14U)
12937 #define USB_ISTR_PMAOVR_Msk             (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
12938 #define USB_ISTR_PMAOVR                 USB_ISTR_PMAOVR_Msk             /*!< PMA OVeR/underrun (clear-only bit) Mask */
12939 #define USB_ISTR_CTR_Pos                (15U)
12940 #define USB_ISTR_CTR_Msk                (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
12941 #define USB_ISTR_CTR                    USB_ISTR_CTR_Msk                /*!< Correct TRansfer (clear-only bit) Mask */
12942 #define USB_ISTR_THR512_Pos             (16U)
12943 #define USB_ISTR_THR512_Msk             (0x1UL << USB_ISTR_THR512_Pos)  /*!< 0x00010000 */
12944 #define USB_ISTR_THR512                 USB_ISTR_THR512_Msk             /*!< 512byte threshold interrupt (used with isochrnous single buffer ) */
12945 #define USB_ISTR_DCON_STAT_Pos          (29U)
12946 #define USB_ISTR_DCON_STAT_Msk          (0x1UL << USB_ISTR_DCON_STAT_Pos)/*!< 0x20000000 */
12947 #define USB_ISTR_DCON_STAT              USB_ISTR_DCON_STAT_Msk           /*!< Device Connection status (connected/Disconnected) don't cause an interrupt */
12948 #define USB_ISTR_LS_DCONN_Pos           (30U)
12949 #define USB_ISTR_LS_DCONN_Msk           (0x1UL << USB_ISTR_LS_DCONN_Pos)/*!< 0x40000000 */
12950 #define USB_ISTR_LS_DCONN               USB_ISTR_LS_DCONN_Msk           /*!< LS_DCONN Mask */
12951 
12952 /******************  Bits definition for USB_DRD_FNR register  ********************/
12953 #define USB_FNR_FN_Pos                  (0U)
12954 #define USB_FNR_FN_Msk                  (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */
12955 #define USB_FNR_FN                      USB_FNR_FN_Msk                  /*!< Frame Number Mask */
12956 #define USB_FNR_LSOF_Pos                (11U)
12957 #define USB_FNR_LSOF_Msk                (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
12958 #define USB_FNR_LSOF                    USB_FNR_LSOF_Msk                /*!< Lost SOF  Mask */
12959 #define USB_FNR_LCK_Pos                 (13U)
12960 #define USB_FNR_LCK_Msk                 (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
12961 #define USB_FNR_LCK                     USB_FNR_LCK_Msk                 /*!< LoCKed Mask */
12962 #define USB_FNR_RXDM_Pos                (14U)
12963 #define USB_FNR_RXDM_Msk                (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
12964 #define USB_FNR_RXDM                    USB_FNR_RXDM_Msk                /*!< status of D- data line Mask */
12965 #define USB_FNR_RXDP_Pos                (15U)
12966 #define USB_FNR_RXDP_Msk                (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
12967 #define USB_FNR_RXDP                    USB_FNR_RXDP_Msk                /*!< status of D+ data line Mask */
12968 
12969 /******************  Bits definition for USB_DRD_DADDR register    ****************/
12970 #define USB_DADDR_ADD_Pos               (0U)
12971 #define USB_DADDR_ADD_Msk               (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
12972 #define USB_DADDR_ADD                   USB_DADDR_ADD_Msk               /*!<  ADD[6:0] bits (Device Address)Mask */
12973 #define USB_DADDR_ADD0_Pos              (0U)
12974 #define USB_DADDR_ADD0_Msk              (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
12975 #define USB_DADDR_ADD0                  USB_DADDR_ADD0_Msk              /*!< Bit 0 Mask */
12976 #define USB_DADDR_ADD1_Pos              (1U)
12977 #define USB_DADDR_ADD1_Msk              (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
12978 #define USB_DADDR_ADD1                  USB_DADDR_ADD1_Msk              /*!< Bit 1 Mask */
12979 #define USB_DADDR_ADD2_Pos              (2U)
12980 #define USB_DADDR_ADD2_Msk              (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
12981 #define USB_DADDR_ADD2                  USB_DADDR_ADD2_Msk              /*!< Bit 2 Mask */
12982 #define USB_DADDR_ADD3_Pos              (3U)
12983 #define USB_DADDR_ADD3_Msk              (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
12984 #define USB_DADDR_ADD3                  USB_DADDR_ADD3_Msk              /*!< Bit 3 Mask */
12985 #define USB_DADDR_ADD4_Pos              (4U)
12986 #define USB_DADDR_ADD4_Msk              (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
12987 #define USB_DADDR_ADD4                  USB_DADDR_ADD4_Msk              /*!< Bit 4 Mask */
12988 #define USB_DADDR_ADD5_Pos              (5U)
12989 #define USB_DADDR_ADD5_Msk              (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
12990 #define USB_DADDR_ADD5                  USB_DADDR_ADD5_Msk              /*!< Bit 5 Mask */
12991 #define USB_DADDR_ADD6_Pos              (6U)
12992 #define USB_DADDR_ADD6_Msk              (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
12993 #define USB_DADDR_ADD6                  USB_DADDR_ADD6_Msk              /*!< Bit 6 Mask */
12994 #define USB_DADDR_EF_Pos                (7U)
12995 #define USB_DADDR_EF_Msk                (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
12996 #define USB_DADDR_EF                    USB_DADDR_EF_Msk                /*!< Enable Function Mask */
12997 
12998 /******************  Bit definition for USB_DRD_BTABLE register  ******************/
12999 #define USB_BTABLE_BTABLE_Pos          (3U)
13000 #define USB_BTABLE_BTABLE_Msk          (0xFFF8UL << USB_BTABLE_BTABLE_Pos)/*!< 0x00000000 */
13001 #define USB_BTABLE_BTABLE              USB_BTABLE_BTABLE_Msk              /*!< Buffer Table Mask */
13002 
13003 /*******************  Bit definition for LPMCSR register  *********************/
13004 #define USB_LPMCSR_LMPEN_Pos           (0U)
13005 #define USB_LPMCSR_LMPEN_Msk           (0x1UL << USB_LPMCSR_LMPEN_Pos)  /*!< 0x00000001 */
13006 #define USB_LPMCSR_LMPEN               USB_LPMCSR_LMPEN_Msk             /*!< LPM support enable Mask */
13007 #define USB_LPMCSR_LPMACK_Pos          (1U)
13008 #define USB_LPMCSR_LPMACK_Msk          (0x1UL << USB_LPMCSR_LPMACK_Pos) /*!< 0x00000002 */
13009 #define USB_LPMCSR_LPMACK              USB_LPMCSR_LPMACK_Msk            /*!< LPM Token acknowledge enable Mask */
13010 #define USB_LPMCSR_REMWAKE_Pos         (3U)
13011 #define USB_LPMCSR_REMWAKE_Msk         (0x1UL << USB_LPMCSR_REMWAKE_Pos)/*!< 0x00000008 */
13012 #define USB_LPMCSR_REMWAKE             USB_LPMCSR_REMWAKE_Msk           /*!< bRemoteWake value received with last ACKed LPM Token Mask */
13013 #define USB_LPMCSR_BESL_Pos            (4U)
13014 #define USB_LPMCSR_BESL_Msk            (0xFUL << USB_LPMCSR_BESL_Pos)   /*!< 0x000000F0 */
13015 #define USB_LPMCSR_BESL                USB_LPMCSR_BESL_Msk              /*!< BESL value received with last ACKed LPM Token Mask */
13016 
13017 /******************  Bits definition for USB_DRD_BCDR register  *******************/
13018 #define USB_BCDR_BCDEN_Pos             (0U)
13019 #define USB_BCDR_BCDEN_Msk             (0x1UL << USB_BCDR_BCDEN_Pos)    /*!< 0x00000001 */
13020 #define USB_BCDR_BCDEN                 USB_BCDR_BCDEN_Msk               /*!< Battery charging detector (BCD) enable Mask */
13021 #define USB_BCDR_DCDEN_Pos             (1U)
13022 #define USB_BCDR_DCDEN_Msk             (0x1UL << USB_BCDR_DCDEN_Pos)    /*!< 0x00000002 */
13023 #define USB_BCDR_DCDEN                 USB_BCDR_DCDEN_Msk               /*!< Data contact detection (DCD) mode enable Mask */
13024 #define USB_BCDR_PDEN_Pos              (2U)
13025 #define USB_BCDR_PDEN_Msk              (0x1UL << USB_BCDR_PDEN_Pos)     /*!< 0x00000004 */
13026 #define USB_BCDR_PDEN                  USB_BCDR_PDEN_Msk                /*!< Primary detection (PD) mode enable Mask */
13027 #define USB_BCDR_SDEN_Pos              (3U)
13028 #define USB_BCDR_SDEN_Msk              (0x1UL << USB_BCDR_SDEN_Pos)     /*!< 0x00000008 */
13029 #define USB_BCDR_SDEN                  USB_BCDR_SDEN_Msk                /*!< Secondary detection (SD) mode enable Mask */
13030 #define USB_BCDR_DCDET_Pos             (4U)
13031 #define USB_BCDR_DCDET_Msk             (0x1UL << USB_BCDR_DCDET_Pos)    /*!< 0x00000010 */
13032 #define USB_BCDR_DCDET                 USB_BCDR_DCDET_Msk               /*!< Data contact detection (DCD) status Mask */
13033 #define USB_BCDR_PDET_Pos              (5U)
13034 #define USB_BCDR_PDET_Msk              (0x1UL << USB_BCDR_PDET_Pos)     /*!< 0x00000020 */
13035 #define USB_BCDR_PDET                  USB_BCDR_PDET_Msk                /*!< Primary detection (PD) status Mask */
13036 #define USB_BCDR_SDET_Pos              (6U)
13037 #define USB_BCDR_SDET_Msk              (0x1UL << USB_BCDR_SDET_Pos)     /*!< 0x00000040 */
13038 #define USB_BCDR_SDET                  USB_BCDR_SDET_Msk                /*!< Secondary detection (SD) status Mask */
13039 #define USB_BCDR_PS2DET_Pos            (7U)
13040 #define USB_BCDR_PS2DET_Msk            (0x1UL << USB_BCDR_PS2DET_Pos)   /*!< 0x00000080 */
13041 #define USB_BCDR_PS2DET                USB_BCDR_PS2DET_Msk              /*!< PS2 port or proprietary charger detected Mask */
13042 #define USB_BCDR_DPPU_Pos              (15U)
13043 #define USB_BCDR_DPPU_Msk              (0x1UL << USB_BCDR_DPPU_Pos)     /*!< 0x00008000 */
13044 #define USB_BCDR_DPPU                  USB_BCDR_DPPU_Msk                /*!< DP Pull-up Enable Mask */
13045 #define USB_BCDR_DPPD_Pos              (15U)
13046 #define USB_BCDR_DPPD_Msk              (0x1UL << USB_BCDR_DPPD_Pos)     /*!< 0x00008000 */
13047 #define USB_BCDR_DPPD                  USB_BCDR_DPPD_Msk                /*!< DP Pull-Down Enable Mask */
13048 
13049 /******************  Bits definition for USB_DRD_CHEP register  *******************/
13050 #define USB_CHEP_ERRRX_Pos             (26U)
13051 #define USB_CHEP_ERRRX_Msk             (0x01UL << USB_CHEP_ERRRX_Pos)   /*!< 0x04000000 */
13052 #define USB_CHEP_ERRRX                 USB_CHEP_ERRRX_Msk               /*!< Receive error */
13053 #define USB_EP_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< EP Receive error */
13054 #define USB_CH_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< CH Receive error */
13055 #define USB_CHEP_ERRTX_Pos             (25U)
13056 #define USB_CHEP_ERRTX_Msk             (0x01UL << USB_CHEP_ERRTX_Pos)   /*!< 0x02000000 */
13057 #define USB_CHEP_ERRTX                 USB_CHEP_ERRTX_Msk               /*!< Transmit error */
13058 #define USB_EP_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< EP Transmit error */
13059 #define USB_CH_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< CH Transmit error */
13060 #define USB_CHEP_LSEP_Pos              (24U)
13061 #define USB_CHEP_LSEP_Msk              (0x01UL << USB_CHEP_LSEP_Pos)    /*!< 0x01000000 */
13062 #define USB_CHEP_LSEP                  USB_CHEP_LSEP_Msk                /*!< Low Speed Endpoint (host with Hub Only) */
13063 #define USB_CHEP_NAK_Pos               (23U)
13064 #define USB_CHEP_NAK_Msk               (0x01UL << USB_CHEP_NAK_Pos)     /*!< 0x00800000 */
13065 #define USB_CHEP_NAK                   USB_CHEP_NAK_Msk                 /*!< Previous NAK detected */
13066 #define USB_CHEP_DEVADDR_Pos           (16U)
13067 #define USB_CHEP_DEVADDR_Msk           (0x7FU << USB_CHEP_DEVADDR_Pos)  /*!< 0x7F000000 */
13068 #define USB_CHEP_DEVADDR               USB_CHEP_DEVADDR_Msk             /* Target Endpoint address*/
13069 #define USB_CHEP_VTRX_Pos              (15U)
13070 #define USB_CHEP_VTRX_Msk              (0x1UL << USB_CHEP_VTRX_Pos)     /*!< 0x00008000 */
13071 #define USB_CHEP_VTRX                  USB_CHEP_VTRX_Msk                /*!< USB valid transaction received Mask */
13072 #define USB_EP_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB Endpoint valid transaction received Mask */
13073 #define USB_CH_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB valid Channel transaction received Mask */
13074 #define USB_CHEP_DTOG_RX_Pos           (14U)
13075 #define USB_CHEP_DTOG_RX_Msk           (0x1UL << USB_CHEP_DTOG_RX_Pos)  /*!< 0x00004000 */
13076 #define USB_CHEP_DTOG_RX               USB_CHEP_DTOG_RX_Msk             /*!< Data Toggle, for reception transfers Mask */
13077 #define USB_EP_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< EP Data Toggle, for reception transfers Mask */
13078 #define USB_CH_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< CH Data Toggle, for reception transfers Mask */
13079 #define USB_CHEP_RX_STRX_Pos           (12U)
13080 #define USB_CHEP_RX_STRX_Msk           (0x3UL << USB_CHEP_RX_STRX_Pos)  /*!< 0x00003000 */
13081 #define USB_CHEP_RX_STRX               USB_CHEP_RX_STRX_Msk             /*!< Status bits, for reception transfers Mask */
13082 #define USB_EP_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for EP reception transfers Mask */
13083 #define USB_CH_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for CH reception transfers Mask */
13084 #define USB_CHEP_SETUP_Pos             (11U)
13085 #define USB_CHEP_SETUP_Msk             (0x1UL << USB_CHEP_SETUP_Pos)    /*!< 0x00000800 */
13086 #define USB_CHEP_SETUP                 USB_CHEP_SETUP_Msk               /*!< Setup transaction completed Mask */
13087 #define USB_EP_SETUP                   USB_CHEP_SETUP_Msk               /*!< EP Setup transaction completed Mask */
13088 #define USB_CH_SETUP                   USB_CHEP_SETUP_Msk               /*!< CH Setup transaction completed Mask */
13089 #define USB_CHEP_UTYPE_Pos             (9U)
13090 #define USB_CHEP_UTYPE_Msk             (0x3UL << USB_CHEP_UTYPE_Pos)    /*!< 0x00000600 */
13091 #define USB_CHEP_UTYPE                 USB_CHEP_UTYPE_Msk               /*!< USB type of transaction Mask */
13092 #define USB_EP_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of EP transaction Mask */
13093 #define USB_CH_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of CH transaction Mask */
13094 #define USB_CHEP_KIND_Pos              (8U)
13095 #define USB_CHEP_KIND_Msk              (0x1UL << USB_CHEP_KIND_Pos)     /*!< 0x00000100 */
13096 #define USB_CHEP_KIND                  USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
13097 #define USB_EP_KIND                    USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
13098 #define USB_CH_KIND                    USB_CHEP_KIND_Msk                /*!< Channel KIND Mask */
13099 #define USB_CHEP_VTTX_Pos              (7U)
13100 #define USB_CHEP_VTTX_Msk              (0x1UL << USB_CHEP_VTTX_Pos)     /*!< 0x00000080 */
13101 #define USB_CHEP_VTTX                  USB_CHEP_VTTX_Msk                /*!< Valid USB transaction transmitted Mask */
13102 #define USB_EP_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB Endpoint valid transaction transmitted Mask */
13103 #define USB_CH_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB valid Channel transaction transmitted Mask */
13104 #define USB_CHEP_DTOG_TX_Pos           (6U)
13105 #define USB_CHEP_DTOG_TX_Msk           (0x1UL << USB_CHEP_DTOG_TX_Pos)  /*!< 0x00000040 */
13106 #define USB_CHEP_DTOG_TX               USB_CHEP_DTOG_TX_Msk             /*!< Data Toggle, for transmission transfers Mask */
13107 #define USB_EP_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< EP Data Toggle, for transmission transfers Mask */
13108 #define USB_CH_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< CH Data Toggle, for transmission transfers Mask */
13109 #define USB_CHEP_TX_STTX_Pos           (4U)
13110 #define USB_CHEP_TX_STTX_Msk           (0x3UL << USB_CHEP_TX_STTX_Pos)  /*!< 0x00000030 */
13111 #define USB_CHEP_TX_STTX               USB_CHEP_TX_STTX_Msk             /*!< Status bits, for transmission transfers Mask */
13112 #define USB_EP_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for EP transmission transfers Mask */
13113 #define USB_CH_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for CH transmission transfers Mask */
13114 #define USB_CHEP_ADDR_Pos              (0U)
13115 #define USB_CHEP_ADDR_Msk              (0xFUL << USB_CHEP_ADDR_Pos)     /*!< 0x0000000F */
13116 #define USB_CHEP_ADDR                  USB_CHEP_ADDR_Msk                /*!< Endpoint address Mask */
13117 
13118 
13119 /* EndPoint Register MASK (no toggle fields) */
13120 #define USB_CHEP_REG_MASK                          (USB_CHEP_ERRRX | USB_CHEP_ERRTX | USB_CHEP_LSEP | \
13121                                                     USB_CHEP_DEVADDR | USB_CHEP_VTRX | USB_CHEP_SETUP | \
13122                                                     USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR | \
13123                                                     USB_CHEP_NAK) /* 0x07FF8F8F */
13124 
13125 #define USB_CHEP_TX_DTOGMASK                       (USB_CHEP_TX_STTX | USB_CHEP_REG_MASK)
13126 #define USB_CHEP_RX_DTOGMASK                       (USB_CHEP_RX_STRX | USB_CHEP_REG_MASK)
13127 
13128 #define USB_CHEP_TX_DTOG1                          (0x00000010UL)           /*!< Channel/EndPoint TX Data Toggle bit1 */
13129 #define USB_CHEP_TX_DTOG2                          (0x00000020UL)           /*!< Channel/EndPoint TX Data Toggle bit2 */
13130 #define USB_CHEP_RX_DTOG1                          (0x00001000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
13131 #define USB_CHEP_RX_DTOG2                          (0x00002000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
13132 
13133 /*!< EP_TYPE[1:0] Channel/EndPoint TYPE */
13134 #define USB_EP_TYPE_MASK                           (0x00000600UL)           /*!< Channel/EndPoint TYPE Mask */
13135 #define USB_EP_BULK                                (0x00000000UL)           /*!< Channel/EndPoint BULK */
13136 #define USB_EP_CONTROL                             (0x00000200UL)           /*!< Channel/EndPoint CONTROL */
13137 #define USB_EP_ISOCHRONOUS                         (0x00000400UL)           /*!< Channel/EndPoint ISOCHRONOUS */
13138 #define USB_EP_INTERRUPT                           (0x00000600UL)           /*!< Channel/EndPoint INTERRUPT */
13139 
13140 #define USB_EP_T_MASK                              ((~USB_EP_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
13141 #define USB_CH_T_MASK                              ((~USB_CH_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
13142 
13143 #define USB_EP_KIND_MASK                           ((~USB_EP_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
13144 #define USB_CH_KIND_MASK                           ((~USB_CH_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
13145 
13146 /*!< STAT_TX[1:0] STATus for TX transfer */
13147 #define USB_EP_TX_DIS                              (0x00000000UL)           /*!< EndPoint TX Disabled */
13148 #define USB_EP_TX_STALL                            (0x00000010UL)           /*!< EndPoint TX STALLed */
13149 #define USB_EP_TX_NAK                              (0x00000020UL)           /*!< EndPoint TX NAKed */
13150 #define USB_EP_TX_VALID                            (0x00000030UL)           /*!< EndPoint TX VALID */
13151 
13152 #define USB_CH_TX_DIS                              (0x00000000UL)           /*!< Channel TX Disabled */
13153 #define USB_CH_TX_STALL                            (0x00000010UL)           /*!< Channel TX STALLed */
13154 #define USB_CH_TX_NAK                              (0x00000020UL)           /*!< Channel TX NAKed */
13155 #define USB_CH_TX_VALID                            (0x00000030UL)           /*!< Channel TX VALID */
13156 
13157 #define USB_EP_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
13158 #define USB_EP_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */
13159 
13160 #define USB_CH_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
13161 #define USB_CH_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */
13162 
13163 /*!< STAT_RX[1:0] STATus for RX transfer */
13164 #define USB_EP_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
13165 #define USB_EP_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
13166 #define USB_EP_RX_NAK                              (0x00002000UL)           /*!< EndPoint RX NAKed */
13167 #define USB_EP_RX_VALID                            (0x00003000UL)           /*!< EndPoint RX VALID */
13168 
13169 #define USB_EP_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
13170 #define USB_EP_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */
13171 
13172 
13173 
13174 #define USB_CH_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
13175 #define USB_CH_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
13176 #define USB_CH_RX_NAK                              (0x00002000UL)           /*!< Channel RX NAKed */
13177 #define USB_CH_RX_VALID                            (0x00003000UL)           /*!< Channel RX VALID */
13178 
13179 #define USB_CH_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
13180 #define USB_CH_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */
13181 
13182 /*! <used For Double Buffer Enable Disable */
13183 #define USB_CHEP_DB_MSK                            (0xFFFF0F0FUL)
13184 
13185 /*Buffer Descriptor Mask*/
13186 #define USB_PMA_TXBD_ADDMSK                        (0xFFFF0000UL)
13187 #define USB_PMA_TXBD_COUNTMSK                      (0x0000FFFFUL)
13188 #define USB_PMA_RXBD_ADDMSK                        (0xFFFF0000UL)
13189 #define USB_PMA_RXBD_COUNTMSK                      (0x03FFFFFFUL)
13190 
13191 /*!< USB PMA SIZE */
13192 #define USB_DRD_PMA_SIZE                                  (2048U)           /*!< USB PMA Size 2Kbyte */
13193 
13194 #define USB_DRD_FS_EP_NBR                                    (8U)           /*!< Number of USB Device endpoints */
13195 #define USB_DRD_FS_CH_NBR                                    (8U)           /*!< Number of USB Host channels */
13196 
13197 
13198 
13199 
13200 /** @addtogroup STM32H5xx_Peripheral_Exported_macros
13201   * @{
13202   */
13203 
13204 /******************************* ADC Instances ********************************/
13205 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS))
13206 
13207 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS))
13208 
13209 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS))
13210 
13211 /******************************* CRC Instances ********************************/
13212 #define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS))
13213 
13214 /******************************* DAC Instances ********************************/
13215 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS))
13216 
13217 /******************************** DMA Instances *******************************/
13218 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
13219                                        ((INSTANCE) == GPDMA1_Channel1_NS)  || \
13220                                        ((INSTANCE) == GPDMA1_Channel2_NS)  || \
13221                                        ((INSTANCE) == GPDMA1_Channel3_NS)  || \
13222                                        ((INSTANCE) == GPDMA1_Channel4_NS)  || \
13223                                        ((INSTANCE) == GPDMA1_Channel5_NS)  || \
13224                                        ((INSTANCE) == GPDMA1_Channel6_NS)  || \
13225                                        ((INSTANCE) == GPDMA1_Channel7_NS)  || \
13226                                        ((INSTANCE) == GPDMA2_Channel0_NS)  || \
13227                                        ((INSTANCE) == GPDMA2_Channel1_NS)  || \
13228                                        ((INSTANCE) == GPDMA2_Channel2_NS)  || \
13229                                        ((INSTANCE) == GPDMA2_Channel3_NS)  || \
13230                                        ((INSTANCE) == GPDMA2_Channel4_NS)  || \
13231                                        ((INSTANCE) == GPDMA2_Channel5_NS)  || \
13232                                        ((INSTANCE) == GPDMA2_Channel6_NS)  || \
13233                                        ((INSTANCE) == GPDMA2_Channel7_NS))
13234 
13235 #define IS_GPDMA_INSTANCE(INSTANCE)   IS_DMA_ALL_INSTANCE(INSTANCE)
13236 
13237 #define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS)  || \
13238                                                  ((INSTANCE) == GPDMA1_Channel7_NS)  || \
13239                                                  ((INSTANCE) == GPDMA2_Channel6_NS)  || \
13240                                                  ((INSTANCE) == GPDMA2_Channel7_NS))
13241 
13242 #define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
13243                                          ((INSTANCE) == GPDMA1_Channel7_NS)  || \
13244                                          ((INSTANCE) == GPDMA2_Channel0_NS)  || \
13245                                          ((INSTANCE) == GPDMA2_Channel7_NS))
13246 
13247 /****************************** RAMCFG Instances ********************************/
13248 #define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \
13249                                           ((INSTANCE) == RAMCFG_SRAM2_NS) || \
13250                                           ((INSTANCE) == RAMCFG_BKPRAM_NS))
13251 
13252 /***************************** RAMCFG ECC Instances *****************************/
13253 #define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \
13254                                           ((INSTANCE) == RAMCFG_SRAM2_NS) || \
13255                                           ((INSTANCE) == RAMCFG_BKPRAM_NS))
13256 
13257 /************************ RAMCFG Write Protection Instances *********************/
13258 #define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS))
13259 
13260 /******************************* GPIO Instances *******************************/
13261 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \
13262                                         ((INSTANCE) == GPIOB_NS) || \
13263                                         ((INSTANCE) == GPIOC_NS) || \
13264                                         ((INSTANCE) == GPIOD_NS) || \
13265                                         ((INSTANCE) == GPIOH_NS))
13266 
13267 /******************************* DTS Instances *******************************/
13268 #define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS))
13269 
13270 /******************************* GPIO AF Instances ****************************/
13271 /* On H5, all GPIO Bank support AF */
13272 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
13273 
13274 /**************************** GPIO Lock Instances *****************************/
13275 /* On H5, all GPIO Bank support the Lock mechanism */
13276 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
13277 
13278 /******************************** I2C Instances *******************************/
13279 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C2_NS))
13280 
13281 /****************** I2C Instances : wakeup capability from stop modes *********/
13282 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
13283 
13284 /******************************** I3C Instances *******************************/
13285 #define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C2_NS))
13286 
13287 /******************************* RNG Instances ********************************/
13288 #define IS_RNG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == RNG_NS))
13289 
13290 /****************************** RTC Instances *********************************/
13291 #define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS))
13292 
13293 /****************************** FDCAN Instances *******************************/
13294 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS))
13295 
13296 /****************************** SMBUS Instances *******************************/
13297 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C2_NS))
13298 
13299 
13300 /******************************** SPI Instances *******************************/
13301 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS))
13302 
13303 #define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) ==  ((SPI_TypeDef *) 0xDEADDEADUL))
13304 
13305 #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS))
13306 
13307 /****************** LPTIM Instances : All supported instances *****************/
13308 #define IS_LPTIM_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13309 
13310 /****************** LPTIM Instances : DMA supported instances *****************/
13311 #define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13312 
13313 /************* LPTIM Instances : at least 1 capture/compare channel ***********/
13314 #define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13315 
13316 /************* LPTIM Instances : at least 2 capture/compare channel ***********/
13317 #define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13318 
13319 /****************** LPTIM Instances : supporting encoder interface **************/
13320 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13321 
13322 /****************** LPTIM Instances : supporting Input Capture **************/
13323 #define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13324 
13325 /****************** TIM Instances : All supported instances *******************/
13326 #define IS_TIM_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
13327                                     ((INSTANCE) == TIM2_NS)  || \
13328                                     ((INSTANCE) == TIM3_NS)  || \
13329                                     ((INSTANCE) == TIM6_NS)  || \
13330                                     ((INSTANCE) == TIM7_NS))
13331 
13332 /****************** TIM Instances : supporting 32 bits counter ****************/
13333 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS))
13334 
13335 /****************** TIM Instances : supporting the break function *************/
13336 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS))
13337 
13338 /************** TIM Instances : supporting Break source selection *************/
13339 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS))
13340 
13341 /****************** TIM Instances : supporting 2 break inputs *****************/
13342 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS))
13343 
13344 /************* TIM Instances : at least 1 capture/compare channel *************/
13345 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13346                                          ((INSTANCE) == TIM2_NS)  || \
13347                                          ((INSTANCE) == TIM3_NS))
13348 /************ TIM Instances : at least 2 capture/compare channels *************/
13349 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13350                                          ((INSTANCE) == TIM2_NS)  || \
13351                                          ((INSTANCE) == TIM3_NS))
13352 
13353 /************ TIM Instances : at least 3 capture/compare channels *************/
13354 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13355                                          ((INSTANCE) == TIM2_NS)  || \
13356                                          ((INSTANCE) == TIM3_NS))
13357 
13358 /************ TIM Instances : at least 4 capture/compare channels *************/
13359 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13360                                          ((INSTANCE) == TIM2_NS)  || \
13361                                          ((INSTANCE) == TIM3_NS))
13362 
13363 /****************** TIM Instances : at least 5 capture/compare channels *******/
13364 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS))
13365 
13366 /****************** TIM Instances : at least 6 capture/compare channels *******/
13367 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS))
13368 
13369 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
13370 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
13371                                             ((INSTANCE) == TIM2_NS)  || \
13372                                             ((INSTANCE) == TIM3_NS)  || \
13373                                             ((INSTANCE) == TIM6_NS)  || \
13374                                             ((INSTANCE) == TIM7_NS))
13375 
13376 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
13377 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13378                                             ((INSTANCE) == TIM2_NS)  || \
13379                                             ((INSTANCE) == TIM3_NS))
13380 
13381 /******************** TIM Instances : DMA burst feature ***********************/
13382 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
13383                                             ((INSTANCE) == TIM2_NS)  || \
13384                                             ((INSTANCE) == TIM3_NS))
13385 
13386 /******************* TIM Instances : output(s) available **********************/
13387 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
13388     ((((INSTANCE) == TIM1_NS)  && \
13389      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13390       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13391       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13392       ((CHANNEL) == TIM_CHANNEL_4) ||          \
13393       ((CHANNEL) == TIM_CHANNEL_5) ||          \
13394       ((CHANNEL) == TIM_CHANNEL_6)))           \
13395      ||                                        \
13396      (((INSTANCE) == TIM2_NS)  && \
13397      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13398       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13399       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13400       ((CHANNEL) == TIM_CHANNEL_4)))           \
13401      ||                                        \
13402      (((INSTANCE) == TIM3_NS)  && \
13403      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13404       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13405       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13406       ((CHANNEL) == TIM_CHANNEL_4))))
13407 
13408 /****************** TIM Instances : supporting complementary output(s) ********/
13409 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
13410     ((((INSTANCE) == TIM1_NS)  && \
13411      (((CHANNEL) == TIM_CHANNEL_1) ||           \
13412       ((CHANNEL) == TIM_CHANNEL_2) ||           \
13413       ((CHANNEL) == TIM_CHANNEL_3) ||           \
13414       ((CHANNEL) == TIM_CHANNEL_4))))
13415 
13416 /****************** TIM Instances : supporting clock division *****************/
13417 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS) || \
13418                                                     ((INSTANCE) == TIM2_NS) || \
13419                                                     ((INSTANCE) == TIM3_NS))
13420 
13421 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
13422 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
13423                                                         ((INSTANCE) == TIM2_NS) || \
13424                                                         ((INSTANCE) == TIM3_NS))
13425 
13426 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
13427 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
13428                                                         ((INSTANCE) == TIM2_NS) || \
13429                                                         ((INSTANCE) == TIM3_NS))
13430 
13431 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
13432 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS) || \
13433                                                         ((INSTANCE) == TIM2_NS) || \
13434                                                         ((INSTANCE) == TIM3_NS))
13435 
13436 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
13437 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS) || \
13438                                                         ((INSTANCE) == TIM2_NS) || \
13439                                                         ((INSTANCE) == TIM3_NS))
13440 
13441 
13442 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
13443 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS))
13444 
13445 /****************** TIM Instances : supporting commutation event generation ***/
13446 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS))
13447 
13448 /****************** TIM Instances : supporting counting mode selection ********/
13449 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS) || \
13450                                                         ((INSTANCE) == TIM2_NS) || \
13451                                                         ((INSTANCE) == TIM3_NS))
13452 
13453 /****************** TIM Instances : supporting encoder interface **************/
13454 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS) || \
13455                                                         ((INSTANCE) == TIM2_NS) || \
13456                                                         ((INSTANCE) == TIM3_NS))
13457 
13458 /****************** TIM Instances : supporting Hall sensor interface **********/
13459 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
13460                                                         ((INSTANCE) == TIM2_NS) || \
13461                                                         ((INSTANCE) == TIM3_NS))
13462 
13463 /**************** TIM Instances : external trigger input available ************/
13464 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS) || \
13465                                                         ((INSTANCE) == TIM2_NS) || \
13466                                                         ((INSTANCE) == TIM3_NS))
13467 
13468 /************* TIM Instances : supporting ETR source selection ***************/
13469 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13470                                              ((INSTANCE) == TIM2_NS) || \
13471                                              ((INSTANCE) == TIM3_NS))
13472 
13473 
13474 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
13475 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13476                                             ((INSTANCE) == TIM2_NS)  || \
13477                                             ((INSTANCE) == TIM3_NS)  || \
13478                                             ((INSTANCE) == TIM6_NS)  || \
13479                                             ((INSTANCE) == TIM7_NS))
13480 
13481 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
13482 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13483                                              ((INSTANCE) == TIM2_NS) || \
13484                                              ((INSTANCE) == TIM3_NS))
13485 
13486 /****************** TIM Instances : supporting OCxREF clear *******************/
13487 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13488                                                    ((INSTANCE) == TIM2_NS) || \
13489                                                    ((INSTANCE) == TIM3_NS))
13490 
13491 /****************** TIM Instances : remapping capability **********************/
13492 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13493                                             ((INSTANCE) == TIM2_NS) || \
13494                                             ((INSTANCE) == TIM3_NS))
13495 
13496 /****************** TIM Instances : supporting repetition counter *************/
13497 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS))
13498 
13499 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
13500 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS))
13501 
13502 /******************* TIM Instances : Timer input XOR function *****************/
13503 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS) || \
13504                                             ((INSTANCE) == TIM2_NS) || \
13505                                             ((INSTANCE) == TIM3_NS))
13506 
13507 /******************* TIM Instances : Timer input selection ********************/
13508 #define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13509                                             ((INSTANCE) == TIM2_NS) || \
13510                                             ((INSTANCE) == TIM3_NS))
13511 
13512 /****************** TIM Instances : Advanced timer instances *******************/
13513 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS))
13514 
13515 /****************** TIM Instances : supporting synchronization ****************/
13516 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((INSTANCE) == TIM1_NS)  || \
13517                                                 ((INSTANCE) == TIM2_NS)  || \
13518                                                 ((INSTANCE) == TIM3_NS)  || \
13519                                                 ((INSTANCE) == TIM6_NS)  || \
13520                                                 ((INSTANCE) == TIM7_NS))
13521 
13522 /******************** USART Instances : Synchronous mode **********************/
13523 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13524                                      ((INSTANCE) == USART2_NS)  || \
13525                                      ((INSTANCE) == USART3_NS))
13526 
13527 /******************** UART Instances : Asynchronous mode **********************/
13528 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13529                                      ((INSTANCE) == USART2_NS) || \
13530                                      ((INSTANCE) == USART3_NS))
13531 
13532 /*********************** UART Instances : FIFO mode ***************************/
13533 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13534                                          ((INSTANCE) == USART2_NS)  || \
13535                                          ((INSTANCE) == USART3_NS)  || \
13536                                          ((INSTANCE) == LPUART1_NS))
13537 
13538 /*********************** UART Instances : SPI Slave mode **********************/
13539 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13540                                               ((INSTANCE) == USART2_NS) || \
13541                                               ((INSTANCE) == USART3_NS))
13542 
13543 /******************************** I2S Instances *******************************/
13544 #define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
13545                                          ((INSTANCE) == SPI2) || \
13546                                          ((INSTANCE) == SPI3))
13547 
13548 /****************** UART Instances : Auto Baud Rate detection ****************/
13549 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13550                                                             ((INSTANCE) == USART2_NS) || \
13551                                                             ((INSTANCE) == USART3_NS))
13552 
13553 /****************** UART Instances : Driver Enable *****************/
13554 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1_NS)  || \
13555                                                       ((INSTANCE) == USART2_NS)  || \
13556                                                       ((INSTANCE) == USART3_NS)  || \
13557                                                       ((INSTANCE) == LPUART1_NS))
13558 
13559 /******************** UART Instances : Half-Duplex mode **********************/
13560 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || \
13561                                                  ((INSTANCE) == USART2_NS)  || \
13562                                                  ((INSTANCE) == USART3_NS)  || \
13563                                                  ((INSTANCE) == LPUART1_NS))
13564 
13565 /****************** UART Instances : Hardware Flow control ********************/
13566 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13567                                            ((INSTANCE) == USART2_NS)  || \
13568                                            ((INSTANCE) == USART3_NS)  || \
13569                                            ((INSTANCE) == LPUART1_NS))
13570 /******************** UART Instances : LIN mode **********************/
13571 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || \
13572                                           ((INSTANCE) == USART2_NS) || \
13573                                           ((INSTANCE) == USART3_NS))
13574 
13575 /******************** UART Instances : Wake-up from Stop mode **********************/
13576 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || \
13577                                                       ((INSTANCE) == USART2_NS)  || \
13578                                                       ((INSTANCE) == USART3_NS)  || \
13579                                                       ((INSTANCE) == LPUART1_NS))
13580 
13581 /*********************** UART Instances : IRDA mode ***************************/
13582 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13583                                     ((INSTANCE) == USART2_NS) || \
13584                                     ((INSTANCE) == USART3_NS))
13585 
13586 /********************* USART Instances : Smard card mode ***********************/
13587 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13588                                          ((INSTANCE) == USART2_NS) || \
13589                                          ((INSTANCE) == USART3_NS))
13590 
13591 /******************** LPUART Instance *****************************************/
13592 #define IS_LPUART_INSTANCE(INSTANCE)    (((INSTANCE) == LPUART1_NS))
13593 
13594 /****************************** IWDG Instances ********************************/
13595 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG_NS))
13596 
13597 /****************************** WWDG Instances ********************************/
13598 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG_NS))
13599 
13600 /******************************* USB DRD FS HCD Instances *************************/
13601 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS)
13602 
13603 /******************************* USB DRD FS PCD Instances *************************/
13604 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS)
13605 
13606 /******************************** COMP Instances ******************************/
13607 #define IS_COMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
13608 
13609 /******************************** OPAMP Instances *****************************/
13610 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
13611 
13612 /** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */
13613 
13614 /** @} */ /* End of group STM32H503xx */
13615 
13616 /** @} */ /* End of group ST */
13617 
13618 #ifdef __cplusplus
13619 }
13620 #endif
13621 
13622 #endif  /* STM32H503xx_H */
13623