1 /* 2 * Copyright (C) 2018-2021 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef PHY_COMPHY_3700_H 9 #define PHY_COMPHY_3700_H 10 11 #define PLL_SET_DELAY_US 600 12 #define COMPHY_PLL_TIMEOUT 1000 13 #define REG_16_BIT_MASK 0xFFFF 14 15 #define COMPHY_SELECTOR_PHY_REG 0xFC 16 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIE */ 17 #define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0) 18 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */ 19 #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4) 20 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */ 21 #define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8) 22 23 /* SATA PHY register offset */ 24 #define SATAPHY_LANE2_REG_BASE_OFFSET 0x200 25 26 /* USB3 PHY offset compared to SATA PHY */ 27 #define USB3PHY_LANE2_REG_BASE_OFFSET 0x200 28 29 /* Comphy lane2 indirect access register offset */ 30 #define COMPHY_LANE2_INDIR_ADDR_OFFSET 0x0 31 #define COMPHY_LANE2_INDIR_DATA_OFFSET 0x4 32 33 /* PHY shift to get related register address */ 34 enum { 35 PCIE = 1, 36 USB3, 37 }; 38 39 #define PCIEPHY_SHFT 2 40 #define USB3PHY_SHFT 2 41 #define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT) 42 43 /* PHY register */ 44 #define COMPHY_POWER_PLL_CTRL 0x01 45 #define PWR_PLL_CTRL_ADDR(unit) (COMPHY_POWER_PLL_CTRL * PHY_SHFT(unit)) 46 #define PU_IVREF_BIT BIT(15) 47 #define PU_PLL_BIT BIT(14) 48 #define PU_RX_BIT BIT(13) 49 #define PU_TX_BIT BIT(12) 50 #define PU_TX_INTP_BIT BIT(11) 51 #define PU_DFE_BIT BIT(10) 52 #define RESET_DTL_RX_BIT BIT(9) 53 #define PLL_LOCK_BIT BIT(8) 54 #define REF_FREF_SEL_OFFSET 0 55 #define REF_FREF_SEL_MASK (0x1F << REF_FREF_SEL_OFFSET) 56 #define REF_FREF_SEL_SERDES_25MHZ (0x1 << REF_FREF_SEL_OFFSET) 57 #define REF_FREF_SEL_SERDES_40MHZ (0x3 << REF_FREF_SEL_OFFSET) 58 #define REF_FREF_SEL_SERDES_50MHZ (0x4 << REF_FREF_SEL_OFFSET) 59 #define REF_FREF_SEL_PCIE_USB3_25MHZ (0x2 << REF_FREF_SEL_OFFSET) 60 #define REF_FREF_SEL_PCIE_USB3_40MHZ (0x3 << REF_FREF_SEL_OFFSET) 61 #define PHY_MODE_OFFSET 5 62 #define PHY_MODE_MASK (7 << PHY_MODE_OFFSET) 63 #define PHY_MODE_SATA (0x0 << PHY_MODE_OFFSET) 64 #define PHY_MODE_PCIE (0x3 << PHY_MODE_OFFSET) 65 #define PHY_MODE_SGMII (0x4 << PHY_MODE_OFFSET) 66 #define PHY_MODE_USB3 (0x5 << PHY_MODE_OFFSET) 67 68 #define COMPHY_KVCO_CAL_CTRL 0x02 69 #define KVCO_CAL_CTRL_ADDR(unit) (COMPHY_KVCO_CAL_CTRL * PHY_SHFT(unit)) 70 #define USE_MAX_PLL_RATE_BIT BIT(12) 71 #define SPEED_PLL_OFFSET 2 72 #define SPEED_PLL_MASK (0x3F << SPEED_PLL_OFFSET) 73 #define SPEED_PLL_VALUE_16 (0x10 << SPEED_PLL_OFFSET) 74 75 #define COMPHY_DIG_LOOPBACK_EN 0x23 76 #define DIG_LOOPBACK_EN_ADDR(unit) (COMPHY_DIG_LOOPBACK_EN * \ 77 PHY_SHFT(unit)) 78 #define SEL_DATA_WIDTH_OFFSET 10 79 #define SEL_DATA_WIDTH_MASK (0x3 << SEL_DATA_WIDTH_OFFSET) 80 #define DATA_WIDTH_10BIT (0x0 << SEL_DATA_WIDTH_OFFSET) 81 #define DATA_WIDTH_20BIT (0x1 << SEL_DATA_WIDTH_OFFSET) 82 #define DATA_WIDTH_40BIT (0x2 << SEL_DATA_WIDTH_OFFSET) 83 #define PLL_READY_TX_BIT BIT(4) 84 85 #define COMPHY_SYNC_PATTERN 0x24 86 #define SYNC_PATTERN_ADDR(unit) (COMPHY_SYNC_PATTERN * PHY_SHFT(unit)) 87 #define TXD_INVERT_BIT BIT(10) 88 #define RXD_INVERT_BIT BIT(11) 89 90 #define COMPHY_SYNC_MASK_GEN 0x25 91 #define PHY_GEN_MAX_OFFSET 10 92 #define PHY_GEN_MAX_MASK (3 << PHY_GEN_MAX_OFFSET) 93 #define PHY_GEN_MAX_USB3_5G (1 << PHY_GEN_MAX_OFFSET) 94 95 #define COMPHY_ISOLATION_CTRL 0x26 96 #define ISOLATION_CTRL_ADDR(unit) (COMPHY_ISOLATION_REG * PHY_SHFT(unit)) 97 #define PHY_ISOLATE_MODE BIT(15) 98 99 #define COMPHY_GEN2_SET2 0x3e 100 #define GEN2_SET2_ADDR(unit) (COMPHY_GEN2_SET2 * PHY_SHFT(unit)) 101 #define GS2_TX_SSC_AMP_VALUE_20 BIT(14) 102 #define GS2_TX_SSC_AMP_OFF 9 103 #define GS2_TX_SSC_AMP_LEN 7 104 #define GS2_TX_SSC_AMP_MASK (((1 << GS2_TX_SSC_AMP_LEN) - 1) << \ 105 GS2_TX_SSC_AMP_OFF) 106 #define GS2_VREG_RXTX_MAS_ISET_OFF 7 107 #define GS2_VREG_RXTX_MAS_ISET_60U (0 << GS2_VREG_RXTX_MAS_ISET_OFF) 108 #define GS2_VREG_RXTX_MAS_ISET_80U (1 << GS2_VREG_RXTX_MAS_ISET_OFF) 109 #define GS2_VREG_RXTX_MAS_ISET_100U (2 << GS2_VREG_RXTX_MAS_ISET_OFF) 110 #define GS2_VREG_RXTX_MAS_ISET_120U (3 << GS2_VREG_RXTX_MAS_ISET_OFF) 111 #define GS2_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8)) 112 #define GS2_RSVD_6_0_OFF 0 113 #define GS2_RSVD_6_0_LEN 7 114 #define GS2_RSVD_6_0_MASK (((1 << GS2_RSVD_6_0_LEN) - 1) << \ 115 GS2_RSVD_6_0_OFF) 116 117 #define COMPHY_GEN3_SET2 0x3f 118 #define GEN3_SET2_ADDR(unit) (COMPHY_GEN3_SET2 * PHY_SHFT(unit)) 119 120 #define COMPHY_IDLE_SYNC_EN 0x48 121 #define IDLE_SYNC_EN_ADDR(unit) (COMPHY_IDLE_SYNC_EN * PHY_SHFT(unit)) 122 #define IDLE_SYNC_EN BIT(12) 123 #define IDLE_SYNC_EN_DEFAULT_VALUE 0x60 124 125 #define COMPHY_MISC_CTRL0 0x4F 126 #define MISC_CTRL0_ADDR(unit) (COMPHY_MISC_CTRL0 * PHY_SHFT(unit)) 127 #define CLK100M_125M_EN BIT(4) 128 #define TXDCLK_2X_SEL BIT(6) 129 #define CLK500M_EN BIT(7) 130 #define PHY_REF_CLK_SEL BIT(10) 131 #define MISC_CTRL0_DEFAULT_VALUE 0xA00D 132 133 #define COMPHY_MISC_CTRL1 0x73 134 #define MISC_CTRL1_ADDR(unit) (COMPHY_MISC_CTRL1 * PHY_SHFT(unit)) 135 #define SEL_BITS_PCIE_FORCE BIT(15) 136 137 #define COMPHY_GEN2_SET3 0x112 138 #define GS3_FFE_CAP_SEL_MASK 0xF 139 #define GS3_FFE_CAP_SEL_VALUE 0xF 140 141 #define COMPHY_LANE_CFG0 0x180 142 #define LANE_CFG0_ADDR(unit) (COMPHY_LANE_CFG0 * PHY_SHFT(unit)) 143 #define PRD_TXDEEMPH0_MASK BIT(0) 144 #define PRD_TXMARGIN_MASK (BIT(1) | BIT(2) | BIT(3)) 145 #define PRD_TXSWING_MASK BIT(4) 146 #define CFG_TX_ALIGN_POS_MASK (BIT(5) | BIT(6) | BIT(7) | BIT(8)) 147 148 #define COMPHY_LANE_CFG1 0x181 149 #define LANE_CFG1_ADDR(unit) (COMPHY_LANE_CFG1 * PHY_SHFT(unit)) 150 #define PRD_TXDEEMPH1_MASK BIT(15) 151 #define USE_MAX_PLL_RATE_EN BIT(9) 152 #define TX_DET_RX_MODE BIT(6) 153 #define GEN2_TX_DATA_DLY_MASK (BIT(3) | BIT(4)) 154 #define GEN2_TX_DATA_DLY_DEFT (2 << 3) 155 #define TX_ELEC_IDLE_MODE_EN BIT(0) 156 157 #define COMPHY_LANE_STAT1 0x183 158 #define LANE_STAT1_ADDR(unit) (COMPHY_LANE_STAT1 * PHY_SHFT(unit)) 159 #define TXDCLK_PCLK_EN BIT(0) 160 161 #define COMPHY_LANE_CFG4 0x188 162 #define LANE_CFG4_ADDR(unit) (COMPHY_LANE_CFG4 * PHY_SHFT(unit)) 163 #define SPREAD_SPECTRUM_CLK_EN BIT(7) 164 165 #define COMPHY_RST_CLK_CTRL 0x1C1 166 #define RST_CLK_CTRL_ADDR(unit) (COMPHY_RST_CLK_CTRL * PHY_SHFT(unit)) 167 #define SOFT_RESET BIT(0) 168 #define MODE_CORE_CLK_FREQ_SEL BIT(9) 169 #define MODE_PIPE_WIDTH_32 BIT(3) 170 #define MODE_REFDIV_OFFSET 4 171 #define MODE_REFDIV_LEN 2 172 #define MODE_REFDIV_MASK (0x3 << MODE_REFDIV_OFFSET) 173 #define MODE_REFDIV_BY_4 (0x2 << MODE_REFDIV_OFFSET) 174 175 #define COMPHY_TEST_MODE_CTRL 0x1C2 176 #define TEST_MODE_CTRL_ADDR(unit) (COMPHY_TEST_MODE_CTRL * PHY_SHFT(unit)) 177 #define MODE_MARGIN_OVERRIDE BIT(2) 178 179 #define COMPHY_CLK_SRC_LO 0x1C3 180 #define CLK_SRC_LO_ADDR(unit) (COMPHY_CLK_SRC_LO * PHY_SHFT(unit)) 181 #define MODE_CLK_SRC BIT(0) 182 #define BUNDLE_PERIOD_SEL BIT(1) 183 #define BUNDLE_PERIOD_SCALE_MASK (BIT(2) | BIT(3)) 184 #define BUNDLE_SAMPLE_CTRL BIT(4) 185 #define PLL_READY_DLY_MASK (BIT(5) | BIT(6) | BIT(7)) 186 #define CFG_SEL_20B BIT(15) 187 188 #define COMPHY_PWR_MGM_TIM1 0x1D0 189 #define PWR_MGM_TIM1_ADDR(unit) (COMPHY_PWR_MGM_TIM1 * PHY_SHFT(unit)) 190 #define CFG_PM_OSCCLK_WAIT_OFF 12 191 #define CFG_PM_OSCCLK_WAIT_LEN 4 192 #define CFG_PM_OSCCLK_WAIT_MASK (((1 << CFG_PM_OSCCLK_WAIT_LEN) - 1) \ 193 << CFG_PM_OSCCLK_WAIT_OFF) 194 #define CFG_PM_RXDEN_WAIT_OFF 8 195 #define CFG_PM_RXDEN_WAIT_LEN 4 196 #define CFG_PM_RXDEN_WAIT_MASK (((1 << CFG_PM_RXDEN_WAIT_LEN) - 1) \ 197 << CFG_PM_RXDEN_WAIT_OFF) 198 #define CFG_PM_RXDEN_WAIT_1_UNIT (1 << CFG_PM_RXDEN_WAIT_OFF) 199 #define CFG_PM_RXDLOZ_WAIT_OFF 0 200 #define CFG_PM_RXDLOZ_WAIT_LEN 8 201 #define CFG_PM_RXDLOZ_WAIT_MASK (((1 << CFG_PM_RXDLOZ_WAIT_LEN) - 1) \ 202 << CFG_PM_RXDLOZ_WAIT_OFF) 203 #define CFG_PM_RXDLOZ_WAIT_7_UNIT (7 << CFG_PM_RXDLOZ_WAIT_OFF) 204 #define CFG_PM_RXDLOZ_WAIT_12_UNIT (0xC << CFG_PM_RXDLOZ_WAIT_OFF) 205 206 /* 207 * This register is not from PHY lane register space. It only exists in the 208 * indirect register space, before the actual PHY lane 2 registers. So the 209 * offset is absolute, not relative to SATAPHY_LANE2_REG_BASE_OFFSET. 210 * It is used only for SATA PHY initialization. 211 */ 212 #define COMPHY_RESERVED_REG 0x0E 213 #define PHYCTRL_FRM_PIN_BIT BIT(13) 214 215 /* SGMII */ 216 #define COMPHY_PHY_CFG1_OFFSET(lane) ((1 - (lane)) * 0x28) 217 #define PIN_PU_IVREF_BIT BIT(1) 218 #define PIN_RESET_CORE_BIT BIT(11) 219 #define PIN_RESET_COMPHY_BIT BIT(12) 220 #define PIN_PU_PLL_BIT BIT(16) 221 #define PIN_PU_RX_BIT BIT(17) 222 #define PIN_PU_TX_BIT BIT(18) 223 #define PIN_TX_IDLE_BIT BIT(19) 224 #define GEN_RX_SEL_OFFSET 22 225 #define GEN_RX_SEL_MASK (0xF << GEN_RX_SEL_OFFSET) 226 #define GEN_TX_SEL_OFFSET 26 227 #define GEN_TX_SEL_MASK (0xF << GEN_TX_SEL_OFFSET) 228 #define PHY_RX_INIT_BIT BIT(30) 229 #define SD_SPEED_1_25_G 0x6 230 #define SD_SPEED_3_125_G 0x8 231 232 /* COMPHY status reg: 233 * lane0: USB3/GbE1 PHY Status 1 234 * lane1: PCIe/GbE0 PHY Status 1 235 */ 236 #define COMPHY_PHY_STATUS_OFFSET(lane) (0x18 + (1 - (lane)) * 0x28) 237 #define PHY_RX_INIT_DONE_BIT BIT(0) 238 #define PHY_PLL_READY_RX_BIT BIT(2) 239 #define PHY_PLL_READY_TX_BIT BIT(3) 240 241 #define SGMIIPHY_ADDR(off, base) ((((off) & 0x00007FF) * 2) + (base)) 242 243 #define MAX_LANE_NR 3 244 245 /* comphy API */ 246 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode); 247 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode); 248 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode); 249 #endif /* PHY_COMPHY_3700_H */ 250
