1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_COMMON_REG_H__ 35 #define __HW_COMMON_REG_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the COMMON_REG register offsets. 40 // 41 //***************************************************************************** 42 #define COMMON_REG_O_I2C_Properties_Register \ 43 0x00000000 44 45 #define COMMON_REG_O_SPI_Properties_Register \ 46 0x00000004 47 48 #define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \ 49 0x0000000C 50 51 #define COMMON_REG_O_APPS_sh_resource_Interrupt_status \ 52 0x00000010 53 54 #define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \ 55 0x00000014 56 57 #define COMMON_REG_O_NWP_sh_resource_Interrupt_status \ 58 0x00000018 59 60 #define COMMON_REG_O_Flash_ctrl_reg \ 61 0x0000001C 62 63 #define COMMON_REG_O_Bus_matrix_M0_segment_access_config \ 64 0x00000024 65 66 #define COMMON_REG_O_Bus_matrix_M1_segment_access_config \ 67 0x00000028 68 69 #define COMMON_REG_O_Bus_matrix_M2_segment_access_config \ 70 0x0000002C 71 72 #define COMMON_REG_O_Bus_matrix_M3_segment_access_config \ 73 0x00000030 74 75 #define COMMON_REG_O_Bus_matrix_M4_segment_access_config \ 76 0x00000034 77 78 #define COMMON_REG_O_Bus_matrix_M5_segment_access_config \ 79 0x00000038 80 81 #define COMMON_REG_O_GPIO_properties_register \ 82 0x0000003C 83 84 #define COMMON_REG_O_APPS_NW_SEMAPHORE1 \ 85 0x00000040 86 87 #define COMMON_REG_O_APPS_NW_SEMAPHORE2 \ 88 0x00000044 89 90 #define COMMON_REG_O_APPS_NW_SEMAPHORE3 \ 91 0x00000048 92 93 #define COMMON_REG_O_APPS_NW_SEMAPHORE4 \ 94 0x0000004C 95 96 #define COMMON_REG_O_APPS_NW_SEMAPHORE5 \ 97 0x00000050 98 99 #define COMMON_REG_O_APPS_NW_SEMAPHORE6 \ 100 0x00000054 101 102 #define COMMON_REG_O_APPS_NW_SEMAPHORE7 \ 103 0x00000058 104 105 #define COMMON_REG_O_APPS_NW_SEMAPHORE8 \ 106 0x0000005C 107 108 #define COMMON_REG_O_APPS_NW_SEMAPHORE9 \ 109 0x00000060 110 111 #define COMMON_REG_O_APPS_NW_SEMAPHORE10 \ 112 0x00000064 113 114 #define COMMON_REG_O_APPS_NW_SEMAPHORE11 \ 115 0x00000068 116 117 #define COMMON_REG_O_APPS_NW_SEMAPHORE12 \ 118 0x0000006C 119 120 #define COMMON_REG_O_APPS_SEMAPPHORE_PEND \ 121 0x00000070 122 123 #define COMMON_REG_O_NW_SEMAPPHORE_PEND \ 124 0x00000074 125 126 #define COMMON_REG_O_SEMAPHORE_STATUS \ 127 0x00000078 128 129 #define COMMON_REG_O_IDMEM_TIM_Update \ 130 0x0000007C 131 132 #define COMMON_REG_O_FPGA_ROM_WR_EN \ 133 0x00000080 134 135 #define COMMON_REG_O_NW_INT_MASK \ 136 0x00000084 137 138 #define COMMON_REG_O_NW_INT_MASK_SET \ 139 0x00000088 140 141 #define COMMON_REG_O_NW_INT_MASK_CLR \ 142 0x0000008C 143 144 #define COMMON_REG_O_NW_INT_STS_CLR \ 145 0x00000090 146 147 #define COMMON_REG_O_NW_INT_ACK 0x00000094 148 #define COMMON_REG_O_NW_INT_TRIG \ 149 0x00000098 150 151 #define COMMON_REG_O_NW_INT_STS_MASKED \ 152 0x0000009C 153 154 #define COMMON_REG_O_NW_INT_STS_RAW \ 155 0x000000A0 156 157 #define COMMON_REG_O_APPS_INT_MASK \ 158 0x000000A4 159 160 #define COMMON_REG_O_APPS_INT_MASK_SET \ 161 0x000000A8 162 163 #define COMMON_REG_O_APPS_INT_MASK_CLR \ 164 0x000000AC 165 166 #define COMMON_REG_O_APPS_INT_STS_CLR \ 167 0x000000B0 168 169 #define COMMON_REG_O_APPS_INT_ACK \ 170 0x000000B4 171 172 #define COMMON_REG_O_APPS_INT_TRIG \ 173 0x000000B8 174 175 #define COMMON_REG_O_APPS_INT_STS_MASKED \ 176 0x000000BC 177 178 #define COMMON_REG_O_APPS_INT_STS_RAW \ 179 0x000000C0 180 181 #define COMMON_REG_O_IDMEM_TIM_Updated \ 182 0x000000C4 183 184 #define COMMON_REG_O_APPS_GPIO_TRIG_EN \ 185 0x000000C8 186 187 #define COMMON_REG_O_EMU_DEBUG_REG \ 188 0x000000CC 189 190 #define COMMON_REG_O_SEMAPHORE_STATUS2 \ 191 0x000000D0 192 193 #define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \ 194 0x000000D4 195 196 #define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \ 197 0x000000D8 198 199 200 201 202 //****************************************************************************** 203 // 204 // The following are defines for the bit fields in the 205 // COMMON_REG_O_I2C_Properties_Register register. 206 // 207 //****************************************************************************** 208 #define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \ 209 0x00000003 // • Each semaphore register is of 210 // 2 bit. • When this register is 211 // set to 2’b01 – Apps have access 212 // and when set to 2’b10 – NW have 213 // access. • Ideally both the master 214 // can modify any of this 2 bit, but 215 // assumption apps will write only 216 // 2’b01 or 2’b00 to this register 217 // and nw will write only 2’b10 or 218 // 2’b00. • Implementation is when 219 // any of the bit of this register 220 // is set, only next write 221 // allowedvis 2’b00 – Again 222 // assumption is one master will not 223 // write 2’b00 if other is already 224 // holding the semaphore. 225 226 #define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0 227 //****************************************************************************** 228 // 229 // The following are defines for the bit fields in the 230 // COMMON_REG_O_SPI_Properties_Register register. 231 // 232 //****************************************************************************** 233 #define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \ 234 0x00000003 // • Each semaphore register is of 235 // 2 bit. • When this register is 236 // set to 2’b01 – Apps have access 237 // and when set to 2’b10 – NW have 238 // access. • Ideally both the master 239 // can modify any of this 2 bit, but 240 // assumption apps will write only 241 // 2’b01 or 2’b00 to this register 242 // and nw will write only 2’b10 or 243 // 2’b00. • Implementation is when 244 // any of the bit of this register 245 // is set, only next write 246 // allowedvis 2’b00 – Again 247 // assumption is one master will not 248 // write 2’b00 if other is already 249 // holding the semaphore. 250 251 #define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0 252 253 //****************************************************************************** 254 // 255 // The following are defines for the bit fields in the 256 // COMMON_REG_O_APPS_sh_resource_Interrupt_enable register. 257 // 258 //****************************************************************************** 259 #define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \ 260 0x0000000F // Interrupt enable APPS bit 0 -> 261 // when '1' enable I2C interrupt bit 262 // 1 -> when '1' enable SPI 263 // interrupt bit 3 -> 264 // when '1' enable GPIO interrupt 265 266 #define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0 267 //****************************************************************************** 268 // 269 // The following are defines for the bit fields in the 270 // COMMON_REG_O_APPS_sh_resource_Interrupt_status register. 271 // 272 //****************************************************************************** 273 #define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \ 274 0x0000000F // Interrupt enable APPS bit 0 -> 275 // when '1' enable I2C interrupt bit 276 // 1 -> when '1' enable SPI 277 // interrupt bit 3 -> 278 // when '1' enable GPIO interrupt 279 280 #define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0 281 //****************************************************************************** 282 // 283 // The following are defines for the bit fields in the 284 // COMMON_REG_O_NWP_sh_resource_Interrupt_enable register. 285 // 286 //****************************************************************************** 287 #define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \ 288 0x0000000F // Interrupt enable NWP bit 0 -> 289 // when '1' enable I2C interrupt bit 290 // 1 -> when '1' enable SPI 291 // interrupt bit 3 -> 292 // when '1' enable GPIO interrupt 293 294 #define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0 295 //****************************************************************************** 296 // 297 // The following are defines for the bit fields in the 298 // COMMON_REG_O_NWP_sh_resource_Interrupt_status register. 299 // 300 //****************************************************************************** 301 #define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \ 302 0x0000000F // Interrupt enable NWP bit 0 -> 303 // when '1' enable I2C interrupt bit 304 // 1 -> when '1' enable SPI 305 // interrupt bit 3 -> 306 // when '1' enable GPIO interrupt 307 308 #define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0 309 //****************************************************************************** 310 // 311 // The following are defines for the bit fields in the 312 // COMMON_REG_O_Flash_ctrl_reg register. 313 // 314 //****************************************************************************** 315 #define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \ 316 0x00000003 // • Each semaphore register is of 317 // 2 bit. • When this register is 318 // set to 2’b01 – Apps have access 319 // and when set to 2’b10 – NW have 320 // access. • Ideally both the master 321 // can modify any of this 2 bit, but 322 // assumption apps will write only 323 // 2’b01 or 2’b00 to this register 324 // and nw will write only 2’b10 or 325 // 2’b00. • Implementation is when 326 // any of the bit of this register 327 // is set, only next write 328 // allowedvis 2’b00 – Again 329 // assumption is one master will not 330 // write 2’b00 if other is already 331 // holding the semaphore. 332 333 #define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0 334 //****************************************************************************** 335 // 336 // The following are defines for the bit fields in the 337 // COMMON_REG_O_Bus_matrix_M0_segment_access_config register. 338 // 339 //****************************************************************************** 340 #define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \ 341 0x0003FFFF // Master 0 control word matrix to 342 // each segment. Tieoff. Bit value 1 343 // indicates segment is accesable. 344 345 #define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0 346 //****************************************************************************** 347 // 348 // The following are defines for the bit fields in the 349 // COMMON_REG_O_Bus_matrix_M1_segment_access_config register. 350 // 351 //****************************************************************************** 352 #define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \ 353 0x0003FFFF // Master 1 control word matrix to 354 // each segment. Tieoff. Bit value 1 355 // indicates segment is accesable. 356 357 #define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0 358 //****************************************************************************** 359 // 360 // The following are defines for the bit fields in the 361 // COMMON_REG_O_Bus_matrix_M2_segment_access_config register. 362 // 363 //****************************************************************************** 364 #define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \ 365 0x0003FFFF // Master 2 control word matrix to 366 // each segment. Tieoff. Bit value 1 367 // indicates segment is accesable. 368 369 #define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0 370 //****************************************************************************** 371 // 372 // The following are defines for the bit fields in the 373 // COMMON_REG_O_Bus_matrix_M3_segment_access_config register. 374 // 375 //****************************************************************************** 376 #define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \ 377 0x0003FFFF // Master 3 control word matrix to 378 // each segment. Tieoff. Bit value 1 379 // indicates segment is accesable. 380 381 #define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0 382 //****************************************************************************** 383 // 384 // The following are defines for the bit fields in the 385 // COMMON_REG_O_Bus_matrix_M4_segment_access_config register. 386 // 387 //****************************************************************************** 388 #define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \ 389 0x0003FFFF // Master 4 control word matrix to 390 // each segment. Tieoff. Bit value 1 391 // indicates segment is accesable. 392 393 #define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0 394 //****************************************************************************** 395 // 396 // The following are defines for the bit fields in the 397 // COMMON_REG_O_Bus_matrix_M5_segment_access_config register. 398 // 399 //****************************************************************************** 400 #define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \ 401 0x0003FFFF // Master 5 control word matrix to 402 // each segment. Tieoff. Bit value 1 403 // indicates segment is accesable. 404 405 #define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0 406 //****************************************************************************** 407 // 408 // The following are defines for the bit fields in the 409 // COMMON_REG_O_GPIO_properties_register register. 410 // 411 //****************************************************************************** 412 #define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \ 413 0x000003FF // Shared GPIO configuration 414 // register. Bit [1:0] to configure 415 // GPIO0 Bit [3:2] to configure 416 // GPIO1 Bit [5:4] to configure 417 // GPIO2 Bit [7:6] to configure 418 // GPIO3 Bit [9:8] to configure 419 // GPIO4 each GPIO can be 420 // individully selected. When “00�? 421 // GPIO is free resource. When “01�? 422 // GPIO is APPS resource. When “10�? 423 // GPIO is NWP resource. Writing 11 424 // doesnt have any affect, i.e. If 425 // one write only relevant gpio 426 // semaphore and other bits are 1s, 427 // it'll not disturb the other 428 // semaphore bits. For example : Say 429 // If NW wants to take control of 430 // gpio-1, one should write 431 // 10'b11_1111_1011 and if one wants 432 // to release it write 433 // 10'b11_1111_0011. 434 435 #define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0 436 //****************************************************************************** 437 // 438 // The following are defines for the bit fields in the 439 // COMMON_REG_O_APPS_NW_SEMAPHORE1 register. 440 // 441 //****************************************************************************** 442 #define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \ 443 0xFFFFFFFF // • Each semaphore register is of 444 // 2 bit. • When this register is 445 // set to 2’b01 – Apps have access 446 // and when set to 2’b10 – NW have 447 // access. • Ideally both the master 448 // can modify any of this 2 bit, but 449 // assumption apps will write only 450 // 2’b01 or 2’b00 to this register 451 // and nw will write only 2’b10 or 452 // 2’b00. • Implementation is when 453 // any of the bit of this register 454 // is set, only next write 455 // allowedvis 2’b00 – Again 456 // assumption is one master will not 457 // write 2’b00 if other is already 458 // holding the semaphore. 459 460 #define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0 461 //****************************************************************************** 462 // 463 // The following are defines for the bit fields in the 464 // COMMON_REG_O_APPS_NW_SEMAPHORE2 register. 465 // 466 //****************************************************************************** 467 #define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \ 468 0xFFFFFFFF // • Each semaphore register is of 469 // 2 bit. • When this register is 470 // set to 2’b01 – Apps have access 471 // and when set to 2’b10 – NW have 472 // access. • Ideally both the master 473 // can modify any of this 2 bit, but 474 // assumption apps will write only 475 // 2’b01 or 2’b00 to this register 476 // and nw will write only 2’b10 or 477 // 2’b00. • Implementation is when 478 // any of the bit of this register 479 // is set, only next write 480 // allowedvis 2’b00 – Again 481 // assumption is one master will not 482 // write 2’b00 if other is already 483 // holding the semaphore. 484 485 #define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0 486 //****************************************************************************** 487 // 488 // The following are defines for the bit fields in the 489 // COMMON_REG_O_APPS_NW_SEMAPHORE3 register. 490 // 491 //****************************************************************************** 492 #define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \ 493 0xFFFFFFFF // • Each semaphore register is of 494 // 2 bit. • When this register is 495 // set to 2’b01 – Apps have access 496 // and when set to 2’b10 – NW have 497 // access. • Ideally both the master 498 // can modify any of this 2 bit, but 499 // assumption apps will write only 500 // 2’b01 or 2’b00 to this register 501 // and nw will write only 2’b10 or 502 // 2’b00. • Implementation is when 503 // any of the bit of this register 504 // is set, only next write 505 // allowedvis 2’b00 – Again 506 // assumption is one master will not 507 // write 2’b00 if other is already 508 // holding the semaphore. 509 510 #define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0 511 //****************************************************************************** 512 // 513 // The following are defines for the bit fields in the 514 // COMMON_REG_O_APPS_NW_SEMAPHORE4 register. 515 // 516 //****************************************************************************** 517 #define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \ 518 0xFFFFFFFF // • Each semaphore register is of 519 // 2 bit. • When this register is 520 // set to 2’b01 – Apps have access 521 // and when set to 2’b10 – NW have 522 // access. • Ideally both the master 523 // can modify any of this 2 bit, but 524 // assumption apps will write only 525 // 2’b01 or 2’b00 to this register 526 // and nw will write only 2’b10 or 527 // 2’b00. • Implementation is when 528 // any of the bit of this register 529 // is set, only next write 530 // allowedvis 2’b00 – Again 531 // assumption is one master will not 532 // write 2’b00 if other is already 533 // holding the semaphore. 534 535 #define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0 536 //****************************************************************************** 537 // 538 // The following are defines for the bit fields in the 539 // COMMON_REG_O_APPS_NW_SEMAPHORE5 register. 540 // 541 //****************************************************************************** 542 #define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \ 543 0xFFFFFFFF // • Each semaphore register is of 544 // 2 bit. • When this register is 545 // set to 2’b01 – Apps have access 546 // and when set to 2’b10 – NW have 547 // access. • Ideally both the master 548 // can modify any of this 2 bit, but 549 // assumption apps will write only 550 // 2’b01 or 2’b00 to this register 551 // and nw will write only 2’b10 or 552 // 2’b00. • Implementation is when 553 // any of the bit of this register 554 // is set, only next write 555 // allowedvis 2’b00 – Again 556 // assumption is one master will not 557 // write 2’b00 if other is already 558 // holding the semaphore. 559 560 #define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0 561 //****************************************************************************** 562 // 563 // The following are defines for the bit fields in the 564 // COMMON_REG_O_APPS_NW_SEMAPHORE6 register. 565 // 566 //****************************************************************************** 567 #define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \ 568 0xFFFFFFFF // • Each semaphore register is of 569 // 2 bit. • When this register is 570 // set to 2’b01 – Apps have access 571 // and when set to 2’b10 – NW have 572 // access. • Ideally both the master 573 // can modify any of this 2 bit, but 574 // assumption apps will write only 575 // 2’b01 or 2’b00 to this register 576 // and nw will write only 2’b10 or 577 // 2’b00. • Implementation is when 578 // any of the bit of this register 579 // is set, only next write 580 // allowedvis 2’b00 – Again 581 // assumption is one master will not 582 // write 2’b00 if other is already 583 // holding the semaphore. 584 585 #define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0 586 //****************************************************************************** 587 // 588 // The following are defines for the bit fields in the 589 // COMMON_REG_O_APPS_NW_SEMAPHORE7 register. 590 // 591 //****************************************************************************** 592 #define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \ 593 0xFFFFFFFF // • Each semaphore register is of 594 // 2 bit. • When this register is 595 // set to 2’b01 – Apps have access 596 // and when set to 2’b10 – NW have 597 // access. • Ideally both the master 598 // can modify any of this 2 bit, but 599 // assumption apps will write only 600 // 2’b01 or 2’b00 to this register 601 // and nw will write only 2’b10 or 602 // 2’b00. • Implementation is when 603 // any of the bit of this register 604 // is set, only next write 605 // allowedvis 2’b00 – Again 606 // assumption is one master will not 607 // write 2’b00 if other is already 608 // holding the semaphore. 609 610 #define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0 611 //****************************************************************************** 612 // 613 // The following are defines for the bit fields in the 614 // COMMON_REG_O_APPS_NW_SEMAPHORE8 register. 615 // 616 //****************************************************************************** 617 #define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \ 618 0xFFFFFFFF // • Each semaphore register is of 619 // 2 bit. • When this register is 620 // set to 2’b01 – Apps have access 621 // and when set to 2’b10 – NW have 622 // access. • Ideally both the master 623 // can modify any of this 2 bit, but 624 // assumption apps will write only 625 // 2’b01 or 2’b00 to this register 626 // and nw will write only 2’b10 or 627 // 2’b00. • Implementation is when 628 // any of the bit of this register 629 // is set, only next write 630 // allowedvis 2’b00 – Again 631 // assumption is one master will not 632 // write 2’b00 if other is already 633 // holding the semaphore. 634 635 #define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0 636 //****************************************************************************** 637 // 638 // The following are defines for the bit fields in the 639 // COMMON_REG_O_APPS_NW_SEMAPHORE9 register. 640 // 641 //****************************************************************************** 642 #define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \ 643 0xFFFFFFFF // • Each semaphore register is of 644 // 2 bit. • When this register is 645 // set to 2’b01 – Apps have access 646 // and when set to 2’b10 – NW have 647 // access. • Ideally both the master 648 // can modify any of this 2 bit, but 649 // assumption apps will write only 650 // 2’b01 or 2’b00 to this register 651 // and nw will write only 2’b10 or 652 // 2’b00. • Implementation is when 653 // any of the bit of this register 654 // is set, only next write 655 // allowedvis 2’b00 – Again 656 // assumption is one master will not 657 // write 2’b00 if other is already 658 // holding the semaphore. 659 660 #define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0 661 //****************************************************************************** 662 // 663 // The following are defines for the bit fields in the 664 // COMMON_REG_O_APPS_NW_SEMAPHORE10 register. 665 // 666 //****************************************************************************** 667 #define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \ 668 0xFFFFFFFF // • Each semaphore register is of 669 // 2 bit. • When this register is 670 // set to 2’b01 – Apps have access 671 // and when set to 2’b10 – NW have 672 // access. • Ideally both the master 673 // can modify any of this 2 bit, but 674 // assumption apps will write only 675 // 2’b01 or 2’b00 to this register 676 // and nw will write only 2’b10 or 677 // 2’b00. • Implementation is when 678 // any of the bit of this register 679 // is set, only next write 680 // allowedvis 2’b00 – Again 681 // assumption is one master will not 682 // write 2’b00 if other is already 683 // holding the semaphore. 684 685 #define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0 686 //****************************************************************************** 687 // 688 // The following are defines for the bit fields in the 689 // COMMON_REG_O_APPS_NW_SEMAPHORE11 register. 690 // 691 //****************************************************************************** 692 #define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \ 693 0xFFFFFFFF // • Each semaphore register is of 694 // 2 bit. • When this register is 695 // set to 2’b01 – Apps have access 696 // and when set to 2’b10 – NW have 697 // access. • Ideally both the master 698 // can modify any of this 2 bit, but 699 // assumption apps will write only 700 // 2’b01 or 2’b00 to this register 701 // and nw will write only 2’b10 or 702 // 2’b00. • Implementation is when 703 // any of the bit of this register 704 // is set, only next write 705 // allowedvis 2’b00 – Again 706 // assumption is one master will not 707 // write 2’b00 if other is already 708 // holding the semaphore. 709 710 #define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0 711 //****************************************************************************** 712 // 713 // The following are defines for the bit fields in the 714 // COMMON_REG_O_APPS_NW_SEMAPHORE12 register. 715 // 716 //****************************************************************************** 717 #define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \ 718 0xFFFFFFFF // APPS NW semaphore register - not 719 // reflected in status. 720 721 #define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0 722 //****************************************************************************** 723 // 724 // The following are defines for the bit fields in the 725 // COMMON_REG_O_APPS_SEMAPPHORE_PEND register. 726 // 727 //****************************************************************************** 728 #define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \ 729 0xFFFFFFFF // APPS SEMAPOHORE STATUS 730 731 #define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0 732 //****************************************************************************** 733 // 734 // The following are defines for the bit fields in the 735 // COMMON_REG_O_NW_SEMAPPHORE_PEND register. 736 // 737 //****************************************************************************** 738 #define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \ 739 0xFFFFFFFF // NW SEMAPHORE STATUS 740 741 #define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0 742 //****************************************************************************** 743 // 744 // The following are defines for the bit fields in the 745 // COMMON_REG_O_SEMAPHORE_STATUS register. 746 // 747 //****************************************************************************** 748 #define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \ 749 0xFFFFFFFF // SEMAPHORE STATUS 9:8 :semaphore 750 // status of flash_control 7:6 751 // :semaphore status of 752 // gpio_properties 5:4 753 // :semaphore status of 754 // spi_propertie 1:0 :semaphore 755 // status of i2c_propertie 756 757 #define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0 758 //****************************************************************************** 759 // 760 // The following are defines for the bit fields in the 761 // COMMON_REG_O_IDMEM_TIM_Update register. 762 // 763 //****************************************************************************** 764 //****************************************************************************** 765 // 766 // The following are defines for the bit fields in the 767 // COMMON_REG_O_FPGA_ROM_WR_EN register. 768 // 769 //****************************************************************************** 770 #define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \ 771 0x00000001 // when '1' enables Write into 772 // IDMEM CORE ROM, APPS ROM, NWP ROM 773 774 //****************************************************************************** 775 // 776 // The following are defines for the bit fields in the 777 // COMMON_REG_O_NW_INT_MASK register. 778 // 779 //****************************************************************************** 780 #define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \ 781 0xFFFFFFFF // 1= disable corresponding 782 // interrupt;0 = interrupt enabled 783 784 #define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0 785 //****************************************************************************** 786 // 787 // The following are defines for the bit fields in the 788 // COMMON_REG_O_NW_INT_MASK_SET register. 789 // 790 //****************************************************************************** 791 #define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \ 792 0xFFFFFFFF // write 1 to set corresponding bit 793 // in NW_INT_MASK;0 = no effect 794 795 #define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0 796 //****************************************************************************** 797 // 798 // The following are defines for the bit fields in the 799 // COMMON_REG_O_NW_INT_MASK_CLR register. 800 // 801 //****************************************************************************** 802 #define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \ 803 0xFFFFFFFF // write 1 to clear corresponding 804 // bit in NW_INT_MASK;0 = no effect 805 806 #define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0 807 //****************************************************************************** 808 // 809 // The following are defines for the bit fields in the 810 // COMMON_REG_O_NW_INT_STS_CLR register. 811 // 812 //****************************************************************************** 813 #define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \ 814 0xFFFFFFFF // write 1 to clear corresponding 815 // interrupt; 0 = no effect; 816 // interrupt is not lost if coincide 817 // with write operation 818 819 #define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0 820 //****************************************************************************** 821 // 822 // The following are defines for the bit fields in the 823 // COMMON_REG_O_NW_INT_ACK register. 824 // 825 //****************************************************************************** 826 #define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \ 827 0xFFFFFFFF // write 1 to clear corresponding 828 // interrupt;0 = no effect 829 830 #define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0 831 //****************************************************************************** 832 // 833 // The following are defines for the bit fields in the 834 // COMMON_REG_O_NW_INT_TRIG register. 835 // 836 //****************************************************************************** 837 #define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \ 838 0xFFFFFFFF // Writing a 1 to a bit in this 839 // register causes the the Host CPU 840 // if enabled (not masked). This 841 // register is self-clearing. 842 // Writing 0 has no effect 843 844 #define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0 845 //****************************************************************************** 846 // 847 // The following are defines for the bit fields in the 848 // COMMON_REG_O_NW_INT_STS_MASKED register. 849 // 850 //****************************************************************************** 851 #define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \ 852 0xFFFFFFFF // 1= corresponding interrupt is 853 // active and not masked. read is 854 // non-destructive;0 = corresponding 855 // interrupt is inactive or masked 856 // by NW_INT mask 857 858 #define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0 859 //****************************************************************************** 860 // 861 // The following are defines for the bit fields in the 862 // COMMON_REG_O_NW_INT_STS_RAW register. 863 // 864 //****************************************************************************** 865 #define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \ 866 0xFFFFFFFF // 1= corresponding interrupt is 867 // active. read is non-destructive;0 868 // = corresponding interrupt is 869 // inactive 870 871 #define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0 872 //****************************************************************************** 873 // 874 // The following are defines for the bit fields in the 875 // COMMON_REG_O_APPS_INT_MASK register. 876 // 877 //****************************************************************************** 878 #define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \ 879 0xFFFFFFFF // 1= disable corresponding 880 // interrupt;0 = interrupt enabled 881 882 #define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0 883 //****************************************************************************** 884 // 885 // The following are defines for the bit fields in the 886 // COMMON_REG_O_APPS_INT_MASK_SET register. 887 // 888 //****************************************************************************** 889 #define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \ 890 0xFFFFFFFF // write 1 to set corresponding bit 891 // in APPS_INT_MASK;0 = no effect 892 893 #define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0 894 //****************************************************************************** 895 // 896 // The following are defines for the bit fields in the 897 // COMMON_REG_O_APPS_INT_MASK_CLR register. 898 // 899 //****************************************************************************** 900 #define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \ 901 0xFFFFFFFF // write 1 to clear corresponding 902 // bit in APPS_INT_MASK;0 = no 903 // effect 904 905 #define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0 906 //****************************************************************************** 907 // 908 // The following are defines for the bit fields in the 909 // COMMON_REG_O_APPS_INT_STS_CLR register. 910 // 911 //****************************************************************************** 912 #define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \ 913 0xFFFFFFFF // write 1 to clear corresponding 914 // interrupt; 0 = no effect; 915 // interrupt is not lost if coincide 916 // with write operation 917 918 #define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0 919 //****************************************************************************** 920 // 921 // The following are defines for the bit fields in the 922 // COMMON_REG_O_APPS_INT_ACK register. 923 // 924 //****************************************************************************** 925 #define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \ 926 0xFFFFFFFF // write 1 to clear corresponding 927 // interrupt;0 = no effect 928 929 #define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0 930 //****************************************************************************** 931 // 932 // The following are defines for the bit fields in the 933 // COMMON_REG_O_APPS_INT_TRIG register. 934 // 935 //****************************************************************************** 936 #define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \ 937 0xFFFFFFFF // Writing a 1 to a bit in this 938 // register causes the the Host CPU 939 // if enabled (not masked). This 940 // register is self-clearing. 941 // Writing 0 has no effect 942 943 #define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0 944 //****************************************************************************** 945 // 946 // The following are defines for the bit fields in the 947 // COMMON_REG_O_APPS_INT_STS_MASKED register. 948 // 949 //****************************************************************************** 950 #define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \ 951 0xFFFFFFFF // 1= corresponding interrupt is 952 // active and not masked. read is 953 // non-destructive;0 = corresponding 954 // interrupt is inactive or masked 955 // by APPS_INT mask 956 957 #define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0 958 //****************************************************************************** 959 // 960 // The following are defines for the bit fields in the 961 // COMMON_REG_O_APPS_INT_STS_RAW register. 962 // 963 //****************************************************************************** 964 #define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \ 965 0xFFFFFFFF // 1= corresponding interrupt is 966 // active. read is non-destructive;0 967 // = corresponding interrupt is 968 // inactive 969 970 #define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0 971 //****************************************************************************** 972 // 973 // The following are defines for the bit fields in the 974 // COMMON_REG_O_IDMEM_TIM_Updated register. 975 // 976 //****************************************************************************** 977 #define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \ 978 0x00000001 // toggle in this signal 979 // indicatesIDMEM_TIM_UPDATE 980 // register mentioned above is 981 // updated. 982 983 //****************************************************************************** 984 // 985 // The following are defines for the bit fields in the 986 // COMMON_REG_O_APPS_GPIO_TRIG_EN register. 987 // 988 //****************************************************************************** 989 #define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \ 990 0x0000001F // APPS GPIO Trigger EN control. 991 // Bit 0: when '1' enable GPIO 0 992 // trigger. This bit enables trigger 993 // for all GPIO 0 pins (GPIO 0 to 994 // GPIO7). Bit 1: when '1' enable 995 // GPIO 1 trigger. This bit enables 996 // trigger for all GPIO 1 pins ( 997 // GPIO8 to GPIO15). Bit 2: when '1' 998 // enable GPIO 2 trigger. This bit 999 // enables trigger for all GPIO 2 1000 // pins (GPIO16 to GPIO23). Bit 3: 1001 // when '1' enable GPIO 3 trigger. 1002 // This bit enables trigger for all 1003 // GPIO 3 pins (GPIO24 to GPIO31). 1004 // Bit 4: when '1' enable GPIO 4 1005 // trigger. This bit enables trigger 1006 // for all GPIO 4 pins.(GPIO32 to 1007 // GPIO39) 1008 1009 #define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0 1010 //****************************************************************************** 1011 // 1012 // The following are defines for the bit fields in the 1013 // COMMON_REG_O_EMU_DEBUG_REG register. 1014 // 1015 //****************************************************************************** 1016 #define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \ 1017 0xFFFFFFFF // 0 th bit used for stalling APPS 1018 // DMA and 1st bit is used for 1019 // stalling NWP DMA for debug 1020 // purpose. Other bits are unused. 1021 1022 #define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0 1023 //****************************************************************************** 1024 // 1025 // The following are defines for the bit fields in the 1026 // COMMON_REG_O_SEMAPHORE_STATUS2 register. 1027 // 1028 //****************************************************************************** 1029 #define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \ 1030 0x00FFFFFF // SEMAPHORE STATUS 23:22 1031 // :semaphore status of 1032 // apps_nw_semaphore11 21:20 1033 // :semaphore status of 1034 // apps_nw_semaphore11 19:18 1035 // :semaphore status of 1036 // apps_nw_semaphore10 17:16 1037 // :semaphore status of 1038 // apps_nw_semaphore9 15:14 1039 // :semaphore status of 1040 // apps_nw_semaphore8 13:12 1041 // :semaphore status of 1042 // apps_nw_semaphore7 11:10 1043 // :semaphore status of 1044 // apps_nw_semaphore6 9:8 :semaphore 1045 // status of apps_nw_semaphore5 7:6 1046 // :semaphore status of 1047 // apps_nw_semaphore4 5:4 :semaphore 1048 // status of apps_nw_semaphore3 3:2 1049 // :semaphore status of 1050 // apps_nw_semaphore2 1:0 :semaphore 1051 // status of apps_nw_semaphore1 1052 1053 #define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0 1054 //****************************************************************************** 1055 // 1056 // The following are defines for the bit fields in the 1057 // COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register. 1058 // 1059 //****************************************************************************** 1060 #define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \ 1061 0x0003FFFF // 1:0 : prvious owner of 1062 // i2c_properties_reg[1:0] 3:2 : 1063 // prvious owner of 1064 // spi_properties_reg[1:0] 5:4 : 1065 // prvious owner of 1066 // gpio_properties_reg[1:0] 9:8 : 1067 // prvious owner of 1068 // gpio_properties_reg[3:2] 11:10 : 1069 // prvious owner of 1070 // gpio_properties_reg[5:4] 13:12 : 1071 // prvious owner of 1072 // gpio_properties_reg[7:6] 15:14 : 1073 // prvious owner of 1074 // gpio_properties_reg[9:8] 17:16 : 1075 // prvious owner of 1076 // flash_control_reg[1:0] 1077 1078 #define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0 1079 //****************************************************************************** 1080 // 1081 // The following are defines for the bit fields in the 1082 // COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register. 1083 // 1084 //****************************************************************************** 1085 #define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \ 1086 0x00FFFFFF // 1:0 : previous owner of 1087 // apps_nw_semaphore1_reg[1:0] 3:2 : 1088 // previous owner of 1089 // apps_nw_semaphore2_reg[1:0] 5:4 : 1090 // previous owner of 1091 // apps_nw_semaphore3_reg[1:0] 7:6 : 1092 // previous owner of 1093 // apps_nw_semaphore4_reg[1:0] 9:8 : 1094 // previous owner of 1095 // apps_nw_semaphore5_reg[1:0] 11:10 1096 // : previous owner of 1097 // apps_nw_semaphore6_reg[1:0] 13:12 1098 // : previous owner of 1099 // apps_nw_semaphore7_reg[1:0] 15:14 1100 // : previous owner of 1101 // apps_nw_semaphore8_reg[1:0] 17:16 1102 // : previous owner of 1103 // apps_nw_semaphore9_reg[1:0] 19:18 1104 // : previous owner of 1105 // apps_nw_semaphore10_reg[1:0] 1106 // 21:20 : previous owner of 1107 // apps_nw_semaphore11_reg[1:0] 1108 // 23:22 : previous owner of 1109 // apps_nw_semaphore12_reg[1:0] 1110 1111 #define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0 1112 1113 1114 1115 #endif // __HW_COMMON_REG_H__ 1116
