1 /*
2  * Copyright (c) 2019 Arm Limited. All rights reserved.
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *     http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef __ARM_LTD_AN524_REGS_H__
18 #define __ARM_LTD_AN524_REGS_H__
19 
20 #include <stdint.h>
21 
22 /* System info memory mapped register access structure */
23 struct sysinfo_t {
24     volatile uint32_t sys_version;      /* (R/ ) System version */
25     volatile uint32_t sys_config;       /* (R/ ) System configuration */
26     volatile uint32_t reserved0[1008];
27     volatile uint32_t pidr4;            /* (R/ ) Peripheral ID 4 */
28     volatile uint32_t reserved1[3];
29     volatile uint32_t pidr0;            /* (R/ ) Peripheral ID 0 */
30     volatile uint32_t pidr1;            /* (R/ ) Peripheral ID 1 */
31     volatile uint32_t pidr2;            /* (R/ ) Peripheral ID 2 */
32     volatile uint32_t pidr3;            /* (R/ ) Peripheral ID 3 */
33     volatile uint32_t cidr0;            /* (R/ ) Component ID 0 */
34     volatile uint32_t cidr1;            /* (R/ ) Component ID 1 */
35     volatile uint32_t cidr2;            /* (R/ ) Component ID 2 */
36     volatile uint32_t cidr3;            /* (R/ ) Component ID 3 */
37 };
38 
39 /* System control memory mapped register access structure */
40 struct sysctrl_t {
41     volatile uint32_t secdbgstat;     /* (R/ ) Secure Debug Configuration
42                                        *       Status Register
43                                        */
44     volatile uint32_t secdbgset;      /* ( /W) Secure Debug Configuration
45                                        *       Set Register
46                                        */
47     volatile uint32_t secdbgclr;      /* ( /W) Secure Debug Configuration
48                                        *       Clear Register
49                                        */
50     volatile uint32_t scsecctrl;      /* (R/W) System Control Security
51                                        *       Control Register
52                                        */
53     volatile uint32_t fclk_div;       /* (R/W) Fast Clock Divider
54                                        *       Configuration Register
55                                        */
56     volatile uint32_t sysclk_div;     /* (R/W) System Clock Divider
57                                        *       Configuration Register
58                                        */
59     volatile uint32_t clockforce;     /* (R/W) Clock Forces */
60     volatile uint32_t reserved0[57];
61     volatile uint32_t resetsyndrome;  /* (R/W) Reset syndrome */
62     volatile uint32_t resetmask;      /* (R/W) Reset MASK */
63     volatile uint32_t swreset;        /* ( /W) Software Reset */
64     volatile uint32_t gretreg;        /* (R/W) General Purpose Retention
65                                        *       Register
66                                        */
67     volatile uint32_t initsvtor0;     /* (R/W) Initial Secure Reset Vector
68                                        *       Register For CPU 0
69                                        */
70     volatile uint32_t initsvtor1;     /* (R/W) Initial Secure Reset
71                                        *       Vector Register For CPU 1
72                                        */
73     volatile uint32_t cpuwait;        /* (R/W) CPU Boot wait control
74                                        *       after reset
75                                        */
76     volatile uint32_t nmi_enable;     /* (R/W) NMI Enable Register */
77     volatile uint32_t wicctrl;        /* (R/W) CPU WIC Request and
78                                        *       Acknowledgment
79                                        */
80     volatile uint32_t ewctrl;         /* (R/W) External Wakeup Control */
81     volatile uint32_t reserved1[54];
82     volatile uint32_t pdcm_pd_sys_sense;      /* (R/W) Power Control Dependency
83                                                * Matrix PD_SYS
84                                                * Power Domain Sensitivity.
85                                                */
86     volatile uint32_t reserved2[2];           /* Reserved */
87     volatile uint32_t pdcm_pd_sram0_sense;    /* (R/W) Power Control Dependency
88                                                * Matrix PD_SRAM0 Power
89                                                * Domain Sensitivity.
90                                                */
91     volatile uint32_t pdcm_pd_sram1_sense;    /* (R/W) Power Control Dependency
92                                                * Matrix PD_SRAM1 Power
93                                                * Domain Sensitivity.
94                                                */
95     volatile uint32_t pdcm_pd_sram2_sense;    /* (R/W) Power Control Dependency
96                                                * Matrix PD_SRAM2 Power
97                                                * Domain Sensitivity.
98                                                */
99     volatile uint32_t pdcm_pd_sram3_sense;    /* (R/W) Power Control Dependency
100                                                * Matrix PD_SRAM3 Power
101                                                * Domain Sensitivity.
102                                                */
103     volatile uint32_t reserved3[877];         /* Reserved */
104     volatile uint32_t pidr4;                  /* (R/ ) Peripheral ID 4 */
105     volatile uint32_t reserved4[3];
106     volatile uint32_t pidr0;                  /* (R/ ) Peripheral ID 0 */
107     volatile uint32_t pidr1;                  /* (R/ ) Peripheral ID 1 */
108     volatile uint32_t pidr2;                  /* (R/ ) Peripheral ID 2 */
109     volatile uint32_t pidr3;                  /* (R/ ) Peripheral ID 3 */
110     volatile uint32_t cidr0;                  /* (R/ ) Component ID 0 */
111     volatile uint32_t cidr1;                  /* (R/ ) Component ID 1 */
112     volatile uint32_t cidr2;                  /* (R/ ) Component ID 2 */
113     volatile uint32_t cidr3;                  /* (R/ ) Component ID 3 */
114 };
115 
116 /* Secure Privilege Control */
117 #define CMSDK_SPCTRL  ((struct spctrl_def *)CMSDK_SPCTRL_BASE_S)
118 
119 /* SPCTRL memory mapped register access structure */
120 struct spctrl_def {
121     volatile uint32_t spcsecctrl;
122     volatile uint32_t buswait;
123     volatile uint32_t reserved[2];
124     volatile uint32_t secrespcfg;
125     volatile uint32_t nsccfg;
126     volatile uint32_t reserved2;
127     volatile uint32_t secmpcintstat;
128     volatile uint32_t secppcintstat;
129     volatile uint32_t secppcintclr;
130     volatile uint32_t secppcinten;
131     volatile uint32_t reserved3;
132     volatile uint32_t secmscintstat;
133     volatile uint32_t secmscintclr;
134     volatile uint32_t secmscinten;
135     volatile uint32_t reserved4;
136     volatile uint32_t brgintstat;
137     volatile uint32_t brgintclr;
138     volatile uint32_t brginten;
139     volatile uint32_t reserved5;
140     volatile uint32_t ahbnsppc0;
141     volatile uint32_t reserved6[3];
142     volatile uint32_t ahbnsppcexp0;
143     volatile uint32_t ahbnsppcexp1;
144     volatile uint32_t ahbnsppcexp2;
145     volatile uint32_t ahbnsppcexp3;
146     volatile uint32_t apbnsppc0;
147     volatile uint32_t apbnsppc1;
148     volatile uint32_t reserved7[2];
149     volatile uint32_t apbnsppcexp0;
150     volatile uint32_t apbnsppcexp1;
151     volatile uint32_t apbnsppcexp2;
152     volatile uint32_t apbnsppcexp3;
153     volatile uint32_t ahbspppc0;
154     volatile uint32_t reserved8[3];
155     volatile uint32_t ahbspppcexp0;
156     volatile uint32_t ahbspppcexp1;
157     volatile uint32_t ahbspppcexp2;
158     volatile uint32_t ahbspppcexp3;
159     volatile uint32_t apbspppc0;
160     volatile uint32_t apbspppc1;
161     volatile uint32_t reserved9[2];
162     volatile uint32_t apbspppcexp0;
163     volatile uint32_t apbspppcexp1;
164     volatile uint32_t apbspppcexp2;
165     volatile uint32_t apbspppcexp3;
166     volatile uint32_t nsmscexp;
167     volatile uint32_t reserved10[959];
168     volatile uint32_t pid4;
169     volatile uint32_t pid5;
170     volatile uint32_t pid6;
171     volatile uint32_t pid7;
172     volatile uint32_t pid0;
173     volatile uint32_t pid1;
174     volatile uint32_t pid2;
175     volatile uint32_t pid3;
176     volatile uint32_t cid0;
177     volatile uint32_t cid1;
178     volatile uint32_t cid2;
179     volatile uint32_t cid3;
180 };
181 
182 /* Throw out bus error when an access causes security violation */
183 #define CMSDK_SECRESPCFG_BUS_ERR_MASK   (1UL << 0)
184 
185 /* PPC interrupt position mask */
186 #define CMSDK_APB_PPC0_INT_POS_MASK     (1UL << 0)
187 #define CMSDK_APB_PPC1_INT_POS_MASK     (1UL << 1)
188 #define CMSDK_APB_PPCEXP0_INT_POS_MASK  (1UL << 4)
189 #define CMSDK_APB_PPCEXP1_INT_POS_MASK  (1UL << 5)
190 #define CMSDK_APB_PPCEXP2_INT_POS_MASK  (1UL << 6)
191 #define CMSDK_APB_PPCEXP3_INT_POS_MASK  (1UL << 7)
192 #define CMSDK_AHB_PPCEXP0_INT_POS_MASK  (1UL << 20)
193 #define CMSDK_AHB_PPCEXP1_INT_POS_MASK  (1UL << 21)
194 #define CMSDK_AHB_PPCEXP2_INT_POS_MASK  (1UL << 22)
195 #define CMSDK_AHB_PPCEXP3_INT_POS_MASK  (1UL << 23)
196 
197 /* Non-Secure Privilege Control */
198 #define CMSDK_NSPCTRL  ((struct nspctrl_def *)CMSDK_NSPCTRL_BASE_NS)
199 
200 /* NSPCTRL memory mapped register access structure */
201 struct nspctrl_def {
202     volatile uint32_t reserved[36];
203     volatile uint32_t ahbnspppc0;
204     volatile uint32_t reserved3[3];
205     volatile uint32_t ahbnspppcexp0;
206     volatile uint32_t ahbnspppcexp1;
207     volatile uint32_t ahbnspppcexp2;
208     volatile uint32_t ahbnspppcexp3;
209     volatile uint32_t apbnspppc0;
210     volatile uint32_t apbnspppc1;
211     volatile uint32_t reserved4[2];
212     volatile uint32_t apbnspppcexp0;
213     volatile uint32_t apbnspppcexp1;
214     volatile uint32_t apbnspppcexp2;
215     volatile uint32_t apbnspppcexp3;
216     volatile uint32_t reserved5[960];
217     volatile uint32_t pidr4;
218     volatile uint32_t reserved7; /* pidr5 */
219     volatile uint32_t reserved8; /* pidr6 */
220     volatile uint32_t reserved9; /* pidr7 */
221     volatile uint32_t pidr0;
222     volatile uint32_t pidr1;
223     volatile uint32_t pidr2;
224     volatile uint32_t pidr3;
225     volatile uint32_t cidr0;
226     volatile uint32_t cidr1;
227     volatile uint32_t cidr2;
228     volatile uint32_t cidr3;
229 };
230 
231 /* ARM APB PPC0 peripherals definition */
232 #define CMSDK_TIMER0_APB_PPC_POS      0U
233 #define CMSDK_TIMER1_APB_PPC_POS      1U
234 #define CMSDK_DTIMER_APB_PPC_POS      2U
235 #define CMSDK_MHU0_APB_PPC_POS        3U
236 #define CMSDK_MHU1_APB_PPC_POS        4U
237 /* The bits 31:5 are reserved */
238 /* End ARM APB PPC0 peripherals definition */
239 
240 /* ARM APB PPC1 peripherals definition */
241 #define CMSDK_S32K_TIMER_PPC_POS      0U
242 /* The bits 31:1 are reserved */
243 /* End ARM APB PPC1 peripherals definition */
244 
245 /* ARM APB PPCEXP0 peripherals definition */
246 #define CMSDK_BRAM_MPC_APB_PPC_POS    0U
247 #define CMSDK_QSPI_MPC_APB_PPC_POS    1U
248 #define CMSDK_DDR4_MPC_APB_PPC_POS    2U
249 /* The bits 31:3 are reserved */
250 /* End ARM APB PPCEXP0 peripherals definition */
251 
252 /* ARM APB PPCEXP1 peripherals definition */
253 #define CMSDK_I2C0_APB_PPC_POS        0U
254 #define CMSDK_I2C1_APB_PPC_POS        1U
255 #define CMSDK_SPI0_APB_PPC_POS        2U
256 #define CMSDK_SPI1_APB_PPC_POS        3U
257 #define CMSDK_SPI2_APB_PPC_POS        4U
258 #define CMSDK_I2C2_APB_PPC_POS        5U
259 #define CMSDK_I2C3_APB_PPC_POS        6U
260 #define CMSDK_I2C4_APB_PPC_POS        8U
261 /* The bits 7 and 31:9 are reserved */
262 /* End ARM APB PPCEXP1 peripherals definition */
263 
264 /* ARM APB PPCEXP2 peripherals definition */
265 #define CMSDK_FPGA_SCC_PPC_POS        0U
266 #define CMSDK_FPGA_AUDIO_PPC_POS      1U
267 #define CMSDK_FPGA_IO_PPC_POS         2U
268 #define CMSDK_UART0_APB_PPC_POS       3U
269 #define CMSDK_UART1_APB_PPC_POS       4U
270 #define CMSDK_UART2_APB_PPC_POS       5U
271 #define CMSDK_UART3_APB_PPC_POS       6U
272 #define CMSDK_UART4_APB_PPC_POS       7U
273 #define CMSDK_UART5_APB_PPC_POS       8U
274 #define CMSDK_CLCD_APB_PPC_POS        10U
275 #define CMSDK_RTC_APB_PPC_POS         11U
276 /* The bits 9 and 31:12 are reserved */
277 /* End ARM APB PPCEXP2 peripherals definition */
278 
279 /* ARM APB PPCEXP3 peripherals definition */
280 /* The bits 31:0 are reserved */
281 /* End ARM APB PPCEXP3 peripherals definition */
282 
283 /* ARM AHB PPC0 peripherals definition */
284 /* The bits 31:0 are reserved */
285 /* End of ARM AHB PPC0 peripherals definition */
286 
287 /* ARM AHB PPCEXP0 peripherals definition */
288 #define CMSDK_GPIO0_PPC_POS           0U
289 #define CMSDK_GPIO1_PPC_POS           1U
290 #define CMSDK_GPIO2_PPC_POS           2U
291 #define CMSDK_GPIO3_PPC_POS           3U
292 #define CMSDK_USB_ETHERNET_PPC_POS    4U
293 #define CMSDK_USER0_PPC_POS           5U
294 #define CMSDK_USER1_PPC_POS           6U
295 #define CMSDK_USER2_PPC_POS           7U
296 /* The bits 31:8 are reserved */
297 /* End of ARM AHB PPCEXP0 peripherals definition */
298 
299 /* ARM AHB PPCEXP1 peripherals definition */
300 /* The bits 31:0 are reserved */
301 /* End of ARM AHB PPCEXP1 peripherals definition */
302 
303 /* ARM AHB PPCEXP2 peripherals definition */
304 /* The bits 31:0 are reserved */
305 /* End of ARM AHB PPCEXP2 peripherals definition */
306 
307 /* ARM AHB PPCEXP3 peripherals definition */
308 /* The bits 31:0 are reserved */
309 /* End of ARM AHB PPCEXP3 peripherals definition */
310 
311 #endif /* __ARM_LTD_AN524_REGS_H__ */
312