1 /*! 2 \file gd32f3x0_cmp.h 3 \brief definitions for the CMP 4 5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0 6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0 7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F3X0_CMP_H 38 #define GD32F3X0_CMP_H 39 40 #include "gd32f3x0.h" 41 42 /* CMP definitions */ 43 #define CMP CMP_BASE /*!< CMP base address */ 44 45 /* registers definitions */ 46 #define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */ 47 48 /* CMP_CS bits definitions */ 49 #define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */ 50 #define CMP_CS_CMP0SW BIT(1) /*!< CMP0 switch */ 51 #define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */ 52 #define CMP_CS_CMP0MSEL BITS(4,6) /*!< COMP0_M input selection */ 53 #define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */ 54 #define CMP_CS_CMP0PL BIT(11) /*!< polarity of CMP0 output */ 55 #define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */ 56 #define CMP_CS_CMP0O BIT(14) /*!< CMP0 output */ 57 #define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */ 58 #define CMP_CS_CMP1EN BIT(16) /*!< CMP1 enable */ 59 #define CMP_CS_CMP1M BITS(18,19) /*!< CMP1 mode */ 60 #define CMP_CS_CMP1MSEL BITS(20,22) /*!< CMP1_M input selection */ 61 #define CMP_CS_WNDEN BIT(23) /*!< window mode enable */ 62 #define CMP_CS_CMP1OSEL BITS(24,26) /*!< CMP1 output selection */ 63 #define CMP_CS_CMP1PL BIT(27) /*!< polarity of CMP1 output */ 64 #define CMP_CS_CMP1HST BITS(28,29) /*!< CMP1 hysteresis */ 65 #define CMP_CS_CMP1O BIT(30) /*!< CMP1 output */ 66 #define CMP_CS_CMP1LK BIT(31) /*!< CMP1 lock */ 67 68 /* consts definitions */ 69 /* operating mode */ 70 typedef enum 71 { 72 CMP_HIGHSPEED = 0, /*!< high speed mode */ 73 CMP_MIDDLESPEED, /*!< medium speed mode */ 74 CMP_LOWSPEED, /*!< low speed mode */ 75 CMP_VERYLOWSPEED /*!< very-low speed mode */ 76 }operating_mode_enum; 77 78 /* inverting input */ 79 typedef enum 80 { 81 CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */ 82 CMP_1_2VREFINT, /*!< VREFINT /2 input */ 83 CMP_3_4VREFINT, /*!< VREFINT *3/4 input */ 84 CMP_VREFINT, /*!< VREFINT input */ 85 CMP_DAC, /*!< PA4 (DAC) input */ 86 CMP_PA5, /*!< PA5 input */ 87 CMP_PA_0_2 /*!< PA0 or PA2 input */ 88 }inverting_input_enum; 89 90 /* hysteresis */ 91 typedef enum 92 { 93 CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */ 94 CMP_HYSTERESIS_LOW, /*!< output low hysteresis */ 95 CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */ 96 CMP_HYSTERESIS_HIGH /*!< output high hysteresis */ 97 }cmp_hysteresis_enum; 98 99 /* output */ 100 typedef enum 101 { 102 CMP_OUTPUT_NONE = 0, /*!< output no selection */ 103 CMP_OUTPUT_TIMER0BKIN, /*!< TIMER 0 break input */ 104 CMP_OUTPUT_TIMER0IC0, /*!< TIMER 0 channel0 input capture */ 105 CMP_OUTPUT_TIMER0OCPRECLR, /*!< TIMER 0 OCPRE_CLR input */ 106 CMP_OUTPUT_TIMER1IC3, /*!< TIMER 1 channel3 input capture */ 107 CMP_OUTPUT_TIMER1OCPRECLR, /*!< TIMER 1 OCPRE_CLR input */ 108 CMP_OUTPUT_TIMER2IC0, /*!< TIMER 2 channel0 input capture */ 109 CMP_OUTPUT_TIMER2OCPRECLR /*!< TIMER 2 OCPRE_CLR input */ 110 }cmp_output_enum; 111 112 /* CMP0 mode */ 113 #define CS_CMP0M(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 114 #define CS_CMP0M_HIGHSPEED CS_CMP0M(0) /*!< CMP0 mode high speed */ 115 #define CS_CMP0M_MIDDLESPEED CS_CMP0M(1) /*!< CMP0 mode middle speed */ 116 #define CS_CMP0M_LOWSPEED CS_CMP0M(2) /*!< CMP0 mode low speed */ 117 #define CS_CMP0M_VERYLOWSPEED CS_CMP0M(3) /*!< CMP0 mode very low speed */ 118 119 /* comparator 0 inverting input */ 120 #define CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) 121 #define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0) /*!< CMP0 inverting input 1/4 Vrefint */ 122 #define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1) /*!< CMP0 inverting input 1/2 Vrefint */ 123 #define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2) /*!< CMP0 inverting input 3/4 Vrefint */ 124 #define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3) /*!< CMP0 inverting input Vrefint */ 125 #define CS_CMP0MSEL_DAC CS_CMP0MSEL(4) /*!< CMP0 inverting input DAC*/ 126 #define CS_CMP0MSEL_PA5 CS_CMP0MSEL(5) /*!< CMP0 inverting input PA5*/ 127 #define CS_CMP0MSEL_PA0 CS_CMP0MSEL(6) /*!< CMP0 inverting input PA0*/ 128 129 /* CMP0 output */ 130 #define CS_CMP0OSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) 131 #define CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0) /*!< CMP0 output none */ 132 #define CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1) /*!< CMP0 output TIMER 0 break input */ 133 #define CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2) /*!< CMP0 output TIMER 0 channel 0 input capture */ 134 #define CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3) /*!< CMP0 output TIMER 0 ocpreclear input */ 135 #define CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4) /*!< CMP0 output TIMER 1 channel 3 input capture */ 136 #define CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5) /*!< CMP0 output TIMER 1 ocpreclear input */ 137 #define CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6) /*!< CMP0 output TIMER 2 channle 0 input capture */ 138 #define CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7) /*!< CMP0 output TIMER 2 ocpreclear input */ 139 140 /* CMP0 hysteresis */ 141 #define CS_CMP0HST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) 142 #define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0) /*!< CMP0 output no hysteresis */ 143 #define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1) /*!< CMP0 output low hysteresis */ 144 #define CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2) /*!< CMP0 output middle hysteresis */ 145 #define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3) /*!< CMP0 output high hysteresis */ 146 147 /* CMP1 mode */ 148 #define CS_CMP1M(regval) (BITS(18,19) & ((uint32_t)(regval) << 18)) 149 #define CS_CMP1M_HIGHSPEED CS_CMP1M(0) /*!< CMP1 mode high speed */ 150 #define CS_CMP1M_MIDDLESPEED CS_CMP1M(1) /*!< CMP1 mode middle speed */ 151 #define CS_CMP1M_LOWSPEED CS_CMP1M(2) /*!< CMP1 mode low speed */ 152 #define CS_CMP1M_VERYLOWSPEED CS_CMP1M(3) /*!< CMP1 mode very low speed */ 153 154 /* CMP1 inverting input */ 155 #define CS_CMP1MSEL(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) 156 #define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0) /*!< CMP1 inverting input 1/4 Vrefint */ 157 #define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1) /*!< CMP1 inverting input 1/2 Vrefint */ 158 #define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2) /*!< CMP1 inverting input 3/4 Vrefint */ 159 #define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3) /*!< CMP1 inverting input Vrefint */ 160 #define CS_CMP1MSEL_DAC CS_CMP1MSEL(4) /*!< CMP1 inverting input DAC */ 161 #define CS_CMP1MSEL_PA5 CS_CMP1MSEL(5) /*!< CMP1 inverting input PA5 */ 162 #define CS_CMP1MSEL_PA2 CS_CMP1MSEL(6) /*!< CMP1 inverting input PA2 */ 163 164 /* CMP1 output */ 165 #define CS_CMP1OSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) 166 #define CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0) /*!< CMP1 output none */ 167 #define CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1) /*!< CMP1 output TIMER 0 break input */ 168 #define CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2) /*!< CMP1 output TIMER 0 channel 0 input capture */ 169 #define CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3) /*!< CMP1 output TIMER 0 ocpreclear input */ 170 #define CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4) /*!< CMP1 output TIMER 1 channel 3 input capture */ 171 #define CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5) /*!< CMP1 output TIMER 1 ocpreclear input */ 172 #define CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6) /*!< CMP1 output TIMER 2 channle 0 input capture */ 173 #define CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7) /*!< CMP1 output TIMER 2 ocpreclear input */ 174 175 /* CMP1 hysteresis */ 176 #define CS_CMP1HST(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) 177 #define CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0) /*!< CMP1 output no hysteresis */ 178 #define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1) /*!< CMP1 output low hysteresis */ 179 #define CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2) /*!< CMP1 output middle hysteresis */ 180 #define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3) /*!< CMP1 output high hysteresis */ 181 182 /* comparator x definitions */ 183 #define CMP0 ((uint32_t)0x00000000U) /*!< comparator 0 */ 184 #define CMP1 ((uint32_t)0x00000010U) /*!< comparator 1 */ 185 186 /* comparator output level */ 187 #define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< comparator output high */ 188 #define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< comparator output low */ 189 190 /* output polarity of comparator */ 191 #define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001U) /*!< output is inverted */ 192 #define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000U) /*!< output is not inverted */ 193 194 /* function declarations */ 195 196 /* initialization functions */ 197 /* CMP deinit */ 198 void cmp_deinit(void); 199 /* CMP mode init */ 200 void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis); 201 /* CMP output init */ 202 void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity); 203 204 /* enable functions */ 205 /* enable CMP */ 206 void cmp_enable(uint32_t cmp_periph); 207 /* disable CMP */ 208 void cmp_disable(uint32_t cmp_periph); 209 /* enable CMP switch */ 210 void cmp_switch_enable(void); 211 /* disable CMP switch */ 212 void cmp_switch_disable(void); 213 /* enable the window mode */ 214 void cmp_window_enable(void); 215 /* disable the window mode */ 216 void cmp_window_disable(void); 217 /* lock the CMP */ 218 void cmp_lock_enable(uint32_t cmp_periph); 219 220 /* output functions */ 221 /* get output level */ 222 uint32_t cmp_output_level_get(uint32_t cmp_periph); 223 224 #endif /* GD32F3X0_CMP_H */ 225
