1 /*
2  * Copyright 2019-2021 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10 
11 #include "fsl_common.h"
12 
13 /*! @addtogroup clock */
14 /*! @{ */
15 
16 /*! @file */
17 
18 /*******************************************************************************
19  * Configurations
20  ******************************************************************************/
21 
22 /*! @brief Configure whether driver controls clock
23  *
24  * When set to 0, peripheral drivers will enable clock in initialize function
25  * and disable clock in de-initialize function. When set to 1, peripheral
26  * driver will not control the clock, application could control the clock out of
27  * the driver.
28  *
29  * @note All drivers share this feature switcher. If it is set to 1, application
30  * should handle clock enable and disable for all drivers.
31  */
32 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34 #endif
35 
36 /*******************************************************************************
37  * Definitions
38  ******************************************************************************/
39 
40 /*! @name Driver version */
41 /*@{*/
42 /*! @brief CLOCK driver version. */
43 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
44 
45 /* Definition for delay API in clock driver, users can redefine it to the real application. */
46 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47 #if __CORTEX_M == 7
48 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (1000000000UL)
49 #else
50 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL)
51 #endif
52 #endif
53 
54 /*@}*/
55 
56 /*!
57  * @brief CCM registers offset.
58  */
59 #define CCSR_OFFSET   0x0C
60 #define CBCDR_OFFSET  0x14
61 #define CBCMR_OFFSET  0x18
62 #define CSCMR1_OFFSET 0x1C
63 #define CSCMR2_OFFSET 0x20
64 #define CSCDR1_OFFSET 0x24
65 #define CDCDR_OFFSET  0x30
66 #define CSCDR2_OFFSET 0x38
67 #define CSCDR3_OFFSET 0x3C
68 #define CACRR_OFFSET  0x10
69 #define CS1CDR_OFFSET 0x28
70 #define CS2CDR_OFFSET 0x2C
71 
72 /*!
73  * @brief CCM Analog registers offset.
74  */
75 #define ARM_PLL_OFFSET   0x00
76 #define PLL_SYS_OFFSET   0x30
77 #define PLL_USB1_OFFSET  0x10
78 #define PLL_AUDIO_OFFSET 0x70
79 #define PLL_VIDEO_OFFSET 0xA0
80 #define PLL_ENET_OFFSET  0xE0
81 #define PLL_USB2_OFFSET  0x20
82 
83 #define CCM_TUPLE(reg, shift, mask, busyShift) \
84     (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
85 #define CCM_TUPLE_REG(base, tuple)  (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
86 #define CCM_TUPLE_SHIFT(tuple)      (((tuple) >> 8U) & 0x1FU)
87 #define CCM_TUPLE_MASK(tuple)       ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
88 #define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)
89 
90 #define CCM_BUSY_WAIT (0x20U)
91 
92 /*!
93  * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
94  */
95 #define CCM_ANALOG_TUPLE(reg, shift)  (((reg & 0xFFFU) << 16U) | (shift))
96 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
97 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
98     (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))
99 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
100 
101 /*!
102  * @brief SYS_PLL_FREQ frequency in Hz.
103  */
104 #define SYS_PLL1_FREQ (1000000000UL)
105 #define SYS_PLL2_MFI  (22UL)
106 #define SYS_PLL2_FREQ (XTAL_FREQ * SYS_PLL2_MFI)
107 #define SYS_PLL3_MFI  (20UL)
108 #define SYS_PLL3_FREQ (XTAL_FREQ * SYS_PLL3_MFI)
109 #define XTAL_FREQ     (24000000UL)
110 
111 /*! @brief Clock gate name array for ADC. */
112 #define LPADC_CLOCKS                                   \
113     {                                                  \
114         kCLOCK_IpInvalid, kCLOCK_Lpadc1, kCLOCK_Lpadc2 \
115     }
116 
117 /*! @brief Clock gate name array for ADC. */
118 #define ADC_ETC_CLOCKS \
119     {                  \
120         kCLOCK_Adc_Etc \
121     }
122 
123 /*! @brief Clock gate name array for AOI. */
124 #define AOI_CLOCKS                                 \
125     {                                              \
126         kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
127     }
128 
129 /*! @brief Clock gate name array for DCDC. */
130 #define DCDC_CLOCKS \
131     {               \
132         kCLOCK_Dcdc \
133     }
134 
135 /*! @brief Clock gate name array for SRC. */
136 #define SRC_CLOCKS \
137     {              \
138         kCLOCK_Src \
139     }
140 
141 /*! @brief Clock gate name array for GPC. */
142 #define GPC_CLOCKS \
143     {              \
144         kCLOCK_Gpc \
145     }
146 
147 /*! @brief Clock gate name array for SSARC. */
148 #define SSARC_CLOCKS \
149     {                \
150         kCLOCK_Ssarc \
151     }
152 
153 /*! @brief Clock gate name array for WDOG. */
154 #define WDOG_CLOCKS                                                              \
155     {                                                                            \
156         kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4 \
157     }
158 
159 /*! @brief Clock gate name array for EWM. */
160 #define EWM_CLOCKS  \
161     {               \
162         kCLOCK_Ewm0 \
163     }
164 
165 /*! @brief Clock gate name array for Sema. */
166 #define SEMA_CLOCKS \
167     {               \
168         kCLOCK_Sema \
169     }
170 
171 /*! @brief Clock gate name array for MU. */
172 #if (__CORTEX_M == 7)
173 #define MU_CLOCKS   \
174     {               \
175         kCLOCK_Mu_A \
176     }
177 #else
178 #define MU_CLOCKS   \
179     {               \
180         kCLOCK_Mu_B \
181     }
182 #endif
183 
184 /*! @brief Clock gate name array for EDMA. */
185 #define EDMA_CLOCKS                   \
186     {                                 \
187         kCLOCK_Edma, kCLOCK_Edma_Lpsr \
188     }
189 
190 /*! @brief Clock gate name array for FLEXRAM. */
191 #define FLEXRAM_CLOCKS \
192     {                  \
193         kCLOCK_Flexram \
194     }
195 
196 /*! @brief Clock gate name array for LMEM. */
197 #define LMEM_CLOCKS \
198     {               \
199         kCLOCK_Lmem \
200     }
201 
202 /*! @brief Clock gate name array for FLEXSPI. */
203 #define FLEXSPI_CLOCKS                                     \
204     {                                                      \
205         kCLOCK_IpInvalid, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \
206     }
207 
208 /*! @brief Clock gate name array for RDC. */
209 #define RDC_CLOCKS                                 \
210     {                                              \
211         kCLOCK_Rdc, kCLOCK_M7_Xrdc, kCLOCK_M4_Xrdc \
212     }
213 
214 /*! @brief Clock ip name array for DCDC. */
215 #define DCDC_CLOCKS \
216     {               \
217         kCLOCK_Dcdc \
218     }
219 
220 /*! @brief Clock ip name array for SEMC. */
221 #define SEMC_CLOCKS \
222     {               \
223         kCLOCK_Semc \
224     }
225 
226 /*! @brief Clock ip name array for XECC. */
227 #define XECC_CLOCKS \
228     {               \
229         kCLOCK_Xecc \
230     }
231 
232 /*! @brief Clock ip name array for IEE. */
233 #define IEE_CLOCKS \
234     {              \
235         kCLOCK_Iee \
236     }
237 
238 /*! @brief Clock ip name array for KEY_MANAGER. */
239 #define KEYMANAGER_CLOCKS  \
240     {                      \
241         kCLOCK_Key_Manager \
242     }
243 
244 /*! @brief Clock ip name array for PUF. */
245 #define PUF_CLOCKS \
246     {              \
247         kCLOCK_Puf \
248     }
249 
250 /*! @brief Clock ip name array for OCOTP. */
251 #define OCOTP_CLOCKS \
252     {                \
253         kCLOCK_Ocotp \
254     }
255 
256 /*! @brief Clock ip name array for CAAM. */
257 #define CAAM_CLOCKS \
258     {               \
259         kCLOCK_Caam \
260     }
261 
262 /*! @brief Clock ip name array for XBAR. */
263 #define XBAR_CLOCKS                                                \
264     {                                                              \
265         kCLOCK_IpInvalid, kCLOCK_Xbar1, kCLOCK_Xbar2, kCLOCK_Xbar3 \
266     }
267 
268 /*! @brief Clock ip name array for IOMUXC. */
269 #define IOMUXC_CLOCKS                     \
270     {                                     \
271         kCLOCK_Iomuxc, kCLOCK_Iomuxc_Lpsr \
272     }
273 
274 /*! @brief Clock ip name array for GPIO. */
275 #define GPIO_CLOCKS                                                                                                  \
276     {                                                                                                                \
277         kCLOCK_IpInvalid, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \
278             kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio,                            \
279     }
280 
281 /*! @brief Clock ip name array for KPP. */
282 #define KPP_CLOCKS \
283     {              \
284         kCLOCK_Kpp \
285     }
286 
287 /*! @brief Clock ip name array for FLEXIO. */
288 #define FLEXIO_CLOCKS                                    \
289     {                                                    \
290         kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
291     }
292 
293 /*! @brief Clock ip name array for DAC. */
294 #define DAC_CLOCKS \
295     {              \
296         kCLOCK_Dac \
297     }
298 
299 /*! @brief Clock ip name array for CMP. */
300 #define CMP_CLOCKS                                                               \
301     {                                                                            \
302         kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
303     }
304 
305 /*! @brief Clock ip name array for PIT. */
306 #define PIT_CLOCKS                                 \
307     {                                              \
308         kCLOCK_IpInvalid, kCLOCK_Pit1, kCLOCK_Pit2 \
309     }
310 
311 /*! @brief Clock ip name array for GPT. */
312 #define GPT_CLOCKS                                                                                     \
313     {                                                                                                  \
314         kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6 \
315     }
316 
317 /*! @brief Clock ip name array for QTIMER. */
318 #define TMR_CLOCKS                                                                       \
319     {                                                                                    \
320         kCLOCK_IpInvalid, kCLOCK_Qtimer1, kCLOCK_Qtimer2, kCLOCK_Qtimer3, kCLOCK_Qtimer4 \
321     }
322 
323 /*! @brief Clock ip name array for ENC. */
324 #define ENC_CLOCKS                                                           \
325     {                                                                        \
326         kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
327     }
328 
329 /*! @brief Clock ip name array for PWM. */
330 #define PWM_CLOCKS                                                                \
331     {                                                                             \
332         {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
333             {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
334             {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
335             {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
336         {                                                                         \
337             kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
338         }                                                                         \
339     }
340 
341 /*! @brief Clock ip name array for FLEXCAN. */
342 #define FLEXCAN_CLOCKS                                          \
343     {                                                           \
344         kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
345     }
346 
347 /*! @brief Clock ip name array for LPUART. */
348 #define LPUART_CLOCKS                                                                                         \
349     {                                                                                                         \
350         kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5,     \
351             kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \
352             kCLOCK_Lpuart12                                                                                   \
353     }
354 
355 /*! @brief Clock ip name array for LPI2C. */
356 #define LPI2C_CLOCKS                                                                                               \
357     {                                                                                                              \
358         kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \
359     }
360 
361 /*! @brief Clock ip name array for LPSPI. */
362 #define LPSPI_CLOCKS                                                                                               \
363     {                                                                                                              \
364         kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6 \
365     }
366 
367 /*! @brief Clock ip name array for EMVSIM. */
368 #define EMVSIM_CLOCKS                              \
369     {                                              \
370         kCLOCK_IpInvalid, kCLOCK_Sim1, kCLOCK_Sim2 \
371     }
372 
373 /*! @brief Clock ip name array for ENET. */
374 #define ENET_CLOCKS                 \
375     {                               \
376         kCLOCK_Enet, kCLOCK_Enet_1g \
377     }
378 
379 /*! @brief Clock ip name array for ENET_QOS. */
380 #define ENETQOS_CLOCKS  \
381     {                   \
382         kCLOCK_Enet_Qos \
383     }
384 
385 /*! @brief Clock ip name array for USB. */
386 #define USB_CLOCKS \
387     {              \
388         kCLOCK_Usb \
389     }
390 
391 /*! @brief Clock ip name array for CDOG. */
392 #define CDOG_CLOCKS \
393     {               \
394         kCLOCK_Cdog \
395     }
396 
397 /*! @brief Clock ip name array for USDHC. */
398 #define USDHC_CLOCKS                                   \
399     {                                                  \
400         kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
401     }
402 
403 /*! @brief Clock ip name array for ASRC. */
404 #define ASRC_CLOCKS \
405     {               \
406         kCLOCK_Asrc \
407     }
408 
409 /*! @brief Clock ip name array for MQS. */
410 #define MQS_CLOCKS \
411     {              \
412         kCLOCK_Mqs \
413     }
414 
415 /*! @brief Clock ip name array for PDM. */
416 #define PDM_CLOCKS \
417     {              \
418         kCLOCK_Pdm \
419     }
420 
421 /*! @brief Clock ip name array for SPDIF. */
422 #define SPDIF_CLOCKS \
423     {                \
424         kCLOCK_Spdif \
425     }
426 
427 /*! @brief Clock ip name array for SAI. */
428 #define SAI_CLOCKS                                                           \
429     {                                                                        \
430         kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4 \
431     }
432 
433 /*! @brief Clock ip name array for PXP. */
434 #define PXP_CLOCKS \
435     {              \
436         kCLOCK_Pxp \
437     }
438 
439 /*! @brief Clock ip name array for GPU2d. */
440 #define GPU2D_CLOCKS \
441     {                \
442         kCLOCK_Gpu2d \
443     }
444 
445 /*! @brief Clock ip name array for LCDIF. */
446 #define LCDIF_CLOCKS \
447     {                \
448         kCLOCK_Lcdif \
449     }
450 
451 /*! @brief Clock ip name array for LCDIFV2. */
452 #define LCDIFV2_CLOCKS \
453     {                  \
454         kCLOCK_Lcdifv2 \
455     }
456 
457 /*! @brief Clock ip name array for MIPI_DSI. */
458 #define MIPI_DSI_HOST_CLOCKS \
459     {                        \
460         kCLOCK_Mipi_Dsi      \
461     }
462 
463 /*! @brief Clock ip name array for MIPI_CSI. */
464 #define MIPI_CSI2RX_CLOCKS \
465     {                      \
466         kCLOCK_Mipi_Csi    \
467     }
468 
469 /*! @brief Clock ip name array for CSI. */
470 #define CSI_CLOCKS \
471     {              \
472         kCLOCK_Csi \
473     }
474 
475 /*! @brief Clock ip name array for DCIC. */
476 #define DCIC_CLOCKS                                         \
477     {                                                       \
478         kCLOCK_IpInvalid, kCLOCK_Dcic_Mipi, kCLOCK_Dcic_Lcd \
479     }
480 
481 /*! @brief Clock ip name array for DMAMUX_CLOCKS. */
482 #define DMAMUX_CLOCKS                 \
483     {                                 \
484         kCLOCK_Edma, kCLOCK_Edma_Lpsr \
485     }
486 
487 /*! @brief Clock ip name array for XBARA. */
488 #define XBARA_CLOCKS \
489     {                \
490         kCLOCK_Xbar1 \
491     }
492 
493 /*! @brief Clock ip name array for XBARB. */
494 #define XBARB_CLOCKS                                                   \
495     {                                                                  \
496         kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
497     }
498 
499 /*!
500  * @brief Clock LPCG index
501  */
502 typedef enum _clock_lpcg
503 {
504     kCLOCK_M7          = 0,   /*!< Clock LPCG M7. */
505     kCLOCK_M4          = 1,   /*!< Clock LPCG M4. */
506     kCLOCK_Sim_M7      = 2,   /*!< Clock LPCG SIM M7. */
507     kCLOCK_Sim_M       = 3,   /*!< Clock LPCG SIM M4. */
508     kCLOCK_Sim_Disp    = 4,   /*!< Clock LPCG SIM DISP. */
509     kCLOCK_Sim_Per     = 5,   /*!< Clock LPCG SIM PER. */
510     kCLOCK_Sim_Lpsr    = 6,   /*!< Clock LPCG SIM LPSR. */
511     kCLOCK_Anadig      = 7,   /*!< Clock LPCG Anadig. */
512     kCLOCK_Dcdc        = 8,   /*!< Clock LPCG DCDC. */
513     kCLOCK_Src         = 9,   /*!< Clock LPCG SRC. */
514     kCLOCK_Ccm         = 10,  /*!< Clock LPCG CCM. */
515     kCLOCK_Gpc         = 11,  /*!< Clock LPCG GPC. */
516     kCLOCK_Ssarc       = 12,  /*!< Clock LPCG SSARC. */
517     kCLOCK_Sim_R       = 13,  /*!< Clock LPCG SIM_R. */
518     kCLOCK_Wdog1       = 14,  /*!< Clock LPCG WDOG1. */
519     kCLOCK_Wdog2       = 15,  /*!< Clock LPCG WDOG2. */
520     kCLOCK_Wdog3       = 16,  /*!< Clock LPCG WDOG3. */
521     kCLOCK_Wdog4       = 17,  /*!< Clock LPCG WDOG4. */
522     kCLOCK_Ewm0        = 18,  /*!< Clock LPCG EWM0. */
523     kCLOCK_Sema        = 19,  /*!< Clock LPCG SEMA. */
524     kCLOCK_Mu_A        = 20,  /*!< Clock LPCG MU_A. */
525     kCLOCK_Mu_B        = 21,  /*!< Clock LPCG MU_B. */
526     kCLOCK_Edma        = 22,  /*!< Clock LPCG EDMA. */
527     kCLOCK_Edma_Lpsr   = 23,  /*!< Clock LPCG EDMA_LPSR. */
528     kCLOCK_Romcp       = 24,  /*!< Clock LPCG ROMCP. */
529     kCLOCK_Ocram       = 25,  /*!< Clock LPCG OCRAM. */
530     kCLOCK_Flexram     = 26,  /*!< Clock LPCG FLEXRAM. */
531     kCLOCK_Lmem        = 27,  /*!< Clock LPCG Lmem. */
532     kCLOCK_Flexspi1    = 28,  /*!< Clock LPCG Flexspi1. */
533     kCLOCK_Flexspi2    = 29,  /*!< Clock LPCG Flexspi2. */
534     kCLOCK_Rdc         = 30,  /*!< Clock LPCG RDC. */
535     kCLOCK_M7_Xrdc     = 31,  /*!< Clock LPCG M7 XRDC. */
536     kCLOCK_M4_Xrdc     = 32,  /*!< Clock LPCG M4 XRDC. */
537     kCLOCK_Semc        = 33,  /*!< Clock LPCG SEMC. */
538     kCLOCK_Xecc        = 34,  /*!< Clock LPCG XECC. */
539     kCLOCK_Iee         = 35,  /*!< Clock LPCG IEE. */
540     kCLOCK_Key_Manager = 36,  /*!< Clock LPCG KEY_MANAGER. */
541     kCLOCK_Puf         = 36,  /*!< Clock LPCG PUF. */
542     kCLOCK_Ocotp       = 37,  /*!< Clock LPCG OSOTP. */
543     kCLOCK_Snvs_Hp     = 38,  /*!< Clock LPCG SNVS_HP. */
544     kCLOCK_Snvs        = 39,  /*!< Clock LPCG SNVS. */
545     kCLOCK_Caam        = 40,  /*!< Clock LPCG Caam. */
546     kCLOCK_Jtag_Mux    = 41,  /*!< Clock LPCG JTAG_MUX. */
547     kCLOCK_Cstrace     = 42,  /*!< Clock LPCG CSTRACE. */
548     kCLOCK_Xbar1       = 43,  /*!< Clock LPCG XBAR1. */
549     kCLOCK_Xbar2       = 44,  /*!< Clock LPCG XBAR2. */
550     kCLOCK_Xbar3       = 45,  /*!< Clock LPCG XBAR3. */
551     kCLOCK_Aoi1        = 46,  /*!< Clock LPCG AOI1. */
552     kCLOCK_Aoi2        = 47,  /*!< Clock LPCG AOI2. */
553     kCLOCK_Adc_Etc     = 48,  /*!< Clock LPCG ADC_ETC. */
554     kCLOCK_Iomuxc      = 49,  /*!< Clock LPCG IOMUXC. */
555     kCLOCK_Iomuxc_Lpsr = 50,  /*!< Clock LPCG IOMUXC_LPSR. */
556     kCLOCK_Gpio        = 51,  /*!< Clock LPCG GPIO. */
557     kCLOCK_Kpp         = 52,  /*!< Clock LPCG KPP. */
558     kCLOCK_Flexio1     = 53,  /*!< Clock LPCG FLEXIO1. */
559     kCLOCK_Flexio2     = 54,  /*!< Clock LPCG FLEXIO2. */
560     kCLOCK_Lpadc1      = 55,  /*!< Clock LPCG LPADC1. */
561     kCLOCK_Lpadc2      = 56,  /*!< Clock LPCG LPADC2. */
562     kCLOCK_Dac         = 57,  /*!< Clock LPCG DAC. */
563     kCLOCK_Acmp1       = 58,  /*!< Clock LPCG ACMP1. */
564     kCLOCK_Acmp2       = 59,  /*!< Clock LPCG ACMP2. */
565     kCLOCK_Acmp3       = 60,  /*!< Clock LPCG ACMP3. */
566     kCLOCK_Acmp4       = 61,  /*!< Clock LPCG ACMP4. */
567     kCLOCK_Pit1        = 62,  /*!< Clock LPCG PIT1. */
568     kCLOCK_Pit2        = 63,  /*!< Clock LPCG PIT2. */
569     kCLOCK_Gpt1        = 64,  /*!< Clock LPCG GPT1. */
570     kCLOCK_Gpt2        = 65,  /*!< Clock LPCG GPT2. */
571     kCLOCK_Gpt3        = 66,  /*!< Clock LPCG GPT3. */
572     kCLOCK_Gpt4        = 67,  /*!< Clock LPCG GPT4. */
573     kCLOCK_Gpt5        = 68,  /*!< Clock LPCG GPT5. */
574     kCLOCK_Gpt6        = 69,  /*!< Clock LPCG GPT6. */
575     kCLOCK_Qtimer1     = 70,  /*!< Clock LPCG QTIMER1. */
576     kCLOCK_Qtimer2     = 71,  /*!< Clock LPCG QTIMER2. */
577     kCLOCK_Qtimer3     = 72,  /*!< Clock LPCG QTIMER3. */
578     kCLOCK_Qtimer4     = 73,  /*!< Clock LPCG QTIMER4. */
579     kCLOCK_Enc1        = 74,  /*!< Clock LPCG Enc1. */
580     kCLOCK_Enc2        = 75,  /*!< Clock LPCG Enc2. */
581     kCLOCK_Enc3        = 76,  /*!< Clock LPCG Enc3. */
582     kCLOCK_Enc4        = 77,  /*!< Clock LPCG Enc4. */
583     kCLOCK_Hrtimer     = 78,  /*!< Clock LPCG Hrtimer. */
584     kCLOCK_Pwm1        = 79,  /*!< Clock LPCG PWM1. */
585     kCLOCK_Pwm2        = 80,  /*!< Clock LPCG PWM2. */
586     kCLOCK_Pwm3        = 81,  /*!< Clock LPCG PWM3. */
587     kCLOCK_Pwm4        = 82,  /*!< Clock LPCG PWM4. */
588     kCLOCK_Can1        = 83,  /*!< Clock LPCG CAN1. */
589     kCLOCK_Can2        = 84,  /*!< Clock LPCG CAN2. */
590     kCLOCK_Can3        = 85,  /*!< Clock LPCG CAN3. */
591     kCLOCK_Lpuart1     = 86,  /*!< Clock LPCG LPUART1. */
592     kCLOCK_Lpuart2     = 87,  /*!< Clock LPCG LPUART2. */
593     kCLOCK_Lpuart3     = 88,  /*!< Clock LPCG LPUART3. */
594     kCLOCK_Lpuart4     = 89,  /*!< Clock LPCG LPUART4. */
595     kCLOCK_Lpuart5     = 90,  /*!< Clock LPCG LPUART5. */
596     kCLOCK_Lpuart6     = 91,  /*!< Clock LPCG LPUART6. */
597     kCLOCK_Lpuart7     = 92,  /*!< Clock LPCG LPUART7. */
598     kCLOCK_Lpuart8     = 93,  /*!< Clock LPCG LPUART8. */
599     kCLOCK_Lpuart9     = 94,  /*!< Clock LPCG LPUART9. */
600     kCLOCK_Lpuart10    = 95,  /*!< Clock LPCG LPUART10. */
601     kCLOCK_Lpuart11    = 96,  /*!< Clock LPCG LPUART11. */
602     kCLOCK_Lpuart12    = 97,  /*!< Clock LPCG LPUART12. */
603     kCLOCK_Lpi2c1      = 98,  /*!< Clock LPCG LPI2C1. */
604     kCLOCK_Lpi2c2      = 99,  /*!< Clock LPCG LPI2C2. */
605     kCLOCK_Lpi2c3      = 100, /*!< Clock LPCG LPI2C3. */
606     kCLOCK_Lpi2c4      = 101, /*!< Clock LPCG LPI2C4. */
607     kCLOCK_Lpi2c5      = 102, /*!< Clock LPCG LPI2C5. */
608     kCLOCK_Lpi2c6      = 103, /*!< Clock LPCG LPI2C6. */
609     kCLOCK_Lpspi1      = 104, /*!< Clock LPCG LPSPI1. */
610     kCLOCK_Lpspi2      = 105, /*!< Clock LPCG LPSPI2. */
611     kCLOCK_Lpspi3      = 106, /*!< Clock LPCG LPSPI3. */
612     kCLOCK_Lpspi4      = 107, /*!< Clock LPCG LPSPI4. */
613     kCLOCK_Lpspi5      = 108, /*!< Clock LPCG LPSPI5. */
614     kCLOCK_Lpspi6      = 109, /*!< Clock LPCG LPSPI6. */
615     kCLOCK_Sim1        = 110, /*!< Clock LPCG SIM1. */
616     kCLOCK_Sim2        = 111, /*!< Clock LPCG SIM2. */
617     kCLOCK_Enet        = 112, /*!< Clock LPCG ENET. */
618     kCLOCK_Enet_1g     = 113, /*!< Clock LPCG ENET 1G. */
619     kCLOCK_Enet_Qos    = 114, /*!< Clock LPCG ENET QOS. */
620     kCLOCK_Usb         = 115, /*!< Clock LPCG USB. */
621     kCLOCK_Cdog        = 116, /*!< Clock LPCG CDOG. */
622     kCLOCK_Usdhc1      = 117, /*!< Clock LPCG USDHC1. */
623     kCLOCK_Usdhc2      = 118, /*!< Clock LPCG USDHC2. */
624     kCLOCK_Asrc        = 119, /*!< Clock LPCG ASRC. */
625     kCLOCK_Mqs         = 120, /*!< Clock LPCG MQS. */
626     kCLOCK_Pdm         = 121, /*!< Clock LPCG PDM. */
627     kCLOCK_Spdif       = 122, /*!< Clock LPCG SPDIF. */
628     kCLOCK_Sai1        = 123, /*!< Clock LPCG SAI1. */
629     kCLOCK_Sai2        = 124, /*!< Clock LPCG SAI2. */
630     kCLOCK_Sai3        = 125, /*!< Clock LPCG SAI3. */
631     kCLOCK_Sai4        = 126, /*!< Clock LPCG SAI4. */
632     kCLOCK_Pxp         = 127, /*!< Clock LPCG PXP. */
633     kCLOCK_Gpu2d       = 128, /*!< Clock LPCG GPU2D. */
634     kCLOCK_Lcdif       = 129, /*!< Clock LPCG LCDIF. */
635     kCLOCK_Lcdifv2     = 130, /*!< Clock LPCG LCDIFV2. */
636     kCLOCK_Mipi_Dsi    = 131, /*!< Clock LPCG MIPI DSI. */
637     kCLOCK_Mipi_Csi    = 132, /*!< Clock LPCG MIPI CSI. */
638     kCLOCK_Csi         = 133, /*!< Clock LPCG CSI. */
639     kCLOCK_Dcic_Mipi   = 134, /*!< Clock LPCG DCIC MIPI. */
640     kCLOCK_Dcic_Lcd    = 135, /*!< Clock LPCG DCIC LCD. */
641     kCLOCK_Video_Mux   = 136, /*!< Clock LPCG VIDEO MUX. */
642     kCLOCK_Uniq_Edt_I  = 137, /*!< Clock LPCG Uniq_Edt_I. */
643 
644     kCLOCK_IpInvalid, /*!< Invalid value. */
645 } clock_lpcg_t;
646 
647 /*!
648  * @brief Clock name.
649  */
650 typedef enum _clock_name
651 {
652     kCLOCK_OscRc16M     = 0,  /*!< 16MHz RC Oscillator. */
653     kCLOCK_OscRc48M     = 1,  /*!< 48MHz RC Oscillator. */
654     kCLOCK_OscRc48MDiv2 = 2,  /*!< 48MHz RC Oscillator Div2. */
655     kCLOCK_OscRc400M    = 3,  /*!< 400MHz RC Oscillator. */
656     kCLOCK_Osc24M       = 4,  /*!< 24MHz Oscillator. */
657     kCLOCK_Osc24MOut    = 5,  /*!< 48MHz Oscillator Out. */
658     kCLOCK_ArmPll       = 6,  /*!< ARM PLL. */
659     kCLOCK_ArmPllOut    = 7,  /*!< ARM PLL Out. */
660     kCLOCK_SysPll2      = 8,  /*!< SYS PLL2. */
661     kCLOCK_SysPll2Out   = 9,  /*!< SYS PLL2 OUT. */
662     kCLOCK_SysPll2Pfd0  = 10, /*!< SYS PLL2 PFD0. */
663     kCLOCK_SysPll2Pfd1  = 11, /*!< SYS PLL2 PFD1. */
664     kCLOCK_SysPll2Pfd2  = 12, /*!< SYS PLL2 PFD2. */
665     kCLOCK_SysPll2Pfd3  = 13, /*!< SYS PLL2 PFD3. */
666     kCLOCK_SysPll3      = 14, /*!< SYS PLL3. */
667     kCLOCK_SysPll3Out   = 15, /*!< SYS PLL3 OUT. */
668     kCLOCK_SysPll3Div2  = 16, /*!< SYS PLL3 DIV2 */
669     kCLOCK_SysPll3Pfd0  = 17, /*!< SYS PLL3 PFD0. */
670     kCLOCK_SysPll3Pfd1  = 18, /*!< SYS PLL3 PFD1 */
671     kCLOCK_SysPll3Pfd2  = 19, /*!< SYS PLL3 PFD2 */
672     kCLOCK_SysPll3Pfd3  = 20, /*!< SYS PLL3 PFD3 */
673     kCLOCK_SysPll1      = 21, /*!< SYS PLL1. */
674     kCLOCK_SysPll1Out   = 22, /*!< SYS PLL1 OUT. */
675     kCLOCK_SysPll1Div2  = 23, /*!< SYS PLL1 DIV2. */
676     kCLOCK_SysPll1Div5  = 24, /*!< SYS PLL1 DIV5. */
677     kCLOCK_AudioPll     = 25, /*!< SYS AUDIO PLL. */
678     kCLOCK_AudioPllOut  = 26, /*!< SYS AUDIO PLL OUT. */
679     kCLOCK_VideoPll     = 27, /*!< SYS VIDEO PLL. */
680     kCLOCK_VideoPllOut  = 28, /*!< SYS VIDEO PLL OUT. */
681     kCLOCK_CpuClk,            /*!< SYS CPU CLK. */
682     kCLOCK_CoreSysClk,        /*!< SYS CORE SYS CLK. */
683 } clock_name_t;
684 
685 /* Clock OBSERVE SIGNALS */
686 #define CCM_OBS_M7_CLK_ROOT          128, 4
687 #define CCM_OBS_M4_CLK_ROOT          129, 0
688 #define CCM_OBS_BUS_CLK_ROOT         130, 2
689 #define CCM_OBS_BUS_LPSR_CLK_ROOT    131, 0
690 #define CCM_OBS_SEMC_CLK_ROOT        132, 2
691 #define CCM_OBS_CSSYS_CLK_ROOT       133, 2
692 #define CCM_OBS_CSTRACE_CLK_ROOT     134, 2
693 #define CCM_OBS_M4_SYSTICK_CLK_ROOT  135, 0
694 #define CCM_OBS_M7_SYSTICK_CLK_ROOT  136, 2
695 #define CCM_OBS_ADC1_CLK_ROOT        137, 2
696 #define CCM_OBS_ADC2_CLK_ROOT        138, 2
697 #define CCM_OBS_ACMP_CLK_ROOT        139, 2
698 #define CCM_OBS_FLEXIO1_CLK_ROOT     140, 2
699 #define CCM_OBS_FLEXIO2_CLK_ROOT     141, 2
700 #define CCM_OBS_GPT1_CLK_ROOT        142, 2
701 #define CCM_OBS_GPT2_CLK_ROOT        143, 2
702 #define CCM_OBS_GPT3_CLK_ROOT        144, 2
703 #define CCM_OBS_GPT4_CLK_ROOT        145, 2
704 #define CCM_OBS_GPT5_CLK_ROOT        146, 2
705 #define CCM_OBS_GPT6_CLK_ROOT        147, 2
706 #define CCM_OBS_FLEXSPI1_CLK_ROOT    148, 2
707 #define CCM_OBS_FLEXSPI2_CLK_ROOT    149, 2
708 #define CCM_OBS_CAN1_CLK_ROOT        150, 2
709 #define CCM_OBS_CAN2_CLK_ROOT        151, 2
710 #define CCM_OBS_CAN3_CLK_ROOT        152, 0
711 #define CCM_OBS_LPUART1_CLK_ROOT     153, 2
712 #define CCM_OBS_LPUART2_CLK_ROOT     154, 2
713 #define CCM_OBS_LPUART3_CLK_ROOT     155, 2
714 #define CCM_OBS_LPUART4_CLK_ROOT     156, 2
715 #define CCM_OBS_LPUART5_CLK_ROOT     157, 2
716 #define CCM_OBS_LPUART6_CLK_ROOT     158, 2
717 #define CCM_OBS_LPUART7_CLK_ROOT     159, 2
718 #define CCM_OBS_LPUART8_CLK_ROOT     160, 2
719 #define CCM_OBS_LPUART9_CLK_ROOT     161, 2
720 #define CCM_OBS_LPUART10_CLK_ROOT    162, 2
721 #define CCM_OBS_LPUART11_CLK_ROOT    163, 0
722 #define CCM_OBS_LPUART12_CLK_ROOT    164, 0
723 #define CCM_OBS_LPI2C1_CLK_ROOT      165, 2
724 #define CCM_OBS_LPI2C2_CLK_ROOT      166, 2
725 #define CCM_OBS_LPI2C3_CLK_ROOT      167, 2
726 #define CCM_OBS_LPI2C4_CLK_ROOT      168, 2
727 #define CCM_OBS_LPI2C5_CLK_ROOT      169, 0
728 #define CCM_OBS_LPI2C6_CLK_ROOT      170, 0
729 #define CCM_OBS_LPSPI1_CLK_ROOT      171, 2
730 #define CCM_OBS_LPSPI2_CLK_ROOT      172, 2
731 #define CCM_OBS_LPSPI3_CLK_ROOT      173, 2
732 #define CCM_OBS_LPSPI4_CLK_ROOT      174, 2
733 #define CCM_OBS_LPSPI5_CLK_ROOT      175, 0
734 #define CCM_OBS_LPSPI6_CLK_ROOT      176, 0
735 #define CCM_OBS_EMV1_CLK_ROOT        177, 2
736 #define CCM_OBS_EMV2_CLK_ROOT        178, 2
737 #define CCM_OBS_ENET1_CLK_ROOT       179, 2
738 #define CCM_OBS_ENET2_CLK_ROOT       180, 2
739 #define CCM_OBS_ENET_QOS_CLK_ROOT    181, 2
740 #define CCM_OBS_ENET_25M_CLK_ROOT    182, 2
741 #define CCM_OBS_ENET_TIMER1_CLK_ROOT 183, 2
742 #define CCM_OBS_ENET_TIMER2_CLK_ROOT 184, 2
743 #define CCM_OBS_ENET_TIMER3_CLK_ROOT 185, 2
744 #define CCM_OBS_USDHC1_CLK_ROOT      186, 2
745 #define CCM_OBS_USDHC2_CLK_ROOT      187, 2
746 #define CCM_OBS_ASRC_CLK_ROOT        188, 2
747 #define CCM_OBS_MQS_CLK_ROOT         189, 2
748 #define CCM_OBS_MIC_CLK_ROOT         190, 0
749 #define CCM_OBS_SPDIF_CLK_ROOT       191, 2
750 #define CCM_OBS_SAI1_CLK_ROOT        192, 2
751 #define CCM_OBS_SAI2_CLK_ROOT        193, 2
752 #define CCM_OBS_SAI3_CLK_ROOT        194, 2
753 #define CCM_OBS_SAI4_CLK_ROOT        195, 0
754 #define CCM_OBS_GC355_CLK_ROOT       196, 2
755 #define CCM_OBS_LCDIF_CLK_ROOT       197, 2
756 #define CCM_OBS_LCDIFV2_CLK_ROOT     198, 2
757 #define CCM_OBS_MIPI_REF_CLK_ROOT    199, 2
758 #define CCM_OBS_MIPI_ESC_CLK_ROOT    200, 2
759 #define CCM_OBS_CSI2_CLK_ROOT        201, 2
760 #define CCM_OBS_CSI2_ESC_CLK_ROOT    202, 2
761 #define CCM_OBS_CSI2_UI_CLK_ROOT     203, 2
762 #define CCM_OBS_CSI_CLK_ROOT         204, 2
763 #define CCM_OBS_CCM_CKO1_CLK_ROOT    205, 0
764 #define CCM_OBS_CCM_CKO2_CLK_ROOT    206, 2
765 #define CCM_OBS_CM7_CORE_STCLKEN     207, 4
766 #define CCM_OBS_CCM_FLEXRAM_CLK_ROOT 208, 4
767 #define CCM_OBS_MIPI_DSI_TXESC       209, 2
768 #define CCM_OBS_MIPI_DSI_RXESC       210, 2
769 #define CCM_OBS_OSC_RC_16M           224, 0
770 #define CCM_OBS_OSC_RC_48M           225, 0
771 #define CCM_OBS_OSC_RC_48M_DIV2      226, 0
772 #define CCM_OBS_OSC_RC_400M          227, 0
773 #define CCM_OBS_OSC_24M_OUT          229, 0
774 #define CCM_OBS_ARM_PLL_OUT          231, 2
775 #define CCM_OBS_SYS_PLL2_OUT         233, 2
776 #define CCM_OBS_SYS_PLL2_PFD0        234, 2
777 #define CCM_OBS_SYS_PLL2_PFD1        235, 2
778 #define CCM_OBS_SYS_PLL2_PFD2        236, 2
779 #define CCM_OBS_SYS_PLL2_PFD3        237, 2
780 #define CCM_OBS_SYS_PLL3_OUT         239, 2
781 #define CCM_OBS_SYS_PLL3_DIV2        240, 2
782 #define CCM_OBS_SYS_PLL3_PFD0        241, 2
783 #define CCM_OBS_SYS_PLL3_PFD1        242, 2
784 #define CCM_OBS_SYS_PLL3_PFD2        243, 2
785 #define CCM_OBS_SYS_PLL3_PFD3        244, 2
786 #define CCM_OBS_SYS_PLL1_OUT         246, 2
787 #define CCM_OBS_SYS_PLL1_DIV2        247, 2
788 #define CCM_OBS_SYS_PLL1_DIV5        248, 2
789 #define CCM_OBS_PLL_AUDIO_OUT        250, 2
790 #define CCM_OBS_PLL_VIDEO_OUT        252, 2
791 
792 #define CCM_OBS_DIV 3
793 
794 /* Clock Source Definitions */
795 /* clang-format off */
796 static const clock_name_t s_clockSourceName[][8] = {
797         /*SRC0,               SRC1,             SRC2,             SRC3,            SRC4,             SRC5,              SRC6,              SRC7,                      name             index */ \
798         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_ArmPllOut, kCLOCK_SysPll1Out, kCLOCK_SysPll3Out, kCLOCK_VideoPllOut},     /* M7               0    */ \
799         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Out, kCLOCK_SysPll1Div5},   /* M4               1    */ \
800         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Out, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},   /* BUS              2    */ \
801         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Out, kCLOCK_SysPll1Div5},   /* BUS_LPSR         3    */ \
802         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd1, kCLOCK_SysPll3Pfd0},  /* SEMC             4    */ \
803         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* CSSYS            5    */ \
804         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1, kCLOCK_SysPll2Out},  /* CSTRACE          6    */ \
805         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll1Div5},  /* M4_SYSTICK       7    */ \
806         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd0},  /* M7_SYSTICK       8    */ \
807         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* ADC1             9    */ \
808         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* ADC2            10    */ \
809         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Out, kCLOCK_SysPll1Div5, kCLOCK_AudioPllOut, kCLOCK_SysPll2Pfd3},  /* ACMP            11    */ \
810         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* FLEXIO1         12    */ \
811         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* FLEXIO2         13    */ \
812         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT1            14    */ \
813         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_AudioPllOut, kCLOCK_VideoPllOut}, /* GPT2            15    */ \
814         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_AudioPllOut, kCLOCK_VideoPllOut}, /* GPT3            16    */ \
815         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT4            17    */ \
816         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT5            18    */ \
817         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT6            19    */ \
818         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd0, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out},   /* FLEXSPI1        20    */ \
819         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd0, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out},   /* FLEXSPI2        21    */ \
820         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* CAN1            22    */ \
821         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* CAN2            23    */ \
822         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* CAN3            24    */ \
823         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART1         25    */ \
824         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART2         26    */ \
825         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART3         27    */ \
826         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART4         28    */ \
827         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART5         29    */ \
828         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART6         30    */ \
829         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART7         31    */ \
830         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART8         32    */ \
831         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART9         33    */ \
832         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART10        34    */ \
833         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* LPUART11        35    */ \
834         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* LPUART12        36    */ \
835         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPI2C1          37    */ \
836         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPI2C2          38    */ \
837         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPI2C3          39    */ \
838         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPI2C4          40    */ \
839         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* LPI2C5          41    */ \
840         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* LPI2C6          42    */ \
841         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPSPI1          43    */ \
842         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPSPI2          44    */ \
843         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPSPI3          45    */ \
844         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPSPI4          46    */ \
845         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5},  /* LPSPI5          47    */ \
846         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5},  /* LPSPI6          48    */ \
847         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* EMV1            49    */ \
848         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* EMV2            50    */ \
849         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET1           51    */ \
850         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET2           52    */ \
851         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_QOS        53    */ \
852         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_25M        54    */ \
853         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_TIMER1     55    */ \
854         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_TIMER2     56    */ \
855         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_TIMER3     57    */ \
856         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll1Div5, kCLOCK_ArmPllOut},   /* USDHC1          58    */ \
857         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll1Div5, kCLOCK_ArmPllOut},   /* USDHC2          59    */ \
858         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll2Pfd3}, /* ASRC            60    */ \
859         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll2Pfd3}, /* MQS             61    */ \
860         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5},  /* MIC             62    */ \
861         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll2Pfd3},  /* SPDIF           63    */ \
862         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd3}, /* SAI1            64    */ \
863         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd3}, /* SAI2            65    */ \
864         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd3}, /* SAI3            66    */ \
865         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5},  /* SAI4            67    */ \
866         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd1, kCLOCK_SysPll3Out, kCLOCK_VideoPllOut},   /* GC355           68    */ \
867         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut},  /* LCDIF           69    */ \
868         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut},  /* LCDIFV2         70    */ \
869         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut},  /* MIPI_REF        71    */ \
870         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut},  /* MIPI_ESC        72    */ \
871         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_VideoPllOut},  /* CSI2            73    */ \
872         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_VideoPllOut},  /* CSI2_ESC        74    */ \
873         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_VideoPllOut},  /* CSI2_UI         75    */ \
874         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd1, kCLOCK_VideoPllOut},  /* CSI             76    */ \
875         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Out, kCLOCK_SysPll3Pfd1, kCLOCK_SysPll1Div5},  /* CKO1            77    */ \
876         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd3, kCLOCK_OscRc48M, kCLOCK_SysPll3Pfd1, kCLOCK_AudioPllOut}     /* CKO2            78    */ \
877 };
878 /* clang-format on */
879 
880 /*!
881  * @brief Root clock index
882  *
883  */
884 typedef enum _clock_root
885 {
886     kCLOCK_Root_M7          = 0,  /*!< CLOCK Root M7. */
887     kCLOCK_Root_M4          = 1,  /*!< CLOCK Root M4. */
888     kCLOCK_Root_Bus         = 2,  /*!< CLOCK Root Bus. */
889     kCLOCK_Root_Bus_Lpsr    = 3,  /*!< CLOCK Root Bus Lpsr. */
890     kCLOCK_Root_Semc        = 4,  /*!< CLOCK Root Semc. */
891     kCLOCK_Root_Cssys       = 5,  /*!< CLOCK Root Cssys. */
892     kCLOCK_Root_Cstrace     = 6,  /*!< CLOCK Root Cstrace. */
893     kCLOCK_Root_M4_Systick  = 7,  /*!< CLOCK Root M4 Systick. */
894     kCLOCK_Root_M7_Systick  = 8,  /*!< CLOCK Root M7 Systick. */
895     kCLOCK_Root_Adc1        = 9,  /*!< CLOCK Root Adc1. */
896     kCLOCK_Root_Adc2        = 10, /*!< CLOCK Root Adc2. */
897     kCLOCK_Root_Acmp        = 11, /*!< CLOCK Root Acmp. */
898     kCLOCK_Root_Flexio1     = 12, /*!< CLOCK Root Flexio1. */
899     kCLOCK_Root_Flexio2     = 13, /*!< CLOCK Root Flexio2. */
900     kCLOCK_Root_Gpt1        = 14, /*!< CLOCK Root Gpt1. */
901     kCLOCK_Root_Gpt2        = 15, /*!< CLOCK Root Gpt2. */
902     kCLOCK_Root_Gpt3        = 16, /*!< CLOCK Root Gpt3. */
903     kCLOCK_Root_Gpt4        = 17, /*!< CLOCK Root Gpt4. */
904     kCLOCK_Root_Gpt5        = 18, /*!< CLOCK Root Gpt5. */
905     kCLOCK_Root_Gpt6        = 19, /*!< CLOCK Root Gpt6. */
906     kCLOCK_Root_Flexspi1    = 20, /*!< CLOCK Root Flexspi1. */
907     kCLOCK_Root_Flexspi2    = 21, /*!< CLOCK Root Flexspi2. */
908     kCLOCK_Root_Can1        = 22, /*!< CLOCK Root Can1. */
909     kCLOCK_Root_Can2        = 23, /*!< CLOCK Root Can2. */
910     kCLOCK_Root_Can3        = 24, /*!< CLOCK Root Can3. */
911     kCLOCK_Root_Lpuart1     = 25, /*!< CLOCK Root Lpuart1. */
912     kCLOCK_Root_Lpuart2     = 26, /*!< CLOCK Root Lpuart2. */
913     kCLOCK_Root_Lpuart3     = 27, /*!< CLOCK Root Lpuart3. */
914     kCLOCK_Root_Lpuart4     = 28, /*!< CLOCK Root Lpuart4. */
915     kCLOCK_Root_Lpuart5     = 29, /*!< CLOCK Root Lpuart5. */
916     kCLOCK_Root_Lpuart6     = 30, /*!< CLOCK Root Lpuart6. */
917     kCLOCK_Root_Lpuart7     = 31, /*!< CLOCK Root Lpuart7. */
918     kCLOCK_Root_Lpuart8     = 32, /*!< CLOCK Root Lpuart8. */
919     kCLOCK_Root_Lpuart9     = 33, /*!< CLOCK Root Lpuart9. */
920     kCLOCK_Root_Lpuart10    = 34, /*!< CLOCK Root Lpuart10. */
921     kCLOCK_Root_Lpuart11    = 35, /*!< CLOCK Root Lpuart11. */
922     kCLOCK_Root_Lpuart12    = 36, /*!< CLOCK Root Lpuart12. */
923     kCLOCK_Root_Lpi2c1      = 37, /*!< CLOCK Root Lpi2c1. */
924     kCLOCK_Root_Lpi2c2      = 38, /*!< CLOCK Root Lpi2c2. */
925     kCLOCK_Root_Lpi2c3      = 39, /*!< CLOCK Root Lpi2c3. */
926     kCLOCK_Root_Lpi2c4      = 40, /*!< CLOCK Root Lpi2c4. */
927     kCLOCK_Root_Lpi2c5      = 41, /*!< CLOCK Root Lpi2c5. */
928     kCLOCK_Root_Lpi2c6      = 42, /*!< CLOCK Root Lpi2c6. */
929     kCLOCK_Root_Lpspi1      = 43, /*!< CLOCK Root Lpspi1. */
930     kCLOCK_Root_Lpspi2      = 44, /*!< CLOCK Root Lpspi2. */
931     kCLOCK_Root_Lpspi3      = 45, /*!< CLOCK Root Lpspi3. */
932     kCLOCK_Root_Lpspi4      = 46, /*!< CLOCK Root Lpspi4. */
933     kCLOCK_Root_Lpspi5      = 47, /*!< CLOCK Root Lpspi5. */
934     kCLOCK_Root_Lpspi6      = 48, /*!< CLOCK Root Lpspi6. */
935     kCLOCK_Root_Emv1        = 49, /*!< CLOCK Root Emv1. */
936     kCLOCK_Root_Emv2        = 50, /*!< CLOCK Root Emv2. */
937     kCLOCK_Root_Enet1       = 51, /*!< CLOCK Root Enet1. */
938     kCLOCK_Root_Enet2       = 52, /*!< CLOCK Root Enet2. */
939     kCLOCK_Root_Enet_Qos    = 53, /*!< CLOCK Root Enet Qos. */
940     kCLOCK_Root_Enet_25m    = 54, /*!< CLOCK Root Enet 25M. */
941     kCLOCK_Root_Enet_Timer1 = 55, /*!< CLOCK Root Enet Timer1. */
942     kCLOCK_Root_Enet_Timer2 = 56, /*!< CLOCK Root Enet Timer2. */
943     kCLOCK_Root_Enet_Timer3 = 57, /*!< CLOCK Root Enet Timer3. */
944     kCLOCK_Root_Usdhc1      = 58, /*!< CLOCK Root Usdhc1. */
945     kCLOCK_Root_Usdhc2      = 59, /*!< CLOCK Root Usdhc2. */
946     kCLOCK_Root_Asrc        = 60, /*!< CLOCK Root Asrc. */
947     kCLOCK_Root_Mqs         = 61, /*!< CLOCK Root Mqs. */
948     kCLOCK_Root_Mic         = 62, /*!< CLOCK Root MIC. */
949     kCLOCK_Root_Spdif       = 63, /*!< CLOCK Root Spdif */
950     kCLOCK_Root_Sai1        = 64, /*!< CLOCK Root Sai1. */
951     kCLOCK_Root_Sai2        = 65, /*!< CLOCK Root Sai2. */
952     kCLOCK_Root_Sai3        = 66, /*!< CLOCK Root Sai3. */
953     kCLOCK_Root_Sai4        = 67, /*!< CLOCK Root Sai4. */
954     kCLOCK_Root_Gc355       = 68, /*!< CLOCK Root Gc355. */
955     kCLOCK_Root_Lcdif       = 69, /*!< CLOCK Root Lcdif. */
956     kCLOCK_Root_Lcdifv2     = 70, /*!< CLOCK Root Lcdifv2. */
957     kCLOCK_Root_Mipi_Ref    = 71, /*!< CLOCK Root Mipi Ref. */
958     kCLOCK_Root_Mipi_Esc    = 72, /*!< CLOCK Root Mipi Esc. */
959     kCLOCK_Root_Csi2        = 73, /*!< CLOCK Root Csi2. */
960     kCLOCK_Root_Csi2_Esc    = 74, /*!< CLOCK Root Csi2 Esc. */
961     kCLOCK_Root_Csi2_Ui     = 75, /*!< CLOCK Root Csi2 Ui. */
962     kCLOCK_Root_Csi         = 76, /*!< CLOCK Root Csi. */
963     kCLOCK_Root_Cko1        = 77, /*!< CLOCK Root CKo1. */
964     kCLOCK_Root_Cko2        = 78, /*!< CLOCK Root CKo2. */
965 } clock_root_t;
966 
967 /*!
968  * @brief The enumerator of clock roots' clock source mux value.
969  */
970 typedef enum _clock_root_mux_source
971 {
972     /* M7 */
973     kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M7 mux from MuxOscRc48MDiv2. */
974     kCLOCK_M7_ClockRoot_MuxOsc24MOut    = 1U, /*!< M7 mux from MuxOsc24MOut. */
975     kCLOCK_M7_ClockRoot_MuxOscRc400M    = 2U, /*!< M7 mux from MuxOscRc400M. */
976     kCLOCK_M7_ClockRoot_MuxOscRc16M     = 3U, /*!< M7 mux from MuxOscRc16M. */
977     kCLOCK_M7_ClockRoot_MuxArmPllOut    = 4U, /*!< M7 mux from MuxArmPllOut. */
978     kCLOCK_M7_ClockRoot_MuxSysPll1Out   = 5U, /*!< M7 mux from MuxSysPll1Out. */
979     kCLOCK_M7_ClockRoot_MuxSysPll3Out   = 6U, /*!< M7 mux from MuxSysPll3Out. */
980     kCLOCK_M7_ClockRoot_MuxVideoPllOut  = 7U, /*!< M7 mux from MuxVideoPllOut. */
981 
982     /* M4 */
983     kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M4 mux from MuxOscRc48MDiv2. */
984     kCLOCK_M4_ClockRoot_MuxOsc24MOut    = 1U, /*!< M4 mux from MuxOsc24MOut. */
985     kCLOCK_M4_ClockRoot_MuxOscRc400M    = 2U, /*!< M4 mux from MuxOscRc400M. */
986     kCLOCK_M4_ClockRoot_MuxOscRc16M     = 3U, /*!< M4 mux from MuxOscRc16M. */
987     kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< M4 mux from MuxSysPll3Pfd3. */
988     kCLOCK_M4_ClockRoot_MuxSysPll3Out   = 5U, /*!< M4 mux from MuxSysPll3Out. */
989     kCLOCK_M4_ClockRoot_MuxSysPll2Out   = 6U, /*!< M4 mux from MuxSysPll2Out. */
990     kCLOCK_M4_ClockRoot_MuxSysPll1Div5  = 7U, /*!< M4 mux from MuxSysPll1Div5. */
991 
992     /* BUS */
993     kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< BUS mux from MuxOscRc48MDiv2. */
994     kCLOCK_BUS_ClockRoot_MuxOsc24MOut    = 1U, /*!< BUS mux from MuxOsc24MOut. */
995     kCLOCK_BUS_ClockRoot_MuxOscRc400M    = 2U, /*!< BUS mux from MuxOscRc400M. */
996     kCLOCK_BUS_ClockRoot_MuxOscRc16M     = 3U, /*!< BUS mux from MuxOscRc16M. */
997     kCLOCK_BUS_ClockRoot_MuxSysPll3Out   = 4U, /*!< BUS mux from MuxSysPll3Out. */
998     kCLOCK_BUS_ClockRoot_MuxSysPll1Div5  = 5U, /*!< BUS mux from MuxSysPll1Div5. */
999     kCLOCK_BUS_ClockRoot_MuxSysPll2Out   = 6U, /*!< BUS mux from MuxSysPll2Out. */
1000     kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< BUS mux from MuxSysPll2Pfd3. */
1001 
1002     /* BUS_LPSR */
1003     kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< BUS_LPSR mux from MuxOscRc48MDiv2. */
1004     kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut    = 1U, /*!< BUS_LPSR mux from MuxOsc24MOut. */
1005     kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M    = 2U, /*!< BUS_LPSR mux from MuxOscRc400M. */
1006     kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M     = 3U, /*!< BUS_LPSR mux from MuxOscRc16M. */
1007     kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< BUS_LPSR mux from MuxSysPll3Pfd3. */
1008     kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out   = 5U, /*!< BUS_LPSR mux from MuxSysPll3Out. */
1009     kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out   = 6U, /*!< BUS_LPSR mux from MuxSysPll2Out. */
1010     kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5  = 7U, /*!< BUS_LPSR mux from MuxSysPll1Div5. */
1011 
1012     /* SEMC */
1013     kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SEMC mux from MuxOscRc48MDiv2. */
1014     kCLOCK_SEMC_ClockRoot_MuxOsc24MOut    = 1U, /*!< SEMC mux from MuxOsc24MOut. */
1015     kCLOCK_SEMC_ClockRoot_MuxOscRc400M    = 2U, /*!< SEMC mux from MuxOscRc400M. */
1016     kCLOCK_SEMC_ClockRoot_MuxOscRc16M     = 3U, /*!< SEMC mux from MuxOscRc16M. */
1017     kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5  = 4U, /*!< SEMC mux from MuxSysPll1Div5. */
1018     kCLOCK_SEMC_ClockRoot_MuxSysPll2Out   = 5U, /*!< SEMC mux from MuxSysPll2Out. */
1019     kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1  = 6U, /*!< SEMC mux from MuxSysPll2Pfd1. */
1020     kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0  = 7U, /*!< SEMC mux from MuxSysPll3Pfd0. */
1021 
1022     /* CSSYS */
1023     kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSSYS mux from MuxOscRc48MDiv2. */
1024     kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSSYS mux from MuxOsc24MOut. */
1025     kCLOCK_CSSYS_ClockRoot_MuxOscRc400M    = 2U, /*!< CSSYS mux from MuxOscRc400M. */
1026     kCLOCK_CSSYS_ClockRoot_MuxOscRc16M     = 3U, /*!< CSSYS mux from MuxOscRc16M. */
1027     kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2  = 4U, /*!< CSSYS mux from MuxSysPll3Div2. */
1028     kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5  = 5U, /*!< CSSYS mux from MuxSysPll1Div5. */
1029     kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out   = 6U, /*!< CSSYS mux from MuxSysPll2Out. */
1030     kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< CSSYS mux from MuxSysPll2Pfd3. */
1031 
1032     /* CSTRACE */
1033     kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSTRACE mux from MuxOscRc48MDiv2. */
1034     kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSTRACE mux from MuxOsc24MOut. */
1035     kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M    = 2U, /*!< CSTRACE mux from MuxOscRc400M. */
1036     kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M     = 3U, /*!< CSTRACE mux from MuxOscRc16M. */
1037     kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2  = 4U, /*!< CSTRACE mux from MuxSysPll3Div2. */
1038     kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5  = 5U, /*!< CSTRACE mux from MuxSysPll1Div5. */
1039     kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1  = 6U, /*!< CSTRACE mux from MuxSysPll2Pfd1. */
1040     kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out   = 7U, /*!< CSTRACE mux from MuxSysPll2Out. */
1041 
1042     /* M4_SYSTICK */
1043     kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M4_SYSTICK mux from MuxOscRc48MDiv2. */
1044     kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut    = 1U, /*!< M4_SYSTICK mux from MuxOsc24MOut. */
1045     kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M    = 2U, /*!< M4_SYSTICK mux from MuxOscRc400M. */
1046     kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M     = 3U, /*!< M4_SYSTICK mux from MuxOscRc16M. */
1047     kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< M4_SYSTICK mux from MuxSysPll3Pfd3. */
1048     kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out   = 5U, /*!< M4_SYSTICK mux from MuxSysPll3Out. */
1049     kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0  = 6U, /*!< M4_SYSTICK mux from MuxSysPll2Pfd0. */
1050     kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5  = 7U, /*!< M4_SYSTICK mux from MuxSysPll1Div5. */
1051 
1052     /* M7_SYSTICK */
1053     kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M7_SYSTICK mux from MuxOscRc48MDiv2. */
1054     kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut    = 1U, /*!< M7_SYSTICK mux from MuxOsc24MOut. */
1055     kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M    = 2U, /*!< M7_SYSTICK mux from MuxOscRc400M. */
1056     kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M     = 3U, /*!< M7_SYSTICK mux from MuxOscRc16M. */
1057     kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out   = 4U, /*!< M7_SYSTICK mux from MuxSysPll2Out. */
1058     kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2  = 5U, /*!< M7_SYSTICK mux from MuxSysPll3Div2. */
1059     kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5  = 6U, /*!< M7_SYSTICK mux from MuxSysPll1Div5. */
1060     kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0  = 7U, /*!< M7_SYSTICK mux from MuxSysPll2Pfd0. */
1061 
1062     /* ADC1 */
1063     kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ADC1 mux from MuxOscRc48MDiv2. */
1064     kCLOCK_ADC1_ClockRoot_MuxOsc24MOut    = 1U, /*!< ADC1 mux from MuxOsc24MOut. */
1065     kCLOCK_ADC1_ClockRoot_MuxOscRc400M    = 2U, /*!< ADC1 mux from MuxOscRc400M. */
1066     kCLOCK_ADC1_ClockRoot_MuxOscRc16M     = 3U, /*!< ADC1 mux from MuxOscRc16M. */
1067     kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< ADC1 mux from MuxSysPll3Div2. */
1068     kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< ADC1 mux from MuxSysPll1Div5. */
1069     kCLOCK_ADC1_ClockRoot_MuxSysPll2Out   = 6U, /*!< ADC1 mux from MuxSysPll2Out. */
1070     kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< ADC1 mux from MuxSysPll2Pfd3. */
1071 
1072     /* ADC2 */
1073     kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ADC2 mux from MuxOscRc48MDiv2. */
1074     kCLOCK_ADC2_ClockRoot_MuxOsc24MOut    = 1U, /*!< ADC2 mux from MuxOsc24MOut. */
1075     kCLOCK_ADC2_ClockRoot_MuxOscRc400M    = 2U, /*!< ADC2 mux from MuxOscRc400M. */
1076     kCLOCK_ADC2_ClockRoot_MuxOscRc16M     = 3U, /*!< ADC2 mux from MuxOscRc16M. */
1077     kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< ADC2 mux from MuxSysPll3Div2. */
1078     kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< ADC2 mux from MuxSysPll1Div5. */
1079     kCLOCK_ADC2_ClockRoot_MuxSysPll2Out   = 6U, /*!< ADC2 mux from MuxSysPll2Out. */
1080     kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< ADC2 mux from MuxSysPll2Pfd3. */
1081 
1082     /* ACMP */
1083     kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ACMP mux from MuxOscRc48MDiv2. */
1084     kCLOCK_ACMP_ClockRoot_MuxOsc24MOut    = 1U, /*!< ACMP mux from MuxOsc24MOut. */
1085     kCLOCK_ACMP_ClockRoot_MuxOscRc400M    = 2U, /*!< ACMP mux from MuxOscRc400M. */
1086     kCLOCK_ACMP_ClockRoot_MuxOscRc16M     = 3U, /*!< ACMP mux from MuxOscRc16M. */
1087     kCLOCK_ACMP_ClockRoot_MuxSysPll3Out   = 4U, /*!< ACMP mux from MuxSysPll3Out. */
1088     kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5  = 5U, /*!< ACMP mux from MuxSysPll1Div5. */
1089     kCLOCK_ACMP_ClockRoot_MuxAudioPllOut  = 6U, /*!< ACMP mux from MuxAudioPllOut. */
1090     kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< ACMP mux from MuxSysPll2Pfd3. */
1091 
1092     /* FLEXIO1 */
1093     kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXIO1 mux from MuxOscRc48MDiv2. */
1094     kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut    = 1U, /*!< FLEXIO1 mux from MuxOsc24MOut. */
1095     kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M    = 2U, /*!< FLEXIO1 mux from MuxOscRc400M. */
1096     kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M     = 3U, /*!< FLEXIO1 mux from MuxOscRc16M. */
1097     kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< FLEXIO1 mux from MuxSysPll3Div2. */
1098     kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< FLEXIO1 mux from MuxSysPll1Div5. */
1099     kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out   = 6U, /*!< FLEXIO1 mux from MuxSysPll2Out. */
1100     kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< FLEXIO1 mux from MuxSysPll2Pfd3. */
1101 
1102     /* FLEXIO2 */
1103     kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXIO2 mux from MuxOscRc48MDiv2. */
1104     kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut    = 1U, /*!< FLEXIO2 mux from MuxOsc24MOut. */
1105     kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M    = 2U, /*!< FLEXIO2 mux from MuxOscRc400M. */
1106     kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M     = 3U, /*!< FLEXIO2 mux from MuxOscRc16M. */
1107     kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< FLEXIO2 mux from MuxSysPll3Div2. */
1108     kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< FLEXIO2 mux from MuxSysPll1Div5. */
1109     kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out   = 6U, /*!< FLEXIO2 mux from MuxSysPll2Out. */
1110     kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< FLEXIO2 mux from MuxSysPll2Pfd3. */
1111 
1112     /* GPT1 */
1113     kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT1 mux from MuxOscRc48MDiv2. */
1114     kCLOCK_GPT1_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT1 mux from MuxOsc24MOut. */
1115     kCLOCK_GPT1_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT1 mux from MuxOscRc400M. */
1116     kCLOCK_GPT1_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT1 mux from MuxOscRc16M. */
1117     kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT1 mux from MuxSysPll3Div2. */
1118     kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT1 mux from MuxSysPll1Div5. */
1119     kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< GPT1 mux from MuxSysPll3Pfd2. */
1120     kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3  = 7U, /*!< GPT1 mux from MuxSysPll3Pfd3. */
1121 
1122     /* GPT2 */
1123     kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT2 mux from MuxOscRc48MDiv2. */
1124     kCLOCK_GPT2_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT2 mux from MuxOsc24MOut. */
1125     kCLOCK_GPT2_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT2 mux from MuxOscRc400M. */
1126     kCLOCK_GPT2_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT2 mux from MuxOscRc16M. */
1127     kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT2 mux from MuxSysPll3Div2. */
1128     kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT2 mux from MuxSysPll1Div5. */
1129     kCLOCK_GPT2_ClockRoot_MuxAudioPllOut  = 6U, /*!< GPT2 mux from MuxAudioPllOut. */
1130     kCLOCK_GPT2_ClockRoot_MuxVideoPllOut  = 7U, /*!< GPT2 mux from MuxVideoPllOut. */
1131 
1132     /* GPT3 */
1133     kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT3 mux from MuxOscRc48MDiv2. */
1134     kCLOCK_GPT3_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT3 mux from MuxOsc24MOut. */
1135     kCLOCK_GPT3_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT3 mux from MuxOscRc400M. */
1136     kCLOCK_GPT3_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT3 mux from MuxOscRc16M. */
1137     kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT3 mux from MuxSysPll3Div2. */
1138     kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT3 mux from MuxSysPll1Div5. */
1139     kCLOCK_GPT3_ClockRoot_MuxAudioPllOut  = 6U, /*!< GPT3 mux from MuxAudioPllOut. */
1140     kCLOCK_GPT3_ClockRoot_MuxVideoPllOut  = 7U, /*!< GPT3 mux from MuxVideoPllOut. */
1141 
1142     /* GPT4 */
1143     kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT4 mux from MuxOscRc48MDiv2. */
1144     kCLOCK_GPT4_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT4 mux from MuxOsc24MOut. */
1145     kCLOCK_GPT4_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT4 mux from MuxOscRc400M. */
1146     kCLOCK_GPT4_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT4 mux from MuxOscRc16M. */
1147     kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT4 mux from MuxSysPll3Div2. */
1148     kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT4 mux from MuxSysPll1Div5. */
1149     kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< GPT4 mux from MuxSysPll3Pfd2. */
1150     kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3  = 7U, /*!< GPT4 mux from MuxSysPll3Pfd3. */
1151 
1152     /* GPT5 */
1153     kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT5 mux from MuxOscRc48MDiv2. */
1154     kCLOCK_GPT5_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT5 mux from MuxOsc24MOut. */
1155     kCLOCK_GPT5_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT5 mux from MuxOscRc400M. */
1156     kCLOCK_GPT5_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT5 mux from MuxOscRc16M. */
1157     kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT5 mux from MuxSysPll3Div2. */
1158     kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT5 mux from MuxSysPll1Div5. */
1159     kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< GPT5 mux from MuxSysPll3Pfd2. */
1160     kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3  = 7U, /*!< GPT5 mux from MuxSysPll3Pfd3. */
1161 
1162     /* GPT6 */
1163     kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT6 mux from MuxOscRc48MDiv2. */
1164     kCLOCK_GPT6_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT6 mux from MuxOsc24MOut. */
1165     kCLOCK_GPT6_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT6 mux from MuxOscRc400M. */
1166     kCLOCK_GPT6_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT6 mux from MuxOscRc16M. */
1167     kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT6 mux from MuxSysPll3Div2. */
1168     kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT6 mux from MuxSysPll1Div5. */
1169     kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< GPT6 mux from MuxSysPll3Pfd2. */
1170     kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3  = 7U, /*!< GPT6 mux from MuxSysPll3Pfd3. */
1171 
1172     /* FLEXSPI1 */
1173     kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXSPI1 mux from MuxOscRc48MDiv2. */
1174     kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut    = 1U, /*!< FLEXSPI1 mux from MuxOsc24MOut. */
1175     kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M    = 2U, /*!< FLEXSPI1 mux from MuxOscRc400M. */
1176     kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M     = 3U, /*!< FLEXSPI1 mux from MuxOscRc16M. */
1177     kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0  = 4U, /*!< FLEXSPI1 mux from MuxSysPll3Pfd0. */
1178     kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out   = 5U, /*!< FLEXSPI1 mux from MuxSysPll2Out. */
1179     kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2  = 6U, /*!< FLEXSPI1 mux from MuxSysPll2Pfd2. */
1180     kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out   = 7U, /*!< FLEXSPI1 mux from MuxSysPll3Out. */
1181 
1182     /* FLEXSPI2 */
1183     kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXSPI2 mux from MuxOscRc48MDiv2. */
1184     kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut    = 1U, /*!< FLEXSPI2 mux from MuxOsc24MOut. */
1185     kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M    = 2U, /*!< FLEXSPI2 mux from MuxOscRc400M. */
1186     kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M     = 3U, /*!< FLEXSPI2 mux from MuxOscRc16M. */
1187     kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0  = 4U, /*!< FLEXSPI2 mux from MuxSysPll3Pfd0. */
1188     kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out   = 5U, /*!< FLEXSPI2 mux from MuxSysPll2Out. */
1189     kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2  = 6U, /*!< FLEXSPI2 mux from MuxSysPll2Pfd2. */
1190     kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out   = 7U, /*!< FLEXSPI2 mux from MuxSysPll3Out. */
1191 
1192     /* CAN1 */
1193     kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CAN1 mux from MuxOscRc48MDiv2. */
1194     kCLOCK_CAN1_ClockRoot_MuxOsc24MOut    = 1U, /*!< CAN1 mux from MuxOsc24MOut. */
1195     kCLOCK_CAN1_ClockRoot_MuxOscRc400M    = 2U, /*!< CAN1 mux from MuxOscRc400M. */
1196     kCLOCK_CAN1_ClockRoot_MuxOscRc16M     = 3U, /*!< CAN1 mux from MuxOscRc16M. */
1197     kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< CAN1 mux from MuxSysPll3Div2. */
1198     kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< CAN1 mux from MuxSysPll1Div5. */
1199     kCLOCK_CAN1_ClockRoot_MuxSysPll2Out   = 6U, /*!< CAN1 mux from MuxSysPll2Out. */
1200     kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< CAN1 mux from MuxSysPll2Pfd3. */
1201 
1202     /* CAN2 */
1203     kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CAN2 mux from MuxOscRc48MDiv2. */
1204     kCLOCK_CAN2_ClockRoot_MuxOsc24MOut    = 1U, /*!< CAN2 mux from MuxOsc24MOut. */
1205     kCLOCK_CAN2_ClockRoot_MuxOscRc400M    = 2U, /*!< CAN2 mux from MuxOscRc400M. */
1206     kCLOCK_CAN2_ClockRoot_MuxOscRc16M     = 3U, /*!< CAN2 mux from MuxOscRc16M. */
1207     kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< CAN2 mux from MuxSysPll3Div2. */
1208     kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< CAN2 mux from MuxSysPll1Div5. */
1209     kCLOCK_CAN2_ClockRoot_MuxSysPll2Out   = 6U, /*!< CAN2 mux from MuxSysPll2Out. */
1210     kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< CAN2 mux from MuxSysPll2Pfd3. */
1211 
1212     /* CAN3 */
1213     kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CAN3 mux from MuxOscRc48MDiv2. */
1214     kCLOCK_CAN3_ClockRoot_MuxOsc24MOut    = 1U, /*!< CAN3 mux from MuxOsc24MOut. */
1215     kCLOCK_CAN3_ClockRoot_MuxOscRc400M    = 2U, /*!< CAN3 mux from MuxOscRc400M. */
1216     kCLOCK_CAN3_ClockRoot_MuxOscRc16M     = 3U, /*!< CAN3 mux from MuxOscRc16M. */
1217     kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< CAN3 mux from MuxSysPll3Pfd3. */
1218     kCLOCK_CAN3_ClockRoot_MuxSysPll3Out   = 5U, /*!< CAN3 mux from MuxSysPll3Out. */
1219     kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< CAN3 mux from MuxSysPll2Pfd3. */
1220     kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5  = 7U, /*!< CAN3 mux from MuxSysPll1Div5. */
1221 
1222     /* LPUART1 */
1223     kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART1 mux from MuxOscRc48MDiv2. */
1224     kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART1 mux from MuxOsc24MOut. */
1225     kCLOCK_LPUART1_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART1 mux from MuxOscRc400M. */
1226     kCLOCK_LPUART1_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART1 mux from MuxOscRc16M. */
1227     kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART1 mux from MuxSysPll3Div2. */
1228     kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART1 mux from MuxSysPll1Div5. */
1229     kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART1 mux from MuxSysPll2Out. */
1230     kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART1 mux from MuxSysPll2Pfd3. */
1231 
1232     /* LPUART2 */
1233     kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART2 mux from MuxOscRc48MDiv2. */
1234     kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART2 mux from MuxOsc24MOut. */
1235     kCLOCK_LPUART2_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART2 mux from MuxOscRc400M. */
1236     kCLOCK_LPUART2_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART2 mux from MuxOscRc16M. */
1237     kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART2 mux from MuxSysPll3Div2. */
1238     kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART2 mux from MuxSysPll1Div5. */
1239     kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART2 mux from MuxSysPll2Out. */
1240     kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART2 mux from MuxSysPll2Pfd3. */
1241 
1242     /* LPUART3 */
1243     kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART3 mux from MuxOscRc48MDiv2. */
1244     kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART3 mux from MuxOsc24MOut. */
1245     kCLOCK_LPUART3_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART3 mux from MuxOscRc400M. */
1246     kCLOCK_LPUART3_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART3 mux from MuxOscRc16M. */
1247     kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART3 mux from MuxSysPll3Div2. */
1248     kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART3 mux from MuxSysPll1Div5. */
1249     kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART3 mux from MuxSysPll2Out. */
1250     kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART3 mux from MuxSysPll2Pfd3. */
1251 
1252     /* LPUART4 */
1253     kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART4 mux from MuxOscRc48MDiv2. */
1254     kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART4 mux from MuxOsc24MOut. */
1255     kCLOCK_LPUART4_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART4 mux from MuxOscRc400M. */
1256     kCLOCK_LPUART4_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART4 mux from MuxOscRc16M. */
1257     kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART4 mux from MuxSysPll3Div2. */
1258     kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART4 mux from MuxSysPll1Div5. */
1259     kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART4 mux from MuxSysPll2Out. */
1260     kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART4 mux from MuxSysPll2Pfd3. */
1261 
1262     /* LPUART5 */
1263     kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART5 mux from MuxOscRc48MDiv2. */
1264     kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART5 mux from MuxOsc24MOut. */
1265     kCLOCK_LPUART5_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART5 mux from MuxOscRc400M. */
1266     kCLOCK_LPUART5_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART5 mux from MuxOscRc16M. */
1267     kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART5 mux from MuxSysPll3Div2. */
1268     kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART5 mux from MuxSysPll1Div5. */
1269     kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART5 mux from MuxSysPll2Out. */
1270     kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART5 mux from MuxSysPll2Pfd3. */
1271 
1272     /* LPUART6 */
1273     kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART6 mux from MuxOscRc48MDiv2. */
1274     kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART6 mux from MuxOsc24MOut. */
1275     kCLOCK_LPUART6_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART6 mux from MuxOscRc400M. */
1276     kCLOCK_LPUART6_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART6 mux from MuxOscRc16M. */
1277     kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART6 mux from MuxSysPll3Div2. */
1278     kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART6 mux from MuxSysPll1Div5. */
1279     kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART6 mux from MuxSysPll2Out. */
1280     kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART6 mux from MuxSysPll2Pfd3. */
1281 
1282     /* LPUART7 */
1283     kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART7 mux from MuxOscRc48MDiv2. */
1284     kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART7 mux from MuxOsc24MOut. */
1285     kCLOCK_LPUART7_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART7 mux from MuxOscRc400M. */
1286     kCLOCK_LPUART7_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART7 mux from MuxOscRc16M. */
1287     kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART7 mux from MuxSysPll3Div2. */
1288     kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART7 mux from MuxSysPll1Div5. */
1289     kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART7 mux from MuxSysPll2Out. */
1290     kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART7 mux from MuxSysPll2Pfd3. */
1291 
1292     /* LPUART8 */
1293     kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART8 mux from MuxOscRc48MDiv2. */
1294     kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART8 mux from MuxOsc24MOut. */
1295     kCLOCK_LPUART8_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART8 mux from MuxOscRc400M. */
1296     kCLOCK_LPUART8_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART8 mux from MuxOscRc16M. */
1297     kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART8 mux from MuxSysPll3Div2. */
1298     kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART8 mux from MuxSysPll1Div5. */
1299     kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART8 mux from MuxSysPll2Out. */
1300     kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART8 mux from MuxSysPll2Pfd3. */
1301 
1302     /* LPUART9 */
1303     kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART9 mux from MuxOscRc48MDiv2. */
1304     kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART9 mux from MuxOsc24MOut. */
1305     kCLOCK_LPUART9_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART9 mux from MuxOscRc400M. */
1306     kCLOCK_LPUART9_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART9 mux from MuxOscRc16M. */
1307     kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART9 mux from MuxSysPll3Div2. */
1308     kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART9 mux from MuxSysPll1Div5. */
1309     kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART9 mux from MuxSysPll2Out. */
1310     kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART9 mux from MuxSysPll2Pfd3. */
1311 
1312     /* LPUART10 */
1313     kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART10 mux from MuxOscRc48MDiv2. */
1314     kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART10 mux from MuxOsc24MOut. */
1315     kCLOCK_LPUART10_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART10 mux from MuxOscRc400M. */
1316     kCLOCK_LPUART10_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART10 mux from MuxOscRc16M. */
1317     kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART10 mux from MuxSysPll3Div2. */
1318     kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART10 mux from MuxSysPll1Div5. */
1319     kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART10 mux from MuxSysPll2Out. */
1320     kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART10 mux from MuxSysPll2Pfd3. */
1321 
1322     /* LPUART11 */
1323     kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART11 mux from MuxOscRc48MDiv2. */
1324     kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART11 mux from MuxOsc24MOut. */
1325     kCLOCK_LPUART11_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART11 mux from MuxOscRc400M. */
1326     kCLOCK_LPUART11_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART11 mux from MuxOscRc16M. */
1327     kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPUART11 mux from MuxSysPll3Pfd3. */
1328     kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPUART11 mux from MuxSysPll3Out. */
1329     kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< LPUART11 mux from MuxSysPll2Pfd3. */
1330     kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPUART11 mux from MuxSysPll1Div5. */
1331 
1332     /* LPUART12 */
1333     kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART12 mux from MuxOscRc48MDiv2. */
1334     kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART12 mux from MuxOsc24MOut. */
1335     kCLOCK_LPUART12_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART12 mux from MuxOscRc400M. */
1336     kCLOCK_LPUART12_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART12 mux from MuxOscRc16M. */
1337     kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPUART12 mux from MuxSysPll3Pfd3. */
1338     kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPUART12 mux from MuxSysPll3Out. */
1339     kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< LPUART12 mux from MuxSysPll2Pfd3. */
1340     kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPUART12 mux from MuxSysPll1Div5. */
1341 
1342     /* LPI2C1 */
1343     kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C1 mux from MuxOscRc48MDiv2. */
1344     kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C1 mux from MuxOsc24MOut. */
1345     kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C1 mux from MuxOscRc400M. */
1346     kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C1 mux from MuxOscRc16M. */
1347     kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPI2C1 mux from MuxSysPll3Div2. */
1348     kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPI2C1 mux from MuxSysPll1Div5. */
1349     kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPI2C1 mux from MuxSysPll2Out. */
1350     kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPI2C1 mux from MuxSysPll2Pfd3. */
1351 
1352     /* LPI2C2 */
1353     kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C2 mux from MuxOscRc48MDiv2. */
1354     kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C2 mux from MuxOsc24MOut. */
1355     kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C2 mux from MuxOscRc400M. */
1356     kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C2 mux from MuxOscRc16M. */
1357     kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPI2C2 mux from MuxSysPll3Div2. */
1358     kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPI2C2 mux from MuxSysPll1Div5. */
1359     kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPI2C2 mux from MuxSysPll2Out. */
1360     kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPI2C2 mux from MuxSysPll2Pfd3. */
1361 
1362     /* LPI2C3 */
1363     kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C3 mux from MuxOscRc48MDiv2. */
1364     kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C3 mux from MuxOsc24MOut. */
1365     kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C3 mux from MuxOscRc400M. */
1366     kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C3 mux from MuxOscRc16M. */
1367     kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPI2C3 mux from MuxSysPll3Div2. */
1368     kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPI2C3 mux from MuxSysPll1Div5. */
1369     kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPI2C3 mux from MuxSysPll2Out. */
1370     kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPI2C3 mux from MuxSysPll2Pfd3. */
1371 
1372     /* LPI2C4 */
1373     kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C4 mux from MuxOscRc48MDiv2. */
1374     kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C4 mux from MuxOsc24MOut. */
1375     kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C4 mux from MuxOscRc400M. */
1376     kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C4 mux from MuxOscRc16M. */
1377     kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPI2C4 mux from MuxSysPll3Div2. */
1378     kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPI2C4 mux from MuxSysPll1Div5. */
1379     kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPI2C4 mux from MuxSysPll2Out. */
1380     kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPI2C4 mux from MuxSysPll2Pfd3. */
1381 
1382     /* LPI2C5 */
1383     kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C5 mux from MuxOscRc48MDiv2. */
1384     kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C5 mux from MuxOsc24MOut. */
1385     kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C5 mux from MuxOscRc400M. */
1386     kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C5 mux from MuxOscRc16M. */
1387     kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPI2C5 mux from MuxSysPll3Pfd3. */
1388     kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPI2C5 mux from MuxSysPll3Out. */
1389     kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< LPI2C5 mux from MuxSysPll2Pfd3. */
1390     kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPI2C5 mux from MuxSysPll1Div5. */
1391 
1392     /* LPI2C6 */
1393     kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C6 mux from MuxOscRc48MDiv2. */
1394     kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C6 mux from MuxOsc24MOut. */
1395     kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C6 mux from MuxOscRc400M. */
1396     kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C6 mux from MuxOscRc16M. */
1397     kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPI2C6 mux from MuxSysPll3Pfd3. */
1398     kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPI2C6 mux from MuxSysPll3Out. */
1399     kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< LPI2C6 mux from MuxSysPll2Pfd3. */
1400     kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPI2C6 mux from MuxSysPll1Div5. */
1401 
1402     /* LPSPI1 */
1403     kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI1 mux from MuxOscRc48MDiv2. */
1404     kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI1 mux from MuxOsc24MOut. */
1405     kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI1 mux from MuxOscRc400M. */
1406     kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI1 mux from MuxOscRc16M. */
1407     kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2  = 4U, /*!< LPSPI1 mux from MuxSysPll3Pfd2. */
1408     kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPSPI1 mux from MuxSysPll1Div5. */
1409     kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPSPI1 mux from MuxSysPll2Out. */
1410     kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPSPI1 mux from MuxSysPll2Pfd3. */
1411 
1412     /* LPSPI2 */
1413     kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI2 mux from MuxOscRc48MDiv2. */
1414     kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI2 mux from MuxOsc24MOut. */
1415     kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI2 mux from MuxOscRc400M. */
1416     kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI2 mux from MuxOscRc16M. */
1417     kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2  = 4U, /*!< LPSPI2 mux from MuxSysPll3Pfd2. */
1418     kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPSPI2 mux from MuxSysPll1Div5. */
1419     kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPSPI2 mux from MuxSysPll2Out. */
1420     kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPSPI2 mux from MuxSysPll2Pfd3. */
1421 
1422     /* LPSPI3 */
1423     kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI3 mux from MuxOscRc48MDiv2. */
1424     kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI3 mux from MuxOsc24MOut. */
1425     kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI3 mux from MuxOscRc400M. */
1426     kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI3 mux from MuxOscRc16M. */
1427     kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2  = 4U, /*!< LPSPI3 mux from MuxSysPll3Pfd2. */
1428     kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPSPI3 mux from MuxSysPll1Div5. */
1429     kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPSPI3 mux from MuxSysPll2Out. */
1430     kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPSPI3 mux from MuxSysPll2Pfd3. */
1431 
1432     /* LPSPI4 */
1433     kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI4 mux from MuxOscRc48MDiv2. */
1434     kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI4 mux from MuxOsc24MOut. */
1435     kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI4 mux from MuxOscRc400M. */
1436     kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI4 mux from MuxOscRc16M. */
1437     kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2  = 4U, /*!< LPSPI4 mux from MuxSysPll3Pfd2. */
1438     kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPSPI4 mux from MuxSysPll1Div5. */
1439     kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPSPI4 mux from MuxSysPll2Out. */
1440     kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPSPI4 mux from MuxSysPll2Pfd3. */
1441 
1442     /* LPSPI5 */
1443     kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI5 mux from MuxOscRc48MDiv2. */
1444     kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI5 mux from MuxOsc24MOut. */
1445     kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI5 mux from MuxOscRc400M. */
1446     kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI5 mux from MuxOscRc16M. */
1447     kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPSPI5 mux from MuxSysPll3Pfd3. */
1448     kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPSPI5 mux from MuxSysPll3Out. */
1449     kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< LPSPI5 mux from MuxSysPll3Pfd2. */
1450     kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPSPI5 mux from MuxSysPll1Div5. */
1451 
1452     /* LPSPI6 */
1453     kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI6 mux from MuxOscRc48MDiv2. */
1454     kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI6 mux from MuxOsc24MOut. */
1455     kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI6 mux from MuxOscRc400M. */
1456     kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI6 mux from MuxOscRc16M. */
1457     kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPSPI6 mux from MuxSysPll3Pfd3. */
1458     kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPSPI6 mux from MuxSysPll3Out. */
1459     kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< LPSPI6 mux from MuxSysPll3Pfd2. */
1460     kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPSPI6 mux from MuxSysPll1Div5. */
1461 
1462     /* EMV1 */
1463     kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< EMV1 mux from MuxOscRc48MDiv2. */
1464     kCLOCK_EMV1_ClockRoot_MuxOsc24MOut    = 1U, /*!< EMV1 mux from MuxOsc24MOut. */
1465     kCLOCK_EMV1_ClockRoot_MuxOscRc400M    = 2U, /*!< EMV1 mux from MuxOscRc400M. */
1466     kCLOCK_EMV1_ClockRoot_MuxOscRc16M     = 3U, /*!< EMV1 mux from MuxOscRc16M. */
1467     kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< EMV1 mux from MuxSysPll3Div2. */
1468     kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< EMV1 mux from MuxSysPll1Div5. */
1469     kCLOCK_EMV1_ClockRoot_MuxSysPll2Out   = 6U, /*!< EMV1 mux from MuxSysPll2Out. */
1470     kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< EMV1 mux from MuxSysPll2Pfd3. */
1471 
1472     /* EMV2 */
1473     kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< EMV2 mux from MuxOscRc48MDiv2. */
1474     kCLOCK_EMV2_ClockRoot_MuxOsc24MOut    = 1U, /*!< EMV2 mux from MuxOsc24MOut. */
1475     kCLOCK_EMV2_ClockRoot_MuxOscRc400M    = 2U, /*!< EMV2 mux from MuxOscRc400M. */
1476     kCLOCK_EMV2_ClockRoot_MuxOscRc16M     = 3U, /*!< EMV2 mux from MuxOscRc16M. */
1477     kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< EMV2 mux from MuxSysPll3Div2. */
1478     kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< EMV2 mux from MuxSysPll1Div5. */
1479     kCLOCK_EMV2_ClockRoot_MuxSysPll2Out   = 6U, /*!< EMV2 mux from MuxSysPll2Out. */
1480     kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< EMV2 mux from MuxSysPll2Pfd3. */
1481 
1482     /* ENET1 */
1483     kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET1 mux from MuxOscRc48MDiv2. */
1484     kCLOCK_ENET1_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET1 mux from MuxOsc24MOut. */
1485     kCLOCK_ENET1_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET1 mux from MuxOscRc400M. */
1486     kCLOCK_ENET1_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET1 mux from MuxOscRc16M. */
1487     kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET1 mux from MuxSysPll1Div2. */
1488     kCLOCK_ENET1_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET1 mux from MuxAudioPllOut. */
1489     kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET1 mux from MuxSysPll1Div5. */
1490     kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET1 mux from MuxSysPll2Pfd1. */
1491 
1492     /* ENET2 */
1493     kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET2 mux from MuxOscRc48MDiv2. */
1494     kCLOCK_ENET2_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET2 mux from MuxOsc24MOut. */
1495     kCLOCK_ENET2_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET2 mux from MuxOscRc400M. */
1496     kCLOCK_ENET2_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET2 mux from MuxOscRc16M. */
1497     kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET2 mux from MuxSysPll1Div2. */
1498     kCLOCK_ENET2_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET2 mux from MuxAudioPllOut. */
1499     kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET2 mux from MuxSysPll1Div5. */
1500     kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET2 mux from MuxSysPll2Pfd1. */
1501 
1502     /* ENET_QOS */
1503     kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_QOS mux from MuxOscRc48MDiv2. */
1504     kCLOCK_ENET_QOS_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET_QOS mux from MuxOsc24MOut. */
1505     kCLOCK_ENET_QOS_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET_QOS mux from MuxOscRc400M. */
1506     kCLOCK_ENET_QOS_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET_QOS mux from MuxOscRc16M. */
1507     kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET_QOS mux from MuxSysPll1Div2. */
1508     kCLOCK_ENET_QOS_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET_QOS mux from MuxAudioPllOut. */
1509     kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET_QOS mux from MuxSysPll1Div5. */
1510     kCLOCK_ENET_QOS_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET_QOS mux from MuxSysPll2Pfd1. */
1511 
1512     /* ENET_25M */
1513     kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_25M mux from MuxOscRc48MDiv2. */
1514     kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET_25M mux from MuxOsc24MOut. */
1515     kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET_25M mux from MuxOscRc400M. */
1516     kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET_25M mux from MuxOscRc16M. */
1517     kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET_25M mux from MuxSysPll1Div2. */
1518     kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET_25M mux from MuxAudioPllOut. */
1519     kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET_25M mux from MuxSysPll1Div5. */
1520     kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET_25M mux from MuxSysPll2Pfd1. */
1521 
1522     /* ENET_TIMER1 */
1523     kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_TIMER1 mux from MuxOscRc48MDiv2. */
1524     kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET_TIMER1 mux from MuxOsc24MOut. */
1525     kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET_TIMER1 mux from MuxOscRc400M. */
1526     kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET_TIMER1 mux from MuxOscRc16M. */
1527     kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET_TIMER1 mux from MuxSysPll1Div2. */
1528     kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET_TIMER1 mux from MuxAudioPllOut. */
1529     kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET_TIMER1 mux from MuxSysPll1Div5. */
1530     kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET_TIMER1 mux from MuxSysPll2Pfd1. */
1531 
1532     /* ENET_TIMER2 */
1533     kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_TIMER2 mux from MuxOscRc48MDiv2. */
1534     kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET_TIMER2 mux from MuxOsc24MOut. */
1535     kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET_TIMER2 mux from MuxOscRc400M. */
1536     kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET_TIMER2 mux from MuxOscRc16M. */
1537     kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET_TIMER2 mux from MuxSysPll1Div2. */
1538     kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET_TIMER2 mux from MuxAudioPllOut. */
1539     kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET_TIMER2 mux from MuxSysPll1Div5. */
1540     kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET_TIMER2 mux from MuxSysPll2Pfd1. */
1541 
1542     /* ENET_TIMER3 */
1543     kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_TIMER3 mux from MuxOscRc48MDiv2. */
1544     kCLOCK_ENET_TIMER3_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET_TIMER3 mux from MuxOsc24MOut. */
1545     kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET_TIMER3 mux from MuxOscRc400M. */
1546     kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET_TIMER3 mux from MuxOscRc16M. */
1547     kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET_TIMER3 mux from MuxSysPll1Div2. */
1548     kCLOCK_ENET_TIMER3_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET_TIMER3 mux from MuxAudioPllOut. */
1549     kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET_TIMER3 mux from MuxSysPll1Div5. */
1550     kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET_TIMER3 mux from MuxSysPll2Pfd1. */
1551 
1552     /* USDHC1 */
1553     kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< USDHC1 mux from MuxOscRc48MDiv2. */
1554     kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut    = 1U, /*!< USDHC1 mux from MuxOsc24MOut. */
1555     kCLOCK_USDHC1_ClockRoot_MuxOscRc400M    = 2U, /*!< USDHC1 mux from MuxOscRc400M. */
1556     kCLOCK_USDHC1_ClockRoot_MuxOscRc16M     = 3U, /*!< USDHC1 mux from MuxOscRc16M. */
1557     kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< USDHC1 mux from MuxSysPll2Pfd2. */
1558     kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0  = 5U, /*!< USDHC1 mux from MuxSysPll2Pfd0. */
1559     kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5  = 6U, /*!< USDHC1 mux from MuxSysPll1Div5. */
1560     kCLOCK_USDHC1_ClockRoot_MuxArmPllOut    = 7U, /*!< USDHC1 mux from MuxArmPllOut. */
1561 
1562     /* USDHC2 */
1563     kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< USDHC2 mux from MuxOscRc48MDiv2. */
1564     kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut    = 1U, /*!< USDHC2 mux from MuxOsc24MOut. */
1565     kCLOCK_USDHC2_ClockRoot_MuxOscRc400M    = 2U, /*!< USDHC2 mux from MuxOscRc400M. */
1566     kCLOCK_USDHC2_ClockRoot_MuxOscRc16M     = 3U, /*!< USDHC2 mux from MuxOscRc16M. */
1567     kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< USDHC2 mux from MuxSysPll2Pfd2. */
1568     kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0  = 5U, /*!< USDHC2 mux from MuxSysPll2Pfd0. */
1569     kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5  = 6U, /*!< USDHC2 mux from MuxSysPll1Div5. */
1570     kCLOCK_USDHC2_ClockRoot_MuxArmPllOut    = 7U, /*!< USDHC2 mux from MuxArmPllOut. */
1571 
1572     /* ASRC */
1573     kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ASRC mux from MuxOscRc48MDiv2. */
1574     kCLOCK_ASRC_ClockRoot_MuxOsc24MOut    = 1U, /*!< ASRC mux from MuxOsc24MOut. */
1575     kCLOCK_ASRC_ClockRoot_MuxOscRc400M    = 2U, /*!< ASRC mux from MuxOscRc400M. */
1576     kCLOCK_ASRC_ClockRoot_MuxOscRc16M     = 3U, /*!< ASRC mux from MuxOscRc16M. */
1577     kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5  = 4U, /*!< ASRC mux from MuxSysPll1Div5. */
1578     kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2  = 5U, /*!< ASRC mux from MuxSysPll3Div2. */
1579     kCLOCK_ASRC_ClockRoot_MuxAudioPllOut  = 6U, /*!< ASRC mux from MuxAudioPllOut. */
1580     kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< ASRC mux from MuxSysPll2Pfd3. */
1581 
1582     /* MQS */
1583     kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MQS mux from MuxOscRc48MDiv2. */
1584     kCLOCK_MQS_ClockRoot_MuxOsc24MOut    = 1U, /*!< MQS mux from MuxOsc24MOut. */
1585     kCLOCK_MQS_ClockRoot_MuxOscRc400M    = 2U, /*!< MQS mux from MuxOscRc400M. */
1586     kCLOCK_MQS_ClockRoot_MuxOscRc16M     = 3U, /*!< MQS mux from MuxOscRc16M. */
1587     kCLOCK_MQS_ClockRoot_MuxSysPll1Div5  = 4U, /*!< MQS mux from MuxSysPll1Div5. */
1588     kCLOCK_MQS_ClockRoot_MuxSysPll3Div2  = 5U, /*!< MQS mux from MuxSysPll3Div2. */
1589     kCLOCK_MQS_ClockRoot_MuxAudioPllOut  = 6U, /*!< MQS mux from MuxAudioPllOut. */
1590     kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< MQS mux from MuxSysPll2Pfd3. */
1591 
1592     /* MIC */
1593     kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MIC mux from MuxOscRc48MDiv2. */
1594     kCLOCK_MIC_ClockRoot_MuxOsc24MOut    = 1U, /*!< MIC mux from MuxOsc24MOut. */
1595     kCLOCK_MIC_ClockRoot_MuxOscRc400M    = 2U, /*!< MIC mux from MuxOscRc400M. */
1596     kCLOCK_MIC_ClockRoot_MuxOscRc16M     = 3U, /*!< MIC mux from MuxOscRc16M. */
1597     kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< MIC mux from MuxSysPll3Pfd3. */
1598     kCLOCK_MIC_ClockRoot_MuxSysPll3Out   = 5U, /*!< MIC mux from MuxSysPll3Out. */
1599     kCLOCK_MIC_ClockRoot_MuxAudioPllOut  = 6U, /*!< MIC mux from MuxAudioPllOut. */
1600     kCLOCK_MIC_ClockRoot_MuxSysPll1Div5  = 7U, /*!< MIC mux from MuxSysPll1Div5. */
1601 
1602     /* SPDIF */
1603     kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SPDIF mux from MuxOscRc48MDiv2. */
1604     kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut    = 1U, /*!< SPDIF mux from MuxOsc24MOut. */
1605     kCLOCK_SPDIF_ClockRoot_MuxOscRc400M    = 2U, /*!< SPDIF mux from MuxOscRc400M. */
1606     kCLOCK_SPDIF_ClockRoot_MuxOscRc16M     = 3U, /*!< SPDIF mux from MuxOscRc16M. */
1607     kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut  = 4U, /*!< SPDIF mux from MuxAudioPllOut. */
1608     kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out   = 5U, /*!< SPDIF mux from MuxSysPll3Out. */
1609     kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< SPDIF mux from MuxSysPll3Pfd2. */
1610     kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< SPDIF mux from MuxSysPll2Pfd3. */
1611 
1612     /* SAI1 */
1613     kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI1 mux from MuxOscRc48MDiv2. */
1614     kCLOCK_SAI1_ClockRoot_MuxOsc24MOut    = 1U, /*!< SAI1 mux from MuxOsc24MOut. */
1615     kCLOCK_SAI1_ClockRoot_MuxOscRc400M    = 2U, /*!< SAI1 mux from MuxOscRc400M. */
1616     kCLOCK_SAI1_ClockRoot_MuxOscRc16M     = 3U, /*!< SAI1 mux from MuxOscRc16M. */
1617     kCLOCK_SAI1_ClockRoot_MuxAudioPllOut  = 4U, /*!< SAI1 mux from MuxAudioPllOut. */
1618     kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2  = 5U, /*!< SAI1 mux from MuxSysPll3Pfd2. */
1619     kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5  = 6U, /*!< SAI1 mux from MuxSysPll1Div5. */
1620     kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< SAI1 mux from MuxSysPll2Pfd3. */
1621 
1622     /* SAI2 */
1623     kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI2 mux from MuxOscRc48MDiv2. */
1624     kCLOCK_SAI2_ClockRoot_MuxOsc24MOut    = 1U, /*!< SAI2 mux from MuxOsc24MOut. */
1625     kCLOCK_SAI2_ClockRoot_MuxOscRc400M    = 2U, /*!< SAI2 mux from MuxOscRc400M. */
1626     kCLOCK_SAI2_ClockRoot_MuxOscRc16M     = 3U, /*!< SAI2 mux from MuxOscRc16M. */
1627     kCLOCK_SAI2_ClockRoot_MuxAudioPllOut  = 4U, /*!< SAI2 mux from MuxAudioPllOut. */
1628     kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2  = 5U, /*!< SAI2 mux from MuxSysPll3Pfd2. */
1629     kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5  = 6U, /*!< SAI2 mux from MuxSysPll1Div5. */
1630     kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< SAI2 mux from MuxSysPll2Pfd3. */
1631 
1632     /* SAI3 */
1633     kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI3 mux from MuxOscRc48MDiv2. */
1634     kCLOCK_SAI3_ClockRoot_MuxOsc24MOut    = 1U, /*!< SAI3 mux from MuxOsc24MOut. */
1635     kCLOCK_SAI3_ClockRoot_MuxOscRc400M    = 2U, /*!< SAI3 mux from MuxOscRc400M. */
1636     kCLOCK_SAI3_ClockRoot_MuxOscRc16M     = 3U, /*!< SAI3 mux from MuxOscRc16M. */
1637     kCLOCK_SAI3_ClockRoot_MuxAudioPllOut  = 4U, /*!< SAI3 mux from MuxAudioPllOut. */
1638     kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2  = 5U, /*!< SAI3 mux from MuxSysPll3Pfd2. */
1639     kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5  = 6U, /*!< SAI3 mux from MuxSysPll1Div5. */
1640     kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< SAI3 mux from MuxSysPll2Pfd3. */
1641 
1642     /* SAI4 */
1643     kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI4 mux from MuxOscRc48MDiv2. */
1644     kCLOCK_SAI4_ClockRoot_MuxOsc24MOut    = 1U, /*!< SAI4 mux from MuxOsc24MOut. */
1645     kCLOCK_SAI4_ClockRoot_MuxOscRc400M    = 2U, /*!< SAI4 mux from MuxOscRc400M. */
1646     kCLOCK_SAI4_ClockRoot_MuxOscRc16M     = 3U, /*!< SAI4 mux from MuxOscRc16M. */
1647     kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< SAI4 mux from MuxSysPll3Pfd3. */
1648     kCLOCK_SAI4_ClockRoot_MuxSysPll3Out   = 5U, /*!< SAI4 mux from MuxSysPll3Out. */
1649     kCLOCK_SAI4_ClockRoot_MuxAudioPllOut  = 6U, /*!< SAI4 mux from MuxAudioPllOut. */
1650     kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5  = 7U, /*!< SAI4 mux from MuxSysPll1Div5. */
1651 
1652     /* GC355 */
1653     kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GC355 mux from MuxOscRc48MDiv2. */
1654     kCLOCK_GC355_ClockRoot_MuxOsc24MOut    = 1U, /*!< GC355 mux from MuxOsc24MOut. */
1655     kCLOCK_GC355_ClockRoot_MuxOscRc400M    = 2U, /*!< GC355 mux from MuxOscRc400M. */
1656     kCLOCK_GC355_ClockRoot_MuxOscRc16M     = 3U, /*!< GC355 mux from MuxOscRc16M. */
1657     kCLOCK_GC355_ClockRoot_MuxSysPll2Out   = 4U, /*!< GC355 mux from MuxSysPll2Out. */
1658     kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1  = 5U, /*!< GC355 mux from MuxSysPll2Pfd1. */
1659     kCLOCK_GC355_ClockRoot_MuxSysPll3Out   = 6U, /*!< GC355 mux from MuxSysPll3Out. */
1660     kCLOCK_GC355_ClockRoot_MuxVideoPllOut  = 7U, /*!< GC355 mux from MuxVideoPllOut. */
1661 
1662     /* LCDIF */
1663     kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LCDIF mux from MuxOscRc48MDiv2. */
1664     kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut    = 1U, /*!< LCDIF mux from MuxOsc24MOut. */
1665     kCLOCK_LCDIF_ClockRoot_MuxOscRc400M    = 2U, /*!< LCDIF mux from MuxOscRc400M. */
1666     kCLOCK_LCDIF_ClockRoot_MuxOscRc16M     = 3U, /*!< LCDIF mux from MuxOscRc16M. */
1667     kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out   = 4U, /*!< LCDIF mux from MuxSysPll2Out. */
1668     kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2  = 5U, /*!< LCDIF mux from MuxSysPll2Pfd2. */
1669     kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0  = 6U, /*!< LCDIF mux from MuxSysPll3Pfd0. */
1670     kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut  = 7U, /*!< LCDIF mux from MuxVideoPllOut. */
1671 
1672     /* LCDIFV2 */
1673     kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LCDIFV2 mux from MuxOscRc48MDiv2. */
1674     kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut    = 1U, /*!< LCDIFV2 mux from MuxOsc24MOut. */
1675     kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M    = 2U, /*!< LCDIFV2 mux from MuxOscRc400M. */
1676     kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M     = 3U, /*!< LCDIFV2 mux from MuxOscRc16M. */
1677     kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out   = 4U, /*!< LCDIFV2 mux from MuxSysPll2Out. */
1678     kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2  = 5U, /*!< LCDIFV2 mux from MuxSysPll2Pfd2. */
1679     kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0  = 6U, /*!< LCDIFV2 mux from MuxSysPll3Pfd0. */
1680     kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut  = 7U, /*!< LCDIFV2 mux from MuxVideoPllOut. */
1681 
1682     /* MIPI_REF */
1683     kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MIPI_REF mux from MuxOscRc48MDiv2. */
1684     kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut    = 1U, /*!< MIPI_REF mux from MuxOsc24MOut. */
1685     kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M    = 2U, /*!< MIPI_REF mux from MuxOscRc400M. */
1686     kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M     = 3U, /*!< MIPI_REF mux from MuxOscRc16M. */
1687     kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out   = 4U, /*!< MIPI_REF mux from MuxSysPll2Out. */
1688     kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0  = 5U, /*!< MIPI_REF mux from MuxSysPll2Pfd0. */
1689     kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0  = 6U, /*!< MIPI_REF mux from MuxSysPll3Pfd0. */
1690     kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut  = 7U, /*!< MIPI_REF mux from MuxVideoPllOut. */
1691 
1692     /* MIPI_ESC */
1693     kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MIPI_ESC mux from MuxOscRc48MDiv2. */
1694     kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut    = 1U, /*!< MIPI_ESC mux from MuxOsc24MOut. */
1695     kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M    = 2U, /*!< MIPI_ESC mux from MuxOscRc400M. */
1696     kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M     = 3U, /*!< MIPI_ESC mux from MuxOscRc16M. */
1697     kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out   = 4U, /*!< MIPI_ESC mux from MuxSysPll2Out. */
1698     kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0  = 5U, /*!< MIPI_ESC mux from MuxSysPll2Pfd0. */
1699     kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0  = 6U, /*!< MIPI_ESC mux from MuxSysPll3Pfd0. */
1700     kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut  = 7U, /*!< MIPI_ESC mux from MuxVideoPllOut. */
1701 
1702     /* CSI2 */
1703     kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI2 mux from MuxOscRc48MDiv2. */
1704     kCLOCK_CSI2_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSI2 mux from MuxOsc24MOut. */
1705     kCLOCK_CSI2_ClockRoot_MuxOscRc400M    = 2U, /*!< CSI2 mux from MuxOscRc400M. */
1706     kCLOCK_CSI2_ClockRoot_MuxOscRc16M     = 3U, /*!< CSI2 mux from MuxOscRc16M. */
1707     kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CSI2 mux from MuxSysPll2Pfd2. */
1708     kCLOCK_CSI2_ClockRoot_MuxSysPll3Out   = 5U, /*!< CSI2 mux from MuxSysPll3Out. */
1709     kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0  = 6U, /*!< CSI2 mux from MuxSysPll2Pfd0. */
1710     kCLOCK_CSI2_ClockRoot_MuxVideoPllOut  = 7U, /*!< CSI2 mux from MuxVideoPllOut. */
1711 
1712     /* CSI2_ESC */
1713     kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI2_ESC mux from MuxOscRc48MDiv2. */
1714     kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSI2_ESC mux from MuxOsc24MOut. */
1715     kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M    = 2U, /*!< CSI2_ESC mux from MuxOscRc400M. */
1716     kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M     = 3U, /*!< CSI2_ESC mux from MuxOscRc16M. */
1717     kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CSI2_ESC mux from MuxSysPll2Pfd2. */
1718     kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out   = 5U, /*!< CSI2_ESC mux from MuxSysPll3Out. */
1719     kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0  = 6U, /*!< CSI2_ESC mux from MuxSysPll2Pfd0. */
1720     kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut  = 7U, /*!< CSI2_ESC mux from MuxVideoPllOut. */
1721 
1722     /* CSI2_UI */
1723     kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI2_UI mux from MuxOscRc48MDiv2. */
1724     kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSI2_UI mux from MuxOsc24MOut. */
1725     kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M    = 2U, /*!< CSI2_UI mux from MuxOscRc400M. */
1726     kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M     = 3U, /*!< CSI2_UI mux from MuxOscRc16M. */
1727     kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CSI2_UI mux from MuxSysPll2Pfd2. */
1728     kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out   = 5U, /*!< CSI2_UI mux from MuxSysPll3Out. */
1729     kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0  = 6U, /*!< CSI2_UI mux from MuxSysPll2Pfd0. */
1730     kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut  = 7U, /*!< CSI2_UI mux from MuxVideoPllOut. */
1731 
1732     /* CSI */
1733     kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI mux from MuxOscRc48MDiv2. */
1734     kCLOCK_CSI_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSI mux from MuxOsc24MOut. */
1735     kCLOCK_CSI_ClockRoot_MuxOscRc400M    = 2U, /*!< CSI mux from MuxOscRc400M. */
1736     kCLOCK_CSI_ClockRoot_MuxOscRc16M     = 3U, /*!< CSI mux from MuxOscRc16M. */
1737     kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CSI mux from MuxSysPll2Pfd2. */
1738     kCLOCK_CSI_ClockRoot_MuxSysPll3Out   = 5U, /*!< CSI mux from MuxSysPll3Out. */
1739     kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1  = 6U, /*!< CSI mux from MuxSysPll3Pfd1. */
1740     kCLOCK_CSI_ClockRoot_MuxVideoPllOut  = 7U, /*!< CSI mux from MuxVideoPllOut. */
1741 
1742     /* CKO1 */
1743     kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CKO1 mux from MuxOscRc48MDiv2. */
1744     kCLOCK_CKO1_ClockRoot_MuxOsc24MOut    = 1U, /*!< CKO1 mux from MuxOsc24MOut. */
1745     kCLOCK_CKO1_ClockRoot_MuxOscRc400M    = 2U, /*!< CKO1 mux from MuxOscRc400M. */
1746     kCLOCK_CKO1_ClockRoot_MuxOscRc16M     = 3U, /*!< CKO1 mux from MuxOscRc16M. */
1747     kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CKO1 mux from MuxSysPll2Pfd2. */
1748     kCLOCK_CKO1_ClockRoot_MuxSysPll2Out   = 5U, /*!< CKO1 mux from MuxSysPll2Out. */
1749     kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1  = 6U, /*!< CKO1 mux from MuxSysPll3Pfd1. */
1750     kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5  = 7U, /*!< CKO1 mux from MuxSysPll1Div5. */
1751 
1752     /* CKO2 */
1753     kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CKO2 mux from MuxOscRc48MDiv2. */
1754     kCLOCK_CKO2_ClockRoot_MuxOsc24MOut    = 1U, /*!< CKO2 mux from MuxOsc24MOut. */
1755     kCLOCK_CKO2_ClockRoot_MuxOscRc400M    = 2U, /*!< CKO2 mux from MuxOscRc400M. */
1756     kCLOCK_CKO2_ClockRoot_MuxOscRc16M     = 3U, /*!< CKO2 mux from MuxOscRc16M. */
1757     kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3  = 4U, /*!< CKO2 mux from MuxSysPll2Pfd3. */
1758     kCLOCK_CKO2_ClockRoot_MuxOscRc48M     = 5U, /*!< CKO2 mux from MuxOscRc48M. */
1759     kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1  = 6U, /*!< CKO2 mux from MuxSysPll3Pfd1. */
1760     kCLOCK_CKO2_ClockRoot_MuxAudioPllOut  = 7U, /*!< CKO2 mux from MuxAudioPllOut. */
1761 } clock_root_mux_source_t;
1762 
1763 /*!
1764  * @brief Clock group enumeration.
1765  */
1766 typedef enum _clock_group
1767 {
1768     kCLOCK_Group_FlexRAM = 0, /*!< FlexRAM clock group. */
1769     kCLOCK_Group_MipiDsi = 1, /*!< Mipi Dsi clock group. */
1770     kCLOCK_Group_Last,        /*!< Last clock group. */
1771 } clock_group_t;
1772 
1773 /*!
1774  * @brief The structure used to configure clock group.
1775  */
1776 typedef struct _clock_group_config
1777 {
1778     bool clockOff;     /*!< Turn off the clock. */
1779     uint16_t resetDiv; /*!< resetDiv + 1 should be common multiple of all dividers, valid range 0 ~ 255. */
1780     uint8_t div0;      /*!< Divide root clock by div0 + 1, valid range: 0 ~ 15. */
1781 } clock_group_config_t;
1782 
1783 #define clock_ip_name_t clock_lpcg_t
1784 
1785 #if (__CORTEX_M == 7)
1786 #define CLOCK_GetCpuClkFreq CLOCK_GetM7Freq
1787 #else
1788 #define CLOCK_GetCpuClkFreq CLOCK_GetM4Freq
1789 #endif
1790 
1791 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
1792 
1793 /* uncomment the following line if want to use OBS to retrieve frequency */
1794 /* #define GET_FREQ_FROM_OBS */
1795 
1796 /*! @brief OSC 24M sorce select */
1797 typedef enum _clock_osc
1798 {
1799     kCLOCK_RcOsc   = 0U, /*!< On chip OSC. */
1800     kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
1801 } clock_osc_t;
1802 
1803 /*! @brief Clock gate value */
1804 typedef enum _clock_gate_value
1805 {
1806     kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK, /*!< Clock is off. */
1807     kCLOCK_On  = CCM_LPCG_DIRECT_ON_MASK,       /*!< Clock is on*/
1808 } clock_gate_value_t;
1809 
1810 /*! @brief System clock mode */
1811 typedef enum _clock_mode_t
1812 {
1813     kCLOCK_ModeRun  = 0U, /*!< Remain in run mode. */
1814     kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
1815     kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
1816 } clock_mode_t;
1817 
1818 /*! @brief USB clock source definition. */
1819 typedef enum _clock_usb_src
1820 {
1821     kCLOCK_Usb480M      = 0,                /*!< Use 480M.      */
1822     kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
1823                                             care the clock source. */
1824 } clock_usb_src_t;
1825 
1826 /*! @brief Source of the USB HS PHY. */
1827 typedef enum _clock_usb_phy_src
1828 {
1829     kCLOCK_Usbphy480M = 0, /*!< Use 480M.      */
1830 } clock_usb_phy_src_t;
1831 
1832 /*! @brief PLL clock source, bypass cloco source also */
1833 enum _clock_pll_clk_src
1834 {
1835     kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
1836     kCLOCK_PllSrcClkPN  = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
1837 };
1838 
1839 /*!
1840  * @brief PLL post divider enumeration.
1841  */
1842 typedef enum _clock_pll_post_div
1843 {
1844     kCLOCK_PllPostDiv2 = 0U, /*!< Divide by 2. */
1845     kCLOCK_PllPostDiv4 = 1U, /*!< Divide by 4. */
1846     kCLOCK_PllPostDiv8 = 2U, /*!< Divide by 8. */
1847     kCLOCK_PllPostDiv1 = 3U, /*!< Divide by 1. */
1848 } clock_pll_post_div_t;
1849 
1850 /*!
1851  * @brief PLL configuration for ARM.
1852  *
1853  * The output clock frequency is:
1854  *
1855  *  Fout=Fin*loopDivider /(2 * postDivider).
1856  *
1857  * Fin is always 24MHz.
1858  */
1859 typedef struct _clock_arm_pll_config
1860 {
1861     clock_pll_post_div_t postDivider; /*!< Post divider. */
1862     uint32_t loopDivider;             /*!< PLL loop divider. Valid range: 104-208. */
1863 } clock_arm_pll_config_t;
1864 
1865 /*! @brief PLL configuration for USB */
1866 typedef struct _clock_usb_pll_config
1867 {
1868     uint8_t loopDivider; /*!< PLL loop divider.
1869                               0 - Fout=Fref*20;
1870                               1 - Fout=Fref*22 */
1871     uint8_t src;         /*!< Pll clock source, reference _clock_pll_clk_src */
1872 
1873 } clock_usb_pll_config_t;
1874 
1875 /*! @brief Spread specturm configure Pll */
1876 typedef struct _clock_pll_ss_config
1877 {
1878     uint16_t stop; /*!< Spread spectrum stop value to get frequency change. */
1879     uint16_t step; /*!< Spread spectrum step value to get frequency change step. */
1880 } clock_pll_ss_config_t;
1881 
1882 /*! @brief PLL configure for Sys Pll2 */
1883 typedef struct _clock_sys_pll2_config
1884 {
1885     uint32_t mfd;              /*!< Denominator of spread spectrum */
1886     clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter,
1887                                  it can be NULL, if ssEnable is set to false */
1888     bool ssEnable;             /*!< Enable spread spectrum flag */
1889 } clock_sys_pll2_config_t;
1890 
1891 /*! @brief PLL configure for Sys Pll1 */
1892 typedef struct _clock_sys_pll1_config
1893 {
1894     bool pllDiv2En;            /*!< Enable Sys Pll1 divide-by-2 clock or not. */
1895     bool pllDiv5En;            /*!< Enable Sys Pll1 divide-by-5 clock or not. */
1896     clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter,
1897                                  it can be NULL, if ssEnable is set to false */
1898     bool ssEnable;             /*!< Enable spread spectrum flag */
1899 } clock_sys_pll1_config_t;
1900 
1901 /*! @brief PLL configuration for AUDIO and VIDEO */
1902 typedef struct _clock_audio_pll_config
1903 {
1904     uint8_t loopDivider;       /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
1905     uint8_t postDivider;       /*!< Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4,
1906                                     0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32.*/
1907     uint32_t numerator;        /*!< 30 bit numerator of fractional loop divider.*/
1908     uint32_t denominator;      /*!< 30 bit denominator of fractional loop divider */
1909     clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter,
1910                                  it can be NULL, if ssEnable is set to false */
1911     bool ssEnable;             /*!< Enable spread spectrum flag */
1912 } clock_av_pll_config_t, clock_audio_pll_config_t, clock_video_pll_config_t;
1913 
1914 /*!
1915  * @brief PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL.
1916  */
1917 typedef struct _clock_audio_pll_gpc_config
1918 {
1919     uint8_t loopDivider;       /*!< PLL loop divider.  */
1920     uint32_t numerator;        /*!< 30 bit numerator of fractional loop divider.*/
1921     uint32_t denominator;      /*!< 30 bit denominator of fractional loop divider */
1922     clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter,
1923                                  it can be NULL, if ssEnable is set to false */
1924     bool ssEnable;             /*!< Enable spread spectrum flag */
1925 } clock_audio_pll_gpc_config_t, clock_video_pll_gpc_config_t, clock_sys_pll1_gpc_config_t;
1926 
1927 /*! @brief PLL configuration for ENET */
1928 typedef struct _clock_enet_pll_config
1929 {
1930     bool enableClkOutput;    /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
1931     bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */
1932     uint8_t loopDivider;     /*!< Controls the frequency of the ENET0 reference clock.
1933                                   b00 25MHz
1934                                   b01 50MHz
1935                                   b10 100MHz (not 50% duty cycle)
1936                                   b11 125MHz */
1937     uint8_t src;             /*!< Pll clock source, reference _clock_pll_clk_src */
1938     bool enableClkOutput1;   /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
1939     uint8_t loopDivider1;    /*!< Controls the frequency of the ENET1 reference clock.
1940                                   b00 25MHz
1941                                   b01 50MHz
1942                                   b10 100MHz (not 50% duty cycle)
1943                                   b11 125MHz */
1944 } clock_enet_pll_config_t;
1945 
1946 /*! @brief Clock root configuration */
1947 typedef struct _clock_root_config_t
1948 {
1949     bool clockOff;
1950     uint8_t mux; /*!< See #clock_root_mux_source_t for details. */
1951     uint8_t div; /*!< it's the actual divider */
1952 } clock_root_config_t;
1953 
1954 /*! @brief Clock root configuration in SetPoint Mode */
1955 typedef struct _clock_root_setpoint_config_t
1956 {
1957     uint8_t grade; /*!< Indicate speed grade for each SetPoint */
1958     bool clockOff;
1959     uint8_t mux; /*!< See #clock_root_mux_source_t for details. */
1960     uint8_t div; /*!< it's the actual divider */
1961 } clock_root_setpoint_config_t;
1962 
1963 /*! @brief PLL name */
1964 typedef enum _clock_pll
1965 {
1966     kCLOCK_PllArm,          /*!< ARM PLL. */
1967     kCLOCK_PllSys1,         /*!< SYS1 PLL, it has a dedicated frequency of 1GHz. */
1968     kCLOCK_PllSys2,         /*!< SYS2 PLL, it has a dedicated frequency of 528MHz. */
1969     kCLOCK_PllSys3,         /*!< SYS3 PLL, it has a dedicated frequency of 480MHz. */
1970     kCLOCK_PllAudio,        /*!< Audio PLL. */
1971     kCLOCK_PllVideo,        /*!< Video PLL. */
1972     kCLOCK_PllInvalid = -1, /*!< Invalid value. */
1973 } clock_pll_t;
1974 
1975 #define PLL_PFD_COUNT 4
1976 
1977 /*! @brief PLL PFD name */
1978 typedef enum _clock_pfd
1979 {
1980     kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
1981     kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
1982     kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
1983     kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
1984 } clock_pfd_t;
1985 
1986 /*!
1987  * @brief The enumeration of control mode.
1988  *
1989  */
1990 typedef enum _clock_control_mode
1991 {
1992     kCLOCK_SoftwareMode = 0U, /*!< Software control mode. */
1993     kCLOCK_GpcMode,           /*!< GPC control mode. */
1994 } clock_control_mode_t;
1995 
1996 /*!
1997  * @brief The enumeration of 24MHz crystal oscillator mode.
1998  */
1999 typedef enum _clock_24MOsc_mode
2000 {
2001     kCLOCK_24MOscHighGainMode = 0U, /*!< 24MHz crystal oscillator work as high gain mode. */
2002     kCLOCK_24MOscBypassMode   = 1U, /*!< 24MHz crystal oscillator work as bypass mode. */
2003     kCLOCK_24MOscLowPowerMode = 2U, /*!< 24MHz crystal oscillator work as low power mode. */
2004 } clock_24MOsc_mode_t;
2005 
2006 /*!
2007  * @brief The enumeration of 16MHz RC oscillator clock source.
2008  */
2009 typedef enum _clock_16MOsc_source
2010 {
2011     kCLOCK_16MOscSourceFrom16MOsc = 0U, /*!< Source from 16MHz RC oscialltor. */
2012     kCLOCK_16MOscSourceFrom24MOsc = 1U, /*!< Source from 24MHz crystal oscillator. */
2013 } clock_16MOsc_source_t;
2014 
2015 /*!
2016  * @brief The enumeration of 1MHz output clock behavior, including disabling 1MHz output,
2017  * enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.
2018  */
2019 typedef enum _clock_1MHzOut_behavior
2020 {
2021     kCLOCK_1MHzOutDisable               = 0U, /*!< Disable 1MHz output clock. */
2022     kCLOCK_1MHzOutEnableLocked1Mhz      = 1U, /*!< Enable 1MHz output clock, and select locked 1MHz to output. */
2023     kCLOCK_1MHzOutEnableFreeRunning1Mhz = 2U, /*!< Enable 1MHZ output clock,
2024                                                    and select free-running 1MHz to output. */
2025 } clock_1MHzOut_behavior_t;
2026 
2027 /*!
2028  * @brief The clock dependence level.
2029  */
2030 typedef enum _clock_level
2031 {
2032     kCLOCK_Level0 = 0x0UL, /*!< Not needed in any mode. */
2033     kCLOCK_Level1 = 0x1UL, /*!< Needed in RUN mode. */
2034     kCLOCK_Level2 = 0x2UL, /*!< Needed in RUN and WAIT mode. */
2035     kCLOCK_Level3 = 0x3UL, /*!< Needed in RUN, WAIT and STOP mode. */
2036     kCLOCK_Level4 = 0x4UL, /*!< Always on in any mode. */
2037 } clock_level_t;
2038 
2039 /*******************************************************************************
2040  * API
2041  ******************************************************************************/
2042 
2043 #if defined(__cplusplus)
2044 extern "C" {
2045 #endif /* __cplusplus */
2046 
2047 /*!
2048  * @brief Set CCM Root Clock MUX node to certain value.
2049  *
2050  * @param root Which root clock node to set, see \ref clock_root_t.
2051  * @param src Clock mux value to set, different mux has different value range. See \ref clock_root_mux_source_t.
2052  */
CLOCK_SetRootClockMux(clock_root_t root,uint8_t src)2053 static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src)
2054 {
2055     assert(src < 8U);
2056     CCM->CLOCK_ROOT[root].CONTROL =
2057         (CCM->CLOCK_ROOT[root].CONTROL & ~(CCM_CLOCK_ROOT_CONTROL_MUX_MASK)) | CCM_CLOCK_ROOT_CONTROL_MUX(src);
2058     __DSB();
2059     __ISB();
2060 #if __CORTEX_M == 4
2061     (void)CCM->CLOCK_ROOT[root].CONTROL;
2062 #endif
2063 }
2064 
2065 /*!
2066  * @brief Get CCM Root Clock MUX value.
2067  *
2068  * @param root Which root clock node to get, see \ref clock_root_t.
2069  * @return Clock mux value.
2070  */
CLOCK_GetRootClockMux(clock_root_t root)2071 static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root)
2072 {
2073     return (CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) >> CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT;
2074 }
2075 
2076 /*!
2077  * @brief Get CCM Root Clock Source.
2078  *
2079  * @param root Which root clock node to get, see \ref clock_root_t.
2080  * @param src Clock mux value to get, see \ref clock_root_mux_source_t.
2081  * @return Clock source
2082  */
CLOCK_GetRootClockSource(clock_root_t root,uint32_t src)2083 static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src)
2084 {
2085     return s_clockSourceName[root][src];
2086 }
2087 
2088 /*!
2089  * @brief Set CCM Root Clock DIV certain value.
2090  *
2091  * @param root Which root clock to set, see \ref clock_root_t.
2092  * @param div Clock div value to set, different divider has different value range.
2093  */
CLOCK_SetRootClockDiv(clock_root_t root,uint8_t div)2094 static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint8_t div)
2095 {
2096     assert(div);
2097     CCM->CLOCK_ROOT[root].CONTROL = (CCM->CLOCK_ROOT[root].CONTROL & ~CCM_CLOCK_ROOT_CONTROL_DIV_MASK) |
2098                                     CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)div - 1UL);
2099     __DSB();
2100     __ISB();
2101 #if __CORTEX_M == 4
2102     (void)CCM->CLOCK_ROOT[root].CONTROL;
2103 #endif
2104 }
2105 
2106 /*!
2107  * @brief Get CCM DIV node value.
2108  *
2109  * @param root Which root clock node to get, see \ref clock_root_t.
2110  * @return divider set for this root
2111  */
CLOCK_GetRootClockDiv(clock_root_t root)2112 static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root)
2113 {
2114     return ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) >> CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT) +
2115            1UL;
2116 }
2117 
2118 /*!
2119  * @brief Power Off Root Clock
2120  *
2121  * @param root Which root clock node to set, see \ref clock_root_t.
2122  */
CLOCK_PowerOffRootClock(clock_root_t root)2123 static inline void CLOCK_PowerOffRootClock(clock_root_t root)
2124 {
2125     if (0UL == (CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_OFF_MASK))
2126     {
2127         CCM->CLOCK_ROOT[root].CONTROL_SET = CCM_CLOCK_ROOT_CONTROL_OFF_MASK;
2128         __DSB();
2129         __ISB();
2130 #if __CORTEX_M == 4
2131         (void)CCM->CLOCK_ROOT[root].CONTROL;
2132 #endif
2133     }
2134 }
2135 
2136 /*!
2137  * @brief Power On Root Clock
2138  *
2139  * @param root Which root clock node to set, see \ref clock_root_t.
2140  */
CLOCK_PowerOnRootClock(clock_root_t root)2141 static inline void CLOCK_PowerOnRootClock(clock_root_t root)
2142 {
2143     CCM->CLOCK_ROOT[root].CONTROL_CLR = CCM_CLOCK_ROOT_CONTROL_OFF_MASK;
2144     __DSB();
2145     __ISB();
2146 #if __CORTEX_M == 4
2147     (void)CCM->CLOCK_ROOT[root].CONTROL;
2148 #endif
2149 }
2150 
2151 /*!
2152  * @brief Configure Root Clock
2153  *
2154  * @param root Which root clock node to set, see \ref clock_root_t.
2155  * @param config root clock config, see \ref clock_root_config_t
2156  */
CLOCK_SetRootClock(clock_root_t root,const clock_root_config_t * config)2157 static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config)
2158 {
2159     assert(config);
2160     CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(config->mux) |
2161                                     CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)config->div - 1UL) |
2162                                     (config->clockOff ? CCM_CLOCK_ROOT_CONTROL_OFF(config->clockOff) : 0UL);
2163     __DSB();
2164     __ISB();
2165 #if __CORTEX_M == 4
2166     (void)CCM->CLOCK_ROOT[root].CONTROL;
2167 #endif
2168 }
2169 
2170 /*!
2171  * @brief Control the clock gate for specific IP.
2172  *
2173  * @note This API will not have any effect when this clock is in CPULPM or SetPoint Mode
2174  *
2175  * @param name  Which clock to enable, see \ref clock_lpcg_t.
2176  * @param value Clock gate value to set, see \ref clock_gate_value_t.
2177  */
CLOCK_ControlGate(clock_ip_name_t name,clock_gate_value_t value)2178 static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
2179 {
2180     if (((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK) != (CCM->LPCG[name].DIRECT & CCM_LPCG_DIRECT_ON_MASK))
2181     {
2182         CCM->LPCG[name].DIRECT = ((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK);
2183         __DSB();
2184         __ISB();
2185 #if __CORTEX_M == 4
2186         (void)CCM->LPCG[name].DIRECT;
2187 #endif
2188     }
2189 }
2190 
2191 /*!
2192  * @brief Enable the clock for specific IP.
2193  *
2194  * @param name  Which clock to enable, see \ref clock_lpcg_t.
2195  */
CLOCK_EnableClock(clock_ip_name_t name)2196 static inline void CLOCK_EnableClock(clock_ip_name_t name)
2197 {
2198     CLOCK_ControlGate(name, kCLOCK_On);
2199 }
2200 
2201 /*!
2202  * @brief Disable the clock for specific IP.
2203  *
2204  * @param name  Which clock to disable, see \ref clock_lpcg_t.
2205  */
CLOCK_DisableClock(clock_ip_name_t name)2206 static inline void CLOCK_DisableClock(clock_ip_name_t name)
2207 {
2208     CLOCK_ControlGate(name, kCLOCK_Off);
2209 }
2210 
2211 /*!
2212  * @brief Set the clock group configuration.
2213  *
2214  * @param group  Which group to configure, see \ref clock_group_t.
2215  * @param config Configuration to set.
2216  */
2217 void CLOCK_SetGroupConfig(clock_group_t group, const clock_group_config_t *config);
2218 
2219 /*!
2220  * @brief Gets the clock frequency for a specific clock name.
2221  *
2222  * This function checks the current clock configurations and then calculates
2223  * the clock frequency for a specific clock name defined in clock_name_t.
2224  *
2225  * @param name Clock names defined in clock_name_t
2226  * @return Clock frequency value in hertz
2227  */
2228 uint32_t CLOCK_GetFreq(clock_name_t name);
2229 
2230 /*!
2231  * @brief Gets the clock frequency for a specific root clock name.
2232  *
2233  * This function checks the current clock configurations and then calculates
2234  * the clock frequency for a specific clock name defined in clock_root_t.
2235  *
2236  * @param root Clock names defined in clock_root_t
2237  * @return Clock frequency value in hertz
2238  */
CLOCK_GetRootClockFreq(clock_root_t root)2239 static inline uint32_t CLOCK_GetRootClockFreq(clock_root_t root)
2240 {
2241     uint32_t freq, mux;
2242     mux  = CLOCK_GetRootClockMux(root);
2243     freq = CLOCK_GetFreq(s_clockSourceName[root][mux]) / (CLOCK_GetRootClockDiv(root));
2244     assert(freq);
2245     return freq;
2246 }
2247 
2248 /*!
2249  * @brief Get the CCM CPU/core/system frequency.
2250  *
2251  * @return  Clock frequency; If the clock is invalid, returns 0.
2252  */
CLOCK_GetM7Freq(void)2253 static inline uint32_t CLOCK_GetM7Freq(void)
2254 {
2255     return CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
2256 }
2257 
2258 /*!
2259  * @brief Get the CCM CPU/core/system frequency.
2260  *
2261  * @return  Clock frequency; If the clock is invalid, returns 0.
2262  */
CLOCK_GetM4Freq(void)2263 static inline uint32_t CLOCK_GetM4Freq(void)
2264 {
2265     return CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
2266 }
2267 
2268 /*!
2269  * @brief Check if PLL is bypassed
2270  *
2271  * @param pll PLL control name (see @ref clock_pll_t enumeration)
2272  * @return PLL bypass status.
2273  *         - true: The PLL is bypassed.
2274  *         - false: The PLL is not bypassed.
2275  */
CLOCK_IsPllBypassed(clock_pll_t pll)2276 static inline bool CLOCK_IsPllBypassed(clock_pll_t pll)
2277 {
2278     if (pll == kCLOCK_PllArm)
2279     {
2280         return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >>
2281                       ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT);
2282     }
2283     else if (pll == kCLOCK_PllSys2)
2284     {
2285         return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >>
2286                       ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT);
2287     }
2288     else if (pll == kCLOCK_PllSys3)
2289     {
2290         return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >>
2291                       ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT);
2292     }
2293     else
2294     {
2295         return false;
2296     }
2297 }
2298 
2299 /*!
2300  * @brief Check if PLL is enabled
2301  *
2302  * @param pll PLL control name (see @ref clock_pll_t enumeration)
2303  * @return PLL bypass status.
2304  *         - true: The PLL is enabled.
2305  *         - false: The PLL is not enabled.
2306  */
CLOCK_IsPllEnabled(clock_pll_t pll)2307 static inline bool CLOCK_IsPllEnabled(clock_pll_t pll)
2308 {
2309     if (pll == kCLOCK_PllArm)
2310     {
2311         return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >>
2312                       ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT);
2313     }
2314     else if (pll == kCLOCK_PllSys2)
2315     {
2316         return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >>
2317                       ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT);
2318     }
2319     else if (pll == kCLOCK_PllSys3)
2320     {
2321         return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >>
2322                       ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT);
2323     }
2324     else if (pll == kCLOCK_PllSys1)
2325     {
2326         return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >>
2327                       ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT);
2328     }
2329     else if (pll == kCLOCK_PllAudio)
2330     {
2331         return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >>
2332                       ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT);
2333     }
2334     else if (pll == kCLOCK_PllVideo)
2335     {
2336         return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >>
2337                       ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT);
2338     }
2339     else
2340     {
2341         return false;
2342     }
2343 }
2344 
2345 /*!
2346  * @name OSC operations
2347  * @{
2348  */
2349 
2350 /*!
2351  * @brief Gets the RTC clock frequency.
2352  *
2353  * @return  Clock frequency; If the clock is invalid, returns 0.
2354  */
CLOCK_GetRtcFreq(void)2355 static inline uint32_t CLOCK_GetRtcFreq(void)
2356 {
2357     return 32768U;
2358 }
2359 
2360 /*!
2361  * @brief Set the control mode of 48MHz RC oscillator.
2362  *
2363  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2364  */
CLOCK_OSC_SetOsc48MControlMode(clock_control_mode_t controlMode)2365 static inline void CLOCK_OSC_SetOsc48MControlMode(clock_control_mode_t controlMode)
2366 {
2367     ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)) |
2368                                ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(controlMode);
2369 }
2370 
2371 /*!
2372  * @brief Enable/disable 48MHz RC oscillator.
2373  *
2374  * @param enable Used to enable or disable the 48MHz RC oscillator.
2375  *          - \b true Enable the 48MHz RC oscillator.
2376  *          - \b false Dissable the 48MHz RC oscillator.
2377  */
CLOCK_OSC_EnableOsc48M(bool enable)2378 static inline void CLOCK_OSC_EnableOsc48M(bool enable)
2379 {
2380     if (enable)
2381     {
2382         ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_TEN_MASK;
2383     }
2384     else
2385     {
2386         ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_TEN_MASK;
2387     }
2388 }
2389 
2390 /*!
2391  * @brief Set the control mode of the 24MHz clock sourced from 48MHz RC oscillator.
2392  *
2393  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2394  */
CLOCK_OSC_SetOsc48MDiv2ControlMode(clock_control_mode_t controlMode)2395 static inline void CLOCK_OSC_SetOsc48MDiv2ControlMode(clock_control_mode_t controlMode)
2396 {
2397     ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)) |
2398                                ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(controlMode);
2399 }
2400 
2401 /*!
2402  * @brief Enable/disable the 24MHz clock sourced from 48MHz RC oscillator.
2403  *
2404  * @note The 48MHz RC oscillator must be enabled before enabling this 24MHz clock.
2405  *
2406  * @param enable Used to enable/disable the 24MHz clock sourced from 48MHz RC oscillator.
2407  *          - \b true Enable the 24MHz clock sourced from 48MHz.
2408  *          - \b false Disable the 24MHz clock sourced from 48MHz.
2409  */
CLOCK_OSC_EnableOsc48MDiv2(bool enable)2410 static inline void CLOCK_OSC_EnableOsc48MDiv2(bool enable)
2411 {
2412     if (enable)
2413     {
2414         ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK;
2415     }
2416     else
2417     {
2418         ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK;
2419     }
2420 }
2421 
2422 /*!
2423  * @brief Set the control mode of 24MHz crystal oscillator.
2424  *
2425  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2426  */
CLOCK_OSC_SetOsc24MControlMode(clock_control_mode_t controlMode)2427 static inline void CLOCK_OSC_SetOsc24MControlMode(clock_control_mode_t controlMode)
2428 {
2429     ANADIG_OSC->OSC_24M_CTRL = (ANADIG_OSC->OSC_24M_CTRL & ~(ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)) |
2430                                ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(controlMode);
2431 }
2432 
2433 /*! @brief Enable OSC 24Mhz
2434  *
2435  * This function enables OSC 24Mhz.
2436  */
2437 void CLOCK_OSC_EnableOsc24M(void);
2438 
2439 /*!
2440  * @brief Gate/ungate the 24MHz crystal oscillator output.
2441  *
2442  * @note Gating the 24MHz crystal oscillator can save power.
2443  *
2444  * @param enableGate Used to gate/ungate the 24MHz crystal oscillator.
2445  *          - \b true Gate the 24MHz crystal oscillator to save power.
2446  *          - \b false Ungate the 24MHz crystal oscillator.
2447  */
CLOCK_OSC_GateOsc24M(bool enableGate)2448 static inline void CLOCK_OSC_GateOsc24M(bool enableGate)
2449 {
2450     if (enableGate)
2451     {
2452         ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK;
2453     }
2454     else
2455     {
2456         ANADIG_OSC->OSC_24M_CTRL &= ~ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK;
2457     }
2458 }
2459 
2460 /*!
2461  * @brief Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and
2462  * bypass mode.
2463  *
2464  * @param workMode The work mode of 24MHz crystal oscillator, please refer to @ref clock_24MOsc_mode_t for details.
2465  */
2466 void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode);
2467 
2468 /*!
2469  * @brief Set the control mode of 400MHz RC oscillator.
2470  *
2471  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2472  */
CLOCK_OSC_SetOscRc400MControlMode(clock_control_mode_t controlMode)2473 static inline void CLOCK_OSC_SetOscRc400MControlMode(clock_control_mode_t controlMode)
2474 {
2475     ANADIG_OSC->OSC_400M_CTRL1 = (ANADIG_OSC->OSC_400M_CTRL1 & (~ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)) |
2476                                  ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(controlMode);
2477 }
2478 
2479 /*! @brief Enable OSC RC 400Mhz
2480  *
2481  * This function enables OSC RC 400Mhz.
2482  */
2483 void CLOCK_OSC_EnableOscRc400M(void);
2484 
2485 /*!
2486  * @brief Gate/ungate 400MHz RC oscillator.
2487  *
2488  * @param enableGate Used to gate/ungate 400MHz RC oscillator.
2489  *          - \b true Gate the 400MHz RC oscillator.
2490  *          - \b false Ungate the 400MHz RC oscillator.
2491  */
CLOCK_OSC_GateOscRc400M(bool enableGate)2492 static inline void CLOCK_OSC_GateOscRc400M(bool enableGate)
2493 {
2494     if (enableGate)
2495     {
2496         ANADIG_OSC->OSC_400M_CTRL1 |= ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK;
2497     }
2498     else
2499     {
2500         ANADIG_OSC->OSC_400M_CTRL1 &= ~ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK;
2501     }
2502 }
2503 
2504 /*!
2505  * @brief Trims OSC RC 400MHz.
2506  *
2507  * @param enable Used to enable trim function.
2508  * @param bypass Bypass the trim function.
2509  * @param trim Trim value.
2510  */
2511 void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim);
2512 
2513 /*!
2514  * @brief Set the divide value for ref_clk to generate slow clock.
2515  *
2516  * @note slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.
2517  *
2518  * @param divValue The divide value to be set, the available range is 0~63.
2519  */
2520 void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue);
2521 
2522 /*!
2523  * @brief Set the target count for the fast clock.
2524  *
2525  * @param targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per
2526  * divided ref_clk.
2527  */
2528 void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount);
2529 
2530 /*!
2531  * @brief Set the negative and positive hysteresis value for the tuned clock.
2532  *
2533  * @note The hysteresis value should be set after the clock is tuned.
2534  *
2535  * @param negHysteresis The negative hysteresis value for the turned clock, this value in number of clock cycles of the
2536  * fast clock
2537  * @param posHysteresis The positive hysteresis value for the turned clock, this value in number of clock cycles of the
2538  * fast clock
2539  */
2540 void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis);
2541 
2542 /*!
2543  * @brief Bypass/un-bypass the tune logic
2544  *
2545  * @param enableBypass Used to control whether to bypass the turn logic.
2546  *        - \b true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator.
2547  *                  Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency.
2548  *        - \b false Use the output of tune logic to run the oscillator.
2549  */
2550 void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass);
2551 
2552 /*!
2553  * @brief Start/Stop the tune logic.
2554  *
2555  * @param enable Used to start or stop the tune logic.
2556  *          - \b true Start tuning
2557  *          - \b false Stop tuning and reset the tuning logic.
2558  */
2559 void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable);
2560 
2561 /*!
2562  * @brief Freeze/Unfreeze the tuning value.
2563  *
2564  * @param enableFreeze Used to control whether to freeze the tune value.
2565  *          - \b true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value.
2566  *          - \b false Unfreezes and continues the tune operation.
2567  */
2568 void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze);
2569 
2570 /*!
2571  * @brief Set the 400MHz RC oscillator tune value when the tune logic is disabled.
2572  *
2573  * @param tuneValue The tune value to determine the frequency of Oscillator.
2574  */
2575 void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue);
2576 
2577 /*!
2578  * @brief Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output,
2579  * enable the free-running 1MHz clock output, enable the locked 1MHz clock output.
2580  *
2581  * @note The 1MHz clock is divided from 400M RC Oscillator.
2582  *
2583  * @param behavior The behavior of 1MHz output clock, please refer to @ref clock_1MHzOut_behavior_t for details.
2584  */
2585 void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior);
2586 
2587 /*!
2588  * @brief Set the count for the locked 1MHz clock out.
2589  *
2590  * @param count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the
2591  * fast clock per divided ref_clk.
2592  */
2593 void CLOCK_OSC_SetLocked1MHzCount(uint16_t count);
2594 
2595 /*!
2596  * @brief Check the error flag for locked 1MHz clock out.
2597  *
2598  * @return The error flag for locked 1MHz clock out.
2599  *      - \b true The count value has been reached within one diviced ref clock period
2600  *      - \b false No effect.
2601  */
2602 bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void);
2603 
2604 /*!
2605  * @brief Clear the error flag for locked 1MHz clock out.
2606  */
2607 void CLOCK_OSC_ClearLocked1MHzErrorFlag(void);
2608 
2609 /*!
2610  * @brief Get current count for the fast clock during the tune process.
2611  *
2612  * @return The current count for the fast clock.
2613  */
2614 uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void);
2615 
2616 /*!
2617  * @brief Get current tune value used by oscillator during tune process.
2618  *
2619  * @return The current tune value.
2620  */
2621 uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void);
2622 
2623 /*!
2624  * @brief Set the control mode of 16MHz crystal oscillator.
2625  *
2626  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2627  */
CLOCK_OSC_SetOsc16MControlMode(clock_control_mode_t controlMode)2628 static inline void CLOCK_OSC_SetOsc16MControlMode(clock_control_mode_t controlMode)
2629 {
2630     ANADIG_OSC->OSC_16M_CTRL = (ANADIG_OSC->OSC_16M_CTRL & (~ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)) |
2631                                ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(controlMode);
2632 }
2633 
2634 /*!
2635  * @brief Configure the 16MHz oscillator.
2636  *
2637  * @param source Used to select the source for 16MHz RC oscillator, please refer to @ref clock_16MOsc_source_t.
2638  * @param enablePowerSave Enable/disable power save mode function at 16MHz OSC.
2639  *          - \b true Enable power save mode function at 16MHz osc.
2640  *          - \b false Disable power save mode function at 16MHz osc.
2641  * @param enableClockOut Enable/Disable clock output for 16MHz RCOSC.
2642  *          - \b true Enable clock output for 16MHz RCOSC.
2643  *          - \b false Disable clock output for 16MHz RCOSC.
2644  */
2645 void CLOCK_OSC_SetOsc16MConfig(clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut);
2646 
2647 /* @} */
2648 
2649 /*!
2650  * @brief Initialize the ARM PLL.
2651  *
2652  * This function initialize the ARM PLL with specific settings
2653  *
2654  * @param config   configuration to set to PLL.
2655  */
2656 void CLOCK_InitArmPll(const clock_arm_pll_config_t *config);
2657 
2658 /*!
2659  * @brief Calculate corresponding config values per given frequency
2660  *
2661  * This function calculates config valudes per given frequency for Arm PLL
2662  *
2663  * @param config pll config structure
2664  * @param freqInMhz target frequency
2665  */
2666 status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz);
2667 
2668 /*!
2669  * @brief Initializes the Arm PLL with Specific Frequency (in Mhz).
2670  *
2671  * This function initializes the Arm PLL with specific frequency
2672  *
2673  * @param freqInMhz target frequency
2674  */
2675 status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz);
2676 
2677 /*!
2678  * @brief De-initialize the ARM PLL.
2679  */
2680 void CLOCK_DeinitArmPll(void);
2681 
2682 /*!
2683  * @brief Calculate spread spectrum step and stop.
2684  *
2685  * This function calculate spread spectrum step and stop according to given
2686  * parameters. For integer PLL (syspll2) the factor is mfd, while for other
2687  * fractional PLLs (audio/video/syspll1), the factor is denominator.
2688  *
2689  * @param factor factor to calculate step/stop
2690  * @param range spread spectrum range
2691  * @param mod spread spectrum modulation frequency
2692  * @param ss calculated spread spectrum values
2693  *
2694  */
2695 void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss);
2696 
2697 /*!
2698  * @brief Initialize the System PLL1.
2699  *
2700  * This function initializes the System PLL1 with specific settings
2701  *
2702  * @param config Configuration to set to PLL1.
2703  */
2704 void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config);
2705 
2706 /*!
2707  * @brief De-initialize the System PLL1.
2708  */
2709 void CLOCK_DeinitSysPll1(void);
2710 
2711 /*!
2712  * @brief Set System PLL1 output frequency in GPC mode.
2713  *
2714  * @param config Pointer to @ref clock_sys_pll1_gpc_config_t.
2715  */
2716 void CLOCK_GPC_SetSysPll1OutputFreq(const clock_sys_pll1_gpc_config_t *config);
2717 
2718 /*!
2719  * @brief Initialize the System PLL2.
2720  *
2721  * This function initializes the System PLL2 with specific settings
2722  *
2723  * @param config Configuration to configure spread spectrum. This parameter can
2724  *            be NULL, if no need to enabled spread spectrum
2725  */
2726 void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config);
2727 
2728 /*!
2729  * @brief De-initialize the System PLL2.
2730  */
2731 void CLOCK_DeinitSysPll2(void);
2732 
2733 /*!
2734  * @brief Check if Sys PLL2 PFD is enabled
2735  *
2736  * @param pfd PFD control name
2737  * @return PFD bypass status.
2738  *         - true: power on.
2739  *         - false: power off.
2740  */
2741 bool CLOCK_IsSysPll2PfdEnabled(clock_pfd_t pfd);
2742 
2743 /*!
2744  * @brief Initialize the System PLL3.
2745  *
2746  * This function initializes the System PLL3 with specific settings
2747  *
2748  */
2749 void CLOCK_InitSysPll3(void);
2750 
2751 /*!
2752  * @brief De-initialize the System PLL3.
2753  */
2754 void CLOCK_DeinitSysPll3(void);
2755 
2756 /*!
2757  * @brief Check if Sys PLL3 PFD is enabled
2758  *
2759  * @param pfd PFD control name
2760  * @return PFD bypass status.
2761  *         - true: power on.
2762  *         - false: power off.
2763  */
2764 bool CLOCK_IsSysPll3PfdEnabled(clock_pfd_t pfd);
2765 
2766 /*!
2767  * @name PLL/PFD operations
2768  * @{
2769  */
2770 /*!
2771  * @brief PLL bypass setting
2772  *
2773  * @param pll PLL control name (see @ref clock_pll_t enumeration)
2774  * @param bypass Bypass the PLL.
2775  *               - true: Bypass the PLL.
2776  *               - false:Not bypass the PLL.
2777  */
2778 void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass);
2779 
2780 /*!
2781  * @brief Calculate corresponding config values per given frequency
2782  *
2783  * This function calculates config valudes per given frequency for Audio/Video
2784  * PLL.
2785  *
2786  * @param config pll config structure
2787  * @param freqInMhz target frequency
2788  */
2789 status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *config, uint32_t freqInMhz);
2790 
2791 /*!
2792  * @brief Initializes the Audio PLL with Specific Frequency (in Mhz).
2793  *
2794  * This function initializes the Audio PLL with specific frequency
2795  *
2796  * @param freqInMhz target frequency
2797  * @param ssEnable  enable spread spectrum or not
2798  * @param ssRange   range spread spectrum range
2799  * @param ssMod spread spectrum modulation frequency
2800  */
2801 status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod);
2802 
2803 /*!
2804  * @brief Initializes the Audio PLL.
2805  *
2806  * This function initializes the Audio PLL with specific settings
2807  *
2808  * @param config Configuration to set to PLL.
2809  */
2810 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
2811 
2812 /*!
2813  * @brief De-initialize the Audio PLL.
2814  */
2815 void CLOCK_DeinitAudioPll(void);
2816 
2817 /*!
2818  * @brief Set Audio PLL output frequency in GPC mode.
2819  *
2820  * @param config Pointer to clock_audio_pll_gpc_config_t structure.
2821  */
2822 void CLOCK_GPC_SetAudioPllOutputFreq(const clock_audio_pll_gpc_config_t *config);
2823 
2824 /*!
2825  * @brief Initializes the Video PLL with Specific Frequency (in Mhz).
2826  *
2827  * This function initializes the Video PLL with specific frequency
2828  *
2829  * @param freqInMhz target frequency
2830  * @param ssEnable  enable spread spectrum or not
2831  * @param ssRange   range spread spectrum range
2832  * @param ssMod spread spectrum modulation frequency
2833  */
2834 status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod);
2835 
2836 /*!
2837  * @brief Initialize the video PLL.
2838  *
2839  * This function configures the Video PLL with specific settings
2840  *
2841  * @param config   configuration to set to PLL.
2842  */
2843 void CLOCK_InitVideoPll(const clock_video_pll_config_t *config);
2844 
2845 /*!
2846  * @brief De-initialize the Video PLL.
2847  */
2848 void CLOCK_DeinitVideoPll(void);
2849 
2850 /*!
2851  * @brief Set Video PLL output frequency in GPC mode.
2852  *
2853  * @param config Pointer to clock_audio_pll_gpc_config_t structure.
2854  */
2855 void CLOCK_GPC_SetVideoPllOutputFreq(const clock_video_pll_gpc_config_t *config);
2856 /*!
2857  * @brief Get current PLL output frequency.
2858  *
2859  * This function get current output frequency of specific PLL
2860  *
2861  * @param pll   pll name to get frequency.
2862  * @return The PLL output frequency in hertz.
2863  */
2864 uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
2865 
2866 /*!
2867  * @brief Initialize PLL PFD.
2868  *
2869  * This function initializes the System PLL PFD. During new value setting,
2870  * the clock output is disabled to prevent glitch.
2871  *
2872  * @param pll Which PLL of targeting PFD to be operated.
2873  * @param pfd Which PFD clock to enable.
2874  * @param frac The PFD FRAC value.
2875  * @note It is recommended that PFD settings are kept between 12-35.
2876  */
2877 void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac);
2878 
2879 /*!
2880  * @brief Get current PFD output frequency.
2881  *
2882  * This function get current output frequency of specific System PLL PFD
2883  *
2884  * @param pll Which PLL of targeting PFD to be operated.
2885  * @param pfd pfd name to get frequency.
2886  * @return The PFD output frequency in hertz.
2887  */
2888 uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd);
2889 
2890 uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex);
2891 
2892 /*! @brief Enable USB HS clock.
2893  *
2894  * This function only enables the access to USB HS prepheral, upper layer
2895  * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
2896  * clock to use USB HS.
2897  *
2898  * @param src  USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
2899  * @param freq USB HS does not care about the clock source, so this parameter is ignored.
2900  * @retval true The clock is set successfully.
2901  * @retval false The clock source is invalid to get proper USB HS clock.
2902  */
2903 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
2904 
2905 /*! @brief Enable USB HS clock.
2906  *
2907  * This function only enables the access to USB HS prepheral, upper layer
2908  * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
2909  * clock to use USB HS.
2910  *
2911  * @param src  USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
2912  * @param freq USB HS does not care about the clock source, so this parameter is ignored.
2913  * @retval true The clock is set successfully.
2914  * @retval false The clock source is invalid to get proper USB HS clock.
2915  */
2916 bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
2917 
2918 /*! @brief Enable USB HS PHY PLL clock.
2919  *
2920  * This function enables the internal 480MHz USB PHY PLL clock.
2921  *
2922  * @param src  USB HS PHY PLL clock source.
2923  * @param freq The frequency specified by src.
2924  * @retval true The clock is set successfully.
2925  * @retval false The clock source is invalid to get proper USB HS clock.
2926  */
2927 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
2928 
2929 /*! @brief Disable USB HS PHY PLL clock.
2930  *
2931  * This function disables USB HS PHY PLL clock.
2932  */
2933 void CLOCK_DisableUsbhs0PhyPllClock(void);
2934 
2935 /*! @brief Enable USB HS PHY PLL clock.
2936  *
2937  * This function enables the internal 480MHz USB PHY PLL clock.
2938  *
2939  * @param src  USB HS PHY PLL clock source.
2940  * @param freq The frequency specified by src.
2941  * @retval true The clock is set successfully.
2942  * @retval false The clock source is invalid to get proper USB HS clock.
2943  */
2944 bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
2945 
2946 /*! @brief Disable USB HS PHY PLL clock.
2947  *
2948  * This function disables USB HS PHY PLL clock.
2949  */
2950 void CLOCK_DisableUsbhs1PhyPllClock(void);
2951 
2952 /*!
2953  * @brief Lock low power and access control mode for this clock.
2954  *
2955  * @note When this bit is set, bits 16-20 can not be changed until next system reset.
2956  *
2957  * @param name Clock source name, see \ref clock_name_t.
2958  */
CLOCK_OSCPLL_LockControlMode(clock_name_t name)2959 static inline void CLOCK_OSCPLL_LockControlMode(clock_name_t name)
2960 {
2961     CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK;
2962 }
2963 
2964 /*!
2965  * @brief Lock the value of Domain ID white list for this clock.
2966  *
2967  * @note Once locked, this bit and domain ID white list can not be changed until next system reset.
2968  *
2969  * @param name Clock source name, see \ref clock_name_t.
2970  */
CLOCK_OSCPLL_LockWhiteList(clock_name_t name)2971 static inline void CLOCK_OSCPLL_LockWhiteList(clock_name_t name)
2972 {
2973     CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK;
2974 }
2975 
2976 /*!
2977  * @brief Set domain ID that can change this clock.
2978  *
2979  * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.
2980  *
2981  * @param name Clock source name, see \ref clock_name_t.
2982  * @param domainId Domains that on the whitelist can change this clock.
2983  */
CLOCK_OSCPLL_SetWhiteList(clock_name_t name,uint8_t domainId)2984 static inline void CLOCK_OSCPLL_SetWhiteList(clock_name_t name, uint8_t domainId)
2985 {
2986     CCM->OSCPLL[name].AUTHEN =
2987         (CCM->OSCPLL[name].AUTHEN & ~CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId);
2988 }
2989 
2990 /*!
2991  * @brief Check whether this clock implement SetPoint control scheme.
2992  *
2993  * @param name Clock source name, see \ref clock_name_t.
2994  * @return  Clock source SetPoint implement status.
2995  *         - true: SetPoint is implemented.
2996  *         - false: SetPoint is not implemented.
2997  */
CLOCK_OSCPLL_IsSetPointImplemented(clock_name_t name)2998 static inline bool CLOCK_OSCPLL_IsSetPointImplemented(clock_name_t name)
2999 {
3000     return (((CCM->OSCPLL[name].CONFIG & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK) >>
3001              CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL);
3002 }
3003 
3004 /*!
3005  * @brief Set this clock works in Unassigned Mode.
3006  *
3007  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3008  *
3009  * @param name Clock source name, see \ref clock_name_t.
3010  */
CLOCK_OSCPLL_ControlByUnassignedMode(clock_name_t name)3011 static inline void CLOCK_OSCPLL_ControlByUnassignedMode(clock_name_t name)
3012 {
3013     CCM->OSCPLL[name].AUTHEN &=
3014         ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK);
3015 }
3016 
3017 /*!
3018  * @brief Set this clock works in SetPoint control Mode.
3019  *
3020  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3021  *
3022  * @param name Clock source name, see \ref clock_name_t.
3023  * @param spValue Bit0~Bit15 hold value for Setpoint 0~16 respectively.
3024  *                A bitfield value of 0 implies clock will be shutdown in this Setpoint.
3025  *                A bitfield value of 1 implies clock will be turn on in this Setpoint.
3026  * @param stbyValue Bit0~Bit15 hold value for Setpoint 0~16 standby.
3027  *                A bitfield value of 0 implies clock will be shutdown during standby.
3028  *                A bitfield value of 1 represent clock will keep Setpoint setting during standby.
3029  */
3030 void CLOCK_OSCPLL_ControlBySetPointMode(clock_name_t name, uint16_t spValue, uint16_t stbyValue);
3031 
3032 /*!
3033  * @brief Set this clock works in CPU Low Power Mode.
3034  *
3035  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3036  *
3037  * @param name Clock source name, see \ref clock_name_t.
3038  * @param domainId Domains that on the whitelist can change this clock.
3039  * @param level0,level1 Depend level of this clock.
3040  */
3041 void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name,
3042                                            uint8_t domainId,
3043                                            clock_level_t level0,
3044                                            clock_level_t level1);
3045 
3046 /*!
3047  * @brief Set clock depend level for current accessing domain.
3048  *
3049  * @note This setting only take effects in CPU Low Power Mode.
3050  *
3051  * @param name Clock source name, see \ref clock_name_t.
3052  * @param level Depend level of this clock.
3053  */
CLOCK_OSCPLL_SetCurrentClockLevel(clock_name_t name,clock_level_t level)3054 static inline void CLOCK_OSCPLL_SetCurrentClockLevel(clock_name_t name, clock_level_t level)
3055 {
3056     CCM->OSCPLL[name].DOMAINr =
3057         (CCM->OSCPLL[name].DOMAINr & ~CCM_OSCPLL_DOMAIN_LEVEL_MASK) | CCM_OSCPLL_DOMAIN_LEVEL(level);
3058 }
3059 
3060 /*!
3061  * @brief Set this clock works in Domain Mode.
3062  *
3063  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3064  *
3065  * @param name Clock source name, see \ref clock_name_t.
3066  * @param domainId Domains that on the whitelist can change this clock.
3067  */
CLOCK_OSCPLL_ControlByDomainMode(clock_name_t name,uint8_t domainId)3068 static inline void CLOCK_OSCPLL_ControlByDomainMode(clock_name_t name, uint8_t domainId)
3069 {
3070     CCM->OSCPLL[name].AUTHEN =
3071         (CCM->OSCPLL[name].AUTHEN &
3072          ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)) |
3073         CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId);
3074 }
3075 
3076 /*!
3077  * @brief Lock low power and access control mode for this clock.
3078  *
3079  * @note When this bit is set, bits 16-20 can not be changed until next system reset.
3080  *
3081  * @param name Clock root name, see \ref clock_root_t.
3082  */
CLOCK_ROOT_LockControlMode(clock_root_t name)3083 static inline void CLOCK_ROOT_LockControlMode(clock_root_t name)
3084 {
3085     CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK;
3086 }
3087 
3088 /*!
3089  * @brief Lock the value of Domain ID white list for this clock.
3090  *
3091  * @note Once locked, this bit and domain ID white list can not be changed until next system reset.
3092  *
3093  * @param name Clock root name, see \ref clock_root_t.
3094  */
CLOCK_ROOT_LockWhiteList(clock_root_t name)3095 static inline void CLOCK_ROOT_LockWhiteList(clock_root_t name)
3096 {
3097     CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK;
3098 }
3099 
3100 /*!
3101  * @brief Set domain ID that can change this clock.
3102  *
3103  * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.
3104  *
3105  * @param name Clock root name, see \ref clock_root_t.
3106  * @param domainId Domains that on the whitelist can change this clock.
3107  */
CLOCK_ROOT_SetWhiteList(clock_root_t name,uint8_t domainId)3108 static inline void CLOCK_ROOT_SetWhiteList(clock_root_t name, uint8_t domainId)
3109 {
3110     CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK) |
3111                                    CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(domainId);
3112 }
3113 
3114 /*!
3115  * @brief Check whether this clock implement SetPoint control scheme.
3116  *
3117  * @param name Clock root name, see \ref clock_root_t.
3118  * @return  Clock root SetPoint implement status.
3119  *         - true: SetPoint is implemented.
3120  *         - false: SetPoint is not implemented.
3121  */
CLOCK_ROOT_IsSetPointImplemented(clock_root_t name)3122 static inline bool CLOCK_ROOT_IsSetPointImplemented(clock_root_t name)
3123 {
3124     return (((CCM->CLOCK_ROOT[name].CONFIG & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK) >>
3125              CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL);
3126 }
3127 
3128 /*!
3129  * @brief Set this clock works in Unassigned Mode.
3130  *
3131  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3132  *
3133  * @param name Clock root name, see \ref clock_root_t.
3134  */
CLOCK_ROOT_ControlByUnassignedMode(clock_root_t name)3135 static inline void CLOCK_ROOT_ControlByUnassignedMode(clock_root_t name)
3136 {
3137     CCM->CLOCK_ROOT[name].AUTHEN &=
3138         ~(CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK);
3139 }
3140 
3141 /*!
3142  * @brief Configure one SetPoint for this clock.
3143  *
3144  * @note SetPoint value could only be changed in Unassigend Mode.
3145  *
3146  * @param name Which clock root to set, see \ref clock_root_t.
3147  * @param spIndex Which SetPoint of this clock root to set.
3148  * @param config SetPoint config, see \ref clock_root_setpoint_config_t
3149  */
CLOCK_ROOT_ConfigSetPoint(clock_root_t name,uint16_t spIndex,const clock_root_setpoint_config_t * config)3150 static inline void CLOCK_ROOT_ConfigSetPoint(clock_root_t name,
3151                                              uint16_t spIndex,
3152                                              const clock_root_setpoint_config_t *config)
3153 {
3154     assert(config != NULL);
3155     CCM->CLOCK_ROOT[name].SETPOINT[spIndex] =
3156         CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(config->grade) |
3157         CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(config->mux) |
3158         CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV((uint32_t)config->div - 1UL) |
3159         CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(config->clockOff);
3160 }
3161 
3162 /*!
3163  * @brief Enable SetPoint control for this clock root.
3164  *
3165  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3166  *
3167  * @param name Clock root name, see \ref clock_root_t.
3168  */
CLOCK_ROOT_EnableSetPointControl(clock_root_t name)3169 static inline void CLOCK_ROOT_EnableSetPointControl(clock_root_t name)
3170 {
3171     CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK) |
3172                                    CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK;
3173 }
3174 
3175 /*!
3176  * @brief Set this clock works in SetPoint controlled Mode.
3177  *
3178  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3179  *
3180  * @param name Clock root name, see \ref clock_root_t.
3181  * @param spTable Point to the array that stores clock root settings for each setpoint. Note that the pointed array must
3182  * have 16 elements.
3183  */
3184 void CLOCK_ROOT_ControlBySetPointMode(clock_root_t name, const clock_root_setpoint_config_t *spTable);
3185 
3186 /*!
3187  * @brief Set this clock works in CPU Low Power Mode.
3188  *
3189  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3190  *
3191  * @param name Clock root name, see \ref clock_root_t.
3192  * @param domainId Domains that on the whitelist can change this clock.
3193  */
CLOCK_ROOT_ControlByDomainMode(clock_root_t name,uint8_t domainId)3194 static inline void CLOCK_ROOT_ControlByDomainMode(clock_root_t name, uint8_t domainId)
3195 {
3196     CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~(CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK |
3197                                                                      CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)) |
3198                                    CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(domainId);
3199 }
3200 
3201 /*!
3202  * @brief Lock low power and access control mode for this clock.
3203  *
3204  * @note When this bit is set, bits 16-20 can not be changed until next system reset.
3205  *
3206  * @param name Clock gate name, see \ref clock_lpcg_t.
3207  */
CLOCK_LPCG_LockControlMode(clock_lpcg_t name)3208 static inline void CLOCK_LPCG_LockControlMode(clock_lpcg_t name)
3209 {
3210     CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_MODE_MASK;
3211 }
3212 
3213 /*!
3214  * @brief Lock the value of Domain ID white list for this clock.
3215  *
3216  * @note Once locked, this bit and domain ID white list can not be changed until next system reset.
3217  *
3218  * @param name Clock gate name, see \ref clock_lpcg_t.
3219  */
CLOCK_LPCG_LockWhiteList(clock_lpcg_t name)3220 static inline void CLOCK_LPCG_LockWhiteList(clock_lpcg_t name)
3221 {
3222     CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_LIST_MASK;
3223 }
3224 
3225 /*!
3226  * @brief Set domain ID that can change this clock.
3227  *
3228  * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.
3229  *
3230  * @param name Clock gate name, see \ref clock_lpcg_t.
3231  * @param domainId Domains that on the whitelist can change this clock.
3232  */
CLOCK_LPCG_SetWhiteList(clock_lpcg_t name,uint8_t domainId)3233 static inline void CLOCK_LPCG_SetWhiteList(clock_lpcg_t name, uint8_t domainId)
3234 {
3235     CCM->LPCG[name].AUTHEN =
3236         (CCM->LPCG[name].AUTHEN & ~CCM_LPCG_AUTHEN_WHITE_LIST_MASK) | CCM_LPCG_AUTHEN_WHITE_LIST(domainId);
3237 }
3238 
3239 /*!
3240  * @brief Check whether this clock implement SetPoint control scheme.
3241  *
3242  * @param name Clock gate name, see \ref clock_lpcg_t.
3243  * @return  Clock gate SetPoint implement status.
3244  *         - true: SetPoint is implemented.
3245  *         - false: SetPoint is not implemented.
3246  */
CLOCK_LPCG_IsSetPointImplemented(clock_lpcg_t name)3247 static inline bool CLOCK_LPCG_IsSetPointImplemented(clock_lpcg_t name)
3248 {
3249     return (((CCM->LPCG[name].CONFIG & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK) >>
3250              CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL);
3251 }
3252 
3253 /*!
3254  * @brief Set this clock works in Unassigned Mode.
3255  *
3256  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3257  *
3258  * @param name Clock gate name, see \ref clock_lpcg_t.
3259  */
CLOCK_LPCG_ControlByUnassignedMode(clock_lpcg_t name)3260 static inline void CLOCK_LPCG_ControlByUnassignedMode(clock_lpcg_t name)
3261 {
3262     CCM->LPCG[name].AUTHEN &=
3263         ~(CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK);
3264 }
3265 
3266 /*!
3267  * @brief Set this clock works in SetPoint control Mode.
3268  *
3269  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3270  *
3271  * @param name Clock gate name, see \ref clock_lpcg_t.
3272  * @param spValue Bit0~Bit15 hold value for Setpoint 0~16 respectively.
3273  *                A bitfield value of 0 implies clock will be shutdown in this Setpoint.
3274  *                A bitfield value of 1 implies clock will be turn on in this Setpoint.
3275  * @param stbyValue Bit0~Bit15 hold value for Setpoint 0~16 standby.
3276  *                A bitfield value of 0 implies clock will be shutdown during standby.
3277  *                A bitfield value of 1 represent clock will keep Setpoint setting during standby.
3278  */
3279 void CLOCK_LPCG_ControlBySetPointMode(clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue);
3280 
3281 /*!
3282  * @brief Set this clock works in CPU Low Power Mode.
3283  *
3284  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3285  *
3286  * @param name Clock gate name, see \ref clock_lpcg_t.
3287  * @param domainId Domains that on the whitelist can change this clock.
3288  * @param level0,level1 Depend level of this clock.
3289  */
3290 void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name,
3291                                          uint8_t domainId,
3292                                          clock_level_t level0,
3293                                          clock_level_t level1);
3294 
3295 /*!
3296  * @brief Set clock depend level for current accessing domain.
3297  *
3298  * @note This setting only take effects in CPU Low Power Mode.
3299  *
3300  * @param name Clock gate name, see \ref clock_lpcg_t.
3301  * @param level Depend level of this clock.
3302  */
CLOCK_LPCG_SetCurrentClockLevel(clock_lpcg_t name,clock_level_t level)3303 static inline void CLOCK_LPCG_SetCurrentClockLevel(clock_lpcg_t name, clock_level_t level)
3304 {
3305     CCM->LPCG[name].DOMAINr = (CCM->LPCG[name].DOMAINr & ~CCM_LPCG_DOMAIN_LEVEL_MASK) | CCM_LPCG_DOMAIN_LEVEL(level);
3306 }
3307 
3308 /*!
3309  * @brief Set this clock works in Domain Mode.
3310  *
3311  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3312  *
3313  * @param name Clock gate name, see \ref clock_lpcg_t.
3314  * @param domainId Domains that on the whitelist can change this clock.
3315  */
CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name,uint8_t domainId)3316 static inline void CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name, uint8_t domainId)
3317 {
3318     CCM->LPCG[name].AUTHEN =
3319         (CCM->LPCG[name].AUTHEN &
3320          ~(CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK | CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_WHITE_LIST_MASK)) |
3321         CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_WHITE_LIST(domainId);
3322 }
3323 
3324 /* @} */
3325 
3326 #if defined(__cplusplus)
3327 }
3328 #endif /* __cplusplus */
3329 
3330 /*! @} */
3331 
3332 #endif /* _FSL_CLOCK_H_ */
3333