1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CLOCK_IP_SPECIFIC_H 8 #define CLOCK_IP_SPECIFIC_H 9 10 /** 11 * @file Clock_Ip_Specific.h 12 * @version 2.0.0 13 * 14 * @brief CLOCK IP specific header file. 15 * @details CLOCK IP specific header file. 16 17 * @addtogroup CLOCK_DRIVER Clock Ip Driver 18 * @{ 19 */ 20 21 #if defined(__cplusplus) 22 extern "C"{ 23 #endif 24 /*================================================================================================== 25 * INCLUDE FILES 26 * 1) system and project includes 27 * 2) needed interfaces from external units 28 * 3) internal and external interfaces from this unit 29 ==================================================================================================*/ 30 #include "Clock_Ip_Cfg_Defines.h" 31 32 #if defined (CLOCK_IP_S32K148) 33 #include "S32K148_SIM.h" 34 #include "S32K148_SCG.h" 35 #include "S32K148_PCC.h" 36 #include "S32K148_SMC.h" 37 #include "S32K148_QUADSPI.h" 38 39 #elif defined (CLOCK_IP_S32K116) 40 #include "S32K116_SIM.h" 41 #include "S32K116_SCG.h" 42 #include "S32K116_PCC.h" 43 #include "S32K116_SMC.h" 44 #include "S32K116_CMU.h" 45 46 #elif defined (CLOCK_IP_S32K118) 47 #include "S32K118_SIM.h" 48 #include "S32K118_SCG.h" 49 #include "S32K118_PCC.h" 50 #include "S32K118_SMC.h" 51 #include "S32K118_CMU.h" 52 53 #elif defined (CLOCK_IP_S32K142) 54 #include "S32K142_SIM.h" 55 #include "S32K142_SCG.h" 56 #include "S32K142_PCC.h" 57 #include "S32K142_SMC.h" 58 59 #elif defined (CLOCK_IP_S32K142W) 60 #include "S32K142W_SIM.h" 61 #include "S32K142W_SCG.h" 62 #include "S32K142W_PCC.h" 63 #include "S32K142W_SMC.h" 64 65 #elif defined (CLOCK_IP_S32K144) 66 #include "S32K144_SIM.h" 67 #include "S32K144_SCG.h" 68 #include "S32K144_PCC.h" 69 #include "S32K144_SMC.h" 70 71 #elif defined (CLOCK_IP_S32K144W) 72 #include "S32K144W_SIM.h" 73 #include "S32K144W_SCG.h" 74 #include "S32K144W_PCC.h" 75 #include "S32K144W_SMC.h" 76 77 #elif defined (CLOCK_IP_S32K146) 78 #include "S32K146_SIM.h" 79 #include "S32K146_SCG.h" 80 #include "S32K146_PCC.h" 81 #include "S32K146_SMC.h" 82 83 #elif (defined (CLOCK_IP_S32M244) || defined (CLOCK_IP_S32M242) || defined (CLOCK_IP_S32M241) || defined (CLOCK_IP_S32M243)) 84 #include "S32M24x_SIM.h" 85 #include "S32M24x_SCG.h" 86 #include "S32M24x_PCC.h" 87 #include "S32M24x_SMC.h" 88 89 #endif 90 91 #include "Mcal.h" 92 93 /*================================================================================================== 94 SOURCE FILE VERSION INFORMATION 95 ==================================================================================================*/ 96 #define CLOCK_IP_SPECIFIC_VENDOR_ID 43 97 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION 4 98 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION 7 99 #define CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION 0 100 #define CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION 2 101 #define CLOCK_IP_SPECIFIC_SW_MINOR_VERSION 0 102 #define CLOCK_IP_SPECIFIC_SW_PATCH_VERSION 0 103 104 /*================================================================================================== 105 FILE VERSION CHECKS 106 ==================================================================================================*/ 107 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Cfg_Defines.h file are of the same vendor */ 108 #if (CLOCK_IP_SPECIFIC_VENDOR_ID != CLOCK_IP_CFG_DEFINES_VENDOR_ID) 109 #error "Clock_Ip_Specific.h and Clock_Ip_Cfg_Defines.h have different vendor ids" 110 #endif 111 112 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Cfg_Defines.h file are of the same Autosar version */ 113 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ 114 (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ 115 (CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION) \ 116 ) 117 #error "AutoSar Version Numbers of Clock_Ip_Specific.h and Clock_Ip_Cfg_Defines.h are different" 118 #endif 119 120 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Cfg_Defines.h file are of the same Software version */ 121 #if ((CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ 122 (CLOCK_IP_SPECIFIC_SW_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ 123 (CLOCK_IP_SPECIFIC_SW_PATCH_VERSION != CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION) \ 124 ) 125 #error "Software Version Numbers of Clock_Ip_Specific.h and Clock_Ip_Cfg_Defines.h are different" 126 #endif 127 128 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 129 /* Check if Clock_Ip_Specific.h file and Mcal.h file are of the same Autosar version */ 130 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ 131 (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION)) 132 #error "AutoSar Version Numbers of Clock_Ip_Specific.h and Mcal.h are different" 133 #endif 134 #endif 135 136 /*================================================================================================== 137 * CONSTANTS 138 ==================================================================================================*/ 139 140 /*================================================================================================== 141 * DEFINES AND MACROS 142 ==================================================================================================*/ 143 #if (defined (CLOCK_IP_S32K118) || defined(CLOCK_IP_S32K116)) 144 145 #define CLOCK_IP_DIVIDER_CALLBACKS_COUNT 11U 146 #define CLOCK_IP_SCG_ASYNC_DIV1 1U 147 #define CLOCK_IP_SCG_ASYNC_DIV2 2U 148 #define CLOCK_IP_SCG_DIVCORE_RUN 3U 149 #define CLOCK_IP_SCG_DIVBUS_RUN 4U 150 #define CLOCK_IP_SCG_DIVSLOW_RUN 5U 151 #define CLOCK_IP_SCG_DIVCORE_VLPR 6U 152 #define CLOCK_IP_SCG_DIVBUS_VLPR 7U 153 #define CLOCK_IP_SCG_DIVSLOW_VLPR 8U 154 #define CLOCK_IP_SIM_CLKOUT_DIV 9U 155 #define CLOCK_IP_PCC_PCD_FRAC 10U 156 157 #define CLOCK_IP_DIVIDERTRIGGER_CALLBACKS_COUNT 1U 158 159 #define CLOCK_IP_XOSC_CALLBACKS_COUNT 2U 160 #define CLOCK_IP_SOSC_ENABLE 1U 161 162 #define CLOCK_IP_IRCOSC_CALLBACKS_COUNT 5U 163 #define CLOCK_IP_SIRC_ENABLE 1U 164 #define CLOCK_IP_SIRC_VLP_ENABLE 2U 165 #define CLOCK_IP_SIRC_STOP_ENABLE 3U 166 #define CLOCK_IP_FIRC_ENABLE 4U 167 168 #define CLOCK_IP_GATE_CALLBACKS_COUNT 6U 169 #define CLOCK_IP_PCC_CGC_ENABLE 1U 170 #define CLOCK_IP_SIM_CLKOUT_ENABLE 2U 171 #define CLOCK_IP_SIM_LPO32K_ENABLE 3U 172 #define CLOCK_IP_SIM_LPO1K_ENABLE 4U 173 #define CLOCK_IP_SIM_PLATCGC_CGC 5U 174 175 #define CLOCK_IP_FRACTIONAL_DIVIDER_CALLBACKS_COUNT 1U 176 #define CLOCK_IP_NUMBER_OF_HARDWARE_DFS 0U 177 178 #define CLOCK_IP_PLL_CALLBACKS_COUNT 1U 179 180 #define CLOCK_IP_SELECTOR_CALLBACKS_COUNT 9U 181 #define CLOCK_IP_SCG_SCS_RUN_SEL 1U 182 #define CLOCK_IP_SCG_SCS_VLPR_SEL 2U 183 #define CLOCK_IP_SIM_RTC_SEL 3U 184 #define CLOCK_IP_SIM_LPO_SEL 4U 185 #define CLOCK_IP_SCG_CLKOUT_SEL 5U 186 #define CLOCK_IP_SIM_FTMOPT_SEL 6U 187 #define CLOCK_IP_SIM_CLKOUT_SEL 7U 188 #define CLOCK_IP_PCC_PCS_SELECT 8U 189 190 #define CLOCK_IP_PCFS_CALLBACKS_COUNT 1U 191 192 #define CLOCK_IP_CMU_CALLBACKS_COUNT 2U 193 #define CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF 1U 194 195 #define CLOCK_IP_ALL_CALLBACKS_COUNT 11U 196 197 #elif (defined (CLOCK_IP_S32K142W) || defined(CLOCK_IP_S32K144W) || defined(CLOCK_IP_S32M244) || \ 198 defined(CLOCK_IP_S32M242) || defined(CLOCK_IP_S32M241) || defined(CLOCK_IP_S32M243)) 199 200 #define CLOCK_IP_DIVIDER_CALLBACKS_COUNT 12U 201 #define CLOCK_IP_SCG_ASYNC_DIV1 1U 202 #define CLOCK_IP_SCG_ASYNC_DIV2 2U 203 #define CLOCK_IP_SCG_DIVCORE_RUN 3U 204 #define CLOCK_IP_SCG_DIVBUS_RUN 4U 205 #define CLOCK_IP_SCG_DIVSLOW_RUN 5U 206 #define CLOCK_IP_SCG_DIVCORE_VLPR 6U 207 #define CLOCK_IP_SCG_DIVBUS_VLPR 7U 208 #define CLOCK_IP_SCG_DIVSLOW_VLPR 8U 209 #define CLOCK_IP_SIM_CLKOUT_DIV 9U 210 #define CLOCK_IP_PCC_PCD_FRAC 10U 211 #define CLOCK_IP_SIM_TRACE_DIV_MUL 11U 212 213 #define CLOCK_IP_DIVIDERTRIGGER_CALLBACKS_COUNT 1U 214 215 #define CLOCK_IP_XOSC_CALLBACKS_COUNT 2U 216 #define CLOCK_IP_SOSC_ENABLE 1U 217 218 #define CLOCK_IP_IRCOSC_CALLBACKS_COUNT 5U 219 #define CLOCK_IP_SIRC_ENABLE 1U 220 #define CLOCK_IP_SIRC_VLP_ENABLE 2U 221 #define CLOCK_IP_SIRC_STOP_ENABLE 3U 222 #define CLOCK_IP_FIRC_ENABLE 4U 223 224 #define CLOCK_IP_GATE_CALLBACKS_COUNT 7U 225 #define CLOCK_IP_PCC_CGC_ENABLE 1U 226 #define CLOCK_IP_SIM_CLKOUT_ENABLE 2U 227 #define CLOCK_IP_SIM_LPO32K_ENABLE 3U 228 #define CLOCK_IP_SIM_LPO1K_ENABLE 4U 229 #define CLOCK_IP_SIM_PLATCGC_CGC 5U 230 #define CLOCK_IP_SIM_TRACE_ENABLE 6U 231 232 #define CLOCK_IP_FRACTIONAL_DIVIDER_CALLBACKS_COUNT 1U 233 #define CLOCK_IP_NUMBER_OF_HARDWARE_DFS 0U 234 235 #define CLOCK_IP_PLL_CALLBACKS_COUNT 2U 236 #define CLOCK_IP_SPLL_ENABLE 1U 237 238 #define CLOCK_IP_SELECTOR_CALLBACKS_COUNT 10U 239 #define CLOCK_IP_SCG_SCS_RUN_SEL 1U 240 #define CLOCK_IP_SCG_SCS_VLPR_SEL 2U 241 #define CLOCK_IP_SIM_RTC_SEL 3U 242 #define CLOCK_IP_SIM_LPO_SEL 4U 243 #define CLOCK_IP_SCG_CLKOUT_SEL 5U 244 #define CLOCK_IP_SIM_FTMOPT_SEL 6U 245 #define CLOCK_IP_SIM_CLKOUT_SEL 7U 246 #define CLOCK_IP_PCC_PCS_SELECT 8U 247 #define CLOCK_IP_SIM_TRACE_SEL 9U 248 249 #define CLOCK_IP_PCFS_CALLBACKS_COUNT 1U 250 251 #define CLOCK_IP_CMU_CALLBACKS_COUNT 1U 252 253 #define CLOCK_IP_ALL_CALLBACKS_COUNT 12U 254 255 #elif (defined (CLOCK_IP_S32K142) || defined(CLOCK_IP_S32K144) || defined(CLOCK_IP_S32K146) || defined(CLOCK_IP_S32K148)) 256 257 #define CLOCK_IP_DIVIDER_CALLBACKS_COUNT 15U 258 #define CLOCK_IP_SCG_ASYNC_DIV1 1U 259 #define CLOCK_IP_SCG_ASYNC_DIV2 2U 260 #define CLOCK_IP_SCG_DIVCORE_RUN 3U 261 #define CLOCK_IP_SCG_DIVBUS_RUN 4U 262 #define CLOCK_IP_SCG_DIVSLOW_RUN 5U 263 #define CLOCK_IP_SCG_DIVCORE_VLPR 6U 264 #define CLOCK_IP_SCG_DIVBUS_VLPR 7U 265 #define CLOCK_IP_SCG_DIVSLOW_VLPR 8U 266 #define CLOCK_IP_SCG_DIVCORE_HSRUN 9U 267 #define CLOCK_IP_SCG_DIVBUS_HSRUN 10U 268 #define CLOCK_IP_SCG_DIVSLOW_HSRUN 11U 269 #define CLOCK_IP_SIM_CLKOUT_DIV 12U 270 #define CLOCK_IP_PCC_PCD_FRAC 13U 271 #define CLOCK_IP_SIM_TRACE_DIV_MUL 14U 272 273 #define CLOCK_IP_DIVIDERTRIGGER_CALLBACKS_COUNT 1U 274 275 #define CLOCK_IP_XOSC_CALLBACKS_COUNT 2U 276 #define CLOCK_IP_SOSC_ENABLE 1U 277 278 #define CLOCK_IP_IRCOSC_CALLBACKS_COUNT 5U 279 #define CLOCK_IP_SIRC_ENABLE 1U 280 #define CLOCK_IP_SIRC_VLP_ENABLE 2U 281 #define CLOCK_IP_SIRC_STOP_ENABLE 3U 282 #define CLOCK_IP_FIRC_ENABLE 4U 283 284 #define CLOCK_IP_GATE_CALLBACKS_COUNT 7U 285 #define CLOCK_IP_PCC_CGC_ENABLE 1U 286 #define CLOCK_IP_SIM_CLKOUT_ENABLE 2U 287 #define CLOCK_IP_SIM_LPO32K_ENABLE 3U 288 #define CLOCK_IP_SIM_LPO1K_ENABLE 4U 289 #define CLOCK_IP_SIM_PLATCGC_CGC 5U 290 #define CLOCK_IP_SIM_TRACE_ENABLE 6U 291 292 #define CLOCK_IP_FRACTIONAL_DIVIDER_CALLBACKS_COUNT 1U 293 #define CLOCK_IP_NUMBER_OF_HARDWARE_DFS 0U 294 295 #define CLOCK_IP_PLL_CALLBACKS_COUNT 2U 296 #define CLOCK_IP_SPLL_ENABLE 1U 297 298 #define CLOCK_IP_SELECTOR_CALLBACKS_COUNT 11U 299 #define CLOCK_IP_SCG_SCS_RUN_SEL 1U 300 #define CLOCK_IP_SCG_SCS_VLPR_SEL 2U 301 #define CLOCK_IP_SCG_SCS_HSRUN_SEL 3U 302 #define CLOCK_IP_SIM_RTC_SEL 4U 303 #define CLOCK_IP_SIM_LPO_SEL 5U 304 #define CLOCK_IP_SCG_CLKOUT_SEL 6U 305 #define CLOCK_IP_SIM_FTMOPT_SEL 7U 306 #define CLOCK_IP_SIM_CLKOUT_SEL 8U 307 #define CLOCK_IP_PCC_PCS_SELECT 9U 308 #define CLOCK_IP_SIM_TRACE_SEL 10U 309 310 #define CLOCK_IP_PCFS_CALLBACKS_COUNT 1U 311 312 #define CLOCK_IP_CMU_CALLBACKS_COUNT 1U 313 314 #define CLOCK_IP_ALL_CALLBACKS_COUNT 15U 315 316 #endif 317 318 /* The source of HCLK is CORE_CLK. */ 319 #define HCLK CORE_CLK 320 321 #if (defined(CLOCK_IP_S32K116) || defined(CLOCK_IP_S32K118)) 322 #define CLOCK_IP_PERIPH_ASYNC_COUNT 3U 323 #else 324 #define CLOCK_IP_PERIPH_ASYNC_COUNT 4U 325 #endif 326 327 #if (defined(CLOCK_IP_S32K116) || defined(CLOCK_IP_S32K118)) 328 #define CLOCK_IP_NUMBER_OF_HARDWARE_PLL 0U 329 #define CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE 2U 330 #define CLOCK_IP_CMU_INFO_SIZE 2U 331 #else 332 #define CLOCK_IP_NUMBER_OF_HARDWARE_PLL 1U 333 #define CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE 0U 334 #define CLOCK_IP_CMU_INFO_SIZE 0U 335 #endif 336 337 #ifdef CMU_GCR_FCE_MASK 338 #define CMU_FC_GCR_FCE_MASK CMU_GCR_FCE_MASK 339 #endif 340 #ifdef CMU_GCR_FCE_SHIFT 341 #define CMU_FC_GCR_FCE_SHIFT CMU_GCR_FCE_SHIFT 342 #endif 343 #ifdef CMU_IER_FHHAIE_MASK 344 #define CMU_FC_IER_FHHAIE_MASK CMU_IER_FHHAIE_MASK 345 #endif 346 #ifdef CMU_IER_FHHIE_MASK 347 #define CMU_FC_IER_FHHIE_MASK CMU_IER_FHHIE_MASK 348 #endif 349 #ifdef CMU_IER_FLLAIE_MASK 350 #define CMU_FC_IER_FLLAIE_MASK CMU_IER_FLLAIE_MASK 351 #endif 352 #ifdef CMU_IER_FLLIE_MASK 353 #define CMU_FC_IER_FLLIE_MASK CMU_IER_FLLIE_MASK 354 #endif 355 #ifdef CMU_SR_FHH_MASK 356 #define CMU_FC_SR_FHH_MASK CMU_SR_FHH_MASK 357 #endif 358 #ifdef CMU_SR_FLL_MASK 359 #define CMU_FC_SR_FLL_MASK CMU_SR_FLL_MASK 360 #endif 361 #ifdef CMU_SR_RS_MASK 362 #define CMU_FC_SR_RS_MASK CMU_SR_RS_MASK 363 #endif 364 365 #ifdef CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF 366 #define CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED CMU_FC_GCR_FCE_MASK 367 #define CLOCK_IP_CMU_FREQUENCY_CHECK_STOPPED 0U 368 #define CLOCK_IP_CMU_ISR_MASK 3U 369 #define CMU_RESET_COUNTER_VALUE 0U 370 #define CMU_RESET_LOW_LIMIT 3U 371 #define CMU_RESET_HIGH_LIMIT 0x00FFFFFCU 372 #endif 373 374 /*================================================================================================== 375 * ENUMS 376 ==================================================================================================*/ 377 378 /*================================================================================================== 379 * STRUCTURES AND OTHER TYPEDEFS 380 ==================================================================================================*/ 381 typedef struct { 382 383 uint32 ASYNC_DIV; /* Peripheral asynchronous clock register */ 384 385 }Clock_Ip_ScgPeriphAsyncDivType; 386 387 #if defined(CLOCK_IP_HAS_FIRC_MON1_CLK) || defined(CLOCK_IP_HAS_FIRC_MON2_CLK) 388 /** CMU - Register Layout Typedef */ 389 typedef struct { 390 uint32 GCR; /**< Global Configuration Register, offset: 0x0 */ 391 uint32 RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ 392 uint32 HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ 393 uint32 LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ 394 volatile uint32 SR; /**< Status Register, offset: 0x10 */ 395 uint32 IER; /**< Interrupt Enable Register, offset: 0x14 */ 396 397 } Clock_Ip_ClockMonitorType; 398 399 typedef struct{ 400 401 Clock_Ip_NameType Name; /* Name of the clock that can be monitored/supports cmu (clock monitor) */ 402 Clock_Ip_NameType Reference; /* Name of the reference clock */ 403 Clock_Ip_NameType Bus; /* Name of the bus clock */ 404 405 Clock_Ip_ClockMonitorType* CmuInstance; 406 407 }Clock_Ip_CmuInfoType; 408 #endif 409 410 411 /*================================================================================================== 412 * GLOBAL VARIABLE DECLARATIONS 413 ==================================================================================================*/ 414 /* Clock start initialized section data */ 415 #define MCU_START_SEC_VAR_INIT_BOOLEAN 416 #include "Mcu_MemMap.h" 417 418 extern boolean Clock_Ip_bSentFromUpdateDriverContext; 419 420 /* Clock stop initialized section data */ 421 #define MCU_STOP_SEC_VAR_INIT_BOOLEAN 422 #include "Mcu_MemMap.h" 423 424 /* Clock start constant section data */ 425 #define MCU_START_SEC_CONST_UNSPECIFIED 426 #include "Mcu_MemMap.h" 427 428 extern volatile Clock_Ip_ScgPeriphAsyncDivType* const Clock_Ip_apxScgPeriphAsyncDivs[CLOCK_IP_PERIPH_ASYNC_COUNT]; 429 #if CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE > 0U 430 extern Clock_Ip_ClockMonitorType * const Clock_Ip_apxCmu[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE]; 431 extern Clock_Ip_NameType const Clock_Ip_aeCmuNames[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE]; 432 #endif 433 434 #if CLOCK_IP_CMU_INFO_SIZE > 0U 435 extern const Clock_Ip_CmuInfoType Clock_Ip_axCmuInfo[CLOCK_IP_CMU_INFO_SIZE]; 436 #endif 437 /* Clock stop constant section data */ 438 #define MCU_STOP_SEC_CONST_UNSPECIFIED 439 #include "Mcu_MemMap.h" 440 441 /* Clock start constant section data */ 442 #define MCU_START_SEC_CONST_16 443 #include "Mcu_MemMap.h" 444 445 extern const uint8 Clock_Ip_au16SelectorEntryHardwareValue[CLOCK_IP_FEATURE_NAMES_NO]; 446 extern const uint8 Clock_Ip_au8SelectorEntryScsHardwareValue[CLOCK_IP_FEATURE_PRODUCERS_NO]; 447 extern const uint8 Clock_Ip_au8SelectorEntryPcsHardwareValue[CLOCK_IP_FEATURE_PRODUCERS_NO]; 448 extern const uint8 Clock_Ip_au8SelectorEntrySIMHardwareValue[CLOCK_IP_FEATURE_PRODUCERS_NO]; 449 extern const uint8 Clock_Ip_au8DividerValueHardwareValue[65U]; 450 451 /* Clock stop constant section data */ 452 #define MCU_STOP_SEC_CONST_16 453 #include "Mcu_MemMap.h" 454 455 /*================================================================================================== 456 * FUNCTION PROTOTYPES 457 ==================================================================================================*/ 458 459 #if defined(__cplusplus) 460 } 461 #endif /* __cplusplus*/ 462 463 464 /*! @}*/ 465 466 #endif /* CLOCK_IP_SPECIFIC_H */ 467 468
