1 /*
2  * Copyright 2022-2023 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 /**
8 *   @file       Clock_Ip_Cfg_Defines.h
9 *   @version    1.0.0
10 *
11 *   @brief   AUTOSAR Mcu - Post-Build(PB) configuration file code template.
12 *   @details Code template for Post-Build(PB) configuration file generation.
13 *
14 *   @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver
15 *   @{
16 */
17 
18 #ifndef CLOCK_IP_CFG_DEFINES_H
19 #define CLOCK_IP_CFG_DEFINES_H
20 
21 
22 #ifdef __cplusplus
23 extern "C"{
24 #endif
25 
26 
27 /*==================================================================================================
28                                          INCLUDE FILES
29  1) system and project includes
30  2) needed interfaces from external units
31  3) internal and external interfaces from this unit
32 ==================================================================================================*/
33 #include "S32Z2_COMMON.h"
34 #include "S32Z2_MC_CGM.h"
35 #include "S32Z2_RTU_MC_CGM.h"
36 #include "S32Z2_FXOSC.h"
37 #include "S32Z2_PLLDIG.h"
38 #include "S32Z2_MC_ME.h"
39 #include "S32Z2_DFS.h"
40 #include "S32Z2_CMU_FC.h"
41 #include "S32Z2_GPR0.h"
42 #include "S32Z2_GPR0_PCTL.h"
43 #include "S32Z2_GPR1.h"
44 #include "S32Z2_GPR1_PCTL.h"
45 #include "S32Z2_GPR3.h"
46 #include "S32Z2_GPR3_PCTL.h"
47 #include "S32Z2_GPR4.h"
48 #include "S32Z2_GPR4_PCTL.h"
49 #include "S32Z2_GPR5.h"
50 #include "S32Z2_GPR5_PCTL.h"
51 #include "S32Z2_GPR6_PCTL.h"
52 #include "S32Z2_SRAMCTL.h"
53 #include "S32Z2_LFAST.h"
54 /*==================================================================================================
55                                SOURCE FILE VERSION INFORMATION
56 ==================================================================================================*/
57 #define CLOCK_IP_CFG_DEFINES_VENDOR_ID                       43
58 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION        4
59 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION        7
60 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION     0
61 #define CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION                1
62 #define CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION                0
63 #define CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION                0
64 
65 /*==================================================================================================
66                                            DEFINES AND MACROS
67 ==================================================================================================*/
68 /**
69 * @brief            Derivative used.
70 */
71 #define CLOCK_IP_DERIVATIVE_001
72 /**
73 * @brief            Platform used.
74 */
75 #define CLOCK_IP_PLATFORM_SPECIFIC
76 
77 /**
78 * @brief            Max number of internal oscillators
79 */
80 #define CLOCK_IP_IRCOSCS_COUNT       (2U)
81 
82 /**
83 * @brief            Max number of external oscillators
84 */
85 #define CLOCK_IP_XOSCS_COUNT       (1U)
86 
87 /**
88 * @brief            Max number of pll devices
89 */
90 #define CLOCK_IP_PLLS_COUNT       (5U)
91 
92 /**
93 * @brief            Max number of selectors
94 */
95 #define CLOCK_IP_SELECTORS_COUNT       (63U)
96 
97 /**
98 * @brief            Max number of dividers
99 */
100 #define CLOCK_IP_DIVIDERS_COUNT       (85U)
101 
102 /**
103 * @brief            Max number of divider triggers
104 */
105 #define CLOCK_IP_DIVIDER_TRIGGERS_COUNT       (1U)
106 
107 /**
108 * @brief            Max number of fractional dividers
109 */
110 #define CLOCK_IP_FRACTIONAL_DIVIDERS_COUNT       (12U)
111 
112 /**
113 * @brief            Max number of external clocks
114 */
115 #define CLOCK_IP_EXT_CLKS_COUNT       (8U)
116 
117 /**
118 * @brief            Max number of pcfs
119 */
120 #define CLOCK_IP_PCFS_COUNT       (11U)
121 
122 /**
123 * @brief            Max number of clock gates
124 */
125 #define CLOCK_IP_GATES_COUNT       (101U)
126 
127 /**
128 * @brief            Max number of clock monitoring units
129 */
130 #define CLOCK_IP_CMUS_COUNT       (25U)
131 
132 /**
133 * @brief            Max number of configured frequencies values
134 */
135 #define CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT       (17U)
136 
137 /**
138 * @brief            Number of clock configurations 0
139 */
140 #define CLOCK_IP_CONFIGURED_XOSCS_0_NO       (1U)
141 #define CLOCK_IP_CONFIGURED_PLLS_0_NO       (5U)
142 #define CLOCK_IP_CONFIGURED_SELECTORS_0_NO       (63U)
143 #define CLOCK_IP_CONFIGURED_DIVIDERS_0_NO       (85U)
144 #define CLOCK_IP_CONFIGURED_DIVIDER_TRIGGERS_0_NO       (1U)
145 #define CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO       (12U)
146 #define CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO       (8U)
147 #define CLOCK_IP_CONFIGURED_GATES_0_NO       (101U)
148 #define CLOCK_IP_CONFIGURED_CMUS_0_NO       (15U)
149 
150 /**
151 * @brief            Firc frequency.
152 */
153 #define CLOCK_IP_FIRC_FREQUENCY                48000000U
154 
155 /**
156 * @brief            Sirc frequency.
157 */
158 #define CLOCK_IP_SIRC_FREQUENCY                32000U
159 
160 /**
161 * @brief            Clock ip supports clock frequency.
162 */
163 #define CLOCK_IP_GET_FREQUENCY_API                (STD_ON)
164 
165 /**
166 * @brief            Supports wait states configuration
167 */
168 #define CLOCK_IP_SUPPORTS_WAIT_STATES                (STD_ON)
169 
170 
171 /**
172 * @brief            Default fxosc frequency.
173 */
174 #define CLOCK_IP_DEFAULT_FXOSC_FREQUENCY                40000000U
175 
176 /**
177 * @brief            Clock ip supports ram wait states.
178 */
179 #define CLOCK_IP_HAS_RAM_WAIT_STATES
180 
181 /**
182 * @brief            Supported clocks.
183 */
184 #define CLOCK_IP_HAS_FIRC_CLK         1U
185 #define CLOCK_IP_HAS_FXOSC_CLK         2U
186 #define CLOCK_IP_HAS_SIRC_CLK         3U
187 #define CLOCK_IP_HAS_COREPLL_CLK         4U
188 #define CLOCK_IP_HAS_PERIPHPLL_CLK         5U
189 #define CLOCK_IP_HAS_DDRPLL_CLK         6U
190 #define CLOCK_IP_HAS_LFAST0_PLL_CLK         7U
191 #define CLOCK_IP_HAS_LFAST1_PLL_CLK         8U
192 #define CLOCK_IP_HAS_COREPLL_PHI0_CLK         9U
193 #define CLOCK_IP_HAS_COREPLL_DFS0_CLK         10U
194 #define CLOCK_IP_HAS_COREPLL_DFS1_CLK         11U
195 #define CLOCK_IP_HAS_COREPLL_DFS2_CLK         12U
196 #define CLOCK_IP_HAS_COREPLL_DFS3_CLK         13U
197 #define CLOCK_IP_HAS_COREPLL_DFS4_CLK         14U
198 #define CLOCK_IP_HAS_COREPLL_DFS5_CLK         15U
199 #define CLOCK_IP_HAS_PERIPHPLL_PHI0_CLK         16U
200 #define CLOCK_IP_HAS_PERIPHPLL_PHI1_CLK         17U
201 #define CLOCK_IP_HAS_PERIPHPLL_PHI2_CLK         18U
202 #define CLOCK_IP_HAS_PERIPHPLL_PHI3_CLK         19U
203 #define CLOCK_IP_HAS_PERIPHPLL_PHI4_CLK         20U
204 #define CLOCK_IP_HAS_PERIPHPLL_PHI5_CLK         21U
205 #define CLOCK_IP_HAS_PERIPHPLL_PHI6_CLK         22U
206 #define CLOCK_IP_HAS_PERIPHPLL_DFS0_CLK         23U
207 #define CLOCK_IP_HAS_PERIPHPLL_DFS1_CLK         24U
208 #define CLOCK_IP_HAS_PERIPHPLL_DFS2_CLK         25U
209 #define CLOCK_IP_HAS_PERIPHPLL_DFS3_CLK         26U
210 #define CLOCK_IP_HAS_PERIPHPLL_DFS4_CLK         27U
211 #define CLOCK_IP_HAS_PERIPHPLL_DFS5_CLK         28U
212 #define CLOCK_IP_HAS_DDRPLL_PHI0_CLK         29U
213 #define CLOCK_IP_HAS_LFAST0_PLL_PH0_CLK         30U
214 #define CLOCK_IP_HAS_LFAST1_PLL_PH0_CLK         31U
215 #define CLOCK_IP_HAS_ETH_RGMII_REF_CLK         32U
216 #define CLOCK_IP_HAS_TMR_1588_CLK         33U
217 #define CLOCK_IP_HAS_ETH0_EXT_RX_CLK         34U
218 #define CLOCK_IP_HAS_ETH0_EXT_TX_CLK         35U
219 #define CLOCK_IP_HAS_ETH1_EXT_RX_CLK         36U
220 #define CLOCK_IP_HAS_ETH1_EXT_TX_CLK         37U
221 #define CLOCK_IP_HAS_LFAST0_EXT_REF_CLK         38U
222 #define CLOCK_IP_HAS_LFAST1_EXT_REF_CLK         39U
223 #define CLOCK_IP_HAS_DDR_CLK         40U
224 #define CLOCK_IP_HAS_P0_SYS_CLK         41U
225 #define CLOCK_IP_HAS_P1_SYS_CLK         42U
226 #define CLOCK_IP_HAS_P1_SYS_DIV2_CLK         43U
227 #define CLOCK_IP_HAS_P1_SYS_DIV4_CLK         44U
228 #define CLOCK_IP_HAS_P2_SYS_CLK         45U
229 #define CLOCK_IP_HAS_CORE_M33_CLK         46U
230 #define CLOCK_IP_HAS_P2_SYS_DIV2_CLK         47U
231 #define CLOCK_IP_HAS_P2_SYS_DIV4_CLK         48U
232 #define CLOCK_IP_HAS_P3_SYS_CLK         49U
233 #define CLOCK_IP_HAS_CE_SYS_DIV2_CLK         50U
234 #define CLOCK_IP_HAS_CE_SYS_DIV4_CLK         51U
235 #define CLOCK_IP_HAS_P3_SYS_DIV2_NOC_CLK         52U
236 #define CLOCK_IP_HAS_P3_SYS_DIV4_CLK         53U
237 #define CLOCK_IP_HAS_P4_SYS_CLK         54U
238 #define CLOCK_IP_HAS_P4_SYS_DIV2_CLK         55U
239 #define CLOCK_IP_HAS_HSE_SYS_DIV2_CLK         56U
240 #define CLOCK_IP_HAS_P5_SYS_CLK         57U
241 #define CLOCK_IP_HAS_P5_SYS_DIV2_CLK         58U
242 #define CLOCK_IP_HAS_P5_SYS_DIV4_CLK         59U
243 #define CLOCK_IP_HAS_P2_MATH_CLK         60U
244 #define CLOCK_IP_HAS_P2_MATH_DIV3_CLK         61U
245 #define CLOCK_IP_HAS_GLB_LBIST_CLK         62U
246 #define CLOCK_IP_HAS_RTU0_CORE_CLK         63U
247 #define CLOCK_IP_HAS_RTU0_CORE_DIV2_CLK         64U
248 #define CLOCK_IP_HAS_RTU1_CORE_CLK         65U
249 #define CLOCK_IP_HAS_RTU1_CORE_DIV2_CLK         66U
250 #define CLOCK_IP_HAS_P0_PSI5_S_UTIL_CLK         67U
251 #define CLOCK_IP_HAS_P4_PSI5_S_UTIL_CLK         68U
252 #define CLOCK_IP_FEATURE_PRODUCERS_NO         69U
253 #define CLOCK_IP_HAS_ADC0_CLK         70U
254 #define CLOCK_IP_HAS_ADC1_CLK         71U
255 #define CLOCK_IP_HAS_CE_EDMA_CLK         72U
256 #define CLOCK_IP_HAS_CE_PIT0_CLK         73U
257 #define CLOCK_IP_HAS_CE_PIT1_CLK         74U
258 #define CLOCK_IP_HAS_CE_PIT2_CLK         75U
259 #define CLOCK_IP_HAS_CE_PIT3_CLK         76U
260 #define CLOCK_IP_HAS_CE_PIT4_CLK         77U
261 #define CLOCK_IP_HAS_CE_PIT5_CLK         78U
262 #define CLOCK_IP_HAS_CLKOUT0_CLK         79U
263 #define CLOCK_IP_HAS_CLKOUT1_CLK         80U
264 #define CLOCK_IP_HAS_CLKOUT2_CLK         81U
265 #define CLOCK_IP_HAS_CLKOUT3_CLK         82U
266 #define CLOCK_IP_HAS_CLKOUT4_CLK         83U
267 #define CLOCK_IP_HAS_CTU_CLK         84U
268 #define CLOCK_IP_HAS_DMACRC0_CLK         85U
269 #define CLOCK_IP_HAS_DMACRC1_CLK         86U
270 #define CLOCK_IP_HAS_DMACRC4_CLK         87U
271 #define CLOCK_IP_HAS_DMACRC5_CLK         88U
272 #define CLOCK_IP_HAS_DMAMUX0_CLK         89U
273 #define CLOCK_IP_HAS_DMAMUX1_CLK         90U
274 #define CLOCK_IP_HAS_DMAMUX4_CLK         91U
275 #define CLOCK_IP_HAS_DMAMUX5_CLK         92U
276 #define CLOCK_IP_HAS_EDMA0_CLK         93U
277 #define CLOCK_IP_HAS_EDMA1_CLK         94U
278 #define CLOCK_IP_HAS_EDMA3_CLK         95U
279 #define CLOCK_IP_HAS_EDMA4_CLK         96U
280 #define CLOCK_IP_HAS_EDMA5_CLK         97U
281 #define CLOCK_IP_HAS_ETH0_TX_MII_CLK         98U
282 #define CLOCK_IP_HAS_ENET0_CLK         99U
283 #define CLOCK_IP_HAS_P3_CAN_PE_CLK         100U
284 #define CLOCK_IP_HAS_FLEXCAN0_CLK         101U
285 #define CLOCK_IP_HAS_FLEXCAN1_CLK         102U
286 #define CLOCK_IP_HAS_FLEXCAN2_CLK         103U
287 #define CLOCK_IP_HAS_FLEXCAN3_CLK         104U
288 #define CLOCK_IP_HAS_FLEXCAN4_CLK         105U
289 #define CLOCK_IP_HAS_FLEXCAN5_CLK         106U
290 #define CLOCK_IP_HAS_FLEXCAN6_CLK         107U
291 #define CLOCK_IP_HAS_FLEXCAN7_CLK         108U
292 #define CLOCK_IP_HAS_FLEXCAN8_CLK         109U
293 #define CLOCK_IP_HAS_FLEXCAN9_CLK         110U
294 #define CLOCK_IP_HAS_FLEXCAN10_CLK         111U
295 #define CLOCK_IP_HAS_FLEXCAN11_CLK         112U
296 #define CLOCK_IP_HAS_FLEXCAN12_CLK         113U
297 #define CLOCK_IP_HAS_FLEXCAN13_CLK         114U
298 #define CLOCK_IP_HAS_FLEXCAN14_CLK         115U
299 #define CLOCK_IP_HAS_FLEXCAN15_CLK         116U
300 #define CLOCK_IP_HAS_FLEXCAN16_CLK         117U
301 #define CLOCK_IP_HAS_FLEXCAN17_CLK         118U
302 #define CLOCK_IP_HAS_FLEXCAN18_CLK         119U
303 #define CLOCK_IP_HAS_FLEXCAN19_CLK         120U
304 #define CLOCK_IP_HAS_FLEXCAN20_CLK         121U
305 #define CLOCK_IP_HAS_FLEXCAN21_CLK         122U
306 #define CLOCK_IP_HAS_FLEXCAN22_CLK         123U
307 #define CLOCK_IP_HAS_FLEXCAN23_CLK         124U
308 #define CLOCK_IP_HAS_P0_FR_PE_CLK         125U
309 #define CLOCK_IP_HAS_FRAY0_CLK         126U
310 #define CLOCK_IP_HAS_FRAY1_CLK         127U
311 #define CLOCK_IP_HAS_GTM_CLK         128U
312 #define CLOCK_IP_HAS_IIIC0_CLK         129U
313 #define CLOCK_IP_HAS_IIIC1_CLK         130U
314 #define CLOCK_IP_HAS_IIIC2_CLK         131U
315 #define CLOCK_IP_HAS_P0_LIN_BAUD_CLK         132U
316 #define CLOCK_IP_HAS_LIN0_CLK         133U
317 #define CLOCK_IP_HAS_LIN1_CLK         134U
318 #define CLOCK_IP_HAS_LIN2_CLK         135U
319 #define CLOCK_IP_HAS_P1_LIN_BAUD_CLK         136U
320 #define CLOCK_IP_HAS_LIN3_CLK         137U
321 #define CLOCK_IP_HAS_LIN4_CLK         138U
322 #define CLOCK_IP_HAS_LIN5_CLK         139U
323 #define CLOCK_IP_HAS_P4_LIN_BAUD_CLK         140U
324 #define CLOCK_IP_HAS_LIN6_CLK         141U
325 #define CLOCK_IP_HAS_LIN7_CLK         142U
326 #define CLOCK_IP_HAS_LIN8_CLK         143U
327 #define CLOCK_IP_HAS_P5_LIN_BAUD_CLK         144U
328 #define CLOCK_IP_HAS_LIN9_CLK         145U
329 #define CLOCK_IP_HAS_LIN10_CLK         146U
330 #define CLOCK_IP_HAS_LIN11_CLK         147U
331 #define CLOCK_IP_HAS_MSCDSPI_CLK         148U
332 #define CLOCK_IP_HAS_MSCLIN_CLK         149U
333 #define CLOCK_IP_HAS_NANO_CLK         150U
334 #define CLOCK_IP_HAS_P0_CLKOUT_SRC_CLK         151U
335 #define CLOCK_IP_HAS_P0_CTU_PER_CLK         152U
336 #define CLOCK_IP_HAS_P0_DSPI_MSC_CLK         153U
337 #define CLOCK_IP_HAS_P0_EMIOS_LCU_CLK         154U
338 #define CLOCK_IP_HAS_P0_GTM_CLK         155U
339 #define CLOCK_IP_HAS_P0_GTM_NOC_CLK         156U
340 #define CLOCK_IP_HAS_P0_GTM_TS_CLK         157U
341 #define CLOCK_IP_HAS_P0_LIN_CLK         158U
342 #define CLOCK_IP_HAS_P0_NANO_CLK         159U
343 #define CLOCK_IP_HAS_P0_PSI5_125K_CLK         160U
344 #define CLOCK_IP_HAS_P0_PSI5_189K_CLK         161U
345 #define CLOCK_IP_HAS_P0_PSI5_S_BAUD_CLK         162U
346 #define CLOCK_IP_HAS_P0_PSI5_S_CORE_CLK         163U
347 #define CLOCK_IP_HAS_P0_PSI5_S_TRIG0_CLK         164U
348 #define CLOCK_IP_HAS_P0_PSI5_S_TRIG1_CLK         165U
349 #define CLOCK_IP_HAS_P0_PSI5_S_TRIG2_CLK         166U
350 #define CLOCK_IP_HAS_P0_PSI5_S_TRIG3_CLK         167U
351 #define CLOCK_IP_HAS_P0_PSI5_S_UART_CLK         168U
352 #define CLOCK_IP_HAS_P0_PSI5_S_WDOG0_CLK         169U
353 #define CLOCK_IP_HAS_P0_PSI5_S_WDOG1_CLK         170U
354 #define CLOCK_IP_HAS_P0_PSI5_S_WDOG2_CLK         171U
355 #define CLOCK_IP_HAS_P0_PSI5_S_WDOG3_CLK         172U
356 #define CLOCK_IP_HAS_P0_REG_INTF_2X_CLK         173U
357 #define CLOCK_IP_HAS_P0_REG_INTF_CLK         174U
358 #define CLOCK_IP_HAS_P1_CLKOUT_SRC_CLK         175U
359 #define CLOCK_IP_HAS_P1_DSPI60_CLK         176U
360 #define CLOCK_IP_HAS_ETH_TS_CLK         177U
361 #define CLOCK_IP_HAS_ETH_TS_DIV4_CLK         178U
362 #define CLOCK_IP_HAS_ETH0_REF_RMII_CLK         179U
363 #define CLOCK_IP_HAS_ETH0_RX_MII_CLK         180U
364 #define CLOCK_IP_HAS_ETH0_RX_RGMII_CLK         181U
365 #define CLOCK_IP_HAS_ETH0_TX_RGMII_CLK         182U
366 #define CLOCK_IP_HAS_ETH0_PS_TX_CLK         183U
367 #define CLOCK_IP_HAS_ETH1_REF_RMII_CLK         184U
368 #define CLOCK_IP_HAS_ETH1_RX_MII_CLK         185U
369 #define CLOCK_IP_HAS_ETH1_RX_RGMII_CLK         186U
370 #define CLOCK_IP_HAS_ETH1_TX_MII_CLK         187U
371 #define CLOCK_IP_HAS_ETH1_TX_RGMII_CLK         188U
372 #define CLOCK_IP_HAS_ETH1_PS_TX_CLK         189U
373 #define CLOCK_IP_HAS_P1_LFAST0_REF_CLK         190U
374 #define CLOCK_IP_HAS_P1_LFAST1_REF_CLK         191U
375 #define CLOCK_IP_HAS_P1_NETC_AXI_CLK         192U
376 #define CLOCK_IP_HAS_P1_LIN_CLK         193U
377 #define CLOCK_IP_HAS_P1_REG_INTF_CLK         194U
378 #define CLOCK_IP_HAS_P2_DBG_ATB_CLK         195U
379 #define CLOCK_IP_HAS_P2_REG_INTF_CLK         196U
380 #define CLOCK_IP_HAS_P3_AES_CLK         197U
381 #define CLOCK_IP_HAS_P3_CLKOUT_SRC_CLK         198U
382 #define CLOCK_IP_HAS_P3_DBG_TS_CLK         199U
383 #define CLOCK_IP_HAS_P3_REG_INTF_CLK         200U
384 #define CLOCK_IP_HAS_P3_SYS_MON1_CLK         201U
385 #define CLOCK_IP_HAS_P3_SYS_MON2_CLK         202U
386 #define CLOCK_IP_HAS_P3_SYS_MON3_CLK         203U
387 #define CLOCK_IP_HAS_P4_CLKOUT_SRC_CLK         204U
388 #define CLOCK_IP_HAS_P4_DSPI60_CLK         205U
389 #define CLOCK_IP_HAS_P4_EMIOS_LCU_CLK         206U
390 #define CLOCK_IP_HAS_P4_LIN_CLK         207U
391 #define CLOCK_IP_HAS_P4_PSI5_125K_CLK         208U
392 #define CLOCK_IP_HAS_P4_PSI5_189K_CLK         209U
393 #define CLOCK_IP_HAS_P4_PSI5_S_BAUD_CLK         210U
394 #define CLOCK_IP_HAS_P4_PSI5_S_CORE_CLK         211U
395 #define CLOCK_IP_HAS_P4_PSI5_S_TRIG0_CLK         212U
396 #define CLOCK_IP_HAS_P4_PSI5_S_TRIG1_CLK         213U
397 #define CLOCK_IP_HAS_P4_PSI5_S_TRIG2_CLK         214U
398 #define CLOCK_IP_HAS_P4_PSI5_S_TRIG3_CLK         215U
399 #define CLOCK_IP_HAS_P4_PSI5_S_UART_CLK         216U
400 #define CLOCK_IP_HAS_P4_PSI5_S_WDOG0_CLK         217U
401 #define CLOCK_IP_HAS_P4_PSI5_S_WDOG1_CLK         218U
402 #define CLOCK_IP_HAS_P4_PSI5_S_WDOG2_CLK         219U
403 #define CLOCK_IP_HAS_P4_PSI5_S_WDOG3_CLK         220U
404 #define CLOCK_IP_HAS_P4_QSPI0_2X_CLK         221U
405 #define CLOCK_IP_HAS_P4_QSPI0_1X_CLK         222U
406 #define CLOCK_IP_HAS_P4_QSPI1_2X_CLK         223U
407 #define CLOCK_IP_HAS_P4_QSPI1_1X_CLK         224U
408 #define CLOCK_IP_HAS_P4_REG_INTF_2X_CLK         225U
409 #define CLOCK_IP_HAS_P4_REG_INTF_CLK         226U
410 #define CLOCK_IP_HAS_P4_SDHC_IP_CLK         227U
411 #define CLOCK_IP_HAS_P4_SDHC_IP_DIV2_CLK         228U
412 #define CLOCK_IP_HAS_P5_DIPORT_CLK         229U
413 #define CLOCK_IP_HAS_P5_AE_CLK         230U
414 #define CLOCK_IP_HAS_P5_CANXL_PE_CLK         231U
415 #define CLOCK_IP_HAS_P5_CANXL_CHI_CLK         232U
416 #define CLOCK_IP_HAS_P5_CLKOUT_SRC_CLK         233U
417 #define CLOCK_IP_HAS_P5_LIN_CLK         234U
418 #define CLOCK_IP_HAS_P5_REG_INTF_CLK         235U
419 #define CLOCK_IP_HAS_P6_REG_INTF_CLK         236U
420 #define CLOCK_IP_HAS_PIT0_CLK         237U
421 #define CLOCK_IP_HAS_PIT1_CLK         238U
422 #define CLOCK_IP_HAS_PIT4_CLK         239U
423 #define CLOCK_IP_HAS_PIT5_CLK         240U
424 #define CLOCK_IP_HAS_P0_PSI5_1US_CLK         241U
425 #define CLOCK_IP_HAS_PSI5_0_CLK         242U
426 #define CLOCK_IP_HAS_P4_PSI5_1US_CLK         243U
427 #define CLOCK_IP_HAS_PSI5_1_CLK         244U
428 #define CLOCK_IP_HAS_PSI5S_0_CLK         245U
429 #define CLOCK_IP_HAS_PSI5S_1_CLK         246U
430 #define CLOCK_IP_HAS_QSPI0_CLK         247U
431 #define CLOCK_IP_HAS_QSPI1_CLK         248U
432 #define CLOCK_IP_HAS_RTU0_CORE_MON1_CLK         249U
433 #define CLOCK_IP_HAS_RTU0_CORE_MON2_CLK         250U
434 #define CLOCK_IP_HAS_RTU0_CORE_DIV2_MON1_CLK         251U
435 #define CLOCK_IP_HAS_RTU0_CORE_DIV2_MON2_CLK         252U
436 #define CLOCK_IP_HAS_RTU0_CORE_DIV2_MON3_CLK         253U
437 #define CLOCK_IP_HAS_RTU0_REG_INTF_CLK         254U
438 #define CLOCK_IP_HAS_RTU1_CORE_MON1_CLK         255U
439 #define CLOCK_IP_HAS_RTU1_CORE_MON2_CLK         256U
440 #define CLOCK_IP_HAS_RTU1_CORE_DIV2_MON1_CLK         257U
441 #define CLOCK_IP_HAS_RTU1_CORE_DIV2_MON2_CLK         258U
442 #define CLOCK_IP_HAS_RTU1_CORE_DIV2_MON3_CLK         259U
443 #define CLOCK_IP_HAS_RTU1_REG_INTF_CLK         260U
444 #define CLOCK_IP_HAS_P4_SDHC_CLK         261U
445 #define CLOCK_IP_HAS_RXLUT_CLK         262U
446 #define CLOCK_IP_HAS_SDHC0_CLK         263U
447 #define CLOCK_IP_HAS_SINC_CLK         264U
448 #define CLOCK_IP_HAS_SIPI0_CLK         265U
449 #define CLOCK_IP_HAS_SIPI1_CLK         266U
450 #define CLOCK_IP_HAS_SIUL2_0_CLK         267U
451 #define CLOCK_IP_HAS_SIUL2_1_CLK         268U
452 #define CLOCK_IP_HAS_SIUL2_4_CLK         269U
453 #define CLOCK_IP_HAS_SIUL2_5_CLK         270U
454 #define CLOCK_IP_HAS_P0_DSPI_CLK         271U
455 #define CLOCK_IP_HAS_SPI0_CLK         272U
456 #define CLOCK_IP_HAS_SPI1_CLK         273U
457 #define CLOCK_IP_HAS_P1_DSPI_CLK         274U
458 #define CLOCK_IP_HAS_SPI2_CLK         275U
459 #define CLOCK_IP_HAS_SPI3_CLK         276U
460 #define CLOCK_IP_HAS_SPI4_CLK         277U
461 #define CLOCK_IP_HAS_P4_DSPI_CLK         278U
462 #define CLOCK_IP_HAS_SPI5_CLK         279U
463 #define CLOCK_IP_HAS_SPI6_CLK         280U
464 #define CLOCK_IP_HAS_SPI7_CLK         281U
465 #define CLOCK_IP_HAS_P5_DSPI_CLK         282U
466 #define CLOCK_IP_HAS_SPI8_CLK         283U
467 #define CLOCK_IP_HAS_SPI9_CLK         284U
468 #define CLOCK_IP_HAS_SRX0_CLK         285U
469 #define CLOCK_IP_HAS_SRX1_CLK         286U
470 #define CLOCK_IP_HAS_CORE_PLL_REFCLKOUT         287U
471 #define CLOCK_IP_HAS_CORE_PLL_FBCLKOUT         288U
472 #define CLOCK_IP_HAS_PERIPH_PLL_REFCLKOUT         289U
473 #define CLOCK_IP_HAS_PERIPH_PLL_FBCLKOUT         290U
474 #define CLOCK_IP_FEATURE_NAMES_NO         291U
475 
476 /*==================================================================================================
477                                              ENUMS
478 ==================================================================================================*/
479 
480 
481 /*==================================================================================================
482                                  STRUCTURES AND OTHER TYPEDEFS
483 ==================================================================================================*/
484 
485 
486 
487 #ifdef __cplusplus
488 }
489 #endif
490 
491 #endif /* #ifndef CLOCK_IP_CFG_DEFINES_H */
492 
493 /** @} */
494