1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /** 8 * @file Clock_Ip_Cfg_Defines.h 9 * @version 3.0.0 10 * 11 * @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template. 12 * @details Code template for Post-Build(PB) configuration file generation. 13 * 14 * @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver 15 * @{ 16 */ 17 18 #ifndef CLOCK_IP_CFG_DEFINES_H 19 #define CLOCK_IP_CFG_DEFINES_H 20 21 22 #ifdef __cplusplus 23 extern "C"{ 24 #endif 25 26 27 /*================================================================================================== 28 INCLUDE FILES 29 1) system and project includes 30 2) needed interfaces from external units 31 3) internal and external interfaces from this unit 32 ==================================================================================================*/ 33 #include "S32K344_MC_CGM.h" 34 #include "S32K344_FIRC.h" 35 #include "S32K344_SIRC.h" 36 #include "S32K344_FXOSC.h" 37 #include "S32K344_SXOSC.h" 38 #include "S32K344_PLL.h" 39 #include "S32K344_MC_ME.h" 40 #include "S32K344_PRAMC.h" 41 #include "S32K344_FLASH.h" 42 #include "S32K344_CMU_FC.h" 43 #include "S32K344_SYSTICK.h" 44 #include "S32K344_EMIOS.h" 45 #include "S32K344_RTC.h" 46 #include "S32K344_CONFIGURATION_GPR.h" 47 48 /*================================================================================================== 49 SOURCE FILE VERSION INFORMATION 50 ==================================================================================================*/ 51 #define CLOCK_IP_CFG_DEFINES_VENDOR_ID 43 52 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4 53 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 7 54 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0 55 #define CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION 3 56 #define CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION 0 57 #define CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION 0 58 59 /*================================================================================================== 60 DEFINES AND MACROS 61 ==================================================================================================*/ 62 /** 63 * @brief Derivative used. 64 */ 65 #define CLOCK_IP_DERIVATIVE_005 66 /** 67 * @brief Max number of internal oscillators 68 */ 69 #define CLOCK_IP_IRCOSCS_COUNT (3U) 70 71 /** 72 * @brief Max number of external oscillators 73 */ 74 #define CLOCK_IP_XOSCS_COUNT (2U) 75 76 /** 77 * @brief Max number of pll devices 78 */ 79 #define CLOCK_IP_PLLS_COUNT (1U) 80 81 /** 82 * @brief Max number of selectors 83 */ 84 #define CLOCK_IP_SELECTORS_COUNT (13U) 85 86 /** 87 * @brief Max number of dividers 88 */ 89 #define CLOCK_IP_DIVIDERS_COUNT (21U) 90 91 /** 92 * @brief Max number of divider triggers 93 */ 94 #define CLOCK_IP_DIVIDER_TRIGGERS_COUNT (1U) 95 96 /** 97 * @brief Max number of fractional dividers 98 */ 99 #define CLOCK_IP_FRACTIONAL_DIVIDERS_COUNT (0U) 100 101 /** 102 * @brief Max number of external clocks 103 */ 104 #define CLOCK_IP_EXT_CLKS_COUNT (2U) 105 106 /** 107 * @brief Max number of pcfs 108 */ 109 #define CLOCK_IP_PCFS_COUNT (1U) 110 111 /** 112 * @brief Max number of clock gates 113 */ 114 #define CLOCK_IP_GATES_COUNT (100U) 115 116 /** 117 * @brief Max number of clock monitoring units 118 */ 119 #define CLOCK_IP_CMUS_COUNT (4U) 120 121 /** 122 * @brief Max number of configured frequencies values 123 */ 124 #define CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT (6U) 125 126 /** 127 * @brief Max number of specific peripheral (eMIOS) units 128 */ 129 #define CLOCK_IP_SPECIFIC_PERIPH_COUNT (0U) 130 131 /** 132 * @brief Number of clock configurations 0 133 */ 134 #define CLOCK_IP_CONFIGURED_IRCOSCS_0_NO (3U) 135 #define CLOCK_IP_CONFIGURED_XOSCS_0_NO (2U) 136 #define CLOCK_IP_CONFIGURED_PLLS_0_NO (1U) 137 #define CLOCK_IP_CONFIGURED_SELECTORS_0_NO (13U) 138 #define CLOCK_IP_CONFIGURED_DIVIDERS_0_NO (21U) 139 #define CLOCK_IP_CONFIGURED_DIVIDER_TRIGGERS_0_NO (1U) 140 #define CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO (2U) 141 #define CLOCK_IP_CONFIGURED_GATES_0_NO (100U) 142 #define CLOCK_IP_CONFIGURED_CMUS_0_NO (4U) 143 #define CLOCK_IP_CONFIGURED_FREQUENCIES_0_NO (6U) 144 145 /** 146 * @brief Number of clock configurations 1 147 */ 148 #define CLOCK_IP_CONFIGURED_SELECTORS_1_NO (3U) 149 #define CLOCK_IP_CONFIGURED_DIVIDERS_1_NO (3U) 150 #define CLOCK_IP_CONFIGURED_EXT_CLKS_1_NO (2U) 151 #define CLOCK_IP_CONFIGURED_GATES_1_NO (100U) 152 #define CLOCK_IP_CONFIGURED_CMUS_1_NO (4U) 153 #define CLOCK_IP_CONFIGURED_FREQUENCIES_1_NO (6U) 154 155 /** 156 * @brief Supported power mode. 157 */ 158 #define CLOCK_IP_HAS_RUN_MODE 0U 159 160 /** 161 * @brief Firc can be configured to run at 48MHz 162 */ 163 #define CLOCK_IP_SUPPORTS_48MHZ_FREQUENCY 1U 164 165 /** 166 * @brief Firc can be configured to run at 16MHz 167 */ 168 #define CLOCK_IP_SUPPORTS_24MHZ_FREQUENCY 2U 169 170 /** 171 * @brief Firc can be configured to run at 2MHz 172 */ 173 #define CLOCK_IP_SUPPORTS_3MHZ_FREQUENCY 3U 174 175 #define CLOCK_IP_FIRC_FREQUENCY 48000000U 176 177 #define CLOCK_IP_SIRC_FREQUENCY 32000U 178 179 #define CLOCK_IP_DEFAULT_SXOSC_FREQUENCY 32768U 180 181 #define CLOCK_IP_DEFAULT_FXOSC_FREQUENCY 16000000U 182 183 /** 184 * @brief Clock ip supports clock frequency. 185 */ 186 #define CLOCK_IP_GET_FREQUENCY_API (STD_ON) 187 188 /** 189 * @brief Clock ip supports ram wait states. 190 */ 191 #define CLOCK_IP_HAS_RAM_WAIT_STATES 192 /** 193 * @brief Clock ip supports ram wait states. 194 */ 195 #define CLOCK_IP_HAS_FLASH_WAIT_STATES 196 /** 197 * @brief Clock ip supports to disable FIRC in STDBY mode 198 */ 199 #define CLOCK_IP_HAS_FIRC_STDBY_CLOCK_DISABLE 200 201 /** 202 * @brief Clock ip supports to enable FIRC in STDBY mode 203 */ 204 #define CLOCK_IP_HAS_FIRC_STDBY_CLOCK_ENABLE 205 206 /** 207 * @brief Clock ip supports to disable SIRC in STDBY mode 208 */ 209 #define CLOCK_IP_HAS_SIRC_STDBY_CLOCK_DISABLE 210 211 /** 212 * @brief Clock ip supports to enable SIRC in STDBY mode 213 */ 214 #define CLOCK_IP_HAS_SIRC_STDBY_CLOCK_ENABLE 215 /** 216 * @brief Supported clocks. 217 */ 218 #define CLOCK_IP_HAS_FIRC_CLK 1U 219 #define CLOCK_IP_HAS_FIRC_STANDBY_CLK 2U 220 #define CLOCK_IP_HAS_SIRC_CLK 3U 221 #define CLOCK_IP_HAS_SIRC_STANDBY_CLK 4U 222 #define CLOCK_IP_HAS_FXOSC_CLK 5U 223 #define CLOCK_IP_HAS_SXOSC_CLK 6U 224 #define CLOCK_IP_HAS_PLL_CLK 7U 225 #define CLOCK_IP_HAS_PLL_POSTDIV_CLK 8U 226 #define CLOCK_IP_HAS_PLL_PHI0_CLK 9U 227 #define CLOCK_IP_HAS_PLL_PHI1_CLK 10U 228 #define CLOCK_IP_HAS_EMAC_MII_RX_CLK 11U 229 #define CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK 12U 230 #define CLOCK_IP_HAS_SCS_CLK 13U 231 #define CLOCK_IP_HAS_CORE_CLK 14U 232 #define CLOCK_IP_HAS_AIPS_PLAT_CLK 15U 233 #define CLOCK_IP_HAS_AIPS_SLOW_CLK 16U 234 #define CLOCK_IP_HAS_HSE_CLK 17U 235 #define CLOCK_IP_HAS_DCM_CLK 18U 236 #define CLOCK_IP_HAS_LBIST_CLK 19U 237 #define CLOCK_IP_HAS_QSPI_MEM_CLK 20U 238 #define CLOCK_IP_HAS_CLKOUT_RUN_CLK 21U 239 #define CLOCK_IP_FEATURE_PRODUCERS_NO 22U 240 #define CLOCK_IP_HAS_ADC0_CLK 23U 241 #define CLOCK_IP_HAS_ADC1_CLK 24U 242 #define CLOCK_IP_HAS_ADC2_CLK 25U 243 #define CLOCK_IP_HAS_BCTU0_CLK 26U 244 #define CLOCK_IP_HAS_CLKOUT_STANDBY_CLK 27U 245 #define CLOCK_IP_HAS_CMP0_CLK 28U 246 #define CLOCK_IP_HAS_CMP1_CLK 29U 247 #define CLOCK_IP_HAS_CMP2_CLK 30U 248 #define CLOCK_IP_HAS_CRC0_CLK 31U 249 #define CLOCK_IP_HAS_DCM0_CLK 32U 250 #define CLOCK_IP_HAS_DMAMUX0_CLK 33U 251 #define CLOCK_IP_HAS_DMAMUX1_CLK 34U 252 #define CLOCK_IP_HAS_EDMA0_CLK 35U 253 #define CLOCK_IP_HAS_EDMA0_TCD0_CLK 36U 254 #define CLOCK_IP_HAS_EDMA0_TCD1_CLK 37U 255 #define CLOCK_IP_HAS_EDMA0_TCD2_CLK 38U 256 #define CLOCK_IP_HAS_EDMA0_TCD3_CLK 39U 257 #define CLOCK_IP_HAS_EDMA0_TCD4_CLK 40U 258 #define CLOCK_IP_HAS_EDMA0_TCD5_CLK 41U 259 #define CLOCK_IP_HAS_EDMA0_TCD6_CLK 42U 260 #define CLOCK_IP_HAS_EDMA0_TCD7_CLK 43U 261 #define CLOCK_IP_HAS_EDMA0_TCD8_CLK 44U 262 #define CLOCK_IP_HAS_EDMA0_TCD9_CLK 45U 263 #define CLOCK_IP_HAS_EDMA0_TCD10_CLK 46U 264 #define CLOCK_IP_HAS_EDMA0_TCD11_CLK 47U 265 #define CLOCK_IP_HAS_EDMA0_TCD12_CLK 48U 266 #define CLOCK_IP_HAS_EDMA0_TCD13_CLK 49U 267 #define CLOCK_IP_HAS_EDMA0_TCD14_CLK 50U 268 #define CLOCK_IP_HAS_EDMA0_TCD15_CLK 51U 269 #define CLOCK_IP_HAS_EDMA0_TCD16_CLK 52U 270 #define CLOCK_IP_HAS_EDMA0_TCD17_CLK 53U 271 #define CLOCK_IP_HAS_EDMA0_TCD18_CLK 54U 272 #define CLOCK_IP_HAS_EDMA0_TCD19_CLK 55U 273 #define CLOCK_IP_HAS_EDMA0_TCD20_CLK 56U 274 #define CLOCK_IP_HAS_EDMA0_TCD21_CLK 57U 275 #define CLOCK_IP_HAS_EDMA0_TCD22_CLK 58U 276 #define CLOCK_IP_HAS_EDMA0_TCD23_CLK 59U 277 #define CLOCK_IP_HAS_EDMA0_TCD24_CLK 60U 278 #define CLOCK_IP_HAS_EDMA0_TCD25_CLK 61U 279 #define CLOCK_IP_HAS_EDMA0_TCD26_CLK 62U 280 #define CLOCK_IP_HAS_EDMA0_TCD27_CLK 63U 281 #define CLOCK_IP_HAS_EDMA0_TCD28_CLK 64U 282 #define CLOCK_IP_HAS_EDMA0_TCD29_CLK 65U 283 #define CLOCK_IP_HAS_EDMA0_TCD30_CLK 66U 284 #define CLOCK_IP_HAS_EDMA0_TCD31_CLK 67U 285 #define CLOCK_IP_HAS_EIM_CLK 68U 286 #define CLOCK_IP_HAS_EMAC_RX_CLK 69U 287 #define CLOCK_IP_HAS_EMAC0_RX_CLK 70U 288 #define CLOCK_IP_HAS_EMAC_TS_CLK 71U 289 #define CLOCK_IP_HAS_EMAC0_TS_CLK 72U 290 #define CLOCK_IP_HAS_EMAC_TX_CLK 73U 291 #define CLOCK_IP_HAS_EMAC0_TX_CLK 74U 292 #define CLOCK_IP_HAS_EMIOS0_CLK 75U 293 #define CLOCK_IP_HAS_EMIOS1_CLK 76U 294 #define CLOCK_IP_HAS_EMIOS2_CLK 77U 295 #define CLOCK_IP_HAS_ERM0_CLK 78U 296 #define CLOCK_IP_HAS_FLEXCANA_CLK 79U 297 #define CLOCK_IP_HAS_FLEXCAN0_CLK 80U 298 #define CLOCK_IP_HAS_FLEXCAN1_CLK 81U 299 #define CLOCK_IP_HAS_FLEXCAN2_CLK 82U 300 #define CLOCK_IP_HAS_FLEXCANB_CLK 83U 301 #define CLOCK_IP_HAS_FLEXCAN3_CLK 84U 302 #define CLOCK_IP_HAS_FLEXCAN4_CLK 85U 303 #define CLOCK_IP_HAS_FLEXCAN5_CLK 86U 304 #define CLOCK_IP_HAS_FLEXIO0_CLK 87U 305 #define CLOCK_IP_HAS_INTM_CLK 88U 306 #define CLOCK_IP_HAS_LCU0_CLK 89U 307 #define CLOCK_IP_HAS_LCU1_CLK 90U 308 #define CLOCK_IP_HAS_LPI2C0_CLK 91U 309 #define CLOCK_IP_HAS_LPI2C1_CLK 92U 310 #define CLOCK_IP_HAS_LPSPI0_CLK 93U 311 #define CLOCK_IP_HAS_LPSPI1_CLK 94U 312 #define CLOCK_IP_HAS_LPSPI2_CLK 95U 313 #define CLOCK_IP_HAS_LPSPI3_CLK 96U 314 #define CLOCK_IP_HAS_LPSPI4_CLK 97U 315 #define CLOCK_IP_HAS_LPSPI5_CLK 98U 316 #define CLOCK_IP_HAS_LPUART0_CLK 99U 317 #define CLOCK_IP_HAS_LPUART1_CLK 100U 318 #define CLOCK_IP_HAS_LPUART2_CLK 101U 319 #define CLOCK_IP_HAS_LPUART3_CLK 102U 320 #define CLOCK_IP_HAS_LPUART4_CLK 103U 321 #define CLOCK_IP_HAS_LPUART5_CLK 104U 322 #define CLOCK_IP_HAS_LPUART6_CLK 105U 323 #define CLOCK_IP_HAS_LPUART7_CLK 106U 324 #define CLOCK_IP_HAS_LPUART8_CLK 107U 325 #define CLOCK_IP_HAS_LPUART9_CLK 108U 326 #define CLOCK_IP_HAS_LPUART10_CLK 109U 327 #define CLOCK_IP_HAS_LPUART11_CLK 110U 328 #define CLOCK_IP_HAS_LPUART12_CLK 111U 329 #define CLOCK_IP_HAS_LPUART13_CLK 112U 330 #define CLOCK_IP_HAS_LPUART14_CLK 113U 331 #define CLOCK_IP_HAS_LPUART15_CLK 114U 332 #define CLOCK_IP_HAS_MSCM_CLK 115U 333 #define CLOCK_IP_HAS_MU2A_CLK 116U 334 #define CLOCK_IP_HAS_MU2B_CLK 117U 335 #define CLOCK_IP_HAS_PIT0_CLK 118U 336 #define CLOCK_IP_HAS_PIT1_CLK 119U 337 #define CLOCK_IP_HAS_PIT2_CLK 120U 338 #define CLOCK_IP_HAS_QSPI0_CLK 121U 339 #define CLOCK_IP_HAS_QSPI0_RAM_CLK 122U 340 #define CLOCK_IP_HAS_QSPI0_TX_MEM_CLK 123U 341 #define CLOCK_IP_HAS_QSPI_SFCK_CLK 124U 342 #define CLOCK_IP_HAS_RTC_CLK 125U 343 #define CLOCK_IP_HAS_RTC0_CLK 126U 344 #define CLOCK_IP_HAS_SAI0_CLK 127U 345 #define CLOCK_IP_HAS_SAI1_CLK 128U 346 #define CLOCK_IP_HAS_SEMA42_CLK 129U 347 #define CLOCK_IP_HAS_SIUL2_CLK 130U 348 #define CLOCK_IP_HAS_STCU0_CLK 131U 349 #define CLOCK_IP_HAS_STMA_CLK 132U 350 #define CLOCK_IP_HAS_STM0_CLK 133U 351 #define CLOCK_IP_HAS_STMB_CLK 134U 352 #define CLOCK_IP_HAS_STM1_CLK 135U 353 #define CLOCK_IP_HAS_SWT0_CLK 136U 354 #define CLOCK_IP_HAS_TEMPSENSE_CLK 137U 355 #define CLOCK_IP_HAS_TRACE_CLK 138U 356 #define CLOCK_IP_HAS_TRGMUX0_CLK 139U 357 #define CLOCK_IP_HAS_TSENSE0_CLK 140U 358 #define CLOCK_IP_HAS_WKPU0_CLK 141U 359 #define CLOCK_IP_FEATURE_NAMES_NO 142U 360 361 362 /*================================================================================================== 363 ENUMS 364 ==================================================================================================*/ 365 366 367 /*================================================================================================== 368 STRUCTURES AND OTHER TYPEDEFS 369 ==================================================================================================*/ 370 371 372 373 #ifdef __cplusplus 374 } 375 #endif 376 377 #endif /* #ifndef CLOCK_IP_CFG_DEFINES_H */ 378 379 /** @} */ 380
