1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /** 8 * @file Clock_Ip_Cfg_Defines.h 9 * @version 2.0.0 10 * 11 * @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template. 12 * @details Code template for Post-Build(PB) configuration file generation. 13 * 14 * @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver 15 * @{ 16 */ 17 18 #ifndef CLOCK_IP_CFG_DEFINES_H 19 #define CLOCK_IP_CFG_DEFINES_H 20 21 22 #ifdef __cplusplus 23 extern "C"{ 24 #endif 25 26 27 /*================================================================================================== 28 INCLUDE FILES 29 1) system and project includes 30 2) needed interfaces from external units 31 3) internal and external interfaces from this unit 32 ==================================================================================================*/ 33 #include "S32K146_SIM.h" 34 #include "S32K146_SCG.h" 35 #include "S32K146_PCC.h" 36 #include "S32K146_SMC.h" 37 /*================================================================================================== 38 SOURCE FILE VERSION INFORMATION 39 ==================================================================================================*/ 40 #define CLOCK_IP_CFG_DEFINES_VENDOR_ID 43 41 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4 42 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 7 43 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0 44 #define CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION 2 45 #define CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION 0 46 #define CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION 0 47 48 /*================================================================================================== 49 DEFINES AND MACROS 50 ==================================================================================================*/ 51 /** 52 * @brief Derivative used. 53 */ 54 #define CLOCK_IP_S32K146 55 /** 56 * @brief HW sseries used. 57 */ 58 #define CLOCK_IP_S32K1 59 /** 60 * @brief Max number of internal oscillators 61 */ 62 #define CLOCK_IP_IRCOSCS_COUNT (2U) 63 64 /** 65 * @brief Max number of external oscillators 66 */ 67 #define CLOCK_IP_XOSCS_COUNT (1U) 68 69 /** 70 * @brief Max number of pll devices 71 */ 72 #define CLOCK_IP_PLLS_COUNT (1U) 73 74 /** 75 * @brief Max number of selectors 76 */ 77 #define CLOCK_IP_SELECTORS_COUNT (32U) 78 79 /** 80 * @brief Max number of dividers 81 */ 82 #define CLOCK_IP_DIVIDERS_COUNT (20U) 83 84 /** 85 * @brief Max number of divider triggers 86 */ 87 #define CLOCK_IP_DIVIDER_TRIGGERS_COUNT (0U) 88 89 /** 90 * @brief Max number of fractional dividers 91 */ 92 #define CLOCK_IP_FRACTIONAL_DIVIDERS_COUNT (0U) 93 94 /** 95 * @brief Max number of external clocks 96 */ 97 #define CLOCK_IP_EXT_CLKS_COUNT (4U) 98 99 /** 100 * @brief Max number of pcfs 101 */ 102 #define CLOCK_IP_PCFS_COUNT (0U) 103 104 /** 105 * @brief Max number of clock gates 106 */ 107 #define CLOCK_IP_GATES_COUNT (43U) 108 109 /** 110 * @brief Max number of clock monitoring units 111 */ 112 #define CLOCK_IP_CMUS_COUNT (0U) 113 114 /** 115 * @brief Max number of configured frequencies values 116 */ 117 #define CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT (1U) 118 119 /** 120 * @brief Max number of specific peripheral (eMIOS) units 121 */ 122 #define CLOCK_IP_SPECIFIC_PERIPH_COUNT (0U) 123 124 /** 125 * @brief Supported power mode. 126 */ 127 #define CLOCK_IP_HAS_RUN_MODE 0U 128 129 #define CLOCK_IP_LPO_128K_FREQUENCY 128000U 130 131 #define CLOCK_IP_FIRC_FREQUENCY 48000000U 132 133 #define CLOCK_IP_SIRC_FREQUENCY 8000000U 134 135 #define CLOCK_IP_DEFAULT_SOSC_FREQUENCY 40000000U 136 137 #define CLOCK_IP_HAS_LOW_GAIN 0U 138 139 #define CLOCK_IP_HAS_HIGH_GAIN 1U 140 141 #define CLOCK_IP_HAS_MONITOR_DISABLE 0U 142 143 #define CLOCK_IP_HAS_MONITOR_INT 1U 144 145 #define CLOCK_IP_HAS_MONITOR_RESET 2U 146 147 #define CLOCK_IP_HAS_SAFE_CLOCK_DISABLEMENT 1U 148 149 #if CLOCK_IP_CMUS_COUNT > 0U 150 /** 151 * @brief Cmu formula constant values. 152 */ 153 #define CLOCK_IP_FEATURE_OFFSET_REFERENCE_COUNT_FORMULA1 1U 154 #define CLOCK_IP_FEATURE_MULTIPLIER_REFERENCE_COUNT_FORMULA1 3U 155 #define CLOCK_IP_FEATURE_OFFSET_REFERENCE_COUNT_FORMULA2 7U 156 #define CLOCK_IP_FEATURE_MULTIPLIER_REFERENCE_COUNT_FORMULA2 3U 157 #endif 158 159 /** 160 * @brief Clock ip supports clock frequency. 161 */ 162 #define CLOCK_IP_GET_FREQUENCY_API (STD_ON) 163 164 /** 165 * @brief Supports wait states configuration 166 */ 167 #define CLOCK_IP_SUPPORTS_WAIT_STATES STD_OFF 168 169 170 /** 171 * @brief Clock ip supports power mode change notification 172 */ 173 #define CLOCK_IP_POWER_MODE_CHANGE_NOTIFICATION STD_ON 174 175 176 /** 177 * @brief Supported clocks. 178 */ 179 #define CLOCK_IP_HAS_LPO_128K_CLK 1U 180 #define CLOCK_IP_HAS_SIRC_CLK 2U 181 #define CLOCK_IP_HAS_SIRC_VLP_CLK 3U 182 #define CLOCK_IP_HAS_SIRC_STOP_CLK 4U 183 #define CLOCK_IP_HAS_FIRC_CLK 5U 184 #define CLOCK_IP_HAS_FIRC_VLP_CLK 6U 185 #define CLOCK_IP_HAS_FIRC_STOP_CLK 7U 186 #define CLOCK_IP_HAS_SOSC_CLK 8U 187 #define CLOCK_IP_HAS_SPLL_CLK 9U 188 #define CLOCK_IP_HAS_SIRCDIV1_CLK 10U 189 #define CLOCK_IP_HAS_SIRCDIV2_CLK 11U 190 #define CLOCK_IP_HAS_FIRCDIV1_CLK 12U 191 #define CLOCK_IP_HAS_FIRCDIV2_CLK 13U 192 #define CLOCK_IP_HAS_SOSCDIV1_CLK 14U 193 #define CLOCK_IP_HAS_SOSCDIV2_CLK 15U 194 #define CLOCK_IP_HAS_SPLLDIV1_CLK 16U 195 #define CLOCK_IP_HAS_SPLLDIV2_CLK 17U 196 #define CLOCK_IP_HAS_LPO_32K_CLK 18U 197 #define CLOCK_IP_HAS_LPO_1K_CLK 19U 198 #define CLOCK_IP_HAS_TCLK0_REF_CLK 20U 199 #define CLOCK_IP_HAS_TCLK1_REF_CLK 21U 200 #define CLOCK_IP_HAS_TCLK2_REF_CLK 22U 201 #define CLOCK_IP_HAS_RTC_CLKIN 23U 202 #define CLOCK_IP_HAS_SCS_CLK 24U 203 #define CLOCK_IP_HAS_SCS_RUN_CLK 25U 204 #define CLOCK_IP_HAS_SCS_VLPR_CLK 26U 205 #define CLOCK_IP_HAS_SCS_HSRUN_CLK 27U 206 #define CLOCK_IP_HAS_CORE_CLK 28U 207 #define CLOCK_IP_HAS_CORE_RUN_CLK 29U 208 #define CLOCK_IP_HAS_CORE_VLPR_CLK 30U 209 #define CLOCK_IP_HAS_CORE_HSRUN_CLK 31U 210 #define CLOCK_IP_HAS_BUS_CLK 32U 211 #define CLOCK_IP_HAS_BUS_RUN_CLK 33U 212 #define CLOCK_IP_HAS_BUS_VLPR_CLK 34U 213 #define CLOCK_IP_HAS_BUS_HSRUN_CLK 35U 214 #define CLOCK_IP_HAS_SLOW_CLK 36U 215 #define CLOCK_IP_HAS_SLOW_RUN_CLK 37U 216 #define CLOCK_IP_HAS_SLOW_VLPR_CLK 38U 217 #define CLOCK_IP_HAS_SLOW_HSRUN_CLK 39U 218 #define CLOCK_IP_HAS_RTC_CLK 40U 219 #define CLOCK_IP_HAS_LPO_CLK 41U 220 #define CLOCK_IP_HAS_SCG_CLKOUT_CLK 42U 221 #define CLOCK_IP_HAS_FTM0_EXT_CLK 43U 222 #define CLOCK_IP_HAS_FTM1_EXT_CLK 44U 223 #define CLOCK_IP_HAS_FTM2_EXT_CLK 45U 224 #define CLOCK_IP_HAS_FTM3_EXT_CLK 46U 225 #define CLOCK_IP_HAS_FTM4_EXT_CLK 47U 226 #define CLOCK_IP_HAS_FTM5_EXT_CLK 48U 227 #define CLOCK_IP_FEATURE_PRODUCERS_NO 49U 228 #define CLOCK_IP_HAS_ADC0_CLK 50U 229 #define CLOCK_IP_HAS_ADC1_CLK 51U 230 #define CLOCK_IP_HAS_CLKOUT0_CLK 52U 231 #define CLOCK_IP_HAS_CMP0_CLK 53U 232 #define CLOCK_IP_HAS_CRC0_CLK 54U 233 #define CLOCK_IP_HAS_DMA0_CLK 55U 234 #define CLOCK_IP_HAS_DMAMUX0_CLK 56U 235 #define CLOCK_IP_HAS_EIM0_CLK 57U 236 #define CLOCK_IP_HAS_ERM0_CLK 58U 237 #define CLOCK_IP_HAS_EWM0_CLK 59U 238 #define CLOCK_IP_HAS_FLEXCAN0_CLK 60U 239 #define CLOCK_IP_HAS_FLEXCAN1_CLK 61U 240 #define CLOCK_IP_HAS_FLEXCAN2_CLK 62U 241 #define CLOCK_IP_HAS_FlexIO_CLK 63U 242 #define CLOCK_IP_HAS_FTFC_CLK 64U 243 #define CLOCK_IP_HAS_FTM0_CLK 65U 244 #define CLOCK_IP_HAS_FTM1_CLK 66U 245 #define CLOCK_IP_HAS_FTM2_CLK 67U 246 #define CLOCK_IP_HAS_FTM3_CLK 68U 247 #define CLOCK_IP_HAS_FTM4_CLK 69U 248 #define CLOCK_IP_HAS_FTM5_CLK 70U 249 #define CLOCK_IP_HAS_LPI2C0_CLK 71U 250 #define CLOCK_IP_HAS_LPIT0_CLK 72U 251 #define CLOCK_IP_HAS_LPSPI0_CLK 73U 252 #define CLOCK_IP_HAS_LPSPI1_CLK 74U 253 #define CLOCK_IP_HAS_LPSPI2_CLK 75U 254 #define CLOCK_IP_HAS_LPTMR0_CLK 76U 255 #define CLOCK_IP_HAS_LPUART0_CLK 77U 256 #define CLOCK_IP_HAS_LPUART1_CLK 78U 257 #define CLOCK_IP_HAS_LPUART2_CLK 79U 258 #define CLOCK_IP_HAS_MPU0_CLK 80U 259 #define CLOCK_IP_HAS_MSCM0_CLK 81U 260 #define CLOCK_IP_HAS_PDB0_CLK 82U 261 #define CLOCK_IP_HAS_PDB1_CLK 83U 262 #define CLOCK_IP_HAS_PORTA_CLK 84U 263 #define CLOCK_IP_HAS_PORTB_CLK 85U 264 #define CLOCK_IP_HAS_PORTC_CLK 86U 265 #define CLOCK_IP_HAS_PORTD_CLK 87U 266 #define CLOCK_IP_HAS_PORTE_CLK 88U 267 #define CLOCK_IP_HAS_RTC0_CLK 89U 268 #define CLOCK_IP_HAS_TRACE_CLK 90U 269 #define CLOCK_IP_FEATURE_NAMES_NO 91U 270 271 /*================================================================================================== 272 ENUMS 273 ==================================================================================================*/ 274 275 276 /*================================================================================================== 277 STRUCTURES AND OTHER TYPEDEFS 278 ==================================================================================================*/ 279 280 281 282 #ifdef __cplusplus 283 } 284 #endif 285 286 #endif /* #ifndef CLOCK_IP_CFG_DEFINES_H */ 287 288 /** @} */ 289
