1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CLOCK_IP_TYPES_H 8 #define CLOCK_IP_TYPES_H 9 10 /** 11 * @file Clock_Ip_Types.h 12 * @version 2.0.0 13 * 14 * @brief CLOCK IP type header file. 15 * @details CLOCK IP type header file. 16 17 * @addtogroup CLOCK_DRIVER Clock Ip Driver 18 * @{ 19 */ 20 21 #if defined(__cplusplus) 22 extern "C"{ 23 #endif 24 /*================================================================================================== 25 * INCLUDE FILES 26 * 1) system and project includes 27 * 2) needed interfaces from external units 28 * 3) internal and external interfaces from this unit 29 ==================================================================================================*/ 30 #include "StandardTypes.h" 31 #include "Clock_Ip_Cfg_Defines.h" 32 33 /*================================================================================================== 34 SOURCE FILE VERSION INFORMATION 35 ==================================================================================================*/ 36 #define CLOCK_IP_TYPES_VENDOR_ID 43 37 #define CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION 4 38 #define CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION 7 39 #define CLOCK_IP_TYPES_AR_RELEASE_REVISION_VERSION 0 40 #define CLOCK_IP_TYPES_SW_MAJOR_VERSION 2 41 #define CLOCK_IP_TYPES_SW_MINOR_VERSION 0 42 #define CLOCK_IP_TYPES_SW_PATCH_VERSION 0 43 44 /*================================================================================================== 45 FILE VERSION CHECKS 46 ==================================================================================================*/ 47 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 48 /* Check if Clock_Ip_Types.h file and StandardTypes.h file are of the same Autosar version */ 49 #if ((CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \ 50 (CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION)) 51 #error "AutoSar Version Numbers of Clock_Ip_Types.h and StandardTypes.h are different" 52 #endif 53 #endif 54 55 /* Check if Clock_Ip_Types.h file and Clock_Ip_Cfg_Defines.h file have same versions */ 56 #if (CLOCK_IP_TYPES_VENDOR_ID != CLOCK_IP_CFG_DEFINES_VENDOR_ID) 57 #error "Clock_Ip_Types.h and Clock_Ip_Cfg_Defines.h have different vendor IDs" 58 #endif 59 60 /* Check if Clock_Ip_Types.h file and Clock_Ip_Cfg_Defines.h file are of the same Autosar version */ 61 #if ((CLOCK_IP_TYPES_AR_RELEASE_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ 62 (CLOCK_IP_TYPES_AR_RELEASE_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ 63 (CLOCK_IP_TYPES_AR_RELEASE_REVISION_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) 64 #error "AutoSar Version Numbers of Clock_Ip_Types.h and Clock_Ip_Cfg_Defines.h are different" 65 #endif 66 67 /* Check if Clock_Ip_Types.h file and Clock_Ip_Cfg_Defines.h file are of the same Software version */ 68 #if ((CLOCK_IP_TYPES_SW_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ 69 (CLOCK_IP_TYPES_SW_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ 70 (CLOCK_IP_TYPES_SW_PATCH_VERSION != CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION)) 71 #error "Software Version Numbers of Clock_Ip_Types.h and Clock_Ip_Cfg_Defines.h are different" 72 #endif 73 74 /*================================================================================================== 75 * CONSTANTS 76 ==================================================================================================*/ 77 78 /*================================================================================================== 79 * DEFINES AND MACROS 80 ==================================================================================================*/ 81 /* Number of internal oscillators */ 82 #if CLOCK_IP_IRCOSCS_COUNT > 0U 83 #define CLOCK_IP_IRCOSCS_NO CLOCK_IP_IRCOSCS_COUNT 84 #else 85 #define CLOCK_IP_IRCOSCS_NO 1U 86 #endif 87 88 /* Number of external oscillators */ 89 #if CLOCK_IP_XOSCS_COUNT > 0U 90 #define CLOCK_IP_XOSCS_NO CLOCK_IP_XOSCS_COUNT 91 #else 92 #define CLOCK_IP_XOSCS_NO 1U 93 #endif 94 95 /* Number of pllS */ 96 #if CLOCK_IP_PLLS_COUNT > 0U 97 #define CLOCK_IP_PLLS_NO CLOCK_IP_PLLS_COUNT 98 #else 99 #define CLOCK_IP_PLLS_NO 1U 100 #endif 101 102 /* Number of selectors */ 103 #if CLOCK_IP_SELECTORS_COUNT > 0U 104 #define CLOCK_IP_SELECTORS_NO CLOCK_IP_SELECTORS_COUNT 105 #else 106 #define CLOCK_IP_SELECTORS_NO 1U 107 #endif 108 109 /* Number of dividers */ 110 #if CLOCK_IP_DIVIDERS_COUNT > 0U 111 #define CLOCK_IP_DIVIDERS_NO CLOCK_IP_DIVIDERS_COUNT 112 #else 113 #define CLOCK_IP_DIVIDERS_NO 1U 114 #endif 115 116 /* Number of dividers */ 117 #if CLOCK_IP_DIVIDER_TRIGGERS_COUNT > 0U 118 #define CLOCK_IP_DIVIDER_TRIGGERS_NO CLOCK_IP_DIVIDER_TRIGGERS_COUNT 119 #else 120 #define CLOCK_IP_DIVIDER_TRIGGERS_NO 1U 121 #endif 122 123 /* Number of fractional dividers */ 124 #if CLOCK_IP_FRACTIONAL_DIVIDERS_COUNT > 0U 125 #define CLOCK_IP_FRACTIONAL_DIVIDERS_NO CLOCK_IP_FRACTIONAL_DIVIDERS_COUNT 126 #else 127 #define CLOCK_IP_FRACTIONAL_DIVIDERS_NO 1U 128 #endif 129 130 /* Number of external clocks */ 131 #if CLOCK_IP_EXT_CLKS_COUNT > 0U 132 #define CLOCK_IP_EXT_CLKS_NO CLOCK_IP_EXT_CLKS_COUNT 133 #else 134 #define CLOCK_IP_EXT_CLKS_NO 1U 135 #endif 136 137 /* Number of external clocks */ 138 #if CLOCK_IP_GATES_COUNT > 0U 139 #define CLOCK_IP_GATES_NO CLOCK_IP_GATES_COUNT 140 #else 141 #define CLOCK_IP_GATES_NO 1U 142 #endif 143 144 /* Number of progressive frequemcy clock switching */ 145 #if CLOCK_IP_PCFS_COUNT > 0U 146 #define CLOCK_IP_PCFS_NO CLOCK_IP_PCFS_COUNT 147 #else 148 #define CLOCK_IP_PCFS_NO 1U 149 #endif 150 151 /* Number of external clocks */ 152 #if CLOCK_IP_CMUS_COUNT > 0U 153 #define CLOCK_IP_CMUS_NO CLOCK_IP_CMUS_COUNT 154 #else 155 #define CLOCK_IP_CMUS_NO 1U 156 #endif 157 158 /* Number of configured frequencies values */ 159 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 0U 160 #define CLOCK_IP_CONFIGURED_FREQUENCIES_NO CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT 161 #else 162 #define CLOCK_IP_CONFIGURED_FREQUENCIES_NO 1U 163 #endif 164 165 /* Number of special peripheral clocks */ 166 #if CLOCK_IP_SPECIFIC_PERIPH_COUNT > 0U 167 #define CLOCK_IP_SPECIFIC_PERIPH_NO CLOCK_IP_SPECIFIC_PERIPH_COUNT 168 #else 169 #define CLOCK_IP_SPECIFIC_PERIPH_NO 1U 170 #endif 171 172 /*================================================================================================== 173 * ENUMS 174 ==================================================================================================*/ 175 #if (defined(CLOCK_IP_POWER_MODE_CHANGE_NOTIFICATION)) 176 /** @brief Power modes. */ 177 typedef enum { 178 179 #if defined(CLOCK_IP_HAS_RUN_MODE) 180 RUN_MODE = CLOCK_IP_HAS_RUN_MODE, 181 VLPR_MODE = 1U, 182 VLPS_MODE = 2U, 183 HSRUN_MODE = 3U, 184 #endif 185 } Clock_Ip_PowerModesType; 186 187 /** @brief Power mode notification. */ 188 typedef enum { 189 190 BEFORE_POWER_MODE_CHANGE, /* Before power mode change command is sent */ 191 POWER_MODE_CHANGE_IN_PROGRESS, /* Power mode transition is in progress */ 192 POWER_MODE_CHANGED, /* Power mode transition completed */ 193 194 } Clock_Ip_PowerNotificationType; 195 #endif 196 197 /** @brief Clock names. */ 198 typedef enum { 199 200 CLOCK_IS_OFF = 0U, 201 202 #if defined(CLOCK_IP_HAS_FIRC_CLK) 203 FIRC_CLK = CLOCK_IP_HAS_FIRC_CLK, 204 #endif 205 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK) 206 FIRC_AE_CLK = CLOCK_IP_HAS_FIRC_AE_CLK, 207 #endif 208 #if defined(CLOCK_IP_HAS_FIRC_MUXED_CLK) 209 FIRC_MUXED_CLK = CLOCK_IP_HAS_FIRC_MUXED_CLK, 210 #endif 211 #if defined(CLOCK_IP_HAS_FIRC_VLP_CLK) 212 FIRC_VLP_CLK = CLOCK_IP_HAS_FIRC_VLP_CLK, 213 #endif 214 #if defined(CLOCK_IP_HAS_FIRC_STOP_CLK) 215 FIRC_STOP_CLK = CLOCK_IP_HAS_FIRC_STOP_CLK, 216 #endif 217 #if defined(CLOCK_IP_HAS_FIRC_STANDBY_CLK) 218 FIRC_STANDBY_CLK = CLOCK_IP_HAS_FIRC_STANDBY_CLK, 219 #endif 220 #if defined(CLOCK_IP_HAS_FIRC_POSTDIV_CLK) 221 FIRC_POSTDIV_CLK = CLOCK_IP_HAS_FIRC_POSTDIV_CLK, 222 #endif 223 #if defined(CLOCK_IP_HAS_FRO_CLK) 224 FRO_CLK = CLOCK_IP_HAS_FRO_CLK, 225 #endif 226 #if defined(CLOCK_IP_HAS_SAFE_CLK) 227 SAFE_CLK = CLOCK_IP_HAS_SAFE_CLK, 228 #endif 229 #if defined(CLOCK_IP_HAS_SIRC_CLK) 230 SIRC_CLK = CLOCK_IP_HAS_SIRC_CLK, 231 #endif 232 #if defined(CLOCK_IP_HAS_SIRC_VLP_CLK) 233 SIRC_VLP_CLK = CLOCK_IP_HAS_SIRC_VLP_CLK, 234 #endif 235 #if defined(CLOCK_IP_HAS_SIRC_STOP_CLK) 236 SIRC_STOP_CLK = CLOCK_IP_HAS_SIRC_STOP_CLK, 237 #endif 238 #if defined(CLOCK_IP_HAS_SIRC_STANDBY_CLK) 239 SIRC_STANDBY_CLK = CLOCK_IP_HAS_SIRC_STANDBY_CLK, 240 #endif 241 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 242 SYSTEM_CLK = CLOCK_IP_HAS_SYSTEM_CLK, 243 #endif 244 #if defined(CLOCK_IP_HAS_LPO_128K_CLK) 245 LPO_128K_CLK = CLOCK_IP_HAS_LPO_128K_CLK, 246 #endif 247 #if defined(CLOCK_IP_HAS_FXOSC_CLK) 248 FXOSC_CLK = CLOCK_IP_HAS_FXOSC_CLK, 249 #endif 250 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 251 SXOSC_CLK = CLOCK_IP_HAS_SXOSC_CLK, 252 #endif 253 #if defined(CLOCK_IP_HAS_SOSC_CLK) 254 SOSC_CLK = CLOCK_IP_HAS_SOSC_CLK, 255 #endif 256 #if defined(CLOCK_IP_HAS_ACCELPLL_CLK) 257 ACCELPLL_CLK = CLOCK_IP_HAS_ACCELPLL_CLK, 258 #endif 259 #if defined(CLOCK_IP_HAS_COREPLL_CLK) 260 COREPLL_CLK = CLOCK_IP_HAS_COREPLL_CLK, 261 #endif 262 #if defined(CLOCK_IP_HAS_DDRPLL_CLK) 263 DDRPLL_CLK = CLOCK_IP_HAS_DDRPLL_CLK, 264 #endif 265 #if defined(CLOCK_IP_HAS_PERIPHPLL_CLK) 266 PERIPHPLL_CLK = CLOCK_IP_HAS_PERIPHPLL_CLK, 267 #endif 268 #if defined(CLOCK_IP_HAS_LFAST0_PLL_CLK) 269 LFAST0_PLL_CLK = CLOCK_IP_HAS_LFAST0_PLL_CLK, 270 #endif 271 #if defined(CLOCK_IP_HAS_LFAST1_PLL_CLK) 272 LFAST1_PLL_CLK = CLOCK_IP_HAS_LFAST1_PLL_CLK, 273 #endif 274 #if defined(CLOCK_IP_HAS_PLL_CLK) 275 PLL_CLK = CLOCK_IP_HAS_PLL_CLK, 276 #endif 277 #if defined(CLOCK_IP_HAS_PLL0_CLK) 278 PLL0_CLK = CLOCK_IP_HAS_PLL0_CLK, 279 #endif 280 #if defined(CLOCK_IP_HAS_PLL1_CLK) 281 PLL1_CLK = CLOCK_IP_HAS_PLL1_CLK, 282 #endif 283 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 284 PLLAUX_CLK = CLOCK_IP_HAS_PLLAUX_CLK, 285 #endif 286 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK) 287 PLLAUX_PHI0_CLK = CLOCK_IP_HAS_PLLAUX_PHI0_CLK, 288 #endif 289 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK) 290 PLLAUX_PHI1_CLK = CLOCK_IP_HAS_PLLAUX_PHI1_CLK, 291 #endif 292 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK) 293 PLLAUX_PHI2_CLK = CLOCK_IP_HAS_PLLAUX_PHI2_CLK, 294 #endif 295 #if defined(CLOCK_IP_HAS_SPLL_CLK) 296 SPLL_CLK = CLOCK_IP_HAS_SPLL_CLK, 297 #endif 298 #if defined(CLOCK_IP_HAS_AURORAPLL_CLK) 299 AURORAPLL_CLK = CLOCK_IP_HAS_AURORAPLL_CLK, 300 #endif 301 #if defined(CLOCK_IP_HAS_ACCEL_PLL_PHI0_CLK) 302 ACCEL_PLL_PHI0_CLK = CLOCK_IP_HAS_ACCEL_PLL_PHI0_CLK, 303 #endif 304 #if defined(CLOCK_IP_HAS_ACCEL_PLL_PHI1_CLK) 305 ACCEL_PLL_PHI1_CLK = CLOCK_IP_HAS_ACCEL_PLL_PHI1_CLK, 306 #endif 307 #if defined(CLOCK_IP_HAS_CORE_PLL_PHI0_CLK) 308 CORE_PLL_PHI0_CLK = CLOCK_IP_HAS_CORE_PLL_PHI0_CLK, 309 #endif 310 #if defined(CLOCK_IP_HAS_CORE_PLL_PHI1_CLK) 311 CORE_PLL_PHI1_CLK = CLOCK_IP_HAS_CORE_PLL_PHI1_CLK, 312 #endif 313 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS0_CLK) 314 CORE_PLL_DFS0_CLK = CLOCK_IP_HAS_CORE_PLL_DFS0_CLK, 315 #endif 316 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS1_CLK) 317 CORE_PLL_DFS1_CLK = CLOCK_IP_HAS_CORE_PLL_DFS1_CLK, 318 #endif 319 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS2_CLK) 320 CORE_PLL_DFS2_CLK = CLOCK_IP_HAS_CORE_PLL_DFS2_CLK, 321 #endif 322 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS3_CLK) 323 CORE_PLL_DFS3_CLK = CLOCK_IP_HAS_CORE_PLL_DFS3_CLK, 324 #endif 325 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS4_CLK) 326 CORE_PLL_DFS4_CLK = CLOCK_IP_HAS_CORE_PLL_DFS4_CLK, 327 #endif 328 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS5_CLK) 329 CORE_PLL_DFS5_CLK = CLOCK_IP_HAS_CORE_PLL_DFS5_CLK, 330 #endif 331 #if defined(CLOCK_IP_HAS_CORE_PLL_DFS6_CLK) 332 CORE_PLL_DFS6_CLK = CLOCK_IP_HAS_CORE_PLL_DFS6_CLK, 333 #endif 334 #if defined(CLOCK_IP_HAS_DDR_PLL_PHI0_CLK) 335 DDR_PLL_PHI0_CLK = CLOCK_IP_HAS_DDR_PLL_PHI0_CLK, 336 #endif 337 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI0_CLK) 338 PERIPH_PLL_PHI0_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI0_CLK, 339 #endif 340 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI1_CLK) 341 PERIPH_PLL_PHI1_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI1_CLK, 342 #endif 343 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI2_CLK) 344 PERIPH_PLL_PHI2_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI2_CLK, 345 #endif 346 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI3_CLK) 347 PERIPH_PLL_PHI3_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI3_CLK, 348 #endif 349 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI4_CLK) 350 PERIPH_PLL_PHI4_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI4_CLK, 351 #endif 352 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI5_CLK) 353 PERIPH_PLL_PHI5_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI5_CLK, 354 #endif 355 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI6_CLK) 356 PERIPH_PLL_PHI6_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI6_CLK, 357 #endif 358 #if defined(CLOCK_IP_HAS_PERIPH_PLL_PHI7_CLK) 359 PERIPH_PLL_PHI7_CLK = CLOCK_IP_HAS_PERIPH_PLL_PHI7_CLK, 360 #endif 361 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS0_CLK) 362 PERIPH_PLL_DFS0_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS0_CLK, 363 #endif 364 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS1_CLK) 365 PERIPH_PLL_DFS1_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS1_CLK, 366 #endif 367 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS2_CLK) 368 PERIPH_PLL_DFS2_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS2_CLK, 369 #endif 370 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS3_CLK) 371 PERIPH_PLL_DFS3_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS3_CLK, 372 #endif 373 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS4_CLK) 374 PERIPH_PLL_DFS4_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS4_CLK, 375 #endif 376 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS5_CLK) 377 PERIPH_PLL_DFS5_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS5_CLK, 378 #endif 379 #if defined(CLOCK_IP_HAS_PERIPH_PLL_DFS6_CLK) 380 PERIPH_PLL_DFS6_CLK = CLOCK_IP_HAS_PERIPH_PLL_DFS6_CLK, 381 #endif 382 #if defined(CLOCK_IP_HAS_COREPLL_PHI0_CLK) 383 COREPLL_PHI0_CLK = CLOCK_IP_HAS_COREPLL_PHI0_CLK, 384 #endif 385 #if defined(CLOCK_IP_HAS_COREPLL_PHI1_CLK) 386 COREPLL_PHI1_CLK = CLOCK_IP_HAS_COREPLL_PHI1_CLK, 387 #endif 388 #if defined(CLOCK_IP_HAS_COREPLL_PHI2_CLK) 389 COREPLL_PHI2_CLK = CLOCK_IP_HAS_COREPLL_PHI2_CLK, 390 #endif 391 #if defined(CLOCK_IP_HAS_COREPLL_PHI3_CLK) 392 COREPLL_PHI3_CLK = CLOCK_IP_HAS_COREPLL_PHI3_CLK, 393 #endif 394 #if defined(CLOCK_IP_HAS_COREPLL_PHI4_CLK) 395 COREPLL_PHI4_CLK = CLOCK_IP_HAS_COREPLL_PHI4_CLK, 396 #endif 397 #if defined(CLOCK_IP_HAS_COREPLL_PHI5_CLK) 398 COREPLL_PHI5_CLK = CLOCK_IP_HAS_COREPLL_PHI5_CLK, 399 #endif 400 #if defined(CLOCK_IP_HAS_COREPLL_PHI6_CLK) 401 COREPLL_PHI6_CLK = CLOCK_IP_HAS_COREPLL_PHI6_CLK, 402 #endif 403 #if defined(CLOCK_IP_HAS_COREPLL_PHI7_CLK) 404 COREPLL_PHI7_CLK = CLOCK_IP_HAS_COREPLL_PHI7_CLK, 405 #endif 406 #if defined(CLOCK_IP_HAS_COREPLL_PHI8_CLK) 407 COREPLL_PHI8_CLK = CLOCK_IP_HAS_COREPLL_PHI8_CLK, 408 #endif 409 #if defined(CLOCK_IP_HAS_COREPLL_PHI9_CLK) 410 COREPLL_PHI9_CLK = CLOCK_IP_HAS_COREPLL_PHI9_CLK, 411 #endif 412 #if defined(CLOCK_IP_HAS_COREPLL_DFS0_CLK) 413 COREPLL_DFS0_CLK = CLOCK_IP_HAS_COREPLL_DFS0_CLK, 414 #endif 415 #if defined(CLOCK_IP_HAS_COREPLL_DFS1_CLK) 416 COREPLL_DFS1_CLK = CLOCK_IP_HAS_COREPLL_DFS1_CLK, 417 #endif 418 #if defined(CLOCK_IP_HAS_COREPLL_DFS2_CLK) 419 COREPLL_DFS2_CLK = CLOCK_IP_HAS_COREPLL_DFS2_CLK, 420 #endif 421 #if defined(CLOCK_IP_HAS_COREPLL_DFS3_CLK) 422 COREPLL_DFS3_CLK = CLOCK_IP_HAS_COREPLL_DFS3_CLK, 423 #endif 424 #if defined(CLOCK_IP_HAS_COREPLL_DFS4_CLK) 425 COREPLL_DFS4_CLK = CLOCK_IP_HAS_COREPLL_DFS4_CLK, 426 #endif 427 #if defined(CLOCK_IP_HAS_COREPLL_DFS5_CLK) 428 COREPLL_DFS5_CLK = CLOCK_IP_HAS_COREPLL_DFS5_CLK, 429 #endif 430 #if defined(CLOCK_IP_HAS_COREPLL_DFS6_CLK) 431 COREPLL_DFS6_CLK = CLOCK_IP_HAS_COREPLL_DFS6_CLK, 432 #endif 433 #if defined(CLOCK_IP_HAS_DDRPLL_PHI0_CLK) 434 DDRPLL_PHI0_CLK = CLOCK_IP_HAS_DDRPLL_PHI0_CLK, 435 #endif 436 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI0_CLK) 437 PERIPHPLL_PHI0_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI0_CLK, 438 #endif 439 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI1_CLK) 440 PERIPHPLL_PHI1_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI1_CLK, 441 #endif 442 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI2_CLK) 443 PERIPHPLL_PHI2_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI2_CLK, 444 #endif 445 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI3_CLK) 446 PERIPHPLL_PHI3_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI3_CLK, 447 #endif 448 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI4_CLK) 449 PERIPHPLL_PHI4_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI4_CLK, 450 #endif 451 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI5_CLK) 452 PERIPHPLL_PHI5_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI5_CLK, 453 #endif 454 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI6_CLK) 455 PERIPHPLL_PHI6_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI6_CLK, 456 #endif 457 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI7_CLK) 458 PERIPHPLL_PHI7_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI7_CLK, 459 #endif 460 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI8_CLK) 461 PERIPHPLL_PHI8_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI8_CLK, 462 #endif 463 #if defined(CLOCK_IP_HAS_PERIPHPLL_PHI9_CLK) 464 PERIPHPLL_PHI9_CLK = CLOCK_IP_HAS_PERIPHPLL_PHI9_CLK, 465 #endif 466 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS0_CLK) 467 PERIPHPLL_DFS0_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS0_CLK, 468 #endif 469 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS1_CLK) 470 PERIPHPLL_DFS1_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS1_CLK, 471 #endif 472 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS2_CLK) 473 PERIPHPLL_DFS2_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS2_CLK, 474 #endif 475 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS3_CLK) 476 PERIPHPLL_DFS3_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS3_CLK, 477 #endif 478 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS4_CLK) 479 PERIPHPLL_DFS4_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS4_CLK, 480 #endif 481 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS5_CLK) 482 PERIPHPLL_DFS5_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS5_CLK, 483 #endif 484 #if defined(CLOCK_IP_HAS_PERIPHPLL_DFS6_CLK) 485 PERIPHPLL_DFS6_CLK = CLOCK_IP_HAS_PERIPHPLL_DFS6_CLK, 486 #endif 487 #if defined(CLOCK_IP_HAS_PLL_PHI0_CLK) 488 PLL_PHI0_CLK = CLOCK_IP_HAS_PLL_PHI0_CLK, 489 #endif 490 #if defined(CLOCK_IP_HAS_PLL_PHI1_CLK) 491 PLL_PHI1_CLK = CLOCK_IP_HAS_PLL_PHI1_CLK, 492 #endif 493 #if defined(CLOCK_IP_HAS_AURORAPLL_PHI0_CLK) 494 AURORAPLL_PHI0_CLK = CLOCK_IP_HAS_AURORAPLL_PHI0_CLK, 495 #endif 496 #if defined(CLOCK_IP_HAS_AURORAPLL_PHI1_CLK) 497 AURORAPLL_PHI1_CLK = CLOCK_IP_HAS_AURORAPLL_PHI1_CLK, 498 #endif 499 #if defined(CLOCK_IP_HAS_AURORAPLL_PHI2_CLK) 500 AURORAPLL_PHI2_CLK = CLOCK_IP_HAS_AURORAPLL_PHI2_CLK, 501 #endif 502 #if defined(CLOCK_IP_HAS_LFAST0_PLL_PH0_CLK) 503 LFAST0_PLL_PH0_CLK = CLOCK_IP_HAS_LFAST0_PLL_PH0_CLK, 504 #endif 505 #if defined(CLOCK_IP_HAS_LFAST1_PLL_PH0_CLK) 506 LFAST1_PLL_PH0_CLK = CLOCK_IP_HAS_LFAST1_PLL_PH0_CLK, 507 #endif 508 #if defined(CLOCK_IP_HAS_PLL_POSTDIV_CLK) 509 PLL_POSTDIV_CLK = CLOCK_IP_HAS_PLL_POSTDIV_CLK, 510 #endif 511 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK) 512 PLLAUX_POSTDIV_CLK = CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK, 513 #endif 514 #if defined(CLOCK_IP_HAS_SIRCDIV1_CLK) 515 SIRCDIV1_CLK = CLOCK_IP_HAS_SIRCDIV1_CLK, 516 #endif 517 #if defined(CLOCK_IP_HAS_SIRCDIV2_CLK) 518 SIRCDIV2_CLK = CLOCK_IP_HAS_SIRCDIV2_CLK, 519 #endif 520 #if defined(CLOCK_IP_HAS_FDIV0_CLK) 521 FDIV0_CLK = CLOCK_IP_HAS_FDIV0_CLK, 522 #endif 523 #if defined(CLOCK_IP_HAS_FIRCDIV1_CLK) 524 FIRCDIV1_CLK = CLOCK_IP_HAS_FIRCDIV1_CLK, 525 #endif 526 #if defined(CLOCK_IP_HAS_FIRCDIV2_CLK) 527 FIRCDIV2_CLK = CLOCK_IP_HAS_FIRCDIV2_CLK, 528 #endif 529 #if defined(CLOCK_IP_HAS_SOSCDIV1_CLK) 530 SOSCDIV1_CLK = CLOCK_IP_HAS_SOSCDIV1_CLK, 531 #endif 532 #if defined(CLOCK_IP_HAS_SOSCDIV2_CLK) 533 SOSCDIV2_CLK = CLOCK_IP_HAS_SOSCDIV2_CLK, 534 #endif 535 #if defined(CLOCK_IP_HAS_SPLLDIV1_CLK) 536 SPLLDIV1_CLK = CLOCK_IP_HAS_SPLLDIV1_CLK, 537 #endif 538 #if defined(CLOCK_IP_HAS_SPLLDIV2_CLK) 539 SPLLDIV2_CLK = CLOCK_IP_HAS_SPLLDIV2_CLK, 540 #endif 541 #if defined(CLOCK_IP_HAS_LPO_32K_CLK) 542 LPO_32K_CLK = CLOCK_IP_HAS_LPO_32K_CLK, 543 #endif 544 #if defined(CLOCK_IP_HAS_LPO_1K_CLK) 545 LPO_1K_CLK = CLOCK_IP_HAS_LPO_1K_CLK, 546 #endif 547 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_0_TX) 548 SERDES_0_LANE_0_TX = CLOCK_IP_HAS_SERDES_0_LANE_0_TX, 549 #endif 550 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_0_CDR) 551 SERDES_0_LANE_0_CDR = CLOCK_IP_HAS_SERDES_0_LANE_0_CDR, 552 #endif 553 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_1_TX) 554 SERDES_0_LANE_1_TX = CLOCK_IP_HAS_SERDES_0_LANE_1_TX, 555 #endif 556 #if defined(CLOCK_IP_HAS_SERDES_0_LANE_1_CDR) 557 SERDES_0_LANE_1_CDR = CLOCK_IP_HAS_SERDES_0_LANE_1_CDR, 558 #endif 559 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_0_TX) 560 SERDES_1_LANE_0_TX = CLOCK_IP_HAS_SERDES_1_LANE_0_TX, 561 #endif 562 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_0_CDR) 563 SERDES_1_LANE_0_CDR = CLOCK_IP_HAS_SERDES_1_LANE_0_CDR, 564 #endif 565 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_1_TX) 566 SERDES_1_LANE_1_TX = CLOCK_IP_HAS_SERDES_1_LANE_1_TX, 567 #endif 568 #if defined(CLOCK_IP_HAS_SERDES_1_LANE_1_CDR) 569 SERDES_1_LANE_1_CDR = CLOCK_IP_HAS_SERDES_1_LANE_1_CDR, 570 #endif 571 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_0_TX) 572 SERDES_0_XPCS_0_TX = CLOCK_IP_HAS_SERDES_0_XPCS_0_TX, 573 #endif 574 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_0_CDR) 575 SERDES_0_XPCS_0_CDR = CLOCK_IP_HAS_SERDES_0_XPCS_0_CDR, 576 #endif 577 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_1_TX) 578 SERDES_0_XPCS_1_TX = CLOCK_IP_HAS_SERDES_0_XPCS_1_TX, 579 #endif 580 #if defined(CLOCK_IP_HAS_SERDES_0_XPCS_1_CDR) 581 SERDES_0_XPCS_1_CDR = CLOCK_IP_HAS_SERDES_0_XPCS_1_CDR, 582 #endif 583 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_0_TX) 584 SERDES_1_XPCS_0_TX = CLOCK_IP_HAS_SERDES_1_XPCS_0_TX, 585 #endif 586 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_0_CDR) 587 SERDES_1_XPCS_0_CDR = CLOCK_IP_HAS_SERDES_1_XPCS_0_CDR, 588 #endif 589 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_1_TX) 590 SERDES_1_XPCS_1_TX = CLOCK_IP_HAS_SERDES_1_XPCS_1_TX, 591 #endif 592 #if defined(CLOCK_IP_HAS_SERDES_1_XPCS_1_CDR) 593 SERDES_1_XPCS_1_CDR = CLOCK_IP_HAS_SERDES_1_XPCS_1_CDR, 594 #endif 595 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK) 596 EMAC_MII_RX_CLK = CLOCK_IP_HAS_EMAC_MII_RX_CLK, 597 #endif 598 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK) 599 EMAC_MII_RMII_TX_CLK = CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK, 600 #endif 601 #if defined(CLOCK_IP_HAS_ETH_RGMII_REF_CLK) 602 ETH_RGMII_REF_CLK = CLOCK_IP_HAS_ETH_RGMII_REF_CLK, 603 #endif 604 #if defined(CLOCK_IP_HAS_ETH_EXT_TS_CLK) 605 ETH_EXT_TS_CLK = CLOCK_IP_HAS_ETH_EXT_TS_CLK, 606 #endif 607 #if defined(CLOCK_IP_HAS_ETH0_EXT_RX_CLK) 608 ETH0_EXT_RX_CLK = CLOCK_IP_HAS_ETH0_EXT_RX_CLK, 609 #endif 610 #if defined(CLOCK_IP_HAS_ETH0_EXT_TX_CLK) 611 ETH0_EXT_TX_CLK = CLOCK_IP_HAS_ETH0_EXT_TX_CLK, 612 #endif 613 #if defined(CLOCK_IP_HAS_ETH1_EXT_RX_CLK) 614 ETH1_EXT_RX_CLK = CLOCK_IP_HAS_ETH1_EXT_RX_CLK, 615 #endif 616 #if defined(CLOCK_IP_HAS_ETH1_EXT_TX_CLK) 617 ETH1_EXT_TX_CLK = CLOCK_IP_HAS_ETH1_EXT_TX_CLK, 618 #endif 619 #if defined(CLOCK_IP_HAS_LFAST0_EXT_REF_CLK) 620 LFAST0_EXT_REF_CLK = CLOCK_IP_HAS_LFAST0_EXT_REF_CLK, 621 #endif 622 #if defined(CLOCK_IP_HAS_LFAST1_EXT_REF_CLK) 623 LFAST1_EXT_REF_CLK = CLOCK_IP_HAS_LFAST1_EXT_REF_CLK, 624 #endif 625 #if defined(CLOCK_IP_HAS_FTM_0_EXT_REF_CLK) 626 FTM_0_EXT_REF_CLK = CLOCK_IP_HAS_FTM_0_EXT_REF_CLK, 627 #endif 628 #if defined(CLOCK_IP_HAS_FTM_1_EXT_REF_CLK) 629 FTM_1_EXT_REF_CLK = CLOCK_IP_HAS_FTM_1_EXT_REF_CLK, 630 #endif 631 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_REF_CLK) 632 GMAC_0_EXT_REF_CLK = CLOCK_IP_HAS_GMAC_0_EXT_REF_CLK, 633 #endif 634 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_RX_CLK) 635 GMAC_0_EXT_RX_CLK = CLOCK_IP_HAS_GMAC_0_EXT_RX_CLK, 636 #endif 637 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_TX_CLK) 638 GMAC_0_EXT_TX_CLK = CLOCK_IP_HAS_GMAC_0_EXT_TX_CLK, 639 #endif 640 #if defined(CLOCK_IP_HAS_GMAC_0_SGMII_REF_CLK) 641 GMAC_0_SGMII_REF_CLK = CLOCK_IP_HAS_GMAC_0_SGMII_REF_CLK, 642 #endif 643 #if defined(CLOCK_IP_HAS_GMAC_0_SGMII_RX_CLK) 644 GMAC_0_SGMII_RX_CLK = CLOCK_IP_HAS_GMAC_0_SGMII_RX_CLK, 645 #endif 646 #if defined(CLOCK_IP_HAS_GMAC_0_SGMII_TX_CLK) 647 GMAC_0_SGMII_TX_CLK = CLOCK_IP_HAS_GMAC_0_SGMII_TX_CLK, 648 #endif 649 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_REF_CLK) 650 GMAC_1_EXT_REF_CLK = CLOCK_IP_HAS_GMAC_1_EXT_REF_CLK, 651 #endif 652 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_RX_CLK) 653 GMAC_1_EXT_RX_CLK = CLOCK_IP_HAS_GMAC_1_EXT_RX_CLK, 654 #endif 655 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_TX_CLK) 656 GMAC_1_EXT_TX_CLK = CLOCK_IP_HAS_GMAC_1_EXT_TX_CLK, 657 #endif 658 #if defined(CLOCK_IP_HAS_GMAC_EXT_TS_CLK) 659 GMAC_EXT_TS_CLK = CLOCK_IP_HAS_GMAC_EXT_TS_CLK, 660 #endif 661 #if defined(CLOCK_IP_HAS_GMAC_0_EXT_TS_CLK) 662 GMAC_0_EXT_TS_CLK = CLOCK_IP_HAS_GMAC_0_EXT_TS_CLK, 663 #endif 664 #if defined(CLOCK_IP_HAS_GMAC_1_EXT_TS_CLK) 665 GMAC_1_EXT_TS_CLK = CLOCK_IP_HAS_GMAC_1_EXT_TS_CLK, 666 #endif 667 #if defined(CLOCK_IP_HAS_GMAC_1_INT_REF_CLK) 668 GMAC_1_INT_REF_CLK = CLOCK_IP_HAS_GMAC_1_INT_REF_CLK, 669 #endif 670 #if defined(CLOCK_IP_HAS_PFE_MAC_0_EXT_REF_CLK) 671 PFE_MAC_0_EXT_REF_CLK = CLOCK_IP_HAS_PFE_MAC_0_EXT_REF_CLK, 672 #endif 673 #if defined(CLOCK_IP_HAS_PFE_MAC_0_EXT_RX_CLK) 674 PFE_MAC_0_EXT_RX_CLK = CLOCK_IP_HAS_PFE_MAC_0_EXT_RX_CLK, 675 #endif 676 #if defined(CLOCK_IP_HAS_PFE_MAC_0_EXT_TX_CLK) 677 PFE_MAC_0_EXT_TX_CLK = CLOCK_IP_HAS_PFE_MAC_0_EXT_TX_CLK, 678 #endif 679 #if defined(CLOCK_IP_HAS_PFE_MAC_1_EXT_REF_CLK) 680 PFE_MAC_1_EXT_REF_CLK = CLOCK_IP_HAS_PFE_MAC_1_EXT_REF_CLK, 681 #endif 682 #if defined(CLOCK_IP_HAS_PFE_MAC_1_EXT_RX_CLK) 683 PFE_MAC_1_EXT_RX_CLK = CLOCK_IP_HAS_PFE_MAC_1_EXT_RX_CLK, 684 #endif 685 #if defined(CLOCK_IP_HAS_PFE_MAC_1_EXT_TX_CLK) 686 PFE_MAC_1_EXT_TX_CLK = CLOCK_IP_HAS_PFE_MAC_1_EXT_TX_CLK, 687 #endif 688 #if defined(CLOCK_IP_HAS_PFE_MAC_2_EXT_REF_CLK) 689 PFE_MAC_2_EXT_REF_CLK = CLOCK_IP_HAS_PFE_MAC_2_EXT_REF_CLK, 690 #endif 691 #if defined(CLOCK_IP_HAS_PFE_MAC_2_EXT_RX_CLK) 692 PFE_MAC_2_EXT_RX_CLK = CLOCK_IP_HAS_PFE_MAC_2_EXT_RX_CLK, 693 #endif 694 #if defined(CLOCK_IP_HAS_PFE_MAC_2_EXT_TX_CLK) 695 PFE_MAC_2_EXT_TX_CLK = CLOCK_IP_HAS_PFE_MAC_2_EXT_TX_CLK, 696 #endif 697 #if defined(CLOCK_IP_HAS_TCLK0_REF_CLK) 698 TCLK0_REF_CLK = CLOCK_IP_HAS_TCLK0_REF_CLK, 699 #endif 700 #if defined(CLOCK_IP_HAS_TCLK1_REF_CLK) 701 TCLK1_REF_CLK = CLOCK_IP_HAS_TCLK1_REF_CLK, 702 #endif 703 #if defined(CLOCK_IP_HAS_TCLK2_REF_CLK) 704 TCLK2_REF_CLK = CLOCK_IP_HAS_TCLK2_REF_CLK, 705 #endif 706 #if defined(CLOCK_IP_HAS_TEST_CLK) 707 TEST_CLK = CLOCK_IP_HAS_TEST_CLK, 708 #endif 709 #if defined(CLOCK_IP_HAS_TPR_CLK) 710 TPR_CLK = CLOCK_IP_HAS_TPR_CLK, 711 #endif 712 #if defined(CLOCK_IP_HAS_RTC_CLKIN) 713 RTC_CLKIN = CLOCK_IP_HAS_RTC_CLKIN, 714 #endif 715 #if defined(CLOCK_IP_HAS_A53_CORE_CLK) 716 A53_CORE_CLK = CLOCK_IP_HAS_A53_CORE_CLK, 717 #endif 718 #if defined(CLOCK_IP_HAS_A53_CORE_DIV2_CLK) 719 A53_CORE_DIV2_CLK = CLOCK_IP_HAS_A53_CORE_DIV2_CLK, 720 #endif 721 #if defined(CLOCK_IP_HAS_A53_CORE_DIV4_CLK) 722 A53_CORE_DIV4_CLK = CLOCK_IP_HAS_A53_CORE_DIV4_CLK, 723 #endif 724 #if defined(CLOCK_IP_HAS_A53_CORE_DIV10_CLK) 725 A53_CORE_DIV10_CLK = CLOCK_IP_HAS_A53_CORE_DIV10_CLK, 726 #endif 727 #if defined(CLOCK_IP_HAS_AIPS_PLAT_CLK) 728 AIPS_PLAT_CLK = CLOCK_IP_HAS_AIPS_PLAT_CLK, 729 #endif 730 #if defined(CLOCK_IP_HAS_AIPS_SLOW_CLK) 731 AIPS_SLOW_CLK = CLOCK_IP_HAS_AIPS_SLOW_CLK, 732 #endif 733 #if defined(CLOCK_IP_HAS_ACCEL3_CLK) 734 ACCEL3_CLK = CLOCK_IP_HAS_ACCEL3_CLK, 735 #endif 736 #if defined(CLOCK_IP_HAS_ACCEL3_DIV3_CLK) 737 ACCEL3_DIV3_CLK = CLOCK_IP_HAS_ACCEL3_DIV3_CLK, 738 #endif 739 #if defined(CLOCK_IP_HAS_ACCEL4_CLK) 740 ACCEL4_CLK = CLOCK_IP_HAS_ACCEL4_CLK, 741 #endif 742 #if defined(CLOCK_IP_HAS_CLKOUT_RUN_CLK) 743 CLKOUT_RUN_CLK = CLOCK_IP_HAS_CLKOUT_RUN_CLK, 744 #endif 745 #if defined(CLOCK_IP_HAS_DCM_CLK) 746 DCM_CLK = CLOCK_IP_HAS_DCM_CLK, 747 #endif 748 #if defined(CLOCK_IP_HAS_DDR_CLK) 749 DDR_CLK = CLOCK_IP_HAS_DDR_CLK, 750 #endif 751 #if defined(CLOCK_IP_HAS_DDR0_CLK) 752 DDR0_CLK = CLOCK_IP_HAS_DDR0_CLK, 753 #endif 754 #if defined(CLOCK_IP_HAS_DMACRC0_CLK) 755 DMACRC0_CLK = CLOCK_IP_HAS_DMACRC0_CLK, 756 #endif 757 #if defined(CLOCK_IP_HAS_DMACRC1_CLK) 758 DMACRC1_CLK = CLOCK_IP_HAS_DMACRC1_CLK, 759 #endif 760 #if defined(CLOCK_IP_HAS_DMACRC4_CLK) 761 DMACRC4_CLK = CLOCK_IP_HAS_DMACRC4_CLK, 762 #endif 763 #if defined(CLOCK_IP_HAS_DMACRC5_CLK) 764 DMACRC5_CLK = CLOCK_IP_HAS_DMACRC5_CLK, 765 #endif 766 #if defined(CLOCK_IP_HAS_GMAC_REF_DIV_CLK) 767 GMAC_REF_DIV_CLK = CLOCK_IP_HAS_GMAC_REF_DIV_CLK, 768 #endif 769 #if defined(CLOCK_IP_HAS_GMAC0_REF_DIV_CLK) 770 GMAC0_REF_DIV_CLK = CLOCK_IP_HAS_GMAC0_REF_DIV_CLK, 771 #endif 772 #if defined(CLOCK_IP_HAS_GMAC0_REF_CLK) 773 GMAC0_REF_CLK = CLOCK_IP_HAS_GMAC0_REF_CLK, 774 #endif 775 #if defined(CLOCK_IP_HAS_GMAC1_REF_DIV_CLK) 776 GMAC1_REF_DIV_CLK = CLOCK_IP_HAS_GMAC1_REF_DIV_CLK, 777 #endif 778 #if defined(CLOCK_IP_HAS_GMAC1_REF_CLK) 779 GMAC1_REF_CLK = CLOCK_IP_HAS_GMAC1_REF_CLK, 780 #endif 781 #if defined(CLOCK_IP_HAS_GMAC1_INT_CLK) 782 GMAC1_INT_CLK = CLOCK_IP_HAS_GMAC1_INT_CLK, 783 #endif 784 #if defined(CLOCK_IP_HAS_AURORA_TRACE_TEST_CLK) 785 AURORA_TRACE_TEST_CLK = CLOCK_IP_HAS_AURORA_TRACE_TEST_CLK, 786 #endif 787 #if defined(CLOCK_IP_HAS_HSE_CLK) 788 HSE_CLK = CLOCK_IP_HAS_HSE_CLK, 789 #endif 790 #if defined(CLOCK_IP_HAS_LBIST_CLK) 791 LBIST_CLK = CLOCK_IP_HAS_LBIST_CLK, 792 #endif 793 #if defined(CLOCK_IP_HAS_PFE_PE_CLK) 794 PFE_PE_CLK = CLOCK_IP_HAS_PFE_PE_CLK, 795 #endif 796 #if defined(CLOCK_IP_HAS_PFE_SYS_CLK) 797 PFE_SYS_CLK = CLOCK_IP_HAS_PFE_SYS_CLK, 798 #endif 799 #if defined(CLOCK_IP_HAS_PER_CLK) 800 PER_CLK = CLOCK_IP_HAS_PER_CLK, 801 #endif 802 #if defined(CLOCK_IP_HAS_PFEMAC0_REF_DIV_CLK) 803 PFEMAC0_REF_DIV_CLK = CLOCK_IP_HAS_PFEMAC0_REF_DIV_CLK, 804 #endif 805 #if defined(CLOCK_IP_HAS_PFEMAC1_REF_DIV_CLK) 806 PFEMAC1_REF_DIV_CLK = CLOCK_IP_HAS_PFEMAC1_REF_DIV_CLK, 807 #endif 808 #if defined(CLOCK_IP_HAS_PFEMAC2_REF_DIV_CLK) 809 PFEMAC2_REF_DIV_CLK = CLOCK_IP_HAS_PFEMAC2_REF_DIV_CLK, 810 #endif 811 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 812 QSPI_MEM_CLK = CLOCK_IP_HAS_QSPI_MEM_CLK, 813 #endif 814 #if defined(CLOCK_IP_HAS_SCS_CLK) 815 SCS_CLK = CLOCK_IP_HAS_SCS_CLK, 816 #endif 817 #if defined(CLOCK_IP_HAS_XBAR_2X_CLK) 818 XBAR_2X_CLK = CLOCK_IP_HAS_XBAR_2X_CLK, 819 #endif 820 #if defined(CLOCK_IP_HAS_XBAR_CLK) 821 XBAR_CLK = CLOCK_IP_HAS_XBAR_CLK, 822 #endif 823 #if defined(CLOCK_IP_HAS_XBAR_DIV2_CLK) 824 XBAR_DIV2_CLK = CLOCK_IP_HAS_XBAR_DIV2_CLK, 825 #endif 826 #if defined(CLOCK_IP_HAS_XBAR_DIV3_CLK) 827 XBAR_DIV3_CLK = CLOCK_IP_HAS_XBAR_DIV3_CLK, 828 #endif 829 #if defined(CLOCK_IP_HAS_XBAR_DIV4_CLK) 830 XBAR_DIV4_CLK = CLOCK_IP_HAS_XBAR_DIV4_CLK, 831 #endif 832 #if defined(CLOCK_IP_HAS_XBAR_DIV6_CLK) 833 XBAR_DIV6_CLK = CLOCK_IP_HAS_XBAR_DIV6_CLK, 834 #endif 835 #if defined(CLOCK_IP_HAS_XMII_CLK_125MHZ) 836 XMII_CLK_125MHZ = CLOCK_IP_HAS_XMII_CLK_125MHZ, 837 #endif 838 #if defined(CLOCK_IP_HAS_XMII_CLK_2M5HZ) 839 XMII_CLK_2M5HZ = CLOCK_IP_HAS_XMII_CLK_2M5HZ, 840 #endif 841 #if defined(CLOCK_IP_HAS_XMII_CLK_25MHZ) 842 XMII_CLK_25MHZ = CLOCK_IP_HAS_XMII_CLK_25MHZ, 843 #endif 844 #if defined(CLOCK_IP_HAS_XMII_CLK_50MHZ) 845 XMII_CLK_50MHZ = CLOCK_IP_HAS_XMII_CLK_50MHZ, 846 #endif 847 #if defined(CLOCK_IP_HAS_XOSC_CLK) 848 XOSC_CLK = CLOCK_IP_HAS_XOSC_CLK, 849 #endif 850 #if defined(CLOCK_IP_HAS_SERDES_REF_CLK) 851 SERDES_REF_CLK = CLOCK_IP_HAS_SERDES_REF_CLK, 852 #endif 853 #if defined(CLOCK_IP_HAS_SERDES0_REF_CLK) 854 SERDES0_REF_CLK = CLOCK_IP_HAS_SERDES0_REF_CLK, 855 #endif 856 #if defined(CLOCK_IP_HAS_SERDES1_REF_CLK) 857 SERDES1_REF_CLK = CLOCK_IP_HAS_SERDES1_REF_CLK, 858 #endif 859 #if defined(CLOCK_IP_HAS_SCS_RUN_CLK) 860 SCS_RUN_CLK = CLOCK_IP_HAS_SCS_RUN_CLK, 861 #endif 862 #if defined(CLOCK_IP_HAS_SCS_VLPR_CLK) 863 SCS_VLPR_CLK = CLOCK_IP_HAS_SCS_VLPR_CLK, 864 #endif 865 #if defined(CLOCK_IP_HAS_SCS_HSRUN_CLK) 866 SCS_HSRUN_CLK = CLOCK_IP_HAS_SCS_HSRUN_CLK, 867 #endif 868 #if defined(CLOCK_IP_HAS_CORE_CLK) 869 CORE_CLK = CLOCK_IP_HAS_CORE_CLK, 870 #endif 871 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 872 CM7_CORE_CLK = CLOCK_IP_HAS_CM7_CORE_CLK, 873 #endif 874 #if defined(CLOCK_IP_HAS_CORE_RUN_CLK) 875 CORE_RUN_CLK = CLOCK_IP_HAS_CORE_RUN_CLK, 876 #endif 877 #if defined(CLOCK_IP_HAS_CORE_VLPR_CLK) 878 CORE_VLPR_CLK = CLOCK_IP_HAS_CORE_VLPR_CLK, 879 #endif 880 #if defined(CLOCK_IP_HAS_CORE_HSRUN_CLK) 881 CORE_HSRUN_CLK = CLOCK_IP_HAS_CORE_HSRUN_CLK, 882 #endif 883 #if defined(CLOCK_IP_HAS_BUS_CLK) 884 BUS_CLK = CLOCK_IP_HAS_BUS_CLK, 885 #endif 886 #if defined(CLOCK_IP_HAS_BUS_RUN_CLK) 887 BUS_RUN_CLK = CLOCK_IP_HAS_BUS_RUN_CLK, 888 #endif 889 #if defined(CLOCK_IP_HAS_BUS_VLPR_CLK) 890 BUS_VLPR_CLK = CLOCK_IP_HAS_BUS_VLPR_CLK, 891 #endif 892 #if defined(CLOCK_IP_HAS_BUS_HSRUN_CLK) 893 BUS_HSRUN_CLK = CLOCK_IP_HAS_BUS_HSRUN_CLK, 894 #endif 895 #if defined(CLOCK_IP_HAS_SLOW_CLK) 896 SLOW_CLK = CLOCK_IP_HAS_SLOW_CLK, 897 #endif 898 #if defined(CLOCK_IP_HAS_SLOW_RUN_CLK) 899 SLOW_RUN_CLK = CLOCK_IP_HAS_SLOW_RUN_CLK, 900 #endif 901 #if defined(CLOCK_IP_HAS_SLOW_VLPR_CLK) 902 SLOW_VLPR_CLK = CLOCK_IP_HAS_SLOW_VLPR_CLK, 903 #endif 904 #if defined(CLOCK_IP_HAS_SLOW_HSRUN_CLK) 905 SLOW_HSRUN_CLK = CLOCK_IP_HAS_SLOW_HSRUN_CLK, 906 #endif 907 #if defined(CLOCK_IP_HAS_LPO_CLK) 908 LPO_CLK = CLOCK_IP_HAS_LPO_CLK, 909 #endif 910 #if defined(CLOCK_IP_HAS_SCG_CLKOUT_CLK) 911 SCG_CLKOUT_CLK = CLOCK_IP_HAS_SCG_CLKOUT_CLK, 912 #endif 913 #if defined(CLOCK_IP_HAS_FTM0_EXT_CLK) 914 FTM0_EXT_CLK = CLOCK_IP_HAS_FTM0_EXT_CLK, 915 #endif 916 #if defined(CLOCK_IP_HAS_FTM1_EXT_CLK) 917 FTM1_EXT_CLK = CLOCK_IP_HAS_FTM1_EXT_CLK, 918 #endif 919 #if defined(CLOCK_IP_HAS_FTM2_EXT_CLK) 920 FTM2_EXT_CLK = CLOCK_IP_HAS_FTM2_EXT_CLK, 921 #endif 922 #if defined(CLOCK_IP_HAS_FTM3_EXT_CLK) 923 FTM3_EXT_CLK = CLOCK_IP_HAS_FTM3_EXT_CLK, 924 #endif 925 #if defined(CLOCK_IP_HAS_FTM4_EXT_CLK) 926 FTM4_EXT_CLK = CLOCK_IP_HAS_FTM4_EXT_CLK, 927 #endif 928 #if defined(CLOCK_IP_HAS_FTM5_EXT_CLK) 929 FTM5_EXT_CLK = CLOCK_IP_HAS_FTM5_EXT_CLK, 930 #endif 931 #if defined(CLOCK_IP_HAS_FTM6_EXT_CLK) 932 FTM6_EXT_CLK = CLOCK_IP_HAS_FTM6_EXT_CLK, 933 #endif 934 #if defined(CLOCK_IP_HAS_FTM7_EXT_CLK) 935 FTM7_EXT_CLK = CLOCK_IP_HAS_FTM7_EXT_CLK, 936 #endif 937 #if defined(CLOCK_IP_HAS_Px_CLKOUT_SRC_CLK) 938 Px_CLKOUT_SRC_CLK = CLOCK_IP_HAS_Px_CLKOUT_SRC_CLK, 939 #endif 940 #if defined(CLOCK_IP_HAS_Px_PSI5_S_UTIL_CLK) 941 Px_PSI5_S_UTIL_CLK = CLOCK_IP_HAS_Px_PSI5_S_UTIL_CLK, 942 #endif 943 #if defined(CLOCK_IP_HAS_SHIFT_LBIST_CLK) 944 SHIFT_LBIST_CLK = CLOCK_IP_HAS_SHIFT_LBIST_CLK, 945 #endif 946 #if defined(CLOCK_IP_HAS_P0_SYS_CLK) 947 P0_SYS_CLK = CLOCK_IP_HAS_P0_SYS_CLK, 948 #endif 949 #if defined(CLOCK_IP_HAS_P1_SYS_CLK) 950 P1_SYS_CLK = CLOCK_IP_HAS_P1_SYS_CLK, 951 #endif 952 #if defined(CLOCK_IP_HAS_P1_SYS_DIV2_CLK) 953 P1_SYS_DIV2_CLK = CLOCK_IP_HAS_P1_SYS_DIV2_CLK, 954 #endif 955 #if defined(CLOCK_IP_HAS_P1_SYS_DIV4_CLK) 956 P1_SYS_DIV4_CLK = CLOCK_IP_HAS_P1_SYS_DIV4_CLK, 957 #endif 958 #if defined(CLOCK_IP_HAS_P2_SYS_CLK) 959 P2_SYS_CLK = CLOCK_IP_HAS_P2_SYS_CLK, 960 #endif 961 #if defined(CLOCK_IP_HAS_CORE_M33_CLK) 962 CORE_M33_CLK = CLOCK_IP_HAS_CORE_M33_CLK, 963 #endif 964 #if defined(CLOCK_IP_HAS_P2_SYS_DIV2_CLK) 965 P2_SYS_DIV2_CLK = CLOCK_IP_HAS_P2_SYS_DIV2_CLK, 966 #endif 967 #if defined(CLOCK_IP_HAS_P2_SYS_DIV4_CLK) 968 P2_SYS_DIV4_CLK = CLOCK_IP_HAS_P2_SYS_DIV4_CLK, 969 #endif 970 #if defined(CLOCK_IP_HAS_P3_SYS_CLK) 971 P3_SYS_CLK = CLOCK_IP_HAS_P3_SYS_CLK, 972 #endif 973 #if defined(CLOCK_IP_HAS_CE_SYS_DIV2_CLK) 974 CE_SYS_DIV2_CLK = CLOCK_IP_HAS_CE_SYS_DIV2_CLK, 975 #endif 976 #if defined(CLOCK_IP_HAS_CE_SYS_DIV4_CLK) 977 CE_SYS_DIV4_CLK = CLOCK_IP_HAS_CE_SYS_DIV4_CLK, 978 #endif 979 #if defined(CLOCK_IP_HAS_P3_SYS_DIV2_NOC_CLK) 980 P3_SYS_DIV2_NOC_CLK = CLOCK_IP_HAS_P3_SYS_DIV2_NOC_CLK, 981 #endif 982 #if defined(CLOCK_IP_HAS_P3_SYS_DIV4_CLK) 983 P3_SYS_DIV4_CLK = CLOCK_IP_HAS_P3_SYS_DIV4_CLK, 984 #endif 985 #if defined(CLOCK_IP_HAS_P4_SYS_CLK) 986 P4_SYS_CLK = CLOCK_IP_HAS_P4_SYS_CLK, 987 #endif 988 #if defined(CLOCK_IP_HAS_P4_SYS_DIV2_CLK) 989 P4_SYS_DIV2_CLK = CLOCK_IP_HAS_P4_SYS_DIV2_CLK, 990 #endif 991 #if defined(CLOCK_IP_HAS_HSE_SYS_DIV2_CLK) 992 HSE_SYS_DIV2_CLK = CLOCK_IP_HAS_HSE_SYS_DIV2_CLK, 993 #endif 994 #if defined(CLOCK_IP_HAS_P5_SYS_CLK) 995 P5_SYS_CLK = CLOCK_IP_HAS_P5_SYS_CLK, 996 #endif 997 #if defined(CLOCK_IP_HAS_P5_SYS_DIV2_CLK) 998 P5_SYS_DIV2_CLK = CLOCK_IP_HAS_P5_SYS_DIV2_CLK, 999 #endif 1000 #if defined(CLOCK_IP_HAS_P5_SYS_DIV4_CLK) 1001 P5_SYS_DIV4_CLK = CLOCK_IP_HAS_P5_SYS_DIV4_CLK, 1002 #endif 1003 #if defined(CLOCK_IP_HAS_P2_MATH_CLK) 1004 P2_MATH_CLK = CLOCK_IP_HAS_P2_MATH_CLK, 1005 #endif 1006 #if defined(CLOCK_IP_HAS_P2_MATH_DIV3_CLK) 1007 P2_MATH_DIV3_CLK = CLOCK_IP_HAS_P2_MATH_DIV3_CLK, 1008 #endif 1009 #if defined(CLOCK_IP_HAS_RTU0_CORE_CLK) 1010 RTU0_CORE_CLK = CLOCK_IP_HAS_RTU0_CORE_CLK, 1011 #endif 1012 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_CLK) 1013 RTU0_CORE_DIV2_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_CLK, 1014 #endif 1015 #if defined(CLOCK_IP_HAS_RTU1_CORE_CLK) 1016 RTU1_CORE_CLK = CLOCK_IP_HAS_RTU1_CORE_CLK, 1017 #endif 1018 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_CLK) 1019 RTU1_CORE_DIV2_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_CLK, 1020 #endif 1021 #if defined(CLOCK_IP_HAS_P0_PSI5_S_UTIL_CLK) 1022 P0_PSI5_S_UTIL_CLK = CLOCK_IP_HAS_P0_PSI5_S_UTIL_CLK, 1023 #endif 1024 #if defined(CLOCK_IP_HAS_P4_PSI5_S_UTIL_CLK) 1025 P4_PSI5_S_UTIL_CLK = CLOCK_IP_HAS_P4_PSI5_S_UTIL_CLK, 1026 #endif 1027 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK) 1028 SYSTEM_DRUN_CLK = CLOCK_IP_HAS_SYSTEM_DRUN_CLK, 1029 #endif 1030 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) 1031 SYSTEM_DIV2_CLK = CLOCK_IP_HAS_SYSTEM_DIV2_CLK, 1032 #endif 1033 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK) 1034 SYSTEM_DIV4_CLK = CLOCK_IP_HAS_SYSTEM_DIV4_CLK, 1035 #endif 1036 #if defined(CLOCK_IP_HAS_SYS_CLK) 1037 SYS_CLK = CLOCK_IP_HAS_SYS_CLK, 1038 #endif 1039 #if defined(CLOCK_IP_HAS_SYS_DIV2_CLK) 1040 SYS_DIV2_CLK = CLOCK_IP_HAS_SYS_DIV2_CLK, 1041 #endif 1042 #if defined(CLOCK_IP_HAS_SYS_DIV4_CLK) 1043 SYS_DIV4_CLK = CLOCK_IP_HAS_SYS_DIV4_CLK, 1044 #endif 1045 #if defined(CLOCK_IP_HAS_SYS_DIV8_CLK) 1046 SYS_DIV8_CLK = CLOCK_IP_HAS_SYS_DIV8_CLK, 1047 #endif 1048 #if defined(CLOCK_IP_HAS_RT_DAPB_CLK) 1049 RT_DAPB_CLK = CLOCK_IP_HAS_RT_DAPB_CLK, 1050 #endif 1051 #if defined(CLOCK_IP_HAS_ACCEL_CLK) 1052 ACCEL_CLK = CLOCK_IP_HAS_ACCEL_CLK, 1053 #endif 1054 #if defined(CLOCK_IP_HAS_ACCEL_DIV3_CLK) 1055 ACCEL_DIV3_CLK = CLOCK_IP_HAS_ACCEL_DIV3_CLK, 1056 #endif 1057 #if defined(CLOCK_IP_HAS_ACCEL_DIV4_CLK) 1058 ACCEL_DIV4_CLK = CLOCK_IP_HAS_ACCEL_DIV4_CLK, 1059 #endif 1060 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_CLK) 1061 ACCEL_XBAR_CLK = CLOCK_IP_HAS_ACCEL_XBAR_CLK, 1062 #endif 1063 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_DIV2_CLK) 1064 ACCEL_XBAR_DIV2_CLK = CLOCK_IP_HAS_ACCEL_XBAR_DIV2_CLK, 1065 #endif 1066 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_DIV4_CLK) 1067 ACCEL_XBAR_DIV4_CLK = CLOCK_IP_HAS_ACCEL_XBAR_DIV4_CLK, 1068 #endif 1069 #if defined(CLOCK_IP_HAS_ACCEL_XBAR_DIV8_CLK) 1070 ACCEL_XBAR_DIV8_CLK = CLOCK_IP_HAS_ACCEL_XBAR_DIV8_CLK, 1071 #endif 1072 #if defined(CLOCK_IP_HAS_AP_DAPB_CLK) 1073 AP_DAPB_CLK = CLOCK_IP_HAS_AP_DAPB_CLK, 1074 #endif 1075 THE_LAST_PRODUCER_CLK = CLOCK_IP_FEATURE_PRODUCERS_NO, /* Number of producers clocks */ 1076 #if defined(CLOCK_IP_HAS_ACCEL4_LAX0_CLK) 1077 ACCEL4_LAX0_CLK = CLOCK_IP_HAS_ACCEL4_LAX0_CLK, 1078 #endif 1079 #if defined(CLOCK_IP_HAS_ACCEL4_LAX1_CLK) 1080 ACCEL4_LAX1_CLK = CLOCK_IP_HAS_ACCEL4_LAX1_CLK, 1081 #endif 1082 #if defined(CLOCK_IP_HAS_ADC0_CLK) 1083 ADC0_CLK = CLOCK_IP_HAS_ADC0_CLK, 1084 #endif 1085 #if defined(CLOCK_IP_HAS_ADC1_CLK) 1086 ADC1_CLK = CLOCK_IP_HAS_ADC1_CLK, 1087 #endif 1088 #if defined(CLOCK_IP_HAS_ADC2_CLK) 1089 ADC2_CLK = CLOCK_IP_HAS_ADC2_CLK, 1090 #endif 1091 #if defined(CLOCK_IP_HAS_ADC3_CLK) 1092 ADC3_CLK = CLOCK_IP_HAS_ADC3_CLK, 1093 #endif 1094 #if defined(CLOCK_IP_HAS_ADC4_CLK) 1095 ADC4_CLK = CLOCK_IP_HAS_ADC4_CLK, 1096 #endif 1097 #if defined(CLOCK_IP_HAS_ADC5_CLK) 1098 ADC5_CLK = CLOCK_IP_HAS_ADC5_CLK, 1099 #endif 1100 #if defined(CLOCK_IP_HAS_ADC6_CLK) 1101 ADC6_CLK = CLOCK_IP_HAS_ADC6_CLK, 1102 #endif 1103 #if defined(CLOCK_IP_HAS_ADCBIST_CLK) 1104 ADCBIST_CLK = CLOCK_IP_HAS_ADCBIST_CLK, 1105 #endif 1106 #if defined(CLOCK_IP_HAS_BCTU0_CLK) 1107 BCTU0_CLK = CLOCK_IP_HAS_BCTU0_CLK, 1108 #endif 1109 #if defined(CLOCK_IP_HAS_BCTU1_CLK) 1110 BCTU1_CLK = CLOCK_IP_HAS_BCTU1_CLK, 1111 #endif 1112 #if defined(CLOCK_IP_HAS_CE_SYS_DIV2_MON_CLK) 1113 CE_SYS_DIV2_MON_CLK = CLOCK_IP_HAS_CE_SYS_DIV2_MON_CLK, 1114 #endif 1115 #if defined(CLOCK_IP_HAS_CE_EDMA_CLK) 1116 CE_EDMA_CLK = CLOCK_IP_HAS_CE_EDMA_CLK, 1117 #endif 1118 #if defined(CLOCK_IP_HAS_CE_PIT0_CLK) 1119 CE_PIT0_CLK = CLOCK_IP_HAS_CE_PIT0_CLK, 1120 #endif 1121 #if defined(CLOCK_IP_HAS_CE_PIT1_CLK) 1122 CE_PIT1_CLK = CLOCK_IP_HAS_CE_PIT1_CLK, 1123 #endif 1124 #if defined(CLOCK_IP_HAS_CE_PIT2_CLK) 1125 CE_PIT2_CLK = CLOCK_IP_HAS_CE_PIT2_CLK, 1126 #endif 1127 #if defined(CLOCK_IP_HAS_CE_PIT3_CLK) 1128 CE_PIT3_CLK = CLOCK_IP_HAS_CE_PIT3_CLK, 1129 #endif 1130 #if defined(CLOCK_IP_HAS_CE_PIT4_CLK) 1131 CE_PIT4_CLK = CLOCK_IP_HAS_CE_PIT4_CLK, 1132 #endif 1133 #if defined(CLOCK_IP_HAS_CE_PIT5_CLK) 1134 CE_PIT5_CLK = CLOCK_IP_HAS_CE_PIT5_CLK, 1135 #endif 1136 #if defined(CLOCK_IP_HAS_CLKOUT_STANDBY_CLK) 1137 CLKOUT_STANDBY_CLK = CLOCK_IP_HAS_CLKOUT_STANDBY_CLK, 1138 #endif 1139 #if defined(CLOCK_IP_HAS_CLKOUT0_CLK) 1140 CLKOUT0_CLK = CLOCK_IP_HAS_CLKOUT0_CLK, 1141 #endif 1142 #if defined(CLOCK_IP_HAS_CLKOUT1_CLK) 1143 CLKOUT1_CLK = CLOCK_IP_HAS_CLKOUT1_CLK, 1144 #endif 1145 #if defined(CLOCK_IP_HAS_CLKOUT2_CLK) 1146 CLKOUT2_CLK = CLOCK_IP_HAS_CLKOUT2_CLK, 1147 #endif 1148 #if defined(CLOCK_IP_HAS_CLKOUT3_CLK) 1149 CLKOUT3_CLK = CLOCK_IP_HAS_CLKOUT3_CLK, 1150 #endif 1151 #if defined(CLOCK_IP_HAS_CLKOUT4_CLK) 1152 CLKOUT4_CLK = CLOCK_IP_HAS_CLKOUT4_CLK, 1153 #endif 1154 #if defined(CLOCK_IP_HAS_CLKOUT5_CLK) 1155 CLKOUT5_CLK = CLOCK_IP_HAS_CLKOUT5_CLK, 1156 #endif 1157 #if defined(CLOCK_IP_HAS_CMP0_CLK) 1158 CMP0_CLK = CLOCK_IP_HAS_CMP0_CLK, 1159 #endif 1160 #if defined(CLOCK_IP_HAS_CMP1_CLK) 1161 CMP1_CLK = CLOCK_IP_HAS_CMP1_CLK, 1162 #endif 1163 #if defined(CLOCK_IP_HAS_CMP2_CLK) 1164 CMP2_CLK = CLOCK_IP_HAS_CMP2_CLK, 1165 #endif 1166 #if defined(CLOCK_IP_HAS_CMU0_CLK) 1167 CMU0_CLK = CLOCK_IP_HAS_CMU0_CLK, 1168 #endif 1169 #if defined(CLOCK_IP_HAS_CMU1_CLK) 1170 CMU1_CLK = CLOCK_IP_HAS_CMU1_CLK, 1171 #endif 1172 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK) 1173 COOLFLUX_D_RAM0_CLK = CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK, 1174 #endif 1175 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK) 1176 COOLFLUX_D_RAM1_CLK = CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK, 1177 #endif 1178 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK) 1179 COOLFLUX_DSP16L_CLK = CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK, 1180 #endif 1181 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK) 1182 COOLFLUX_I_RAM0_CLK = CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK, 1183 #endif 1184 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK) 1185 COOLFLUX_I_RAM1_CLK = CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK, 1186 #endif 1187 #if defined(CLOCK_IP_HAS_CORE_A53_CLUSTER_0_CLK) 1188 CORE_A53_CLUSTER_0_CLK = CLOCK_IP_HAS_CORE_A53_CLUSTER_0_CLK, 1189 #endif 1190 #if defined(CLOCK_IP_HAS_CORE_A53_CLUSTER_1_CLK) 1191 CORE_A53_CLUSTER_1_CLK = CLOCK_IP_HAS_CORE_A53_CLUSTER_1_CLK, 1192 #endif 1193 #if defined(CLOCK_IP_HAS_CORE_M7_0_CLK) 1194 CORE_M7_0_CLK = CLOCK_IP_HAS_CORE_M7_0_CLK, 1195 #endif 1196 #if defined(CLOCK_IP_HAS_CORE_M7_1_CLK) 1197 CORE_M7_1_CLK = CLOCK_IP_HAS_CORE_M7_1_CLK, 1198 #endif 1199 #if defined(CLOCK_IP_HAS_CORE_M7_2_CLK) 1200 CORE_M7_2_CLK = CLOCK_IP_HAS_CORE_M7_2_CLK, 1201 #endif 1202 #if defined(CLOCK_IP_HAS_CORE_M7_3_CLK) 1203 CORE_M7_3_CLK = CLOCK_IP_HAS_CORE_M7_3_CLK, 1204 #endif 1205 #if defined(CLOCK_IP_HAS_CRC0_CLK) 1206 CRC0_CLK = CLOCK_IP_HAS_CRC0_CLK, 1207 #endif 1208 #if defined(CLOCK_IP_HAS_CTU0_CLK) 1209 CTU0_CLK = CLOCK_IP_HAS_CTU0_CLK, 1210 #endif 1211 #if defined(CLOCK_IP_HAS_CTU1_CLK) 1212 CTU1_CLK = CLOCK_IP_HAS_CTU1_CLK, 1213 #endif 1214 #if defined(CLOCK_IP_HAS_DAPB_CLK) 1215 DAPB_CLK = CLOCK_IP_HAS_DAPB_CLK, 1216 #endif 1217 #if defined(CLOCK_IP_HAS_DCM0_CLK) 1218 DCM0_CLK = CLOCK_IP_HAS_DCM0_CLK, 1219 #endif 1220 #if defined(CLOCK_IP_HAS_DMA_CRC0_CLK) 1221 DMA_CRC0_CLK = CLOCK_IP_HAS_DMA_CRC0_CLK, 1222 #endif 1223 #if defined(CLOCK_IP_HAS_DMA_CRC1_CLK) 1224 DMA_CRC1_CLK = CLOCK_IP_HAS_DMA_CRC1_CLK, 1225 #endif 1226 #if defined(CLOCK_IP_HAS_DMA0_CLK) 1227 DMA0_CLK = CLOCK_IP_HAS_DMA0_CLK, 1228 #endif 1229 #if defined(CLOCK_IP_HAS_DMA1_CLK) 1230 DMA1_CLK = CLOCK_IP_HAS_DMA1_CLK, 1231 #endif 1232 #if defined(CLOCK_IP_HAS_DMAMUX0_CLK) 1233 DMAMUX0_CLK = CLOCK_IP_HAS_DMAMUX0_CLK, 1234 #endif 1235 #if defined(CLOCK_IP_HAS_DMAMUX1_CLK) 1236 DMAMUX1_CLK = CLOCK_IP_HAS_DMAMUX1_CLK, 1237 #endif 1238 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK) 1239 DMAMUX2_CLK = CLOCK_IP_HAS_DMAMUX2_CLK, 1240 #endif 1241 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK) 1242 DMAMUX3_CLK = CLOCK_IP_HAS_DMAMUX3_CLK, 1243 #endif 1244 #if defined(CLOCK_IP_HAS_DMAMUX4_CLK) 1245 DMAMUX4_CLK = CLOCK_IP_HAS_DMAMUX4_CLK, 1246 #endif 1247 #if defined(CLOCK_IP_HAS_DMAMUX5_CLK) 1248 DMAMUX5_CLK = CLOCK_IP_HAS_DMAMUX5_CLK, 1249 #endif 1250 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK) 1251 DSPI_MSC_CLK = CLOCK_IP_HAS_DSPI_MSC_CLK, 1252 #endif 1253 #if defined(CLOCK_IP_HAS_EDMA_CLK) 1254 EDMA_CLK = CLOCK_IP_HAS_EDMA_CLK, 1255 #endif 1256 #if defined(CLOCK_IP_HAS_EDMA0_CLK) 1257 EDMA0_CLK = CLOCK_IP_HAS_EDMA0_CLK, 1258 #endif 1259 #if defined(CLOCK_IP_HAS_EDMA0_TCD0_CLK) 1260 EDMA0_TCD0_CLK = CLOCK_IP_HAS_EDMA0_TCD0_CLK, 1261 #endif 1262 #if defined(CLOCK_IP_HAS_EDMA0_TCD1_CLK) 1263 EDMA0_TCD1_CLK = CLOCK_IP_HAS_EDMA0_TCD1_CLK, 1264 #endif 1265 #if defined(CLOCK_IP_HAS_EDMA0_TCD2_CLK) 1266 EDMA0_TCD2_CLK = CLOCK_IP_HAS_EDMA0_TCD2_CLK, 1267 #endif 1268 #if defined(CLOCK_IP_HAS_EDMA0_TCD3_CLK) 1269 EDMA0_TCD3_CLK = CLOCK_IP_HAS_EDMA0_TCD3_CLK, 1270 #endif 1271 #if defined(CLOCK_IP_HAS_EDMA0_TCD4_CLK) 1272 EDMA0_TCD4_CLK = CLOCK_IP_HAS_EDMA0_TCD4_CLK, 1273 #endif 1274 #if defined(CLOCK_IP_HAS_EDMA0_TCD5_CLK) 1275 EDMA0_TCD5_CLK = CLOCK_IP_HAS_EDMA0_TCD5_CLK, 1276 #endif 1277 #if defined(CLOCK_IP_HAS_EDMA0_TCD6_CLK) 1278 EDMA0_TCD6_CLK = CLOCK_IP_HAS_EDMA0_TCD6_CLK, 1279 #endif 1280 #if defined(CLOCK_IP_HAS_EDMA0_TCD7_CLK) 1281 EDMA0_TCD7_CLK = CLOCK_IP_HAS_EDMA0_TCD7_CLK, 1282 #endif 1283 #if defined(CLOCK_IP_HAS_EDMA0_TCD8_CLK) 1284 EDMA0_TCD8_CLK = CLOCK_IP_HAS_EDMA0_TCD8_CLK, 1285 #endif 1286 #if defined(CLOCK_IP_HAS_EDMA0_TCD9_CLK) 1287 EDMA0_TCD9_CLK = CLOCK_IP_HAS_EDMA0_TCD9_CLK, 1288 #endif 1289 #if defined(CLOCK_IP_HAS_EDMA0_TCD10_CLK) 1290 EDMA0_TCD10_CLK = CLOCK_IP_HAS_EDMA0_TCD10_CLK, 1291 #endif 1292 #if defined(CLOCK_IP_HAS_EDMA0_TCD11_CLK) 1293 EDMA0_TCD11_CLK = CLOCK_IP_HAS_EDMA0_TCD11_CLK, 1294 #endif 1295 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK) 1296 EDMA0_TCD12_CLK = CLOCK_IP_HAS_EDMA0_TCD12_CLK, 1297 #endif 1298 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK) 1299 EDMA0_TCD13_CLK = CLOCK_IP_HAS_EDMA0_TCD13_CLK, 1300 #endif 1301 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK) 1302 EDMA0_TCD14_CLK = CLOCK_IP_HAS_EDMA0_TCD14_CLK, 1303 #endif 1304 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK) 1305 EDMA0_TCD15_CLK = CLOCK_IP_HAS_EDMA0_TCD15_CLK, 1306 #endif 1307 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK) 1308 EDMA0_TCD16_CLK = CLOCK_IP_HAS_EDMA0_TCD16_CLK, 1309 #endif 1310 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK) 1311 EDMA0_TCD17_CLK = CLOCK_IP_HAS_EDMA0_TCD17_CLK, 1312 #endif 1313 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK) 1314 EDMA0_TCD18_CLK = CLOCK_IP_HAS_EDMA0_TCD18_CLK, 1315 #endif 1316 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK) 1317 EDMA0_TCD19_CLK = CLOCK_IP_HAS_EDMA0_TCD19_CLK, 1318 #endif 1319 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK) 1320 EDMA0_TCD20_CLK = CLOCK_IP_HAS_EDMA0_TCD20_CLK, 1321 #endif 1322 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK) 1323 EDMA0_TCD21_CLK = CLOCK_IP_HAS_EDMA0_TCD21_CLK, 1324 #endif 1325 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK) 1326 EDMA0_TCD22_CLK = CLOCK_IP_HAS_EDMA0_TCD22_CLK, 1327 #endif 1328 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK) 1329 EDMA0_TCD23_CLK = CLOCK_IP_HAS_EDMA0_TCD23_CLK, 1330 #endif 1331 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK) 1332 EDMA0_TCD24_CLK = CLOCK_IP_HAS_EDMA0_TCD24_CLK, 1333 #endif 1334 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK) 1335 EDMA0_TCD25_CLK = CLOCK_IP_HAS_EDMA0_TCD25_CLK, 1336 #endif 1337 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK) 1338 EDMA0_TCD26_CLK = CLOCK_IP_HAS_EDMA0_TCD26_CLK, 1339 #endif 1340 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK) 1341 EDMA0_TCD27_CLK = CLOCK_IP_HAS_EDMA0_TCD27_CLK, 1342 #endif 1343 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1344 EDMA0_TCD28_CLK = CLOCK_IP_HAS_EDMA0_TCD28_CLK, 1345 #endif 1346 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK) 1347 EDMA0_TCD29_CLK = CLOCK_IP_HAS_EDMA0_TCD29_CLK, 1348 #endif 1349 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK) 1350 EDMA0_TCD30_CLK = CLOCK_IP_HAS_EDMA0_TCD30_CLK, 1351 #endif 1352 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK) 1353 EDMA0_TCD31_CLK = CLOCK_IP_HAS_EDMA0_TCD31_CLK, 1354 #endif 1355 #if defined(CLOCK_IP_HAS_EDMA1_CLK) 1356 EDMA1_CLK = CLOCK_IP_HAS_EDMA1_CLK, 1357 #endif 1358 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK) 1359 EDMA1_TCD0_CLK = CLOCK_IP_HAS_EDMA1_TCD0_CLK, 1360 #endif 1361 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK) 1362 EDMA1_TCD1_CLK = CLOCK_IP_HAS_EDMA1_TCD1_CLK, 1363 #endif 1364 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK) 1365 EDMA1_TCD2_CLK = CLOCK_IP_HAS_EDMA1_TCD2_CLK, 1366 #endif 1367 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK) 1368 EDMA1_TCD3_CLK = CLOCK_IP_HAS_EDMA1_TCD3_CLK, 1369 #endif 1370 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK) 1371 EDMA1_TCD4_CLK = CLOCK_IP_HAS_EDMA1_TCD4_CLK, 1372 #endif 1373 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK) 1374 EDMA1_TCD5_CLK = CLOCK_IP_HAS_EDMA1_TCD5_CLK, 1375 #endif 1376 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK) 1377 EDMA1_TCD6_CLK = CLOCK_IP_HAS_EDMA1_TCD6_CLK, 1378 #endif 1379 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK) 1380 EDMA1_TCD7_CLK = CLOCK_IP_HAS_EDMA1_TCD7_CLK, 1381 #endif 1382 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK) 1383 EDMA1_TCD8_CLK = CLOCK_IP_HAS_EDMA1_TCD8_CLK, 1384 #endif 1385 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK) 1386 EDMA1_TCD9_CLK = CLOCK_IP_HAS_EDMA1_TCD9_CLK, 1387 #endif 1388 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK) 1389 EDMA1_TCD10_CLK = CLOCK_IP_HAS_EDMA1_TCD10_CLK, 1390 #endif 1391 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK) 1392 EDMA1_TCD11_CLK = CLOCK_IP_HAS_EDMA1_TCD11_CLK, 1393 #endif 1394 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK) 1395 EDMA1_TCD12_CLK = CLOCK_IP_HAS_EDMA1_TCD12_CLK, 1396 #endif 1397 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK) 1398 EDMA1_TCD13_CLK = CLOCK_IP_HAS_EDMA1_TCD13_CLK, 1399 #endif 1400 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK) 1401 EDMA1_TCD14_CLK = CLOCK_IP_HAS_EDMA1_TCD14_CLK, 1402 #endif 1403 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK) 1404 EDMA1_TCD15_CLK = CLOCK_IP_HAS_EDMA1_TCD15_CLK, 1405 #endif 1406 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK) 1407 EDMA1_TCD16_CLK = CLOCK_IP_HAS_EDMA1_TCD16_CLK, 1408 #endif 1409 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK) 1410 EDMA1_TCD17_CLK = CLOCK_IP_HAS_EDMA1_TCD17_CLK, 1411 #endif 1412 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK) 1413 EDMA1_TCD18_CLK = CLOCK_IP_HAS_EDMA1_TCD18_CLK, 1414 #endif 1415 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK) 1416 EDMA1_TCD19_CLK = CLOCK_IP_HAS_EDMA1_TCD19_CLK, 1417 #endif 1418 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK) 1419 EDMA1_TCD20_CLK = CLOCK_IP_HAS_EDMA1_TCD20_CLK, 1420 #endif 1421 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK) 1422 EDMA1_TCD21_CLK = CLOCK_IP_HAS_EDMA1_TCD21_CLK, 1423 #endif 1424 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK) 1425 EDMA1_TCD22_CLK = CLOCK_IP_HAS_EDMA1_TCD22_CLK, 1426 #endif 1427 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK) 1428 EDMA1_TCD23_CLK = CLOCK_IP_HAS_EDMA1_TCD23_CLK, 1429 #endif 1430 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK) 1431 EDMA1_TCD24_CLK = CLOCK_IP_HAS_EDMA1_TCD24_CLK, 1432 #endif 1433 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK) 1434 EDMA1_TCD25_CLK = CLOCK_IP_HAS_EDMA1_TCD25_CLK, 1435 #endif 1436 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK) 1437 EDMA1_TCD26_CLK = CLOCK_IP_HAS_EDMA1_TCD26_CLK, 1438 #endif 1439 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK) 1440 EDMA1_TCD27_CLK = CLOCK_IP_HAS_EDMA1_TCD27_CLK, 1441 #endif 1442 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK) 1443 EDMA1_TCD28_CLK = CLOCK_IP_HAS_EDMA1_TCD28_CLK, 1444 #endif 1445 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK) 1446 EDMA1_TCD29_CLK = CLOCK_IP_HAS_EDMA1_TCD29_CLK, 1447 #endif 1448 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK) 1449 EDMA1_TCD30_CLK = CLOCK_IP_HAS_EDMA1_TCD30_CLK, 1450 #endif 1451 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK) 1452 EDMA1_TCD31_CLK = CLOCK_IP_HAS_EDMA1_TCD31_CLK, 1453 #endif 1454 #if defined(CLOCK_IP_HAS_EDMA3_CLK) 1455 EDMA3_CLK = CLOCK_IP_HAS_EDMA3_CLK, 1456 #endif 1457 #if defined(CLOCK_IP_HAS_EDMA4_CLK) 1458 EDMA4_CLK = CLOCK_IP_HAS_EDMA4_CLK, 1459 #endif 1460 #if defined(CLOCK_IP_HAS_EDMA5_CLK) 1461 EDMA5_CLK = CLOCK_IP_HAS_EDMA5_CLK, 1462 #endif 1463 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK) 1464 EFLEX_PWM0_CLK = CLOCK_IP_HAS_EFLEX_PWM0_CLK, 1465 #endif 1466 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK) 1467 EFLEX_PWM1_CLK = CLOCK_IP_HAS_EFLEX_PWM1_CLK, 1468 #endif 1469 #if defined(CLOCK_IP_HAS_FDMA0_CLK) 1470 FDMA0_CLK = CLOCK_IP_HAS_FDMA0_CLK, 1471 #endif 1472 #if defined(CLOCK_IP_HAS_ENET_CLK) 1473 ENET_CLK = CLOCK_IP_HAS_ENET_CLK, 1474 #endif 1475 #if defined(CLOCK_IP_HAS_EIM_CLK) 1476 EIM_CLK = CLOCK_IP_HAS_EIM_CLK, 1477 #endif 1478 #if defined(CLOCK_IP_HAS_EIM0_CLK) 1479 EIM0_CLK = CLOCK_IP_HAS_EIM0_CLK, 1480 #endif 1481 #if defined(CLOCK_IP_HAS_EIM1_CLK) 1482 EIM1_CLK = CLOCK_IP_HAS_EIM1_CLK, 1483 #endif 1484 #if defined(CLOCK_IP_HAS_EIM2_CLK) 1485 EIM2_CLK = CLOCK_IP_HAS_EIM2_CLK, 1486 #endif 1487 #if defined(CLOCK_IP_HAS_EIM3_CLK) 1488 EIM3_CLK = CLOCK_IP_HAS_EIM3_CLK, 1489 #endif 1490 #if defined(CLOCK_IP_HAS_EIM_BBE32DSP_CLK) 1491 EIM_BBE32DSP_CLK = CLOCK_IP_HAS_EIM_BBE32DSP_CLK, 1492 #endif 1493 #if defined(CLOCK_IP_HAS_EIM_LAX0_CLK) 1494 EIM_LAX0_CLK = CLOCK_IP_HAS_EIM_LAX0_CLK, 1495 #endif 1496 #if defined(CLOCK_IP_HAS_EIM_LAX1_CLK) 1497 EIM_LAX1_CLK = CLOCK_IP_HAS_EIM_LAX1_CLK, 1498 #endif 1499 #if defined(CLOCK_IP_HAS_EIM_PER1_CLK) 1500 EIM_PER1_CLK = CLOCK_IP_HAS_EIM_PER1_CLK, 1501 #endif 1502 #if defined(CLOCK_IP_HAS_ENET0_CLK) 1503 ENET0_CLK = CLOCK_IP_HAS_ENET0_CLK, 1504 #endif 1505 #if defined(CLOCK_IP_HAS_ENET1_CLK) 1506 ENET1_CLK = CLOCK_IP_HAS_ENET1_CLK, 1507 #endif 1508 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK) 1509 EMAC_RX_CLK = CLOCK_IP_HAS_EMAC_RX_CLK, 1510 #endif 1511 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) 1512 EMAC_TS_CLK = CLOCK_IP_HAS_EMAC_TS_CLK, 1513 #endif 1514 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK) 1515 EMAC_TX_CLK = CLOCK_IP_HAS_EMAC_TX_CLK, 1516 #endif 1517 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) 1518 EMAC_TX_RMII_CLK = CLOCK_IP_HAS_EMAC_TX_RMII_CLK, 1519 #endif 1520 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK) 1521 EMAC0_RX_CLK = CLOCK_IP_HAS_EMAC0_RX_CLK, 1522 #endif 1523 #if defined(CLOCK_IP_HAS_EMAC0_TS_CLK) 1524 EMAC0_TS_CLK = CLOCK_IP_HAS_EMAC0_TS_CLK, 1525 #endif 1526 #if defined(CLOCK_IP_HAS_EMAC0_TX_CLK) 1527 EMAC0_TX_CLK = CLOCK_IP_HAS_EMAC0_TX_CLK, 1528 #endif 1529 #if defined(CLOCK_IP_HAS_EMIOS0_CLK) 1530 EMIOS0_CLK = CLOCK_IP_HAS_EMIOS0_CLK, 1531 #endif 1532 #if defined(CLOCK_IP_HAS_EMIOS1_CLK) 1533 EMIOS1_CLK = CLOCK_IP_HAS_EMIOS1_CLK, 1534 #endif 1535 #if defined(CLOCK_IP_HAS_EMIOS2_CLK) 1536 EMIOS2_CLK = CLOCK_IP_HAS_EMIOS2_CLK, 1537 #endif 1538 #if defined(CLOCK_IP_HAS_ERM0_CLK) 1539 ERM0_CLK = CLOCK_IP_HAS_ERM0_CLK, 1540 #endif 1541 #if defined(CLOCK_IP_HAS_ERM1_CLK) 1542 ERM1_CLK = CLOCK_IP_HAS_ERM1_CLK, 1543 #endif 1544 #if defined(CLOCK_IP_HAS_ERM_CPU0_CLK) 1545 ERM_CPU0_CLK = CLOCK_IP_HAS_ERM_CPU0_CLK, 1546 #endif 1547 #if defined(CLOCK_IP_HAS_ERM_CPU1_CLK) 1548 ERM_CPU1_CLK = CLOCK_IP_HAS_ERM_CPU1_CLK, 1549 #endif 1550 #if defined(CLOCK_IP_HAS_ERM_CPU2_CLK) 1551 ERM_CPU2_CLK = CLOCK_IP_HAS_ERM_CPU2_CLK, 1552 #endif 1553 #if defined(CLOCK_IP_HAS_ERM_EDMA0_CLK) 1554 ERM_EDMA0_CLK = CLOCK_IP_HAS_ERM_EDMA0_CLK, 1555 #endif 1556 #if defined(CLOCK_IP_HAS_ERM_EDMA1_CLK) 1557 ERM_EDMA1_CLK = CLOCK_IP_HAS_ERM_EDMA1_CLK, 1558 #endif 1559 #if defined(CLOCK_IP_HAS_ERM_LAX0_CLK) 1560 ERM_LAX0_CLK = CLOCK_IP_HAS_ERM_LAX0_CLK, 1561 #endif 1562 #if defined(CLOCK_IP_HAS_ERM_LAX1_CLK) 1563 ERM_LAX1_CLK = CLOCK_IP_HAS_ERM_LAX1_CLK, 1564 #endif 1565 #if defined(CLOCK_IP_HAS_ERM_PER_CLK) 1566 ERM_PER_CLK = CLOCK_IP_HAS_ERM_PER_CLK, 1567 #endif 1568 #if defined(CLOCK_IP_HAS_ERM_PER1_CLK) 1569 ERM_PER1_CLK = CLOCK_IP_HAS_ERM_PER1_CLK, 1570 #endif 1571 #if defined(CLOCK_IP_HAS_ERM_CLK) 1572 ERM_CLK = CLOCK_IP_HAS_ERM_CLK, 1573 #endif 1574 #if defined(CLOCK_IP_HAS_EWM0_CLK) 1575 EWM0_CLK = CLOCK_IP_HAS_EWM0_CLK, 1576 #endif 1577 #if defined(CLOCK_IP_HAS_FIRC_MON1_CLK) 1578 FIRC_MON1_CLK = CLOCK_IP_HAS_FIRC_MON1_CLK, 1579 #endif 1580 #if defined(CLOCK_IP_HAS_FIRC_MON2_CLK) 1581 FIRC_MON2_CLK = CLOCK_IP_HAS_FIRC_MON2_CLK, 1582 #endif 1583 #if defined(CLOCK_IP_HAS_FLASH0_CLK) 1584 FLASH0_CLK = CLOCK_IP_HAS_FLASH0_CLK, 1585 #endif 1586 #if defined(CLOCK_IP_HAS_CAN_PE_CLK) 1587 CAN_PE_CLK = CLOCK_IP_HAS_CAN_PE_CLK, 1588 #endif 1589 #if defined(CLOCK_IP_HAS_FLEXCAN_CLK) 1590 FLEXCAN_CLK = CLOCK_IP_HAS_FLEXCAN_CLK, 1591 #endif 1592 #if defined(CLOCK_IP_HAS_FLEXCAN0_CLK) 1593 FLEXCAN0_CLK = CLOCK_IP_HAS_FLEXCAN0_CLK, 1594 #endif 1595 #if defined(CLOCK_IP_HAS_FLEXCAN1_CLK) 1596 FLEXCAN1_CLK = CLOCK_IP_HAS_FLEXCAN1_CLK, 1597 #endif 1598 #if defined(CLOCK_IP_HAS_FLEXCAN2_CLK) 1599 FLEXCAN2_CLK = CLOCK_IP_HAS_FLEXCAN2_CLK, 1600 #endif 1601 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK) 1602 FLEXCAN3_CLK = CLOCK_IP_HAS_FLEXCAN3_CLK, 1603 #endif 1604 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK) 1605 FLEXCAN4_CLK = CLOCK_IP_HAS_FLEXCAN4_CLK, 1606 #endif 1607 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK) 1608 FLEXCAN5_CLK = CLOCK_IP_HAS_FLEXCAN5_CLK, 1609 #endif 1610 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK) 1611 FLEXCAN6_CLK = CLOCK_IP_HAS_FLEXCAN6_CLK, 1612 #endif 1613 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK) 1614 FLEXCAN7_CLK = CLOCK_IP_HAS_FLEXCAN7_CLK, 1615 #endif 1616 #if defined(CLOCK_IP_HAS_FLEXCAN8_CLK) 1617 FLEXCAN8_CLK = CLOCK_IP_HAS_FLEXCAN8_CLK, 1618 #endif 1619 #if defined(CLOCK_IP_HAS_FLEXCAN9_CLK) 1620 FLEXCAN9_CLK = CLOCK_IP_HAS_FLEXCAN9_CLK, 1621 #endif 1622 #if defined(CLOCK_IP_HAS_FLEXCAN10_CLK) 1623 FLEXCAN10_CLK = CLOCK_IP_HAS_FLEXCAN10_CLK, 1624 #endif 1625 #if defined(CLOCK_IP_HAS_FLEXCAN11_CLK) 1626 FLEXCAN11_CLK = CLOCK_IP_HAS_FLEXCAN11_CLK, 1627 #endif 1628 #if defined(CLOCK_IP_HAS_FLEXCAN12_CLK) 1629 FLEXCAN12_CLK = CLOCK_IP_HAS_FLEXCAN12_CLK, 1630 #endif 1631 #if defined(CLOCK_IP_HAS_FLEXCAN13_CLK) 1632 FLEXCAN13_CLK = CLOCK_IP_HAS_FLEXCAN13_CLK, 1633 #endif 1634 #if defined(CLOCK_IP_HAS_FLEXCAN14_CLK) 1635 FLEXCAN14_CLK = CLOCK_IP_HAS_FLEXCAN14_CLK, 1636 #endif 1637 #if defined(CLOCK_IP_HAS_FLEXCAN15_CLK) 1638 FLEXCAN15_CLK = CLOCK_IP_HAS_FLEXCAN15_CLK, 1639 #endif 1640 #if defined(CLOCK_IP_HAS_FLEXCAN16_CLK) 1641 FLEXCAN16_CLK = CLOCK_IP_HAS_FLEXCAN16_CLK, 1642 #endif 1643 #if defined(CLOCK_IP_HAS_FLEXCAN17_CLK) 1644 FLEXCAN17_CLK = CLOCK_IP_HAS_FLEXCAN17_CLK, 1645 #endif 1646 #if defined(CLOCK_IP_HAS_FLEXCAN18_CLK) 1647 FLEXCAN18_CLK = CLOCK_IP_HAS_FLEXCAN18_CLK, 1648 #endif 1649 #if defined(CLOCK_IP_HAS_FLEXCAN19_CLK) 1650 FLEXCAN19_CLK = CLOCK_IP_HAS_FLEXCAN19_CLK, 1651 #endif 1652 #if defined(CLOCK_IP_HAS_FLEXCAN20_CLK) 1653 FLEXCAN20_CLK = CLOCK_IP_HAS_FLEXCAN20_CLK, 1654 #endif 1655 #if defined(CLOCK_IP_HAS_FLEXCAN21_CLK) 1656 FLEXCAN21_CLK = CLOCK_IP_HAS_FLEXCAN21_CLK, 1657 #endif 1658 #if defined(CLOCK_IP_HAS_FLEXCAN22_CLK) 1659 FLEXCAN22_CLK = CLOCK_IP_HAS_FLEXCAN22_CLK, 1660 #endif 1661 #if defined(CLOCK_IP_HAS_FLEXCAN23_CLK) 1662 FLEXCAN23_CLK = CLOCK_IP_HAS_FLEXCAN23_CLK, 1663 #endif 1664 #if defined(CLOCK_IP_HAS_FLEXCANA_CLK) 1665 FLEXCANA_CLK = CLOCK_IP_HAS_FLEXCANA_CLK, 1666 #endif 1667 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK) 1668 FLEXCANB_CLK = CLOCK_IP_HAS_FLEXCANB_CLK, 1669 #endif 1670 #if defined(CLOCK_IP_HAS_FlexIO_CLK) 1671 FlexIO_CLK = CLOCK_IP_HAS_FlexIO_CLK, 1672 #endif 1673 #if defined(CLOCK_IP_HAS_FlexIO0_CLK) 1674 FlexIO0_CLK = CLOCK_IP_HAS_FlexIO0_CLK, 1675 #endif 1676 #if defined(CLOCK_IP_HAS_FLEXIO0_CLK) 1677 FLEXIO0_CLK = CLOCK_IP_HAS_FLEXIO0_CLK, 1678 #endif 1679 #if defined(CLOCK_IP_HAS_FLEXRAY_CLK) 1680 FLEXRAY_CLK = CLOCK_IP_HAS_FLEXRAY_CLK, 1681 #endif 1682 #if defined(CLOCK_IP_HAS_FLEXTIMERA_CLK) 1683 FLEXTIMERA_CLK = CLOCK_IP_HAS_FLEXTIMERA_CLK, 1684 #endif 1685 #if defined(CLOCK_IP_HAS_FLEXTIMERB_CLK) 1686 FLEXTIMERB_CLK = CLOCK_IP_HAS_FLEXTIMERB_CLK, 1687 #endif 1688 #if defined(CLOCK_IP_HAS_FRAY0_CLK) 1689 FRAY0_CLK = CLOCK_IP_HAS_FRAY0_CLK, 1690 #endif 1691 #if defined(CLOCK_IP_HAS_FRAY1_CLK) 1692 FRAY1_CLK = CLOCK_IP_HAS_FRAY1_CLK, 1693 #endif 1694 #if defined(CLOCK_IP_HAS_FTFC_CLK) 1695 FTFC_CLK = CLOCK_IP_HAS_FTFC_CLK, 1696 #endif 1697 #if defined(CLOCK_IP_HAS_FTFM_CLK) 1698 FTFM_CLK = CLOCK_IP_HAS_FTFM_CLK, 1699 #endif 1700 #if defined(CLOCK_IP_HAS_FTIMER0_CLK) 1701 FTIMER0_CLK = CLOCK_IP_HAS_FTIMER0_CLK, 1702 #endif 1703 #if defined(CLOCK_IP_HAS_FTIMER1_CLK) 1704 FTIMER1_CLK = CLOCK_IP_HAS_FTIMER1_CLK, 1705 #endif 1706 #if defined(CLOCK_IP_HAS_FTM0_CLK) 1707 FTM0_CLK = CLOCK_IP_HAS_FTM0_CLK, 1708 #endif 1709 #if defined(CLOCK_IP_HAS_FTM1_CLK) 1710 FTM1_CLK = CLOCK_IP_HAS_FTM1_CLK, 1711 #endif 1712 #if defined(CLOCK_IP_HAS_FTM2_CLK) 1713 FTM2_CLK = CLOCK_IP_HAS_FTM2_CLK, 1714 #endif 1715 #if defined(CLOCK_IP_HAS_FTM3_CLK) 1716 FTM3_CLK = CLOCK_IP_HAS_FTM3_CLK, 1717 #endif 1718 #if defined(CLOCK_IP_HAS_FTM4_CLK) 1719 FTM4_CLK = CLOCK_IP_HAS_FTM4_CLK, 1720 #endif 1721 #if defined(CLOCK_IP_HAS_FTM5_CLK) 1722 FTM5_CLK = CLOCK_IP_HAS_FTM5_CLK, 1723 #endif 1724 #if defined(CLOCK_IP_HAS_FTM6_CLK) 1725 FTM6_CLK = CLOCK_IP_HAS_FTM6_CLK, 1726 #endif 1727 #if defined(CLOCK_IP_HAS_FTM7_CLK) 1728 FTM7_CLK = CLOCK_IP_HAS_FTM7_CLK, 1729 #endif 1730 #if defined(CLOCK_IP_HAS_GLB_LBIST_CLK) 1731 GLB_LBIST_CLK = CLOCK_IP_HAS_GLB_LBIST_CLK, 1732 #endif 1733 #if defined(CLOCK_IP_HAS_GMAC0_CLK) 1734 GMAC0_CLK = CLOCK_IP_HAS_GMAC0_CLK, 1735 #endif 1736 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK) 1737 GMAC_TS_CLK = CLOCK_IP_HAS_GMAC_TS_CLK, 1738 #endif 1739 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK) 1740 GMAC0_RX_CLK = CLOCK_IP_HAS_GMAC0_RX_CLK, 1741 #endif 1742 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK) 1743 GMAC0_TX_CLK = CLOCK_IP_HAS_GMAC0_TX_CLK, 1744 #endif 1745 #if defined(CLOCK_IP_HAS_GMAC0_TS_CLK) 1746 GMAC0_TS_CLK = CLOCK_IP_HAS_GMAC0_TS_CLK, 1747 #endif 1748 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK) 1749 GMAC0_TX_RMII_CLK = CLOCK_IP_HAS_GMAC0_TX_RMII_CLK, 1750 #endif 1751 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK) 1752 GMAC0_MII_RX_CLK = CLOCK_IP_HAS_GMAC0_MII_RX_CLK, 1753 #endif 1754 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK) 1755 GMAC0_MII_RMII_TX_CLK = CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK, 1756 #endif 1757 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK) 1758 GMAC1_RX_CLK = CLOCK_IP_HAS_GMAC1_RX_CLK, 1759 #endif 1760 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK) 1761 GMAC1_TX_CLK = CLOCK_IP_HAS_GMAC1_TX_CLK, 1762 #endif 1763 #if defined(CLOCK_IP_HAS_GMAC1_TS_CLK) 1764 GMAC1_TS_CLK = CLOCK_IP_HAS_GMAC1_TS_CLK, 1765 #endif 1766 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 1767 GMAC1_RMII_CLK = CLOCK_IP_HAS_GMAC1_RMII_CLK, 1768 #endif 1769 #if defined(CLOCK_IP_HAS_GPIO0_CLK) 1770 GPIO0_CLK = CLOCK_IP_HAS_GPIO0_CLK, 1771 #endif 1772 #if defined(CLOCK_IP_HAS_GTM_CLK) 1773 GTM_CLK = CLOCK_IP_HAS_GTM_CLK, 1774 #endif 1775 #if defined(CLOCK_IP_HAS_IDIV0_CLK) 1776 IDIV0_CLK = CLOCK_IP_HAS_IDIV0_CLK, 1777 #endif 1778 #if defined(CLOCK_IP_HAS_IDIV1_CLK) 1779 IDIV1_CLK = CLOCK_IP_HAS_IDIV1_CLK, 1780 #endif 1781 #if defined(CLOCK_IP_HAS_IDIV2_CLK) 1782 IDIV2_CLK = CLOCK_IP_HAS_IDIV2_CLK, 1783 #endif 1784 #if defined(CLOCK_IP_HAS_IDIV3_CLK) 1785 IDIV3_CLK = CLOCK_IP_HAS_IDIV3_CLK, 1786 #endif 1787 #if defined(CLOCK_IP_HAS_IDIV4_CLK) 1788 IDIV4_CLK = CLOCK_IP_HAS_IDIV4_CLK, 1789 #endif 1790 #if defined(CLOCK_IP_HAS_I3C0_CLK) 1791 I3C0_CLK = CLOCK_IP_HAS_I3C0_CLK, 1792 #endif 1793 #if defined(CLOCK_IP_HAS_I3C1_CLK) 1794 I3C1_CLK = CLOCK_IP_HAS_I3C1_CLK, 1795 #endif 1796 #if defined(CLOCK_IP_HAS_IGF0_CLK) 1797 IGF0_CLK = CLOCK_IP_HAS_IGF0_CLK, 1798 #endif 1799 #if defined(CLOCK_IP_HAS_IIIC0_CLK) 1800 IIIC0_CLK = CLOCK_IP_HAS_IIIC0_CLK, 1801 #endif 1802 #if defined(CLOCK_IP_HAS_IIIC1_CLK) 1803 IIIC1_CLK = CLOCK_IP_HAS_IIIC1_CLK, 1804 #endif 1805 #if defined(CLOCK_IP_HAS_IIIC2_CLK) 1806 IIIC2_CLK = CLOCK_IP_HAS_IIIC2_CLK, 1807 #endif 1808 #if defined(CLOCK_IP_HAS_IIC0_CLK) 1809 IIC0_CLK = CLOCK_IP_HAS_IIC0_CLK, 1810 #endif 1811 #if defined(CLOCK_IP_HAS_IIC1_CLK) 1812 IIC1_CLK = CLOCK_IP_HAS_IIC1_CLK, 1813 #endif 1814 #if defined(CLOCK_IP_HAS_IIC2_CLK) 1815 IIC2_CLK = CLOCK_IP_HAS_IIC2_CLK, 1816 #endif 1817 #if defined(CLOCK_IP_HAS_IIC3_CLK) 1818 IIC3_CLK = CLOCK_IP_HAS_IIC3_CLK, 1819 #endif 1820 #if defined(CLOCK_IP_HAS_IIC4_CLK) 1821 IIC4_CLK = CLOCK_IP_HAS_IIC4_CLK, 1822 #endif 1823 #if defined(CLOCK_IP_HAS_INTM_CLK) 1824 INTM_CLK = CLOCK_IP_HAS_INTM_CLK, 1825 #endif 1826 #if defined(CLOCK_IP_HAS_ISO_CLK) 1827 ISO_CLK = CLOCK_IP_HAS_ISO_CLK, 1828 #endif 1829 #if defined(CLOCK_IP_HAS_LBIST0_CLK) 1830 LBIST0_CLK = CLOCK_IP_HAS_LBIST0_CLK, 1831 #endif 1832 #if defined(CLOCK_IP_HAS_LBIST1_CLK) 1833 LBIST1_CLK = CLOCK_IP_HAS_LBIST1_CLK, 1834 #endif 1835 #if defined(CLOCK_IP_HAS_LBIST2_CLK) 1836 LBIST2_CLK = CLOCK_IP_HAS_LBIST2_CLK, 1837 #endif 1838 #if defined(CLOCK_IP_HAS_LBIST3_CLK) 1839 LBIST3_CLK = CLOCK_IP_HAS_LBIST3_CLK, 1840 #endif 1841 #if defined(CLOCK_IP_HAS_LBIST4_CLK) 1842 LBIST4_CLK = CLOCK_IP_HAS_LBIST4_CLK, 1843 #endif 1844 #if defined(CLOCK_IP_HAS_LBIST5_CLK) 1845 LBIST5_CLK = CLOCK_IP_HAS_LBIST5_CLK, 1846 #endif 1847 #if defined(CLOCK_IP_HAS_LBIST6_CLK) 1848 LBIST6_CLK = CLOCK_IP_HAS_LBIST6_CLK, 1849 #endif 1850 #if defined(CLOCK_IP_HAS_LBIST7_CLK) 1851 LBIST7_CLK = CLOCK_IP_HAS_LBIST7_CLK, 1852 #endif 1853 #if defined(CLOCK_IP_HAS_LCU0_CLK) 1854 LCU0_CLK = CLOCK_IP_HAS_LCU0_CLK, 1855 #endif 1856 #if defined(CLOCK_IP_HAS_LCU1_CLK) 1857 LCU1_CLK = CLOCK_IP_HAS_LCU1_CLK, 1858 #endif 1859 #if defined(CLOCK_IP_HAS_LIN_BAUD_CLK) 1860 LIN_BAUD_CLK = CLOCK_IP_HAS_LIN_BAUD_CLK, 1861 #endif 1862 #if defined(CLOCK_IP_HAS_LINFLEXD_CLK) 1863 LINFLEXD_CLK = CLOCK_IP_HAS_LINFLEXD_CLK, 1864 #endif 1865 #if defined(CLOCK_IP_HAS_LIN0_CLK) 1866 LIN0_CLK = CLOCK_IP_HAS_LIN0_CLK, 1867 #endif 1868 #if defined(CLOCK_IP_HAS_LIN1_CLK) 1869 LIN1_CLK = CLOCK_IP_HAS_LIN1_CLK, 1870 #endif 1871 #if defined(CLOCK_IP_HAS_LIN2_CLK) 1872 LIN2_CLK = CLOCK_IP_HAS_LIN2_CLK, 1873 #endif 1874 #if defined(CLOCK_IP_HAS_LIN3_CLK) 1875 LIN3_CLK = CLOCK_IP_HAS_LIN3_CLK, 1876 #endif 1877 #if defined(CLOCK_IP_HAS_LIN4_CLK) 1878 LIN4_CLK = CLOCK_IP_HAS_LIN4_CLK, 1879 #endif 1880 #if defined(CLOCK_IP_HAS_LIN5_CLK) 1881 LIN5_CLK = CLOCK_IP_HAS_LIN5_CLK, 1882 #endif 1883 #if defined(CLOCK_IP_HAS_LIN6_CLK) 1884 LIN6_CLK = CLOCK_IP_HAS_LIN6_CLK, 1885 #endif 1886 #if defined(CLOCK_IP_HAS_LIN7_CLK) 1887 LIN7_CLK = CLOCK_IP_HAS_LIN7_CLK, 1888 #endif 1889 #if defined(CLOCK_IP_HAS_LIN8_CLK) 1890 LIN8_CLK = CLOCK_IP_HAS_LIN8_CLK, 1891 #endif 1892 #if defined(CLOCK_IP_HAS_LIN9_CLK) 1893 LIN9_CLK = CLOCK_IP_HAS_LIN9_CLK, 1894 #endif 1895 #if defined(CLOCK_IP_HAS_LIN10_CLK) 1896 LIN10_CLK = CLOCK_IP_HAS_LIN10_CLK, 1897 #endif 1898 #if defined(CLOCK_IP_HAS_LIN11_CLK) 1899 LIN11_CLK = CLOCK_IP_HAS_LIN11_CLK, 1900 #endif 1901 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK) 1902 LFAST_REF_CLK = CLOCK_IP_HAS_LFAST_REF_CLK, 1903 #endif 1904 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK) 1905 LFAST_REF_EXT_CLK = CLOCK_IP_HAS_LFAST_REF_EXT_CLK, 1906 #endif 1907 #if defined(CLOCK_IP_HAS_LPI2C0_CLK) 1908 LPI2C0_CLK = CLOCK_IP_HAS_LPI2C0_CLK, 1909 #endif 1910 #if defined(CLOCK_IP_HAS_LPI2C1_CLK) 1911 LPI2C1_CLK = CLOCK_IP_HAS_LPI2C1_CLK, 1912 #endif 1913 #if defined(CLOCK_IP_HAS_LPIT0_CLK) 1914 LPIT0_CLK = CLOCK_IP_HAS_LPIT0_CLK, 1915 #endif 1916 #if defined(CLOCK_IP_HAS_LPSPI_CLK) 1917 LPSPI_CLK = CLOCK_IP_HAS_LPSPI_CLK, 1918 #endif 1919 #if defined(CLOCK_IP_HAS_LPSPI0_CLK) 1920 LPSPI0_CLK = CLOCK_IP_HAS_LPSPI0_CLK, 1921 #endif 1922 #if defined(CLOCK_IP_HAS_LPSPI1_CLK) 1923 LPSPI1_CLK = CLOCK_IP_HAS_LPSPI1_CLK, 1924 #endif 1925 #if defined(CLOCK_IP_HAS_LPSPI2_CLK) 1926 LPSPI2_CLK = CLOCK_IP_HAS_LPSPI2_CLK, 1927 #endif 1928 #if defined(CLOCK_IP_HAS_LPSPI3_CLK) 1929 LPSPI3_CLK = CLOCK_IP_HAS_LPSPI3_CLK, 1930 #endif 1931 #if defined(CLOCK_IP_HAS_LPSPI4_CLK) 1932 LPSPI4_CLK = CLOCK_IP_HAS_LPSPI4_CLK, 1933 #endif 1934 #if defined(CLOCK_IP_HAS_LPSPI5_CLK) 1935 LPSPI5_CLK = CLOCK_IP_HAS_LPSPI5_CLK, 1936 #endif 1937 #if defined(CLOCK_IP_HAS_LPTMR0_CLK) 1938 LPTMR0_CLK = CLOCK_IP_HAS_LPTMR0_CLK, 1939 #endif 1940 #if defined(CLOCK_IP_HAS_LPUART0_CLK) 1941 LPUART0_CLK = CLOCK_IP_HAS_LPUART0_CLK, 1942 #endif 1943 #if defined(CLOCK_IP_HAS_LPUART1_CLK) 1944 LPUART1_CLK = CLOCK_IP_HAS_LPUART1_CLK, 1945 #endif 1946 #if defined(CLOCK_IP_HAS_LPUART2_CLK) 1947 LPUART2_CLK = CLOCK_IP_HAS_LPUART2_CLK, 1948 #endif 1949 #if defined(CLOCK_IP_HAS_LPUART3_CLK) 1950 LPUART3_CLK = CLOCK_IP_HAS_LPUART3_CLK, 1951 #endif 1952 #if defined(CLOCK_IP_HAS_LPUART4_CLK) 1953 LPUART4_CLK = CLOCK_IP_HAS_LPUART4_CLK, 1954 #endif 1955 #if defined(CLOCK_IP_HAS_LPUART5_CLK) 1956 LPUART5_CLK = CLOCK_IP_HAS_LPUART5_CLK, 1957 #endif 1958 #if defined(CLOCK_IP_HAS_LPUART6_CLK) 1959 LPUART6_CLK = CLOCK_IP_HAS_LPUART6_CLK, 1960 #endif 1961 #if defined(CLOCK_IP_HAS_LPUART7_CLK) 1962 LPUART7_CLK = CLOCK_IP_HAS_LPUART7_CLK, 1963 #endif 1964 #if defined(CLOCK_IP_HAS_LPUART8_CLK) 1965 LPUART8_CLK = CLOCK_IP_HAS_LPUART8_CLK, 1966 #endif 1967 #if defined(CLOCK_IP_HAS_LPUART9_CLK) 1968 LPUART9_CLK = CLOCK_IP_HAS_LPUART9_CLK, 1969 #endif 1970 #if defined(CLOCK_IP_HAS_LPUART10_CLK) 1971 LPUART10_CLK = CLOCK_IP_HAS_LPUART10_CLK, 1972 #endif 1973 #if defined(CLOCK_IP_HAS_LPUART11_CLK) 1974 LPUART11_CLK = CLOCK_IP_HAS_LPUART11_CLK, 1975 #endif 1976 #if defined(CLOCK_IP_HAS_LPUART12_CLK) 1977 LPUART12_CLK = CLOCK_IP_HAS_LPUART12_CLK, 1978 #endif 1979 #if defined(CLOCK_IP_HAS_LPUART13_CLK) 1980 LPUART13_CLK = CLOCK_IP_HAS_LPUART13_CLK, 1981 #endif 1982 #if defined(CLOCK_IP_HAS_LPUART14_CLK) 1983 LPUART14_CLK = CLOCK_IP_HAS_LPUART14_CLK, 1984 #endif 1985 #if defined(CLOCK_IP_HAS_LPUART15_CLK) 1986 LPUART15_CLK = CLOCK_IP_HAS_LPUART15_CLK, 1987 #endif 1988 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK) 1989 LPUART_MSC_CLK = CLOCK_IP_HAS_LPUART_MSC_CLK, 1990 #endif 1991 #if defined(CLOCK_IP_HAS_LVDS_CLK) 1992 LVDS_CLK = CLOCK_IP_HAS_LVDS_CLK, 1993 #endif 1994 #if defined(CLOCK_IP_HAS_MCSS_CLK) 1995 MCSS_CLK = CLOCK_IP_HAS_MCSS_CLK, 1996 #endif 1997 #if defined(CLOCK_IP_HAS_MPU0_CLK) 1998 MPU0_CLK = CLOCK_IP_HAS_MPU0_CLK, 1999 #endif 2000 #if defined(CLOCK_IP_HAS_MSCM_CLK) 2001 MSCM_CLK = CLOCK_IP_HAS_MSCM_CLK, 2002 #endif 2003 #if defined(CLOCK_IP_HAS_MSCM0_CLK) 2004 MSCM0_CLK = CLOCK_IP_HAS_MSCM0_CLK, 2005 #endif 2006 #if defined(CLOCK_IP_HAS_MUA_CLK) 2007 MUA_CLK = CLOCK_IP_HAS_MUA_CLK, 2008 #endif 2009 #if defined(CLOCK_IP_HAS_MUB_CLK) 2010 MUB_CLK = CLOCK_IP_HAS_MUB_CLK, 2011 #endif 2012 #if defined(CLOCK_IP_HAS_MU2A_CLK) 2013 MU2A_CLK = CLOCK_IP_HAS_MU2A_CLK, 2014 #endif 2015 #if defined(CLOCK_IP_HAS_MU2B_CLK) 2016 MU2B_CLK = CLOCK_IP_HAS_MU2B_CLK, 2017 #endif 2018 #if defined(CLOCK_IP_HAS_MU3A_CLK) 2019 MU3A_CLK = CLOCK_IP_HAS_MU3A_CLK, 2020 #endif 2021 #if defined(CLOCK_IP_HAS_MU3B_CLK) 2022 MU3B_CLK = CLOCK_IP_HAS_MU3B_CLK, 2023 #endif 2024 #if defined(CLOCK_IP_HAS_MU4A_CLK) 2025 MU4A_CLK = CLOCK_IP_HAS_MU4A_CLK, 2026 #endif 2027 #if defined(CLOCK_IP_HAS_MU4B_CLK) 2028 MU4B_CLK = CLOCK_IP_HAS_MU4B_CLK, 2029 #endif 2030 #if defined(CLOCK_IP_HAS_OCOTP_CLK) 2031 OCOTP_CLK = CLOCK_IP_HAS_OCOTP_CLK, 2032 #endif 2033 #if defined(CLOCK_IP_HAS_PDB0_CLK) 2034 PDB0_CLK = CLOCK_IP_HAS_PDB0_CLK, 2035 #endif 2036 #if defined(CLOCK_IP_HAS_PDB1_CLK) 2037 PDB1_CLK = CLOCK_IP_HAS_PDB1_CLK, 2038 #endif 2039 #if defined(CLOCK_IP_HAS_PFEMAC0_RX_CLK) 2040 PFEMAC0_RX_CLK = CLOCK_IP_HAS_PFEMAC0_RX_CLK, 2041 #endif 2042 #if defined(CLOCK_IP_HAS_PFEMAC0_TX_DIV_CLK) 2043 PFEMAC0_TX_DIV_CLK = CLOCK_IP_HAS_PFEMAC0_TX_DIV_CLK, 2044 #endif 2045 #if defined(CLOCK_IP_HAS_PFEMAC1_TX_DIV_CLK) 2046 PFEMAC1_TX_DIV_CLK = CLOCK_IP_HAS_PFEMAC1_TX_DIV_CLK, 2047 #endif 2048 #if defined(CLOCK_IP_HAS_PFEMAC2_TX_DIV_CLK) 2049 PFEMAC2_TX_DIV_CLK = CLOCK_IP_HAS_PFEMAC2_TX_DIV_CLK, 2050 #endif 2051 #if defined(CLOCK_IP_HAS_PFEMAC0_TX_CLK) 2052 PFEMAC0_TX_CLK = CLOCK_IP_HAS_PFEMAC0_TX_CLK, 2053 #endif 2054 #if defined(CLOCK_IP_HAS_PFEMAC1_RX_CLK) 2055 PFEMAC1_RX_CLK = CLOCK_IP_HAS_PFEMAC1_RX_CLK, 2056 #endif 2057 #if defined(CLOCK_IP_HAS_PFEMAC1_TX_CLK) 2058 PFEMAC1_TX_CLK = CLOCK_IP_HAS_PFEMAC1_TX_CLK, 2059 #endif 2060 #if defined(CLOCK_IP_HAS_PFEMAC2_RX_CLK) 2061 PFEMAC2_RX_CLK = CLOCK_IP_HAS_PFEMAC2_RX_CLK, 2062 #endif 2063 #if defined(CLOCK_IP_HAS_PFEMAC2_TX_CLK) 2064 PFEMAC2_TX_CLK = CLOCK_IP_HAS_PFEMAC2_TX_CLK, 2065 #endif 2066 #if defined(CLOCK_IP_HAS_PIT0_CLK) 2067 PIT0_CLK = CLOCK_IP_HAS_PIT0_CLK, 2068 #endif 2069 #if defined(CLOCK_IP_HAS_PIT1_CLK) 2070 PIT1_CLK = CLOCK_IP_HAS_PIT1_CLK, 2071 #endif 2072 #if defined(CLOCK_IP_HAS_PIT2_CLK) 2073 PIT2_CLK = CLOCK_IP_HAS_PIT2_CLK, 2074 #endif 2075 #if defined(CLOCK_IP_HAS_PIT3_CLK) 2076 PIT3_CLK = CLOCK_IP_HAS_PIT3_CLK, 2077 #endif 2078 #if defined(CLOCK_IP_HAS_PIT4_CLK) 2079 PIT4_CLK = CLOCK_IP_HAS_PIT4_CLK, 2080 #endif 2081 #if defined(CLOCK_IP_HAS_PIT5_CLK) 2082 PIT5_CLK = CLOCK_IP_HAS_PIT5_CLK, 2083 #endif 2084 #if defined(CLOCK_IP_HAS_PORTA_CLK) 2085 PORTA_CLK = CLOCK_IP_HAS_PORTA_CLK, 2086 #endif 2087 #if defined(CLOCK_IP_HAS_PORTB_CLK) 2088 PORTB_CLK = CLOCK_IP_HAS_PORTB_CLK, 2089 #endif 2090 #if defined(CLOCK_IP_HAS_PORTC_CLK) 2091 PORTC_CLK = CLOCK_IP_HAS_PORTC_CLK, 2092 #endif 2093 #if defined(CLOCK_IP_HAS_PORTD_CLK) 2094 PORTD_CLK = CLOCK_IP_HAS_PORTD_CLK, 2095 #endif 2096 #if defined(CLOCK_IP_HAS_PORTE_CLK) 2097 PORTE_CLK = CLOCK_IP_HAS_PORTE_CLK, 2098 #endif 2099 #if defined(CLOCK_IP_HAS_PSI5_0_CLK) 2100 PSI5_0_CLK = CLOCK_IP_HAS_PSI5_0_CLK, 2101 #endif 2102 #if defined(CLOCK_IP_HAS_PSI5_1_CLK) 2103 PSI5_1_CLK = CLOCK_IP_HAS_PSI5_1_CLK, 2104 #endif 2105 #if defined(CLOCK_IP_HAS_PSI5S_0_CLK) 2106 PSI5S_0_CLK = CLOCK_IP_HAS_PSI5S_0_CLK, 2107 #endif 2108 #if defined(CLOCK_IP_HAS_PSI5S_1_CLK) 2109 PSI5S_1_CLK = CLOCK_IP_HAS_PSI5S_1_CLK, 2110 #endif 2111 #if defined(CLOCK_IP_HAS_QSPI_CLK) 2112 QSPI_CLK = CLOCK_IP_HAS_QSPI_CLK, 2113 #endif 2114 #if defined(CLOCK_IP_HAS_QSPI_SFIF_CLK_HYP_PREMUX_CLK) 2115 QSPI_SFIF_CLK_HYP_PREMUX_CLK = CLOCK_IP_HAS_QSPI_SFIF_CLK_HYP_PREMUX_CLK, 2116 #endif 2117 #if defined(CLOCK_IP_HAS_QSPI_SFIF_CLK) 2118 QSPI_SFIF_CLK = CLOCK_IP_HAS_QSPI_SFIF_CLK, 2119 #endif 2120 #if defined(CLOCK_IP_HAS_QSPI_2xSFIF_CLK) 2121 QSPI_2xSFIF_CLK = CLOCK_IP_HAS_QSPI_2xSFIF_CLK, 2122 #endif 2123 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 2124 QSPI_2XSFIF_CLK = CLOCK_IP_HAS_QSPI_2XSFIF_CLK, 2125 #endif 2126 #if defined(CLOCK_IP_HAS_QSPI_2X_CLK) 2127 QSPI_2X_CLK = CLOCK_IP_HAS_QSPI_2X_CLK, 2128 #endif 2129 #if defined(CLOCK_IP_HAS_QSPI_1X_CLK) 2130 QSPI_1X_CLK = CLOCK_IP_HAS_QSPI_1X_CLK, 2131 #endif 2132 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) 2133 QSPI_SFCK_CLK = CLOCK_IP_HAS_QSPI_SFCK_CLK, 2134 #endif 2135 #if defined(CLOCK_IP_HAS_QSPI0_CLK) 2136 QSPI0_CLK = CLOCK_IP_HAS_QSPI0_CLK, 2137 #endif 2138 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK) 2139 QSPI0_RAM_CLK = CLOCK_IP_HAS_QSPI0_RAM_CLK, 2140 #endif 2141 #if defined(CLOCK_IP_HAS_QSPI0_SFCK_CLK) 2142 QSPI0_SFCK_CLK = CLOCK_IP_HAS_QSPI0_SFCK_CLK, 2143 #endif 2144 #if defined(CLOCK_IP_HAS_QSPI0_TX_MEM_CLK) 2145 QSPI0_TX_MEM_CLK = CLOCK_IP_HAS_QSPI0_TX_MEM_CLK, 2146 #endif 2147 #if defined(CLOCK_IP_HAS_QSPI1_CLK) 2148 QSPI1_CLK = CLOCK_IP_HAS_QSPI1_CLK, 2149 #endif 2150 #if defined(CLOCK_IP_HAS_P0_CLKOUT_SRC_CLK) 2151 P0_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P0_CLKOUT_SRC_CLK, 2152 #endif 2153 #if defined(CLOCK_IP_HAS_P0_CTU_PER_CLK) 2154 P0_CTU_PER_CLK = CLOCK_IP_HAS_P0_CTU_PER_CLK, 2155 #endif 2156 #if defined(CLOCK_IP_HAS_P0_DSPI_CLK) 2157 P0_DSPI_CLK = CLOCK_IP_HAS_P0_DSPI_CLK, 2158 #endif 2159 #if defined(CLOCK_IP_HAS_P0_DSPI_MSC_CLK) 2160 P0_DSPI_MSC_CLK = CLOCK_IP_HAS_P0_DSPI_MSC_CLK, 2161 #endif 2162 #if defined(CLOCK_IP_HAS_P0_EMIOS_LCU_CLK) 2163 P0_EMIOS_LCU_CLK = CLOCK_IP_HAS_P0_EMIOS_LCU_CLK, 2164 #endif 2165 #if defined(CLOCK_IP_HAS_P0_FR_PE_CLK) 2166 P0_FR_PE_CLK = CLOCK_IP_HAS_P0_FR_PE_CLK, 2167 #endif 2168 #if defined(CLOCK_IP_HAS_P0_GTM_CLK) 2169 P0_GTM_CLK = CLOCK_IP_HAS_P0_GTM_CLK, 2170 #endif 2171 #if defined(CLOCK_IP_HAS_P0_GTM_NOC_CLK) 2172 P0_GTM_NOC_CLK = CLOCK_IP_HAS_P0_GTM_NOC_CLK, 2173 #endif 2174 #if defined(CLOCK_IP_HAS_P0_GTM_TS_CLK) 2175 P0_GTM_TS_CLK = CLOCK_IP_HAS_P0_GTM_TS_CLK, 2176 #endif 2177 #if defined(CLOCK_IP_HAS_P0_LIN_BAUD_CLK) 2178 P0_LIN_BAUD_CLK = CLOCK_IP_HAS_P0_LIN_BAUD_CLK, 2179 #endif 2180 #if defined(CLOCK_IP_HAS_P0_LIN_CLK) 2181 P0_LIN_CLK = CLOCK_IP_HAS_P0_LIN_CLK, 2182 #endif 2183 #if defined(CLOCK_IP_HAS_P0_NANO_CLK) 2184 P0_NANO_CLK = CLOCK_IP_HAS_P0_NANO_CLK, 2185 #endif 2186 #if defined(CLOCK_IP_HAS_P0_PSI5_125K_CLK) 2187 P0_PSI5_125K_CLK = CLOCK_IP_HAS_P0_PSI5_125K_CLK, 2188 #endif 2189 #if defined(CLOCK_IP_HAS_P0_PSI5_189K_CLK) 2190 P0_PSI5_189K_CLK = CLOCK_IP_HAS_P0_PSI5_189K_CLK, 2191 #endif 2192 #if defined(CLOCK_IP_HAS_P0_PSI5_1US_CLK) 2193 P0_PSI5_1US_CLK = CLOCK_IP_HAS_P0_PSI5_1US_CLK, 2194 #endif 2195 #if defined(CLOCK_IP_HAS_P0_PSI5_S_BAUD_CLK) 2196 P0_PSI5_S_BAUD_CLK = CLOCK_IP_HAS_P0_PSI5_S_BAUD_CLK, 2197 #endif 2198 #if defined(CLOCK_IP_HAS_P0_PSI5_S_CORE_CLK) 2199 P0_PSI5_S_CORE_CLK = CLOCK_IP_HAS_P0_PSI5_S_CORE_CLK, 2200 #endif 2201 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG0_CLK) 2202 P0_PSI5_S_TRIG0_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG0_CLK, 2203 #endif 2204 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG1_CLK) 2205 P0_PSI5_S_TRIG1_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG1_CLK, 2206 #endif 2207 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG2_CLK) 2208 P0_PSI5_S_TRIG2_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG2_CLK, 2209 #endif 2210 #if defined(CLOCK_IP_HAS_P0_PSI5_S_TRIG3_CLK) 2211 P0_PSI5_S_TRIG3_CLK = CLOCK_IP_HAS_P0_PSI5_S_TRIG3_CLK, 2212 #endif 2213 #if defined(CLOCK_IP_HAS_P0_PSI5_S_UART_CLK) 2214 P0_PSI5_S_UART_CLK = CLOCK_IP_HAS_P0_PSI5_S_UART_CLK, 2215 #endif 2216 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG0_CLK) 2217 P0_PSI5_S_WDOG0_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG0_CLK, 2218 #endif 2219 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG1_CLK) 2220 P0_PSI5_S_WDOG1_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG1_CLK, 2221 #endif 2222 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG2_CLK) 2223 P0_PSI5_S_WDOG2_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG2_CLK, 2224 #endif 2225 #if defined(CLOCK_IP_HAS_P0_PSI5_S_WDOG3_CLK) 2226 P0_PSI5_S_WDOG3_CLK = CLOCK_IP_HAS_P0_PSI5_S_WDOG3_CLK, 2227 #endif 2228 #if defined(CLOCK_IP_HAS_P0_REG_INTF_2X_CLK) 2229 P0_REG_INTF_2X_CLK = CLOCK_IP_HAS_P0_REG_INTF_2X_CLK, 2230 #endif 2231 #if defined(CLOCK_IP_HAS_P0_REG_INTF_CLK) 2232 P0_REG_INTF_CLK = CLOCK_IP_HAS_P0_REG_INTF_CLK, 2233 #endif 2234 #if defined(CLOCK_IP_HAS_P1_CLKOUT_SRC_CLK) 2235 P1_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P1_CLKOUT_SRC_CLK, 2236 #endif 2237 #if defined(CLOCK_IP_HAS_P1_DSPI_CLK) 2238 P1_DSPI_CLK = CLOCK_IP_HAS_P1_DSPI_CLK, 2239 #endif 2240 #if defined(CLOCK_IP_HAS_P1_DSPI60_CLK) 2241 P1_DSPI60_CLK = CLOCK_IP_HAS_P1_DSPI60_CLK, 2242 #endif 2243 #if defined(CLOCK_IP_HAS_P1_LFAST0_REF_CLK) 2244 P1_LFAST0_REF_CLK = CLOCK_IP_HAS_P1_LFAST0_REF_CLK, 2245 #endif 2246 #if defined(CLOCK_IP_HAS_P1_LFAST1_REF_CLK) 2247 P1_LFAST1_REF_CLK = CLOCK_IP_HAS_P1_LFAST1_REF_CLK, 2248 #endif 2249 #if defined(CLOCK_IP_HAS_P1_LFAST_DFT_CLK) 2250 P1_LFAST_DFT_CLK = CLOCK_IP_HAS_P1_LFAST_DFT_CLK, 2251 #endif 2252 #if defined(CLOCK_IP_HAS_P1_NETC_AXI_CLK) 2253 P1_NETC_AXI_CLK = CLOCK_IP_HAS_P1_NETC_AXI_CLK, 2254 #endif 2255 #if defined(CLOCK_IP_HAS_P1_LIN_BAUD_CLK) 2256 P1_LIN_BAUD_CLK = CLOCK_IP_HAS_P1_LIN_BAUD_CLK, 2257 #endif 2258 #if defined(CLOCK_IP_HAS_P1_LIN_CLK) 2259 P1_LIN_CLK = CLOCK_IP_HAS_P1_LIN_CLK, 2260 #endif 2261 #if defined(CLOCK_IP_HAS_ETH_TS_CLK) 2262 ETH_TS_CLK = CLOCK_IP_HAS_ETH_TS_CLK, 2263 #endif 2264 #if defined(CLOCK_IP_HAS_ETH_TS_DIV4_CLK) 2265 ETH_TS_DIV4_CLK = CLOCK_IP_HAS_ETH_TS_DIV4_CLK, 2266 #endif 2267 #if defined(CLOCK_IP_HAS_ETH0_REF_RMII_CLK) 2268 ETH0_REF_RMII_CLK = CLOCK_IP_HAS_ETH0_REF_RMII_CLK, 2269 #endif 2270 #if defined(CLOCK_IP_HAS_ETH0_RX_MII_CLK) 2271 ETH0_RX_MII_CLK = CLOCK_IP_HAS_ETH0_RX_MII_CLK, 2272 #endif 2273 #if defined(CLOCK_IP_HAS_ETH0_RX_RGMII_CLK) 2274 ETH0_RX_RGMII_CLK = CLOCK_IP_HAS_ETH0_RX_RGMII_CLK, 2275 #endif 2276 #if defined(CLOCK_IP_HAS_ETH0_TX_MII_CLK) 2277 ETH0_TX_MII_CLK = CLOCK_IP_HAS_ETH0_TX_MII_CLK, 2278 #endif 2279 #if defined(CLOCK_IP_HAS_ETH0_TX_RGMII_CLK) 2280 ETH0_TX_RGMII_CLK = CLOCK_IP_HAS_ETH0_TX_RGMII_CLK, 2281 #endif 2282 #if defined(CLOCK_IP_HAS_ETH0_TX_RGMII_LPBK_CLK) 2283 ETH0_TX_RGMII_LPBK_CLK = CLOCK_IP_HAS_ETH0_TX_RGMII_LPBK_CLK, 2284 #endif 2285 #if defined(CLOCK_IP_HAS_ETH1_REF_RMII_CLK) 2286 ETH1_REF_RMII_CLK = CLOCK_IP_HAS_ETH1_REF_RMII_CLK, 2287 #endif 2288 #if defined(CLOCK_IP_HAS_ETH1_RX_MII_CLK) 2289 ETH1_RX_MII_CLK = CLOCK_IP_HAS_ETH1_RX_MII_CLK, 2290 #endif 2291 #if defined(CLOCK_IP_HAS_ETH1_RX_RGMII_CLK) 2292 ETH1_RX_RGMII_CLK = CLOCK_IP_HAS_ETH1_RX_RGMII_CLK, 2293 #endif 2294 #if defined(CLOCK_IP_HAS_ETH1_TX_MII_CLK) 2295 ETH1_TX_MII_CLK = CLOCK_IP_HAS_ETH1_TX_MII_CLK, 2296 #endif 2297 #if defined(CLOCK_IP_HAS_ETH1_TX_RGMII_CLK) 2298 ETH1_TX_RGMII_CLK = CLOCK_IP_HAS_ETH1_TX_RGMII_CLK, 2299 #endif 2300 #if defined(CLOCK_IP_HAS_ETH1_TX_RGMII_LPBK_CLK) 2301 ETH1_TX_RGMII_LPBK_CLK = CLOCK_IP_HAS_ETH1_TX_RGMII_LPBK_CLK, 2302 #endif 2303 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK) 2304 ETPU_AB_REGISTERS_CLK = CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK, 2305 #endif 2306 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK) 2307 ETPU_CODE_RAM1_CLK = CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK, 2308 #endif 2309 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK) 2310 ETPU_CODE_RAM2_CLK = CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK, 2311 #endif 2312 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK) 2313 ETPU_RAM_MIRROR_CLK = CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK, 2314 #endif 2315 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK) 2316 ETPU_RAM_SDM_CLK = CLOCK_IP_HAS_ETPU_RAM_SDM_CLK, 2317 #endif 2318 #if defined(CLOCK_IP_HAS_P1_REG_INTF_CLK) 2319 P1_REG_INTF_CLK = CLOCK_IP_HAS_P1_REG_INTF_CLK, 2320 #endif 2321 #if defined(CLOCK_IP_HAS_P2_DBG_ATB_CLK) 2322 P2_DBG_ATB_CLK = CLOCK_IP_HAS_P2_DBG_ATB_CLK, 2323 #endif 2324 #if defined(CLOCK_IP_HAS_P2_REG_INTF_CLK) 2325 P2_REG_INTF_CLK = CLOCK_IP_HAS_P2_REG_INTF_CLK, 2326 #endif 2327 #if defined(CLOCK_IP_HAS_P3_AES_CLK) 2328 P3_AES_CLK = CLOCK_IP_HAS_P3_AES_CLK, 2329 #endif 2330 #if defined(CLOCK_IP_HAS_P3_CAN_PE_CLK) 2331 P3_CAN_PE_CLK = CLOCK_IP_HAS_P3_CAN_PE_CLK, 2332 #endif 2333 #if defined(CLOCK_IP_HAS_P3_CLKOUT_SRC_CLK) 2334 P3_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P3_CLKOUT_SRC_CLK, 2335 #endif 2336 #if defined(CLOCK_IP_HAS_P3_DBG_TS_CLK) 2337 P3_DBG_TS_CLK = CLOCK_IP_HAS_P3_DBG_TS_CLK, 2338 #endif 2339 #if defined(CLOCK_IP_HAS_P3_REG_INTF_CLK) 2340 P3_REG_INTF_CLK = CLOCK_IP_HAS_P3_REG_INTF_CLK, 2341 #endif 2342 #if defined(CLOCK_IP_HAS_P3_SYS_MON1_CLK) 2343 P3_SYS_MON1_CLK = CLOCK_IP_HAS_P3_SYS_MON1_CLK, 2344 #endif 2345 #if defined(CLOCK_IP_HAS_P3_SYS_MON2_CLK) 2346 P3_SYS_MON2_CLK = CLOCK_IP_HAS_P3_SYS_MON2_CLK, 2347 #endif 2348 #if defined(CLOCK_IP_HAS_P3_SYS_MON3_CLK) 2349 P3_SYS_MON3_CLK = CLOCK_IP_HAS_P3_SYS_MON3_CLK, 2350 #endif 2351 #if defined(CLOCK_IP_HAS_P4_CLKOUT_SRC_CLK) 2352 P4_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P4_CLKOUT_SRC_CLK, 2353 #endif 2354 #if defined(CLOCK_IP_HAS_P4_DSPI_CLK) 2355 P4_DSPI_CLK = CLOCK_IP_HAS_P4_DSPI_CLK, 2356 #endif 2357 #if defined(CLOCK_IP_HAS_P4_DSPI60_CLK) 2358 P4_DSPI60_CLK = CLOCK_IP_HAS_P4_DSPI60_CLK, 2359 #endif 2360 #if defined(CLOCK_IP_HAS_P4_EMIOS_LCU_CLK) 2361 P4_EMIOS_LCU_CLK = CLOCK_IP_HAS_P4_EMIOS_LCU_CLK, 2362 #endif 2363 #if defined(CLOCK_IP_HAS_P4_LIN_BAUD_CLK) 2364 P4_LIN_BAUD_CLK = CLOCK_IP_HAS_P4_LIN_BAUD_CLK, 2365 #endif 2366 #if defined(CLOCK_IP_HAS_P4_LIN_CLK) 2367 P4_LIN_CLK = CLOCK_IP_HAS_P4_LIN_CLK, 2368 #endif 2369 #if defined(CLOCK_IP_HAS_P4_PSI5_125K_CLK) 2370 P4_PSI5_125K_CLK = CLOCK_IP_HAS_P4_PSI5_125K_CLK, 2371 #endif 2372 #if defined(CLOCK_IP_HAS_P4_PSI5_189K_CLK) 2373 P4_PSI5_189K_CLK = CLOCK_IP_HAS_P4_PSI5_189K_CLK, 2374 #endif 2375 #if defined(CLOCK_IP_HAS_P4_PSI5_1US_CLK) 2376 P4_PSI5_1US_CLK = CLOCK_IP_HAS_P4_PSI5_1US_CLK, 2377 #endif 2378 #if defined(CLOCK_IP_HAS_P4_PSI5_S_BAUD_CLK) 2379 P4_PSI5_S_BAUD_CLK = CLOCK_IP_HAS_P4_PSI5_S_BAUD_CLK, 2380 #endif 2381 #if defined(CLOCK_IP_HAS_P4_PSI5_S_CORE_CLK) 2382 P4_PSI5_S_CORE_CLK = CLOCK_IP_HAS_P4_PSI5_S_CORE_CLK, 2383 #endif 2384 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG0_CLK) 2385 P4_PSI5_S_TRIG0_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG0_CLK, 2386 #endif 2387 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG1_CLK) 2388 P4_PSI5_S_TRIG1_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG1_CLK, 2389 #endif 2390 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG2_CLK) 2391 P4_PSI5_S_TRIG2_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG2_CLK, 2392 #endif 2393 #if defined(CLOCK_IP_HAS_P4_PSI5_S_TRIG3_CLK) 2394 P4_PSI5_S_TRIG3_CLK = CLOCK_IP_HAS_P4_PSI5_S_TRIG3_CLK, 2395 #endif 2396 #if defined(CLOCK_IP_HAS_P4_PSI5_S_UART_CLK) 2397 P4_PSI5_S_UART_CLK = CLOCK_IP_HAS_P4_PSI5_S_UART_CLK, 2398 #endif 2399 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG0_CLK) 2400 P4_PSI5_S_WDOG0_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG0_CLK, 2401 #endif 2402 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG1_CLK) 2403 P4_PSI5_S_WDOG1_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG1_CLK, 2404 #endif 2405 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG2_CLK) 2406 P4_PSI5_S_WDOG2_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG2_CLK, 2407 #endif 2408 #if defined(CLOCK_IP_HAS_P4_PSI5_S_WDOG3_CLK) 2409 P4_PSI5_S_WDOG3_CLK = CLOCK_IP_HAS_P4_PSI5_S_WDOG3_CLK, 2410 #endif 2411 #if defined(CLOCK_IP_HAS_P4_QSPI0_2X_CLK) 2412 P4_QSPI0_2X_CLK = CLOCK_IP_HAS_P4_QSPI0_2X_CLK, 2413 #endif 2414 #if defined(CLOCK_IP_HAS_P4_QSPI0_1X_CLK) 2415 P4_QSPI0_1X_CLK = CLOCK_IP_HAS_P4_QSPI0_1X_CLK, 2416 #endif 2417 #if defined(CLOCK_IP_HAS_P4_QSPI1_2X_CLK) 2418 P4_QSPI1_2X_CLK = CLOCK_IP_HAS_P4_QSPI1_2X_CLK, 2419 #endif 2420 #if defined(CLOCK_IP_HAS_P4_QSPI1_1X_CLK) 2421 P4_QSPI1_1X_CLK = CLOCK_IP_HAS_P4_QSPI1_1X_CLK, 2422 #endif 2423 #if defined(CLOCK_IP_HAS_P4_REG_INTF_2X_CLK) 2424 P4_REG_INTF_2X_CLK = CLOCK_IP_HAS_P4_REG_INTF_2X_CLK, 2425 #endif 2426 #if defined(CLOCK_IP_HAS_P4_REG_INTF_CLK) 2427 P4_REG_INTF_CLK = CLOCK_IP_HAS_P4_REG_INTF_CLK, 2428 #endif 2429 #if defined(CLOCK_IP_HAS_P4_SDHC_CLK) 2430 P4_SDHC_CLK = CLOCK_IP_HAS_P4_SDHC_CLK, 2431 #endif 2432 #if defined(CLOCK_IP_HAS_P4_SDHC_IP_CLK) 2433 P4_SDHC_IP_CLK = CLOCK_IP_HAS_P4_SDHC_IP_CLK, 2434 #endif 2435 #if defined(CLOCK_IP_HAS_P4_SDHC_IP_DIV2_CLK) 2436 P4_SDHC_IP_DIV2_CLK = CLOCK_IP_HAS_P4_SDHC_IP_DIV2_CLK, 2437 #endif 2438 #if defined(CLOCK_IP_HAS_P5_AE_CLK) 2439 P5_AE_CLK = CLOCK_IP_HAS_P5_AE_CLK, 2440 #endif 2441 #if defined(CLOCK_IP_HAS_P5_CANXL_PE_CLK) 2442 P5_CANXL_PE_CLK = CLOCK_IP_HAS_P5_CANXL_PE_CLK, 2443 #endif 2444 #if defined(CLOCK_IP_HAS_P5_CANXL_CHI_CLK) 2445 P5_CANXL_CHI_CLK = CLOCK_IP_HAS_P5_CANXL_CHI_CLK, 2446 #endif 2447 #if defined(CLOCK_IP_HAS_P5_CLKOUT_SRC_CLK) 2448 P5_CLKOUT_SRC_CLK = CLOCK_IP_HAS_P5_CLKOUT_SRC_CLK, 2449 #endif 2450 #if defined(CLOCK_IP_HAS_P5_DSPI_CLK) 2451 P5_DSPI_CLK = CLOCK_IP_HAS_P5_DSPI_CLK, 2452 #endif 2453 #if defined(CLOCK_IP_HAS_P5_DIPORT_CLK) 2454 P5_DIPORT_CLK = CLOCK_IP_HAS_P5_DIPORT_CLK, 2455 #endif 2456 #if defined(CLOCK_IP_HAS_P5_LIN_BAUD_CLK) 2457 P5_LIN_BAUD_CLK = CLOCK_IP_HAS_P5_LIN_BAUD_CLK, 2458 #endif 2459 #if defined(CLOCK_IP_HAS_P5_LIN_CLK) 2460 P5_LIN_CLK = CLOCK_IP_HAS_P5_LIN_CLK, 2461 #endif 2462 #if defined(CLOCK_IP_HAS_P5_REG_INTF_CLK) 2463 P5_REG_INTF_CLK = CLOCK_IP_HAS_P5_REG_INTF_CLK, 2464 #endif 2465 #if defined(CLOCK_IP_HAS_P6_REG_INTF_CLK) 2466 P6_REG_INTF_CLK = CLOCK_IP_HAS_P6_REG_INTF_CLK, 2467 #endif 2468 #if defined(CLOCK_IP_HAS_RTU0_REG_INTF_CLK) 2469 RTU0_REG_INTF_CLK = CLOCK_IP_HAS_RTU0_REG_INTF_CLK, 2470 #endif 2471 #if defined(CLOCK_IP_HAS_RTU0_CORE_MON1_CLK) 2472 RTU0_CORE_MON1_CLK = CLOCK_IP_HAS_RTU0_CORE_MON1_CLK, 2473 #endif 2474 #if defined(CLOCK_IP_HAS_RTU0_CORE_MON2_CLK) 2475 RTU0_CORE_MON2_CLK = CLOCK_IP_HAS_RTU0_CORE_MON2_CLK, 2476 #endif 2477 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_MON1_CLK) 2478 RTU0_CORE_DIV2_MON1_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_MON1_CLK, 2479 #endif 2480 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_MON2_CLK) 2481 RTU0_CORE_DIV2_MON2_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_MON2_CLK, 2482 #endif 2483 #if defined(CLOCK_IP_HAS_RTU0_CORE_DIV2_MON3_CLK) 2484 RTU0_CORE_DIV2_MON3_CLK = CLOCK_IP_HAS_RTU0_CORE_DIV2_MON3_CLK, 2485 #endif 2486 #if defined(CLOCK_IP_HAS_RTU1_REG_INTF_CLK) 2487 RTU1_REG_INTF_CLK = CLOCK_IP_HAS_RTU1_REG_INTF_CLK, 2488 #endif 2489 #if defined(CLOCK_IP_HAS_RTU1_CORE_MON1_CLK) 2490 RTU1_CORE_MON1_CLK = CLOCK_IP_HAS_RTU1_CORE_MON1_CLK, 2491 #endif 2492 #if defined(CLOCK_IP_HAS_RTU1_CORE_MON2_CLK) 2493 RTU1_CORE_MON2_CLK = CLOCK_IP_HAS_RTU1_CORE_MON2_CLK, 2494 #endif 2495 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_MON1_CLK) 2496 RTU1_CORE_DIV2_MON1_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_MON1_CLK, 2497 #endif 2498 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_MON2_CLK) 2499 RTU1_CORE_DIV2_MON2_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_MON2_CLK, 2500 #endif 2501 #if defined(CLOCK_IP_HAS_RTU1_CORE_DIV2_MON3_CLK) 2502 RTU1_CORE_DIV2_MON3_CLK = CLOCK_IP_HAS_RTU1_CORE_DIV2_MON3_CLK, 2503 #endif 2504 #if defined(CLOCK_IP_HAS_RFE_PLL_CLK) 2505 RFE_PLL_CLK = CLOCK_IP_HAS_RFE_PLL_CLK, 2506 #endif 2507 #if defined(CLOCK_IP_HAS_RTC_CLK) 2508 RTC_CLK = CLOCK_IP_HAS_RTC_CLK, 2509 #endif 2510 #if defined(CLOCK_IP_HAS_RTC0_CLK) 2511 RTC0_CLK = CLOCK_IP_HAS_RTC0_CLK, 2512 #endif 2513 #if defined(CLOCK_IP_HAS_RTC_EXT_REF_CLK) 2514 RTC_EXT_REF_CLK = CLOCK_IP_HAS_RTC_EXT_REF_CLK, 2515 #endif 2516 #if defined(CLOCK_IP_HAS_RXLUT_CLK) 2517 RXLUT_CLK = CLOCK_IP_HAS_RXLUT_CLK, 2518 #endif 2519 #if defined(CLOCK_IP_HAS_SAI0_CLK) 2520 SAI0_CLK = CLOCK_IP_HAS_SAI0_CLK, 2521 #endif 2522 #if defined(CLOCK_IP_HAS_SAI1_CLK) 2523 SAI1_CLK = CLOCK_IP_HAS_SAI1_CLK, 2524 #endif 2525 #if defined(CLOCK_IP_HAS_SDHC0_CLK) 2526 SDHC0_CLK = CLOCK_IP_HAS_SDHC0_CLK, 2527 #endif 2528 #if defined(CLOCK_IP_HAS_SEMA42_CLK) 2529 SEMA42_CLK = CLOCK_IP_HAS_SEMA42_CLK, 2530 #endif 2531 #if defined(CLOCK_IP_HAS_SIPI0_CLK) 2532 SIPI0_CLK = CLOCK_IP_HAS_SIPI0_CLK, 2533 #endif 2534 #if defined(CLOCK_IP_HAS_SIPI1_CLK) 2535 SIPI1_CLK = CLOCK_IP_HAS_SIPI1_CLK, 2536 #endif 2537 #if defined(CLOCK_IP_HAS_SINC_CLK) 2538 SINC_CLK = CLOCK_IP_HAS_SINC_CLK, 2539 #endif 2540 #if defined(CLOCK_IP_HAS_SIUL0_CLK) 2541 SIUL0_CLK = CLOCK_IP_HAS_SIUL0_CLK, 2542 #endif 2543 #if defined(CLOCK_IP_HAS_SIUL1_CLK) 2544 SIUL1_CLK = CLOCK_IP_HAS_SIUL1_CLK, 2545 #endif 2546 #if defined(CLOCK_IP_HAS_SIUL2_0_CLK) 2547 SIUL2_0_CLK = CLOCK_IP_HAS_SIUL2_0_CLK, 2548 #endif 2549 #if defined(CLOCK_IP_HAS_SIUL2_1_CLK) 2550 SIUL2_1_CLK = CLOCK_IP_HAS_SIUL2_1_CLK, 2551 #endif 2552 #if defined(CLOCK_IP_HAS_SIUL2_4_CLK) 2553 SIUL2_4_CLK = CLOCK_IP_HAS_SIUL2_4_CLK, 2554 #endif 2555 #if defined(CLOCK_IP_HAS_SIUL2_5_CLK) 2556 SIUL2_5_CLK = CLOCK_IP_HAS_SIUL2_5_CLK, 2557 #endif 2558 #if defined(CLOCK_IP_HAS_SPI_CLK) 2559 SPI_CLK = CLOCK_IP_HAS_SPI_CLK, 2560 #endif 2561 #if defined(CLOCK_IP_HAS_SPI0_CLK) 2562 SPI0_CLK = CLOCK_IP_HAS_SPI0_CLK, 2563 #endif 2564 #if defined(CLOCK_IP_HAS_SPI1_CLK) 2565 SPI1_CLK = CLOCK_IP_HAS_SPI1_CLK, 2566 #endif 2567 #if defined(CLOCK_IP_HAS_SPI2_CLK) 2568 SPI2_CLK = CLOCK_IP_HAS_SPI2_CLK, 2569 #endif 2570 #if defined(CLOCK_IP_HAS_SPI3_CLK) 2571 SPI3_CLK = CLOCK_IP_HAS_SPI3_CLK, 2572 #endif 2573 #if defined(CLOCK_IP_HAS_SPI4_CLK) 2574 SPI4_CLK = CLOCK_IP_HAS_SPI4_CLK, 2575 #endif 2576 #if defined(CLOCK_IP_HAS_SPI5_CLK) 2577 SPI5_CLK = CLOCK_IP_HAS_SPI5_CLK, 2578 #endif 2579 #if defined(CLOCK_IP_HAS_SPI6_CLK) 2580 SPI6_CLK = CLOCK_IP_HAS_SPI6_CLK, 2581 #endif 2582 #if defined(CLOCK_IP_HAS_SPI7_CLK) 2583 SPI7_CLK = CLOCK_IP_HAS_SPI7_CLK, 2584 #endif 2585 #if defined(CLOCK_IP_HAS_SPI8_CLK) 2586 SPI8_CLK = CLOCK_IP_HAS_SPI8_CLK, 2587 #endif 2588 #if defined(CLOCK_IP_HAS_SPI9_CLK) 2589 SPI9_CLK = CLOCK_IP_HAS_SPI9_CLK, 2590 #endif 2591 #if defined(CLOCK_IP_HAS_SRX0_CLK) 2592 SRX0_CLK = CLOCK_IP_HAS_SRX0_CLK, 2593 #endif 2594 #if defined(CLOCK_IP_HAS_SRX1_CLK) 2595 SRX1_CLK = CLOCK_IP_HAS_SRX1_CLK, 2596 #endif 2597 #if defined(CLOCK_IP_HAS_STCU0_CLK) 2598 STCU0_CLK = CLOCK_IP_HAS_STCU0_CLK, 2599 #endif 2600 #if defined(CLOCK_IP_HAS_STM0_CLK) 2601 STM0_CLK = CLOCK_IP_HAS_STM0_CLK, 2602 #endif 2603 #if defined(CLOCK_IP_HAS_STM1_CLK) 2604 STM1_CLK = CLOCK_IP_HAS_STM1_CLK, 2605 #endif 2606 #if defined(CLOCK_IP_HAS_STM2_CLK) 2607 STM2_CLK = CLOCK_IP_HAS_STM2_CLK, 2608 #endif 2609 #if defined(CLOCK_IP_HAS_STM3_CLK) 2610 STM3_CLK = CLOCK_IP_HAS_STM3_CLK, 2611 #endif 2612 #if defined(CLOCK_IP_HAS_STM4_CLK) 2613 STM4_CLK = CLOCK_IP_HAS_STM4_CLK, 2614 #endif 2615 #if defined(CLOCK_IP_HAS_STM5_CLK) 2616 STM5_CLK = CLOCK_IP_HAS_STM5_CLK, 2617 #endif 2618 #if defined(CLOCK_IP_HAS_STM6_CLK) 2619 STM6_CLK = CLOCK_IP_HAS_STM6_CLK, 2620 #endif 2621 #if defined(CLOCK_IP_HAS_STM7_CLK) 2622 STM7_CLK = CLOCK_IP_HAS_STM7_CLK, 2623 #endif 2624 #if defined(CLOCK_IP_HAS_STMA_CLK) 2625 STMA_CLK = CLOCK_IP_HAS_STMA_CLK, 2626 #endif 2627 #if defined(CLOCK_IP_HAS_STMB_CLK) 2628 STMB_CLK = CLOCK_IP_HAS_STMB_CLK, 2629 #endif 2630 #if defined(CLOCK_IP_HAS_STMC_CLK) 2631 STMC_CLK = CLOCK_IP_HAS_STMC_CLK, 2632 #endif 2633 #if defined(CLOCK_IP_HAS_STMD_CLK) 2634 STMD_CLK = CLOCK_IP_HAS_STMD_CLK, 2635 #endif 2636 #if defined(CLOCK_IP_HAS_SWG_CLK) 2637 SWG_CLK = CLOCK_IP_HAS_SWG_CLK, 2638 #endif 2639 #if defined(CLOCK_IP_HAS_SWG0_CLK) 2640 SWG0_CLK = CLOCK_IP_HAS_SWG0_CLK, 2641 #endif 2642 #if defined(CLOCK_IP_HAS_SWG1_CLK) 2643 SWG1_CLK = CLOCK_IP_HAS_SWG1_CLK, 2644 #endif 2645 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK) 2646 SWG_PAD_CLK = CLOCK_IP_HAS_SWG_PAD_CLK, 2647 #endif 2648 #if defined(CLOCK_IP_HAS_SWT0_CLK) 2649 SWT0_CLK = CLOCK_IP_HAS_SWT0_CLK, 2650 #endif 2651 #if defined(CLOCK_IP_HAS_SWT1_CLK) 2652 SWT1_CLK = CLOCK_IP_HAS_SWT1_CLK, 2653 #endif 2654 #if defined(CLOCK_IP_HAS_SWT2_CLK) 2655 SWT2_CLK = CLOCK_IP_HAS_SWT2_CLK, 2656 #endif 2657 #if defined(CLOCK_IP_HAS_SWT3_CLK) 2658 SWT3_CLK = CLOCK_IP_HAS_SWT3_CLK, 2659 #endif 2660 #if defined(CLOCK_IP_HAS_SWT4_CLK) 2661 SWT4_CLK = CLOCK_IP_HAS_SWT4_CLK, 2662 #endif 2663 #if defined(CLOCK_IP_HAS_SWT5_CLK) 2664 SWT5_CLK = CLOCK_IP_HAS_SWT5_CLK, 2665 #endif 2666 #if defined(CLOCK_IP_HAS_SWT6_CLK) 2667 SWT6_CLK = CLOCK_IP_HAS_SWT6_CLK, 2668 #endif 2669 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK) 2670 TCM_CM7_0_CLK = CLOCK_IP_HAS_TCM_CM7_0_CLK, 2671 #endif 2672 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK) 2673 TCM_CM7_1_CLK = CLOCK_IP_HAS_TCM_CM7_1_CLK, 2674 #endif 2675 #if defined(CLOCK_IP_HAS_TEMPSENSE_CLK) 2676 TEMPSENSE_CLK = CLOCK_IP_HAS_TEMPSENSE_CLK, 2677 #endif 2678 #if defined(CLOCK_IP_HAS_TIMER_CLK) 2679 TIMER_CLK = CLOCK_IP_HAS_TIMER_CLK, 2680 #endif 2681 #if defined(CLOCK_IP_HAS_ENET0_TIME_CLK) 2682 ENET0_TIME_CLK = CLOCK_IP_HAS_ENET0_TIME_CLK, 2683 #endif 2684 #if defined(CLOCK_IP_HAS_TRACE_CLK) 2685 TRACE_CLK = CLOCK_IP_HAS_TRACE_CLK, 2686 #endif 2687 #if defined(CLOCK_IP_HAS_TRGMUX0_CLK) 2688 TRGMUX0_CLK = CLOCK_IP_HAS_TRGMUX0_CLK, 2689 #endif 2690 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK) 2691 TRGMUX1_CLK = CLOCK_IP_HAS_TRGMUX1_CLK, 2692 #endif 2693 #if defined(CLOCK_IP_HAS_TSENSE0_CLK) 2694 TSENSE0_CLK = CLOCK_IP_HAS_TSENSE0_CLK, 2695 #endif 2696 #if defined(CLOCK_IP_HAS_SDHC_CLK) 2697 SDHC_CLK = CLOCK_IP_HAS_SDHC_CLK, 2698 #endif 2699 #if defined(CLOCK_IP_HAS_USDHC_CLK) 2700 USDHC_CLK = CLOCK_IP_HAS_USDHC_CLK, 2701 #endif 2702 #if defined(CLOCK_IP_HAS_USDHC0_CLK) 2703 USDHC0_CLK = CLOCK_IP_HAS_USDHC0_CLK, 2704 #endif 2705 #if defined(CLOCK_IP_HAS_WKPU0_CLK) 2706 WKPU0_CLK = CLOCK_IP_HAS_WKPU0_CLK, 2707 #endif 2708 #if defined(CLOCK_IP_HAS_XBAR_DIV3_FAIL_CLK) 2709 XBAR_DIV3_FAIL_CLK = CLOCK_IP_HAS_XBAR_DIV3_FAIL_CLK, 2710 #endif 2711 #if defined(CLOCK_IP_HAS_XBAR_MIPICSI201_CLK) 2712 XBAR_MIPICSI201_CLK = CLOCK_IP_HAS_XBAR_MIPICSI201_CLK, 2713 #endif 2714 #if defined(CLOCK_IP_HAS_XBAR_MIPICSI223_CLK) 2715 XBAR_MIPICSI223_CLK = CLOCK_IP_HAS_XBAR_MIPICSI223_CLK, 2716 #endif 2717 #if defined(CLOCK_IP_HAS_BBE32EP_DSP_CLK) 2718 BBE32EP_DSP_CLK = CLOCK_IP_HAS_BBE32EP_DSP_CLK, 2719 #endif 2720 #if defined(CLOCK_IP_HAS_CAN_CHI_CLK) 2721 CAN_CHI_CLK = CLOCK_IP_HAS_CAN_CHI_CLK, 2722 #endif 2723 #if defined(CLOCK_IP_HAS_CAN_TS_CLK) 2724 CAN_TS_CLK = CLOCK_IP_HAS_CAN_TS_CLK, 2725 #endif 2726 #if defined(CLOCK_IP_HAS_CAN0_CLK) 2727 CAN0_CLK = CLOCK_IP_HAS_CAN0_CLK, 2728 #endif 2729 #if defined(CLOCK_IP_HAS_CAN1_CLK) 2730 CAN1_CLK = CLOCK_IP_HAS_CAN1_CLK, 2731 #endif 2732 #if defined(CLOCK_IP_HAS_CRC_CLK) 2733 CRC_CLK = CLOCK_IP_HAS_CRC_CLK, 2734 #endif 2735 #if defined(CLOCK_IP_HAS_CSI_CFG_CLK) 2736 CSI_CLK = CLOCK_IP_HAS_CSI_CLK, 2737 #endif 2738 #if defined(CLOCK_IP_HAS_CSI_CFG_CLK) 2739 CSI_CFG_CLK = CLOCK_IP_HAS_CSI_CFG_CLK, 2740 #endif 2741 #if defined(CLOCK_IP_HAS_CSI_IPS_CLK) 2742 CSI_IPS_CLK = CLOCK_IP_HAS_CSI_IPS_CLK, 2743 #endif 2744 #if defined(CLOCK_IP_HAS_CSI_TXCLK_CLK) 2745 CSI_TXCLK_CLK = CLOCK_IP_HAS_CSI_TXCLK_CLK, 2746 #endif 2747 #if defined(CLOCK_IP_HAS_CTE_CLK) 2748 CTE_CLK = CLOCK_IP_HAS_CTE_CLK, 2749 #endif 2750 #if defined(CLOCK_IP_HAS_CTU_CLK) 2751 CTU_CLK = CLOCK_IP_HAS_CTU_CLK, 2752 #endif 2753 #if defined(CLOCK_IP_HAS_CTU_IPS_CLK) 2754 CTU_IPS_CLK = CLOCK_IP_HAS_CTU_IPS_CLK, 2755 #endif 2756 #if defined(CLOCK_IP_HAS_DMA_CLK) 2757 DMA_CLK = CLOCK_IP_HAS_DMA_CLK, 2758 #endif 2759 #if defined(CLOCK_IP_HAS_DMA_CRC_CLK) 2760 DMA_CRC_CLK = CLOCK_IP_HAS_DMA_CRC_CLK, 2761 #endif 2762 #if defined(CLOCK_IP_HAS_DMA_TCD_CLK) 2763 DMA_TCD_CLK = CLOCK_IP_HAS_DMA_TCD_CLK, 2764 #endif 2765 #if defined(CLOCK_IP_HAS_EIM_AP1_CLK) 2766 EIM_AP1_CLK = CLOCK_IP_HAS_EIM_AP1_CLK, 2767 #endif 2768 #if defined(CLOCK_IP_HAS_EIM_CM70_CLK) 2769 EIM_CM70_CLK = CLOCK_IP_HAS_EIM_CM70_CLK, 2770 #endif 2771 #if defined(CLOCK_IP_HAS_EIM_CM71_CLK) 2772 EIM_CM71_CLK = CLOCK_IP_HAS_EIM_CM71_CLK, 2773 #endif 2774 #if defined(CLOCK_IP_HAS_EIM_DSP_CLK) 2775 EIM_DSP_CLK = CLOCK_IP_HAS_EIM_DSP_CLK, 2776 #endif 2777 #if defined(CLOCK_IP_HAS_EIM_RT0_CLK) 2778 EIM_RT0_CLK = CLOCK_IP_HAS_EIM_RT0_CLK, 2779 #endif 2780 #if defined(CLOCK_IP_HAS_EIM_RT2_CLK) 2781 EIM_RT2_CLK = CLOCK_IP_HAS_EIM_RT2_CLK, 2782 #endif 2783 #if defined(CLOCK_IP_HAS_ERM_AP1_CLK) 2784 ERM_AP1_CLK = CLOCK_IP_HAS_ERM_AP1_CLK, 2785 #endif 2786 #if defined(CLOCK_IP_HAS_ERM_RT0_CLK) 2787 ERM_RT0_CLK = CLOCK_IP_HAS_ERM_RT0_CLK, 2788 #endif 2789 #if defined(CLOCK_IP_HAS_ERM_RT1_CLK) 2790 ERM_RT1_CLK = CLOCK_IP_HAS_ERM_RT1_CLK, 2791 #endif 2792 #if defined(CLOCK_IP_HAS_ERM_RT2_CLK) 2793 ERM_RT2_CLK = CLOCK_IP_HAS_ERM_RT2_CLK, 2794 #endif 2795 #if defined(CLOCK_IP_HAS_FCCU_IPS_CLK) 2796 FCCU_IPS_CLK = CLOCK_IP_HAS_FCCU_IPS_CLK, 2797 #endif 2798 #if defined(CLOCK_IP_HAS_SYS_M7_0_CLK) 2799 SYS_M7_0_CLK = CLOCK_IP_HAS_SYS_M7_0_CLK, 2800 #endif 2801 #if defined(CLOCK_IP_HAS_SYS_M7_1_CLK) 2802 SYS_M7_1_CLK = CLOCK_IP_HAS_SYS_M7_1_CLK, 2803 #endif 2804 #if defined(CLOCK_IP_HAS_SYS_HSE_CLK) 2805 SYS_HSE_CLK = CLOCK_IP_HAS_SYS_HSE_CLK, 2806 #endif 2807 #if defined(CLOCK_IP_HAS_MC_CLK) 2808 MC_CLK = CLOCK_IP_HAS_MC_CLK, 2809 #endif 2810 #if defined(CLOCK_IP_HAS_MIPICSI2_0_CLK) 2811 MIPICSI2_0_CLK = CLOCK_IP_HAS_MIPICSI2_0_CLK, 2812 #endif 2813 #if defined(CLOCK_IP_HAS_MIPICSI2_1_CLK) 2814 MIPICSI2_1_CLK = CLOCK_IP_HAS_MIPICSI2_1_CLK, 2815 #endif 2816 #if defined(CLOCK_IP_HAS_MSCDSPI_CLK) 2817 MSCDSPI_CLK = CLOCK_IP_HAS_MSCDSPI_CLK, 2818 #endif 2819 #if defined(CLOCK_IP_HAS_MSCLIN_CLK) 2820 MSCLIN_CLK = CLOCK_IP_HAS_MSCLIN_CLK, 2821 #endif 2822 #if defined(CLOCK_IP_HAS_NOC_TRACE_CLK) 2823 NOC_TRACE_CLK = CLOCK_IP_HAS_NOC_TRACE_CLK, 2824 #endif 2825 #if defined(CLOCK_IP_HAS_NANO_CLK) 2826 NANO_CLK = CLOCK_IP_HAS_NANO_CLK, 2827 #endif 2828 #if defined(CLOCK_IP_HAS_SAR_ADC_CLK) 2829 SAR_ADC_CLK = CLOCK_IP_HAS_SAR_ADC_CLK, 2830 #endif 2831 #if defined(CLOCK_IP_HAS_SDA_AP_CLK) 2832 SDA_AP_CLK = CLOCK_IP_HAS_SDA_AP_CLK, 2833 #endif 2834 #if defined(CLOCK_IP_HAS_SDADC0_CLK) 2835 SDADC0_CLK = CLOCK_IP_HAS_SDADC0_CLK, 2836 #endif 2837 #if defined(CLOCK_IP_HAS_SDADC1_CLK) 2838 SDADC1_CLK = CLOCK_IP_HAS_SDADC1_CLK, 2839 #endif 2840 #if defined(CLOCK_IP_HAS_SDADC2_CLK) 2841 SDADC2_CLK = CLOCK_IP_HAS_SDADC2_CLK, 2842 #endif 2843 #if defined(CLOCK_IP_HAS_SDADC3_CLK) 2844 SDADC3_CLK = CLOCK_IP_HAS_SDADC3_CLK, 2845 #endif 2846 #if defined(CLOCK_IP_HAS_SEMA42_1_CLK) 2847 SEMA42_1_CLK = CLOCK_IP_HAS_SEMA42_1_CLK, 2848 #endif 2849 #if defined(CLOCK_IP_HAS_SIUL2_CLK) 2850 SIUL2_CLK = CLOCK_IP_HAS_SIUL2_CLK, 2851 #endif 2852 #if defined(CLOCK_IP_HAS_SPT_CLK) 2853 SPT_CLK = CLOCK_IP_HAS_SPT_CLK, 2854 #endif 2855 #if defined(CLOCK_IP_HAS_SRAM_CLK) 2856 SRAM_CLK = CLOCK_IP_HAS_SRAM_CLK, 2857 #endif 2858 #if defined(CLOCK_IP_HAS_STCU_CLK) 2859 STCU_CLK = CLOCK_IP_HAS_STCU_CLK, 2860 #endif 2861 #if defined(CLOCK_IP_HAS_TMU_CLK) 2862 TMU_CLK = CLOCK_IP_HAS_TMU_CLK, 2863 #endif 2864 #if defined(CLOCK_IP_HAS_WKPU_CLK) 2865 WKPU_CLK = CLOCK_IP_HAS_WKPU_CLK, 2866 #endif 2867 #if defined(CLOCK_IP_HAS_XRDC0_CLK) 2868 XRDC0_CLK = CLOCK_IP_HAS_XRDC0_CLK, 2869 #endif 2870 #if defined(CLOCK_IP_HAS_XRDC1_CLK) 2871 XRDC1_CLK = CLOCK_IP_HAS_XRDC1_CLK, 2872 #endif 2873 #if defined(CLOCK_IP_HAS_CORE_PLL_REFCLKOUT) 2874 CORE_PLL_REFCLKOUT = CLOCK_IP_HAS_CORE_PLL_REFCLKOUT, 2875 #endif 2876 #if defined(CLOCK_IP_HAS_CORE_PLL_FBCLKOUT) 2877 CORE_PLL_FBCLKOUT = CLOCK_IP_HAS_CORE_PLL_FBCLKOUT, 2878 #endif 2879 #if defined(CLOCK_IP_HAS_PERIPH_PLL_REFCLKOUT) 2880 PERIPH_PLL_REFCLKOUT = CLOCK_IP_HAS_PERIPH_PLL_REFCLKOUT, 2881 #endif 2882 #if defined(CLOCK_IP_HAS_PERIPH_PLL_FBCLKOUT) 2883 PERIPH_PLL_FBCLKOUT = CLOCK_IP_HAS_PERIPH_PLL_FBCLKOUT, 2884 #endif 2885 #if defined(CLOCK_IP_HAS_TCLK_CLK) 2886 TCLK_CLK = CLOCK_IP_HAS_TCLK_CLK, 2887 #endif 2888 #if defined(CLOCK_IP_HAS_TCK_CLK) 2889 TCK_CLK = CLOCK_IP_HAS_TCK_CLK, 2890 #endif 2891 #if defined(CLOCK_IP_HAS_AES_CLK) 2892 AES_CLK = CLOCK_IP_HAS_AES_CLK, 2893 #endif 2894 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK) 2895 AES_ACCEL_CLK = CLOCK_IP_HAS_AES_ACCEL_CLK, 2896 #endif 2897 #if defined(CLOCK_IP_HAS_AES_APP0_CLK) 2898 AES_APP0_CLK = CLOCK_IP_HAS_AES_APP0_CLK, 2899 #endif 2900 #if defined(CLOCK_IP_HAS_AES_APP1_CLK) 2901 AES_APP1_CLK = CLOCK_IP_HAS_AES_APP1_CLK, 2902 #endif 2903 #if defined(CLOCK_IP_HAS_AES_APP2_CLK) 2904 AES_APP2_CLK = CLOCK_IP_HAS_AES_APP2_CLK, 2905 #endif 2906 #if defined(CLOCK_IP_HAS_AES_APP3_CLK) 2907 AES_APP3_CLK = CLOCK_IP_HAS_AES_APP3_CLK, 2908 #endif 2909 #if defined(CLOCK_IP_HAS_AES_APP4_CLK) 2910 AES_APP4_CLK = CLOCK_IP_HAS_AES_APP4_CLK, 2911 #endif 2912 #if defined(CLOCK_IP_HAS_AES_APP5_CLK) 2913 AES_APP5_CLK = CLOCK_IP_HAS_AES_APP5_CLK, 2914 #endif 2915 #if defined(CLOCK_IP_HAS_AES_APP6_CLK) 2916 AES_APP6_CLK = CLOCK_IP_HAS_AES_APP6_CLK, 2917 #endif 2918 #if defined(CLOCK_IP_HAS_AES_APP7_CLK) 2919 AES_APP7_CLK = CLOCK_IP_HAS_AES_APP7_CLK, 2920 #endif 2921 #if defined(CLOCK_IP_HAS_DSPI_SCK_TST_CLK) 2922 DSPI_SCK_TST_CLK = CLOCK_IP_HAS_DSPI_SCK_TST_CLK, 2923 #endif 2924 RESERVED_CLK = CLOCK_IP_FEATURE_NAMES_NO, /* Invalid clock name */ 2925 } Clock_Ip_NameType; 2926 2927 /** @brief Clock ip status return codes. */ 2928 typedef enum 2929 { 2930 CLOCK_IP_SUCCESS = 0x00U, /**< Clock tree was initialized successfully. */ 2931 CLOCK_IP_ERROR = 0x01U, /**< One of the elements timeout, clock tree couldn't be initialized. */ 2932 2933 } Clock_Ip_StatusType; 2934 2935 /** @brief Clock ip pll status return codes. */ 2936 typedef enum 2937 { 2938 CLOCK_IP_PLL_LOCKED = 0x00U, /**< PLL is locked */ 2939 CLOCK_IP_PLL_UNLOCKED = 0x01U, /**< PLL is unlocked */ 2940 CLOCK_IP_PLL_STATUS_UNDEFINED = 0x02U, /**< PLL Status is unknown */ 2941 2942 } Clock_Ip_PllStatusType; 2943 2944 /** @brief Clock ip cmu status return codes. */ 2945 typedef enum 2946 { 2947 CLOCK_IP_CMU_IN_RANGE = 0x00U, /**< Frequency is in range */ 2948 CLOCK_IP_CMU_HIGH_FREQ = 0x01U, /**< Frequency is higher than high limit */ 2949 CLOCK_IP_CMU_LOW_FREQ = 0x02U, /**< Frequency is lower than low limit */ 2950 CLOCK_IP_CMU_STATUS_UNDEFINED = 0X03U, /**< CMU status is unknown */ 2951 } Clock_Ip_CmuStatusType; 2952 2953 /** @brief Clock ip report error types. */ 2954 typedef enum 2955 { 2956 CLOCK_IP_CMU_ERROR = 0U, /**< @brief Cmu Fccu notification. */ 2957 CLOCK_IP_REPORT_TIMEOUT_ERROR = 1U, /**< @brief Report Timeout Error. */ 2958 CLOCK_IP_REPORT_FXOSC_CONFIGURATION_ERROR = 2U, /**< @brief Report Fxosc Configuration Error. */ 2959 CLOCK_IP_REPORT_CLOCK_MUX_SWITCH_ERROR = 3U, /**< @brief Report Clock Mux Switch Error. */ 2960 CLOCK_IP_RAM_MEMORY_CONFIG_ENTRY = 4U, /**< @brief Ram config entry point. */ 2961 CLOCK_IP_RAM_MEMORY_CONFIG_EXIT = 5U, /**< @brief Ram config exit point. */ 2962 CLOCK_IP_FLASH_MEMORY_CONFIG_ENTRY = 6U, /**< @brief Flash config entry point. */ 2963 CLOCK_IP_FLASH_MEMORY_CONFIG_EXIT = 7U, /**< @brief Flash config exit point. */ 2964 CLOCK_IP_ACTIVE = 8U, /**< @brief Report Clock Active. */ 2965 CLOCK_IP_INACTIVE = 9U, /**< @brief Report Clock Inactive. */ 2966 CLOCK_IP_REPORT_WRITE_PROTECTION_ERROR = 10U, /**< @brief Report Write Protection Error. */ 2967 } Clock_Ip_NotificationType; 2968 2969 /** @brief Clock ip trigger divider type. */ 2970 typedef enum 2971 { 2972 IMMEDIATE_DIVIDER_UPDATE, /**< @brief Immediate divider update. */ 2973 COMMON_TRIGGER_DIVIDER_UPDATE, /**< @brief Common trigger divider update. */ 2974 2975 } Clock_Ip_TriggerDividerType; 2976 2977 /** @brief specific peripheral. */ 2978 typedef enum 2979 { 2980 RESERVED_VALUE, 2981 } Clock_Ip_SpecificPeriphParamType; 2982 2983 /*================================================================================================== 2984 * STRUCTURES AND OTHER TYPEDEFS 2985 ==================================================================================================*/ 2986 /*! 2987 * @brief Clock notifications callback type. 2988 * Implements ClockNotificationsCallbackType_Class 2989 */ 2990 typedef void (*Clock_Ip_NotificationsCallbackType)(Clock_Ip_NotificationType Error, Clock_Ip_NameType ClockName); 2991 2992 /*! 2993 * @brief Register value structure. 2994 * Implements Clock_Ip_RegisterValueType_Class 2995 */ 2996 typedef struct 2997 { 2998 uint32* RegisterAddr; /**< Register address. */ 2999 uint32 RegisterData; /**< Register value. */ 3000 3001 } Clock_Ip_RegisterValueType; 3002 3003 /*! 3004 * @brief Register index structure. 3005 * Implements Clock_Ip_RegisterIndexType_Class 3006 */ 3007 typedef struct 3008 { 3009 uint16 StartIndex; /**< Start index in register array. */ 3010 uint16 EndIndex; /**< End index in register array. */ 3011 3012 } Clock_Ip_RegisterIndexType; 3013 3014 3015 3016 /*! 3017 * @brief Clock Source IRCOSC configuration structure. 3018 * Implements Clock_Ip_IrcoscConfigType_Class 3019 */ 3020 typedef struct 3021 { 3022 Clock_Ip_NameType Name; /**< Clock name associated to ircosc */ 3023 uint16 Enable; /**< Enable ircosc. */ 3024 3025 uint8 Regulator; /**< Enable regulator. */ 3026 uint8 Range; /**< Ircosc range. */ 3027 uint8 LowPowerModeEnable; /**< Ircosc enable in VLP mode */ 3028 uint8 StopModeEnable; /**< Ircosc enable in STOP mode */ 3029 3030 } Clock_Ip_IrcoscConfigType; 3031 3032 /*! 3033 * @brief CGM Clock Source XOSC configuration structure. 3034 * Implements Clock_Ip_XoscConfigType_Class 3035 */ 3036 typedef struct 3037 { 3038 Clock_Ip_NameType Name; /**< Clock name associated to xosc */ 3039 3040 uint32 Freq; /**< External oscillator frequency. */ 3041 3042 uint16 Enable; /**< Enable xosc. */ 3043 3044 uint16 StartupDelay; /**< Startup stabilization time. */ 3045 uint8 BypassOption; /**< XOSC bypass option */ 3046 uint8 CompEn; /**< Comparator enable */ 3047 uint8 TransConductance; /**< Crystal overdrive protection */ 3048 3049 uint8 Gain; /**< Gain value */ 3050 uint8 Monitor; /**< Monitor type */ 3051 uint8 AutoLevelController; /**< Automatic level controller */ 3052 3053 } Clock_Ip_XoscConfigType; 3054 3055 /*! 3056 * @brief CGM Clock Source PLLDIG configuration structure. 3057 * Implements Clock_Ip_PllConfigType_Class 3058 */ 3059 typedef struct 3060 { 3061 Clock_Ip_NameType Name; /**< Clock name associated to pll */ 3062 3063 uint16 Enable; /**< Enable pll. */ 3064 3065 Clock_Ip_NameType InputReference; /**< Input reference. */ 3066 3067 uint8 Bypass; /**< Bypass pll. */ 3068 3069 uint8 Predivider; /**< Input clock predivider. */ 3070 uint16 Multiplier; /**< Clock multiplier. */ 3071 uint8 Postdivider; /**< Clock postidivder.*/ 3072 3073 uint16 NumeratorFracLoopDiv; /**< Numerator of fractional loop division factor (MFN) */ 3074 uint8 MulFactorDiv; /**< Multiplication factor divider (MFD) */ 3075 3076 uint8 FrequencyModulationBypass; /**< Enable/disable modulation */ 3077 uint8 ModulationType; /**< Modulation type */ 3078 uint16 ModulationPeriod; /**< Stepsize - modulation period */ 3079 uint16 IncrementStep; /**< Stepno - step no */ 3080 3081 uint8 SigmaDelta; /**< Sigma Delta Modulation Enable */ 3082 3083 uint8 DitherControl; /**< Dither control enable */ 3084 uint8 DitherControlValue; /**< Dither control value */ 3085 3086 uint8 Monitor; /**< Monitor type */ 3087 3088 uint16 Dividers[3U]; /**< Dividers values */ 3089 3090 } Clock_Ip_PllConfigType; 3091 3092 /*! 3093 * @brief Clock selector configuration structure. 3094 * Implements Clock_Ip_SelectorConfigType_Class 3095 */ 3096 typedef struct 3097 { 3098 Clock_Ip_NameType Name; /**< Clock name associated to selector */ 3099 Clock_Ip_NameType Value; /**< Name of the selected input source */ 3100 3101 } Clock_Ip_SelectorConfigType; 3102 3103 /*! 3104 * @brief Clock divider configuration structure. 3105 * Implements Clock_Ip_DividerConfigType_Class 3106 */ 3107 typedef struct 3108 { 3109 Clock_Ip_NameType Name; /**< Clock name associated to divider. */ 3110 uint32 Value; /**< Divider value - if value is zero then divider is disabled. */ 3111 uint8 Options[1U]; /**< Option divider value - this value depend hardware information. */ 3112 } Clock_Ip_DividerConfigType; 3113 3114 /*! 3115 * @brief Clock divider trigger configuration structure. 3116 * Implements Clock_Ip_DividerTriggerConfigType_Class 3117 */ 3118 typedef struct 3119 { 3120 Clock_Ip_NameType Name; /**< Clock name associated to divider for which trigger is configured. */ 3121 Clock_Ip_TriggerDividerType TriggerType; /**< Trigger value - if value is zero then divider is updated immediately, divider is not triggered. */ 3122 Clock_Ip_NameType Source; /**< Clock name of the common input source of all dividers from the same group that support a common update */ 3123 3124 } Clock_Ip_DividerTriggerConfigType; 3125 3126 3127 3128 /*! 3129 * @brief Clock fractional divider configuration structure. 3130 * Implements Clock_Ip_FracDivConfigType_Class 3131 */ 3132 typedef struct 3133 { 3134 Clock_Ip_NameType Name; /**< Clock name associated to fractional divider. */ 3135 uint8 Enable; /**< Enable control for port n */ 3136 uint32 Value[2U]; /**< Fractional dividers */ 3137 3138 } Clock_Ip_FracDivConfigType; 3139 3140 /*! 3141 * @brief Clock external clock configuration structure. 3142 * Implements Clock_Ip_ExtClkConfigType_Class 3143 */ 3144 typedef struct 3145 { 3146 Clock_Ip_NameType Name; /**< Clock name of the external clock. */ 3147 uint32 Value; /**< Enable value - if value is zero then clock is gated, otherwise is enabled in different modes. */ 3148 3149 } Clock_Ip_ExtClkConfigType; 3150 3151 /*! 3152 * @brief Clock Source PCFS configuration structure. 3153 * Implements Clock_Ip_PcfsConfigType_Class 3154 */ 3155 typedef struct 3156 { 3157 Clock_Ip_NameType Name; /**< Clock source from which ramp-down and to which ramp-up are processed. */ 3158 uint32 MaxAllowableIDDchange; /**< Maximum variation of current per time (mA/microsec) - max allowable IDD change is determined by the user's power supply design. */ 3159 uint32 StepDuration; /**< Step duration of each PCFS step */ 3160 Clock_Ip_NameType SelectorName; /**< Name of the selector that supports PCFS and name is one the inputs that can be selected */ 3161 uint32 ClockSourceFrequency; /**< Frequency of the clock source from which ramp-down and to which ramp-up are processed. */ 3162 3163 } Clock_Ip_PcfsConfigType; 3164 3165 /*! 3166 * @brief Clock gate clock configuration structure. 3167 * Implements Clock_Ip_GateConfigType_Class 3168 */ 3169 typedef struct 3170 { 3171 Clock_Ip_NameType Name; /**< Clock name associated to clock gate. */ 3172 uint16 Enable; /**< Enable or disable clock */ 3173 3174 } Clock_Ip_GateConfigType; 3175 3176 /*! 3177 * @brief Clock cmu configuration structure. 3178 * Implements Clock_Ip_CmuConfigType_Class 3179 */ 3180 typedef struct 3181 { 3182 Clock_Ip_NameType Name; /**< Clock name associated to clock monitor. */ 3183 uint8 Enable; /**< Enable/disable clock monitor */ 3184 uint32 Interrupt; /**< Enable/disable interrupt */ 3185 uint32 MonitoredClockFrequency; /**< Frequency of the clock source from which ramp-down and to which ramp-up are processed. */ 3186 Clock_Ip_RegisterIndexType Indexes; /**< Register index if register value optimization is enabled. */ 3187 } Clock_Ip_CmuConfigType; 3188 3189 /*! 3190 * @brief Configured frequency structure. 3191 * Implements Clock_Ip_ConfiguredFrequencyType_Class 3192 */ 3193 typedef struct 3194 { 3195 Clock_Ip_NameType Name; /**< Clock name of the configured frequency value */ 3196 uint32 ConfiguredFrequencyValue; /**< Configured frequency value */ 3197 } Clock_Ip_ConfiguredFrequencyType; 3198 3199 /*! 3200 * @brief Clock Specific peripheral configure. 3201 * Implements Clock_Ip_SpecificPerpihParamType_Class 3202 */ 3203 typedef struct 3204 { 3205 Clock_Ip_SpecificPeriphParamType ParamsType; 3206 uint32 ParamsValue; 3207 } Clock_Ip_SpecificPerpihParamType; 3208 3209 /*! 3210 * @brief Clock Specific peripheral structure. 3211 * Implements Clock_IP_SpecificPeriphConfigType_Class 3212 */ 3213 typedef struct 3214 { 3215 uint8 ParamsNo; 3216 Clock_Ip_SpecificPerpihParamType Params[CLOCK_IP_SPECIFIC_PERIPH_NO]; 3217 } Clock_IP_SpecificPeriphConfigType; 3218 3219 /*! 3220 * @brief Clock configuration structure. 3221 * Implements Clock_Ip_ClockConfigType_Class 3222 */ 3223 typedef struct 3224 { 3225 uint32 ClkConfigId; /**< The ID for Clock configuration */ 3226 3227 const Clock_Ip_RegisterValueType (*RegValues)[]; /**< Pointer to register values array */ 3228 3229 uint8 IrcoscsCount; /**< IRCOSCs count */ 3230 uint8 XoscsCount; /**< XOSCs count */ 3231 uint8 PllsCount; /**< PLLs count */ 3232 uint8 SelectorsCount; /**< Selectors count */ 3233 uint8 DividersCount; /**< Dividers count */ 3234 uint8 DividerTriggersCount; /**< Divider triggers count */ 3235 uint8 FracDivsCount; /**< Fractional dividers count */ 3236 uint8 ExtClksCount; /**< External clocks count */ 3237 uint8 GatesCount; /**< Clock gates count */ 3238 uint8 PcfsCount; /**< Clock pcfs count */ 3239 uint8 CmusCount; /**< Clock cmus count */ 3240 uint8 ConfigureFrequenciesCount; /**< Configured frequencies count */ 3241 3242 Clock_Ip_IrcoscConfigType Ircoscs[CLOCK_IP_IRCOSCS_NO]; /**< IRCOSCs */ 3243 Clock_Ip_XoscConfigType Xoscs[CLOCK_IP_XOSCS_NO]; /**< XOSCs */ 3244 Clock_Ip_PllConfigType Plls[CLOCK_IP_PLLS_NO]; /**< PLLs */ 3245 Clock_Ip_SelectorConfigType Selectors[CLOCK_IP_SELECTORS_NO]; /**< Selectors */ 3246 Clock_Ip_DividerConfigType Dividers[CLOCK_IP_DIVIDERS_NO]; /**< Dividers */ 3247 Clock_Ip_DividerTriggerConfigType DividerTriggers[CLOCK_IP_DIVIDER_TRIGGERS_NO]; /**< Divider triggers */ 3248 Clock_Ip_FracDivConfigType FracDivs[CLOCK_IP_FRACTIONAL_DIVIDERS_NO]; /**< Fractional dividers */ 3249 Clock_Ip_ExtClkConfigType ExtClks[CLOCK_IP_EXT_CLKS_NO]; /**< External clocks */ 3250 Clock_Ip_GateConfigType Gates[CLOCK_IP_GATES_NO]; /**< Clock gates */ 3251 Clock_Ip_PcfsConfigType Pcfs[CLOCK_IP_PCFS_NO]; /**< Progressive clock switching */ 3252 Clock_Ip_CmuConfigType Cmus[CLOCK_IP_CMUS_NO]; /**< Clock cmus */ 3253 Clock_IP_SpecificPeriphConfigType SpecificPeriphalConfiguration; /**< Clock specific peripheral configuration */ 3254 3255 Clock_Ip_ConfiguredFrequencyType ConfiguredFrequencies[CLOCK_IP_CONFIGURED_FREQUENCIES_NO]; /**< Configured frequency values */ 3256 } Clock_Ip_ClockConfigType; 3257 3258 /*================================================================================================== 3259 * GLOBAL VARIABLE DECLARATIONS 3260 ==================================================================================================*/ 3261 3262 /*================================================================================================== 3263 * FUNCTION PROTOTYPES 3264 ==================================================================================================*/ 3265 3266 /*================================================================================================== 3267 CONFIGURATION STRUCTURE 3268 ==================================================================================================*/ 3269 3270 3271 #if defined(__cplusplus) 3272 } 3273 #endif /* __cplusplus*/ 3274 3275 /*! @}*/ 3276 3277 #endif /* CLOCK_IP_TYPES_H */ 3278 3279 3280
