1 /* 2 * Copyright (c) 2024 Silicon Laboratories Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ 9 10 /* 11 * DT macros for clock branches. 12 * Must stay in sync with the enum sl_clock_branch_t in the Silicon Labs HAL to be 13 * interpreted correctly by the clock control driver. 14 */ 15 #define CLOCK_BRANCH_SYSCLK 0 16 #define CLOCK_BRANCH_HCLK 1 17 #define CLOCK_BRANCH_HCLKRADIO 2 18 #define CLOCK_BRANCH_PCLK 3 19 #define CLOCK_BRANCH_LSPCLK 4 20 #define CLOCK_BRANCH_TRACECLK 5 21 #define CLOCK_BRANCH_ADCCLK 6 22 #define CLOCK_BRANCH_EXPORTCLK 7 23 #define CLOCK_BRANCH_EM01GRPACLK 8 24 #define CLOCK_BRANCH_EM01GRPBCLK 9 25 #define CLOCK_BRANCH_EM01GRPCCLK 10 26 #define CLOCK_BRANCH_EM01GRPDCLK 11 27 #define CLOCK_BRANCH_EM23GRPACLK 12 28 #define CLOCK_BRANCH_EM4GRPACLK 13 29 #define CLOCK_BRANCH_QSPISYSCLK 14 30 #define CLOCK_BRANCH_IADCCLK 15 31 #define CLOCK_BRANCH_WDOG0CLK 16 32 #define CLOCK_BRANCH_WDOG1CLK 17 33 #define CLOCK_BRANCH_RTCCCLK 18 34 #define CLOCK_BRANCH_SYSRTCCLK 19 35 #define CLOCK_BRANCH_EUART0CLK 20 36 #define CLOCK_BRANCH_EUSART0CLK 21 37 #define CLOCK_BRANCH_DPLLREFCLK 22 38 #define CLOCK_BRANCH_I2C0CLK 23 39 #define CLOCK_BRANCH_LCDCLK 24 40 #define CLOCK_BRANCH_PIXELRZCLK 25 41 #define CLOCK_BRANCH_PCNT0CLK 26 42 #define CLOCK_BRANCH_PRORTCCLK 27 43 #define CLOCK_BRANCH_SYSTICKCLK 28 44 #define CLOCK_BRANCH_LESENSEHFCLK 29 45 #define CLOCK_BRANCH_VDAC0CLK 30 46 #define CLOCK_BRANCH_VDAC1CLK 31 47 #define CLOCK_BRANCH_USB0CLK 32 48 #define CLOCK_BRANCH_FLPLLREFCLK 33 49 #define CLOCK_BRANCH_INVALID 34 50 51 #define CLOCK_BIT_MASK 0x03FUL 52 #define CLOCK_REG_MASK 0x1C0UL 53 54 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ */ 55
