1 /**************************************************************************//** 2 * @file clk_reg.h 3 * @version V1.00 4 * @brief CLK register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CLK_REG_H__ 10 #define __CLK_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- System Clock Controller -------------------------*/ 20 /** 21 @addtogroup CLK System Clock Controller(CLK) 22 Memory Mapped Structure for CLK Controller 23 @{ 24 */ 25 26 typedef struct 27 { 28 29 /** 30 * @var CLK_T::PWRCTL 31 * Offset: 0x00 System Power-down Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |HXTEN |HXT Enable Bit (Write Protect) 36 * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. 37 * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. 38 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 39 * | | |Note2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT). 40 * |[1] |LXTEN |LXT Enable Bit (Write Protect) 41 * | | |0 = 32.768 kHz external low speed crystal (extLXT) Disabled. 42 * | | |1 = 32.768 kHz external low speed crystal (extLXT) Enabled. 43 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 44 * | | |Note2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as extLXT by setting C32KS(RTC_LXTCTL[7]) to 1. 45 * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) 46 * | | |The HCLK default clock source is from HIRC and this bit default value is 1. 47 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. 48 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. 49 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 50 * | | |Note2: HIRC cannot be disabled and HIRCEN will always read as 1 if HCLK clock source is selected from HIRC or PLL (clock source from HIRC). 51 * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) 52 * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) Disabled. 53 * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) Enabled. 54 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 55 * | | |Note2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC. 56 * | | |Note3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]). 57 * | | |If CWDTEN(CONFIG0[31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode and LIRCEN will always read as 1 58 * | | |In Power-down mode, LIRC clock is controlled by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN (CONFIG0[30]) setting. 59 * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) 60 * | | |0 = Power-down mode wake-up interrupt Disabled. 61 * | | |1 = Power-down mode wake-up interrupt Enabled. 62 * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from Power-down mode. 63 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 64 * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status 65 * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode. 66 * | | |The flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, EWDT, SDH0, TIMER, I2C0~2, USCI0~1, RTC, TAMPER and CLKD wake-up occurred. 67 * | | |Note1: Write 1 to clear the bit to 0. 68 * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 69 * |[7] |PDEN |System Power-down Enable (Write Protect) 70 * | | |When this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. 71 * | | |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. 72 * | | |In Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection. 73 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT, LIRC or MIRC. 74 * | | |0 = Chip operating normally or chip in idle mode because of WFI command. 75 * | | |1 = Chip waits CPU sleep command WFI and then enters Power-down mode. 76 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 77 * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) 78 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally. 79 * | | |If gain control is enabled, crystal will consume more power than gain control off. 80 * | | |00 = HXT frequency is lower than from 8 MHz. 81 * | | |01 = HXT frequency is from 8 MHz to 12 MHz. 82 * | | |10 = HXT frequency is from 12 MHz to 16 MHz. 83 * | | |11 = HXT frequency is higher than 16 MHz. 84 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 85 * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) 86 * | | |0 = Select INV type. 87 * | | |1 = Select GM type. 88 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 89 * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) 90 * | | |0 = HXT Crystal TURBO mode disabled. 91 * | | |1 = HXT Crystal TURBO mode enabled. 92 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 93 * |[18] |HIRC48EN |HIRC48 Enable Bit (Write Protect) 94 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48) Disabled. 95 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48) Enabled. 96 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 97 * | | |Note 2: HIRC48 cannot be disabled and HIRC48EN will always read as 1 if HCLK clock source is selected from HIRC48. 98 * |[20] |MIRC1P2MEN|MIRC1P2M Enable Bit (Write Protect) 99 * | | |0 = 1.2 MHz internal medium speed RC oscillator (MIRC1P2M) Disabled. 100 * | | |1 = 1.2 MHz internal medium speed RC oscillator (MIRC1P2M) Enabled. 101 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 102 * | | |Note 2: This clock source only for LCD use. 103 * |[21] |MIRCEN |MIRC Enable Bit (Write Protect) 104 * | | |0 = 4 MHz internal medium speed RC oscillator (MIRC) Disabled. 105 * | | |1 = 4 MHz internal medium speed RC oscillator (MIRC) Enabled. 106 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 107 * | | |Note 2: MIRC cannot be disabled and MIRC will always read as 1 if HCLK clock source is selected from MIRC. 108 * @var CLK_T::AHBCLK 109 * Offset: 0x04 AHB Devices Clock Enable Control Register 110 * --------------------------------------------------------------------------------------------------- 111 * |Bits |Field |Descriptions 112 * | :----: | :----: | :---- | 113 * |[0] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit (Secure) 114 * | | |0 = PDMA0 peripheral clock Disabled. 115 * | | |1 = PDMA0 peripheral clock Enabled. 116 * |[1] |PDMA1CKEN |PDMA1 Controller Clock Enable Bit 117 * | | |0 = PDMA1 peripheral clock Disabled. 118 * | | |1 = PDMA1 peripheral clock Enabled. 119 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit 120 * | | |0 = Flash ISP peripheral clock Disabled. 121 * | | |1 = Flash ISP peripheral clock Enabled. 122 * |[3] |EBICKEN |EBI Controller Clock Enable Bit 123 * | | |0 = EBI peripheral clock Disabled. 124 * | | |1 = EBI peripheral clock Enabled. 125 * |[4] |EXSTCKEN |External System Tick Clock Enable Bit 126 * | | |0 = External System tick clock Disabled. 127 * | | |1 = External System tick clock Enabled. 128 * |[6] |SDH0CKEN |SDHOST0 Controller Clock Enable Bit 129 * | | |0 = SDHOST0 peripheral clock Disabled. 130 * | | |1 = SDHOST0 peripheral clock Enabled. 131 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit 132 * | | |0 = CRC peripheral clock Disabled. 133 * | | |1 = CRC peripheral clock Enabled. 134 * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit 135 * | | |0 = Cryptographic Accelerator clock Disabled. 136 * | | |1 = Cryptographic Accelerator clock Enabled. 137 * |[13] |KSCKEN |Key Store Clock Enable Bit 138 * | | |0 = Key store clock Disabled. 139 * | | |1 = Key store clock Enabled. 140 * |[14] |TRACECKEN |Trace Clock Enable Bit 141 * | | |0 = Trace clock Disabled. 142 * | | |1 = Trace clock Enabled. 143 * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode 144 * | | |0 = FMC clock Disabled when chip is under IDLE mode. 145 * | | |1 = FMC clock Enabled when chip is under IDLE mode. 146 * |[16] |USBHCKEN |USB HOST 1.1 Controller Clock Enable Bit 147 * | | |0 = USB HOST 1.1 peripheral clock Disabled. 148 * | | |1 = USB HOST 1.1 peripheral clock Enabled. 149 * |[20] |SRAM0CKEN |SRAM Bank0 Controller Clock Enable Bit 150 * | | |0 = SRAM bank0 clock Disabled. 151 * | | |1 = SRAM bank0 clock Enabled. 152 * |[21] |SRAM1CKEN |SRAM Bank1 Controller Clock Enable Bit 153 * | | |0 = SRAM bank1 clock Disabled. 154 * | | |1 = SRAM bank1 clock Enabled. 155 * |[22] |SRAM2CKEN |SRAM Bank2 Controller Clock Enable Bit 156 * | | |0 = SRAM bank2 clock Disabled. 157 * | | |1 = SRAM bank2 clock Enabled. 158 * |[24] |GPACKEN |GPIOA Clock Enable Bit 159 * | | |0 = GPIOA port clock Disabled. 160 * | | |1 = GPIOA port clock Enabled. 161 * |[25] |GPBCKEN |GPIOB Clock Enable Bit 162 * | | |0 = GPIOB port clock Disabled. 163 * | | |1 = GPIOB port clock Enabled. 164 * |[26] |GPCCKEN |GPIOC Clock Enable Bit 165 * | | |0 = GPIOC port clock Disabled. 166 * | | |1 = GPIOC port clock Enabled. 167 * |[27] |GPDCKEN |GPIOD Clock Enable Bit 168 * | | |0 = GPIOD port clock Disabled. 169 * | | |1 = GPIOD port clock Enabled. 170 * |[28] |GPECKEN |GPIOE Clock Enable Bit 171 * | | |0 = GPIOE port clock Disabled. 172 * | | |1 = GPIOE port clock Enabled. 173 * |[29] |GPFCKEN |GPIOF Clock Enable Bit 174 * | | |0 = GPIOF port clock Disabled. 175 * | | |1 = GPIOF port clock Enabled. 176 * |[30] |GPGCKEN |GPIOG Clock Enable Bit 177 * | | |0 = GPIOG port clock Disabled. 178 * | | |1 = GPIOG port clock Enabled. 179 * |[31] |GPHCKEN |GPIOH Clock Enable Bit 180 * | | |0 = GPIOH port clock Disabled. 181 * | | |1 = GPIOH port clock Enabled. 182 * @var CLK_T::APBCLK0 183 * Offset: 0x08 APB Devices Clock Enable Control Register 0 184 * --------------------------------------------------------------------------------------------------- 185 * |Bits |Field |Descriptions 186 * | :----: | :----: | :---- | 187 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) 188 * | | |0 = Watchdog timer and Windows watchdog timer clock Disabled. 189 * | | |1 = Watchdog timer and Windows watchdog timer clock Enabled. 190 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 191 * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit 192 * | | |This bit is used to control the RTC APB clock only. 193 * | | |The RTC peripheral clock source is selected from RTCCKSEL(RTC_LXTCTL[7]). 194 * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 32 kHz internal low speed RC oscillator (LIRC). 195 * | | |0 = RTC clock Disabled. 196 * | | |1 = RTC clock Enabled. 197 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit 198 * | | |0 = Timer0 clock Disabled. 199 * | | |1 = Timer0 clock Enabled. 200 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit 201 * | | |0 = Timer1 clock Disabled. 202 * | | |1 = Timer1 clock Enabled. 203 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit 204 * | | |0 = Timer2 clock Disabled. 205 * | | |1 = Timer2 clock Enabled. 206 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit 207 * | | |0 = Timer3 clock Disabled. 208 * | | |1 = Timer3 clock Enabled. 209 * |[6] |CLKOCKEN |CLKO Clock Enable Bit 210 * | | |0 = CLKO clock Disabled. 211 * | | |1 = CLKO clock Enabled. 212 * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit 213 * | | |0 = Analog comparator 0/1 clock Disabled. 214 * | | |1 = Analog comparator 0/1 clock Enabled. 215 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit 216 * | | |0 = I2C0 clock Disabled. 217 * | | |1 = I2C0 clock Enabled. 218 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit 219 * | | |0 = I2C1 clock Disabled. 220 * | | |1 = I2C1 clock Enabled. 221 * |[10] |I2C2CKEN |I2C2 Clock Enable Bit 222 * | | |0 = I2C2 clock Disabled. 223 * | | |1 = I2C2 clock Enabled. 224 * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit 225 * | | |0 = QSPI0 clock Disabled. 226 * | | |1 = QSPI0 clock Enabled. 227 * |[13] |SPI0CKEN |SPI0 Clock Enable Bit 228 * | | |0 = SPI0 clock Disabled. 229 * | | |1 = SPI0 clock Enabled. 230 * |[14] |SPI1CKEN |SPI1 Clock Enable Bit 231 * | | |0 = SPI1 clock Disabled. 232 * | | |1 = SPI1 clock Enabled. 233 * |[15] |SPI2CKEN |SPI2 Clock Enable Bit 234 * | | |0 = SPI2 clock Disabled. 235 * | | |1 = SPI2 clock Enabled. 236 * |[16] |UART0CKEN |UART0 Clock Enable Bit 237 * | | |0 = UART0 clock Disabled. 238 * | | |1 = UART0 clock Enabled. 239 * |[17] |UART1CKEN |UART1 Clock Enable Bit 240 * | | |0 = UART1 clock Disabled. 241 * | | |1 = UART1 clock Enabled. 242 * |[18] |UART2CKEN |UART2 Clock Enable Bit 243 * | | |0 = UART2 clock Disabled. 244 * | | |1 = UART2 clock Enabled. 245 * |[19] |UART3CKEN |UART3 Clock Enable Bit 246 * | | |0 = UART3 clock Disabled. 247 * | | |1 = UART3 clock Enabled. 248 * |[20] |UART4CKEN |UART4 Clock Enable Bit 249 * | | |0 = UART4 clock Disabled. 250 * | | |1 = UART4 clock Enabled. 251 * |[21] |UART5CKEN |UART5 Clock Enable Bit 252 * | | |0 = UART5 clock Disabled. 253 * | | |1 = UART5 clock Enabled. 254 * |[24] |CAN0CKEN |CAN0 Clock Enable Bit 255 * | | |0 = CAN0 clock Disabled. 256 * | | |1 = CAN0 clock Enabled. 257 * |[26] |OTGCKEN |USB OTG Clock Enable Bit 258 * | | |0 = USB OTG clock Disabled. 259 * | | |1 = USB OTG clock Enabled. 260 * |[27] |USBDCKEN |USB Device Clock Enable Bit 261 * | | |0 = USB Device clock Disabled. 262 * | | |1 = USB Device clock Enabled. 263 * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit 264 * | | |0 = EADC clock Disabled. 265 * | | |1 = EADC clock Enabled. 266 * |[29] |I2S0CKEN |I2S0 Clock Enable Bit 267 * | | |0 = I2S0 Clock Disabled. 268 * | | |1 = I2S0 Clock Enabled. 269 * |[31] |EWDTCKEN |Extra Watchdog Timer Clock Enable Bit (Write Protect) 270 * | | |0 = Extra Watchdog timer and Extra Windows watchdog timer clock Disabled. 271 * | | |1 = Extra Watchdog timer and Extra Windows watchdog timer clock Enabled. 272 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 273 * @var CLK_T::APBCLK1 274 * Offset: 0x0C APB Devices Clock Enable Control Register 1 275 * --------------------------------------------------------------------------------------------------- 276 * |Bits |Field |Descriptions 277 * | :----: | :----: | :---- | 278 * |[0] |SC0CKEN |Smart Card 0 (SC0) Clock Enable Bit 279 * | | |0 = SC0 clock Disabled. 280 * | | |1 = SC0 clock Enabled. 281 * |[1] |SC1CKEN |Smart Card 1 (SC1) Clock Enable Bit 282 * | | |0 = SC1 clock Disabled. 283 * | | |1 = SC1 clock Enabled. 284 * |[2] |SC2CKEN |Smart Card 2 (SC2) Clock Enable Bit 285 * | | |0 = SC2 clock Disabled. 286 * | | |1 = SC2 clock Enabled. 287 * |[4] |TMR4CKEN |Timer4 Clock Enable Bit 288 * | | |0 = Timer4 clock Disabled. 289 * | | |1 = Timer4 clock Enabled. 290 * |[5] |TMR5CKEN |Timer5 Clock Enable Bit 291 * | | |0 = Timer5 clock Disabled. 292 * | | |1 = Timer5 clock Enabled. 293 * |[6] |SPI3CKEN |SPI3 Clock Enable Bit 294 * | | |0 = SPI3 clock Disabled. 295 * | | |1 = SPI3 clock Enabled. 296 * |[8] |USCI0CKEN |USCI0 Clock Enable Bit 297 * | | |0 = USCI0 clock Disabled. 298 * | | |1 = USCI0 clock Enabled. 299 * |[9] |USCI1CKEN |USCI1 Clock Enable Bit 300 * | | |0 = USCI1 clock Disabled. 301 * | | |1 = USCI1 clock Enabled. 302 * |[12] |DACCKEN |DAC Clock Enable Bit 303 * | | |0 = DAC clock Disabled. 304 * | | |1 = DAC clock Enabled. 305 * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit 306 * | | |0 = EPWM0 clock Disabled. 307 * | | |1 = EPWM0 clock Enabled. 308 * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit 309 * | | |0 = EPWM1 clock Disabled. 310 * | | |1 = EPWM1 clock Enabled. 311 * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit 312 * | | |0 = BPWM0 clock Disabled. 313 * | | |1 = BPWM0 clock Enabled. 314 * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit 315 * | | |0 = BPWM1 clock Disabled. 316 * | | |1 = BPWM1 clock Enabled. 317 * |[22] |QEI0CKEN |QEI0 Clock Enable Bit 318 * | | |0 = QEI0 clock Disabled. 319 * | | |1 = QEI0 clock Enabled. 320 * |[23] |QEI1CKEN |QEI1 Clock Enable Bit 321 * | | |0 = QEI1 clock Disabled. 322 * | | |1 = QEI1 clock Enabled. 323 * |[25] |TRNGCKEN |TRNG Clock Enable Bit 324 * | | |0 = TRNG clock Disabled. 325 * | | |1 = TRNG clock Enabled. 326 * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit 327 * | | |0 = ECAP0 clock Disabled. 328 * | | |1 = ECAP0 clock Enabled. 329 * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit 330 * | | |0 = ECAP1 clock Disabled. 331 * | | |1 = ECAP1 clock Enabled. 332 * |[28] |LCDCPCKEN |LCD Charge Pump Clock Enable Bit 333 * | | |0 = LCD charge pump clock Disabled. 334 * | | |1 = LCD charge pump clock Enabled. 335 * @var CLK_T::CLKSEL0 336 * Offset: 0x10 Clock Source Select Control Register 0 337 * --------------------------------------------------------------------------------------------------- 338 * |Bits |Field |Descriptions 339 * | :----: | :----: | :---- | 340 * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) 341 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. 342 * | | |000 = Clock source from HXT. 343 * | | |001 = Clock source from LXT. 344 * | | |010 = Clock source from PLL. 345 * | | |011 = Clock source from LIRC. 346 * | | |100 = Reserved. 347 * | | |101 = Clock source from HIRC48. 348 * | | |110 = Clock source from MIRC. 349 * | | |111 = Clock source from HIRC. 350 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 351 * |[5:3] |STCLKSEL |SysTick Clock Source Selection (Write Protect) 352 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. 353 * | | |000 = Clock source from HXT. 354 * | | |001 = Clock source from LXT. 355 * | | |010 = Clock source from HXT/2. 356 * | | |011 = Clock source from HCLK/2. 357 * | | |111 = Clock source from HIRC/2. 358 * | | |Others = Reserved. 359 * | | |Note1: if SysTick clock source is not from HCLK (i.e SYST_CTRL[2] = 0), 360 * | | |SysTick need to enable EXSTCKEN(CLK_AHBCLK[4]) and clock frequency must less than or equal to HCLK/2. 361 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 362 * |[8] |USBSEL |USB Clock Source Selection (Write Protect) 363 * | | |0 = Clock source from HIRC48. 364 * | | |1 = Clock source from PLL. 365 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 366 * |[21:20] |SDH0SEL |SDHOST0 Peripheral Clock Source Selection (Write Protect) 367 * | | |00 = Clock source from HXT clock. 368 * | | |01 = Clock source from PLL clock. 369 * | | |10 = Clock source from HCLK. 370 * | | |11 = Clock source from HIRC clock. 371 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 372 * @var CLK_T::CLKSEL1 373 * Offset: 0x14 Clock Source Select Control Register 1 374 * --------------------------------------------------------------------------------------------------- 375 * |Bits |Field |Descriptions 376 * | :----: | :----: | :---- | 377 * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) 378 * | | |00 = Reserved. 379 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 380 * | | |10 = Clock source from HCLK/2048. 381 * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 382 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 383 * |[2] |LCDSEL |LCD Clock Source Selection 384 * | | |0 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 385 * | | |1 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 386 * |[3] |LCDCPSEL |LCD Charge Pump Clock Source Selection 387 * | | |0 = Clock source from 1.2 MHz internal medium speed RC oscillator (MIRC1P2M). 388 * | | |1 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). 389 * |[5:4] |EWDTSEL |Extra Watchdog Timer Clock Source Selection (Write Protect) 390 * | | |00 = Reserved. 391 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 392 * | | |10 = Clock source from HCLK/2048. 393 * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 394 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 395 * |[7:6] |EWWDTSEL |Extra Window Watchdog Timer Clock Source Selection (Write Protect) 396 * | | |10 = Clock source from HCLK/2048. 397 * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 398 * | | |Others = Reserved. 399 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 400 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection 401 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 402 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 403 * | | |010 = Clock source from PCLK0. 404 * | | |011 = Clock source from external clock TM0 pin. 405 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 406 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 407 * | | |Others = Reserved. 408 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection 409 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 410 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 411 * | | |010 = Clock source from PCLK0. 412 * | | |011 = Clock source from external clock TM1 pin. 413 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 414 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 415 * | | |Others = Reserved. 416 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection 417 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 418 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 419 * | | |010 = Clock source from PCLK1. 420 * | | |011 = Clock source from external clock TM2 pin. 421 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 422 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 423 * | | |Others = Reserved. 424 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection 425 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 426 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 427 * | | |010 = Clock source from PCLK1. 428 * | | |011 = Clock source from external clock TM3 pin. 429 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 430 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 431 * | | |Others = Reserved. 432 * |[29:28] |CLKOSEL |Clock Output Clock Source Selection 433 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 434 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 435 * | | |10 = Clock source from HCLK. 436 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 437 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection (Write Protect) 438 * | | |10 = Clock source from HCLK/2048. 439 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 440 * | | |Others = Reserved. 441 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 442 * @var CLK_T::CLKSEL2 443 * Offset: 0x18 Clock Source Select Control Register 2 444 * --------------------------------------------------------------------------------------------------- 445 * |Bits |Field |Descriptions 446 * | :----: | :----: | :---- | 447 * |[0] |EPWM0SEL |EPWM0 Clock Source Selection (Read Only) 448 * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. 449 * | | |1 = Clock source from PCLK0. 450 * |[1] |EPWM1SEL |EPWM1 Clock Source Selection (Read Only) 451 * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. 452 * | | |1 = Clock source from PCLK1. 453 * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection 454 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 455 * | | |01 = Clock source from PLL. 456 * | | |10 = Clock source from PCLK0. 457 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 458 * |[5:4] |SPI0SEL |SPI0 Clock Source Selection 459 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 460 * | | |01 = Clock source from PLL. 461 * | | |10 = Clock source from PCLK1. 462 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 463 * |[7:6] |SPI1SEL |SPI1 Clock Source Selection 464 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 465 * | | |01 = Clock source from PLL. 466 * | | |10 = Clock source from PCLK0. 467 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 468 * |[8] |BPWM0SEL |BPWM0 Clock Source Selection (Read Only) 469 * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. 470 * | | |1 = Clock source from PCLK0. 471 * |[9] |BPWM1SEL |BPWM1 Clock Source Selection (Read Only) 472 * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. 473 * | | |1 = Clock source from PCLK1. 474 * |[11:10] |SPI2SEL |SPI2 Clock Source Selection 475 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 476 * | | |01 = Clock source from PLL. 477 * | | |10 = Clock source from PCLK1. 478 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 479 * |[13:12] |SPI3SEL |SPI3 Clock Source Selection 480 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 481 * | | |01 = Clock source from PLL. 482 * | | |10 = Clock source from PCLK0. 483 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 484 * |[18:16] |UART0SEL |UART0 Clock Source Selection 485 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 486 * | | |001 = Clock source from PLL. 487 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 488 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 489 * | | |100 = Clock source from PCLK0. 490 * | | |Others = Reserved. 491 * |[22:20] |UART1SEL |UART1 Clock Source Selection 492 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 493 * | | |001 = Clock source from PLL. 494 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 495 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 496 * | | |100 = Clock source from PCLK1. 497 * | | |Others = Reserved. 498 * |[26:24] |UART2SEL |UART2 Clock Source Selection 499 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 500 * | | |001 = Clock source from PLL. 501 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 502 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 503 * | | |100 = Clock source from PCLK0. 504 * | | |Others = Reserved. 505 * |[32:28] |UART3SEL |UART3 Clock Source Selection 506 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 507 * | | |001 = Clock source from PLL. 508 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 509 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 510 * | | |100 = Clock source from PCLK1. 511 * | | |Others = Reserved. 512 * @var CLK_T::CLKSEL3 513 * Offset: 0x1C Clock Source Select Control Register 3 514 * --------------------------------------------------------------------------------------------------- 515 * |Bits |Field |Descriptions 516 * | :----: | :----: | :---- | 517 * |[1:0] |SC0SEL |Smart Card 0 (SC0) Clock Source Selection 518 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 519 * | | |01 = Clock source from PLL. 520 * | | |10 = Clock source from PCLK0. 521 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 522 * |[3:2] |SC1SEL |Smart Card 1 (SC1) Clock Source Selection 523 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 524 * | | |01 = Clock source from PLL. 525 * | | |10 = Clock source from PCLK1. 526 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 527 * |[5:4] |SC2SEL |Smart Card 2 (SC2) Clock Source Selection 528 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 529 * | | |01 = Clock source from PLL. 530 * | | |10 = Clock source from PCLK0. 531 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 532 * |[10:8] |TMR4SEL |TIMER4 Clock Source Selection 533 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 534 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 535 * | | |010 = Clock source from PCLK0. 536 * | | |011 = Clock source from external clock TM4 pin. 537 * | | |100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). 538 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 539 * | | |110 = Reserved. 540 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 541 * |[14:12] |TMR5SEL |TIMER5 Clock Source Selection 542 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 543 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 544 * | | |010 = Clock source from PCLK0. 545 * | | |011 = Clock source from external clock TM5 pin. 546 * | | |100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). 547 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 548 * | | |110 = Reserved. 549 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 550 * |[17:16] |I2S0SEL |I2S0 Clock Source Selection 551 * | | |00 = Clock source from HXT clock. 552 * | | |01 = Clock source from PLL clock. 553 * | | |10 = Clock source from PCLK0. 554 * | | |11 = Clock source from HIRC clock. 555 * |[27:24] |UART4SEL |UART4 Clock Source Selection 556 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 557 * | | |001 = Clock source from PLL. 558 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 559 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 560 * | | |100 = Clock source from PCLK0. 561 * | | |Others = Reserved. 562 * |[28:30] |UART5SEL |UART5 Clock Source Selection 563 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 564 * | | |001 = Clock source from PLL. 565 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 566 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 567 * | | |100 = Clock source from PCLK1. 568 * | | |Others = Reserved. 569 * @var CLK_T::CLKDIV0 570 * Offset: 0x20 Clock Divider Number Register 0 571 * --------------------------------------------------------------------------------------------------- 572 * |Bits |Field |Descriptions 573 * | :----: | :----: | :---- | 574 * |[3:0] |HCLKDIV |HCLK Clock Divide Number from HCLK Clock Source 575 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). 576 * |[7:4] |USBDIV |USB Clock Divide Number from USB Clock Source 577 * | | |USB clock frequency = (USB clock source frequency) / (USBDIV + 1). 578 * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source 579 * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). 580 * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source 581 * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). 582 * |[23:16] |EADCDIV |EADC Clock Divide Number from EADC Clock Source 583 * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). 584 * |[31:24] |SDH0DIV |SDHOST0 Clock Divide Number from SDHOST0 Clock Source 585 * | | |SDHOST0 clock frequency = (SDHOST0 clock source frequency) / (SDH0DIV + 1). 586 * @var CLK_T::CLKDIV1 587 * Offset: 0x24 Clock Divider Number Register 1 588 * --------------------------------------------------------------------------------------------------- 589 * |Bits |Field |Descriptions 590 * | :----: | :----: | :---- | 591 * |[7:0] |SC0DIV |Smart Card 0 (SC0) Clock Divide Number from SC0 Clock Source 592 * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). 593 * |[15:8] |SC1DIV |Smart Card 1 (SC1) Clock Divide Number from SC1 Clock Source 594 * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). 595 * |[23:16] |SC2DIV |Smart Card 2 (SC2) Clock Divide Number from SC2 Clock Source 596 * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1). 597 * @var CLK_T::CLKDIV4 598 * Offset: 0x30 Clock Divider Number Register 4 599 * --------------------------------------------------------------------------------------------------- 600 * |Bits |Field |Descriptions 601 * | :----: | :----: | :---- | 602 * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source 603 * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). 604 * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source 605 * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). 606 * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source 607 * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). 608 * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source 609 * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). 610 * @var CLK_T::PLLCTL 611 * Offset: 0x40 PLL Control Register 612 * --------------------------------------------------------------------------------------------------- 613 * |Bits |Field |Descriptions 614 * | :----: | :----: | :---- | 615 * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) 616 * | | |Refer to the PLL formulas. 617 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 618 * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) 619 * | | |Refer to the PLL formulas. 620 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 621 * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) 622 * | | |Refer to the PLL formulas. 623 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 624 * |[16] |PD |Power-down Mode (Write Protect) 625 * | | |0 = PLL is enable (in normal mode). 626 * | | |1 = PLL is disable (in Power-down mode) (default). 627 * | | |Note1: If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. 628 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 629 * |[17] |BP |PLL Bypass Control (Write Protect) 630 * | | |0 = PLL is in normal mode (default). 631 * | | |1 = PLL clock output is same as PLL input clock FIN. 632 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 633 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) 634 * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). 635 * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). 636 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 637 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) 638 * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). 639 * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). 640 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 641 * @var CLK_T::STATUS 642 * Offset: 0x50 Clock Status Monitor Register 643 * --------------------------------------------------------------------------------------------------- 644 * |Bits |Field |Descriptions 645 * | :----: | :----: | :---- | 646 * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) 647 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. 648 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. 649 * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) 650 * | | |LXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]). 651 * | | |If C32KS is set to 0 the LXT stable flag is set when extLXT clock source is stable. 652 * | | |If C32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable. 653 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. 654 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. 655 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) 656 * | | |0 = Internal PLL clock is not stable or disabled. 657 * | | |1 = Internal PLL clock is stable and enabled. 658 * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) 659 * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. 660 * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. 661 * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) 662 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. 663 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. 664 * |[5] |MIRCSTB |MIRC Clock Source Stable Flag (Read Only) 665 * | | |0 = 4 MHz internal medium speed RC oscillator (MIRC) clock is not stable or disabled. 666 * | | |1 = 4 MHz internal medium speed RC oscillator (MIRC) clock is stable and enabled. 667 * |[6] |HIRC48STB |HIRC48 Clock Source Stable Flag (Read Only) 668 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48) clock is not stable or disabled. 669 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48) clock is stable and enabled. 670 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) 671 * | | |This bit is updated when software switches system clock source. 672 * | | |If switch target clock is stable, this bit will be set to 0. 673 * | | |If switch target clock is not stable, this bit will be set to 1. 674 * | | |0 = Clock switching success. 675 * | | |1 = Clock switching failure. 676 * | | |Note: This bit is read only. 677 * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. 678 * |[8] |EXTLXTSTB |EXTLXT Clock Source Stable Flag (Read Only) 679 * | | |0 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is not stable or disabled. 680 * | | |1 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is stable and enabled. 681 * |[9] |LIRC32STB |LIRC32 Clock Source Stable Flag (Read Only) 682 * | | |0 = 32 kHz internal low speed RC oscillator (LIRC32) clock is not stable or disabled. 683 * | | |1 = 32 kHz internal low speed RC oscillator (LIRC32) clock is stable and enabled. 684 * @var CLK_T::CLKOCTL 685 * Offset: 0x60 Clock Output Control Register 686 * --------------------------------------------------------------------------------------------------- 687 * |Bits |Field |Descriptions 688 * | :----: | :----: | :---- | 689 * |[3:0] |FREQSEL |Clock Output Frequency Selection 690 * | | |The formula of output frequency is Fout = Fin/2^(N+1). 691 * | | |Fin is the input clock frequency. 692 * | | |Fout is the frequency of divider output clock. 693 * | | |N is the 4-bit value of FREQSEL[3:0]. 694 * |[4] |CLKOEN |Clock Output Enable Bit 695 * | | |0 = Clock Output function Disabled. 696 * | | |1 = Clock Output function Enabled. 697 * |[5] |DIV1EN |Clock Output Divide One Enable Bit 698 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. 699 * | | |1 = Clock Output will output clock with source frequency. 700 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit 701 * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. 702 * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. 703 * @var CLK_T::CLKDCTL 704 * Offset: 0x70 Clock Fail Detector Control Register 705 * --------------------------------------------------------------------------------------------------- 706 * |Bits |Field |Descriptions 707 * | :----: | :----: | :---- | 708 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit 709 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. 710 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. 711 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit 712 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. 713 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. 714 * |[6] |HXTFDSEL |HXT Clock Fail Detector Selection 715 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector after HXT stable. 716 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector bypass HXT stable. 717 * | | |Note: When HXT Clock Fail Detector Selection is set, detector will keep detect whether HXT is stable or not, prevent HXT fail before stable. 718 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit 719 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. 720 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. 721 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit 722 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. 723 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. 724 * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit 725 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled. 726 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled. 727 * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit 728 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled. 729 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled. 730 * @var CLK_T::CLKDSTS 731 * Offset: 0x74 Clock Fail Detector Status Register 732 * --------------------------------------------------------------------------------------------------- 733 * |Bits |Field |Descriptions 734 * | :----: | :----: | :---- | 735 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) 736 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. 737 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. 738 * | | |Note1: Write 1 to clear the bit to 0. 739 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 740 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) 741 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. 742 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. 743 * | | |Note1: Write 1 to clear the bit to 0. 744 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 745 * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag (Write Protect) 746 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. 747 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. 748 * | | |Note1: Write 1 to clear the bit to 0. 749 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 750 * @var CLK_T::CDUPB 751 * Offset: 0x78 Clock Frequency Detector Upper Boundary Register 752 * --------------------------------------------------------------------------------------------------- 753 * |Bits |Field |Descriptions 754 * | :----: | :----: | :---- | 755 * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary 756 * | | |The bits define the high value of frequency monitor window. 757 * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. 758 * @var CLK_T::CDLOWB 759 * Offset: 0x7C Clock Frequency Detector Lower Boundary Register 760 * --------------------------------------------------------------------------------------------------- 761 * |Bits |Field |Descriptions 762 * | :----: | :----: | :---- | 763 * |[9:0] |LOWERBD |HXT Clock Frequency Detector Lower Boundary 764 * | | |The bits define the low value of frequency monitor window. 765 * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. 766 * @var CLK_T::PMUCTL 767 * Offset: 0x90 Power Manager Control Register 768 * --------------------------------------------------------------------------------------------------- 769 * |Bits |Field |Descriptions 770 * | :----: | :----: | :---- | 771 * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) 772 * | | |These bits control chip Power-down mode grade selection when CPU execute WFI/WFE instruction. 773 * | | |000 = Power-down mode is selected (PD). 774 * | | |001 = Low leakage Power-down mode is selected (LLPD). 775 * | | |010 = Fast wake-up Power-down (FWPD). 776 * | | |011 = Ultra low leakage Power-down mode is selected (ULLPD). 777 * | | |100 = Standby Power-down mode is selected (SPD). 778 * | | |101 = Reserved. 779 * | | |110 = Deep Power-down mode is selected (DPD). 780 * | | |111 = Reserved. 781 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 782 * |[4] |VDROPEN |Standby Power Down Mode Regulator Output Voltage Drop Enable Bit (Write Protect) 783 * | | |If this bit be asserted, regulator output voltage drop to 0.9V when SPD mode. 784 * | | |0 = Regulator voltage auto drop function Disabled. 785 * | | |1 = Regulator voltage auto drop function Enabled. (default) 786 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 787 * |[7] |WRBUSY |Write Busy Flag (Read Only) 788 * | | |If CLK_PMUCTL be written, this bit be asserted automatic by hardware, and be de-asserted when write procedure finish. 789 * | | |0 = CLK_PMUCTL write ready. 790 * | | |1 = CLK_PMUCTL write ignore. 791 * |[8] |WKTMREN |Wake-up Timer Enable Bit (Write Protect) 792 * | | |0 = Wake-up timer Disable in Deep Power-down mode or Standby Power-down mode. 793 * | | |1 = Wake-up timer Enabled in Deep Power-down mode or Standby Power-down mode. 794 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 795 * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) 796 * | | |These bits control wake-up timer time-out interval when chip under Deep Power-down mode or Standby Power-down mode. 797 * | | |000 = Time-out interval is 410 LIRC clocks (12.8ms). 798 * | | |001 = Time-out interval is 819 LIRC clocks (25.6ms). 799 * | | |010 = Time-out interval is 1638 LIRC clocks (51.2ms). 800 * | | |011 = Time-out interval is 3277 LIRC clocks (102.4ms). 801 * | | |100 = Time-out interval is 13107 LIRC clocks (409.6ms). 802 * | | |101 = Time-out interval is 26214 LIRC clocks (819.2ms). 803 * | | |110 = Time-out interval is 52429 LIRC clocks (1638.4ms). 804 * | | |111 = Time-out interval is 209715 LIRC clocks (6553.6ms). 805 * |[17:16] |WKPINEN0 |Wake-up Pin 0 Enable (Write Protect) 806 * | | |This is control register for GPC.0 to wake-up pin. 807 * | | |00 = Wake-up pin Disable in Deep Power-down mode. 808 * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. 809 * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. 810 * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. 811 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 812 * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) 813 * | | |0 = ACMP wake-up disable in Standby Power-down mode. 814 * | | |1 = ACMP wake-up enabled in Standby Power-down mode. 815 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 816 * |[19] |TAMPERWK |Tamper Standby Power-down Mode Wake-up Enable Bit (Write Protect) 817 * | | |0 = Tamper wake-up disable at Standby Power-down mode. 818 * | | |1 = Tamper wake-up enabled at Standby Power-down mode. 819 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 820 * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) 821 * | | |This is a protected register. Please refer to open lock sequence to program it. 822 * | | |0 = RTC wake-up Disable in Deep Power-down mode or Standby Power-down mode. 823 * | | |1 = RTC wake-up Enabled in Deep Power-down mode or Standby Power-down mode. 824 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 825 * |[25:24] |WKPINEN1 |Wake-up Pin 1 Enable (Write Protect) 826 * | | |This is control register for GPB.0 to wake-up pin. 827 * | | |00 = Wake-up pin Disable in Deep Power-down mode. 828 * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. 829 * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. 830 * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. 831 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 832 * |[27:26] |WKPINEN2 |Wake-up Pin 2 Enable (Write Protect) 833 * | | |This is control register for GPB.2 to wake-up pin. 834 * | | |00 = Wake-up pin Disable in Deep Power-down mode. 835 * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. 836 * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. 837 * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. 838 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 839 * |[29:28] |WKPINEN3 |Wake-up Pin 3 Enable (Write Protect) 840 * | | |This is control register for GPB.12 to wake-up pin. 841 * | | |00 = Wake-up pin Disable in Deep Power-down mode. 842 * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. 843 * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. 844 * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. 845 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 846 * |[31:30] |WKPINEN4 |Wake-up Pin 4 Enable (Write Protect) 847 * | | |This is control register for GPF.6 to wake-up pin. 848 * | | |00 = Wake-up pin Disable in Deep Power-down mode. 849 * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. 850 * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. 851 * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. 852 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 853 * @var CLK_T::PMUSTS 854 * Offset: 0x94 Power Manager Status Register 855 * --------------------------------------------------------------------------------------------------- 856 * |Bits |Field |Descriptions 857 * | :----: | :----: | :---- | 858 * |[0] |PINWK0 |Pin 0 Wake-up Flag (Read Only) 859 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0). 860 * | | |This flag is cleared when DPD mode is entered. 861 * |[1] |TMRWK |Timer Wake-up Flag (Read Only) 862 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. 863 * | | |This flag is cleared when DPD or SPD mode is entered. 864 * |[2] |RTCWK |RTC Wake-up Flag (Read Only) 865 * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. 866 * | | |This flag is cleared when DPD or SPD mode is entered. 867 * |[3] |PINWK1 |Pin 1 Wake-up Flag (Read Only) 868 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.0). 869 * | | |This flag is cleared when DPD mode is entered. 870 * |[4] |PINWK2 |Pin 2 Wake-up Flag (Read Only) 871 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.2). 872 * | | |This flag is cleared when DPD mode is entered. 873 * |[5] |PINWK3 |Pin 3 Wake-up Flag (Read Only) 874 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.12). 875 * | | |This flag is cleared when DPD mode is entered. 876 * |[6] |PINWK4 |Pin 4 Wake-up Flag (Read Only) 877 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPF.6). 878 * | | |This flag is cleared when DPD mode is entered. 879 * |[8] |GPAWK |GPA Wake-up Flag (Read Only) 880 * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins. 881 * | | |This flag is cleared when SPD mode is entered. 882 * |[9] |GPBWK |GPB Wake-up Flag (Read Only) 883 * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins. 884 * | | |This flag is cleared when SPD mode is entered. 885 * |[10] |GPCWK |GPC Wake-up Flag (Read Only) 886 * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins. 887 * | | |This flag is cleared when SPD mode is entered. 888 * |[11] |GPDWK |GPD Wake-up Flag (Read Only) 889 * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins. 890 * | | |This flag is cleared when SPD mode is entered. 891 * |[12] |LVRWK |LVR Wake-up Flag (Read Only) 892 * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a LVR happened. 893 * | | |This flag is cleared when SPD mode is entered. 894 * |[13] |BODWK |BOD Wake-up Flag (Read Only) 895 * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a BOD happened. 896 * | | |This flag is cleared when SPD mode is entered. 897 * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) 898 * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a ACMP transition. 899 * | | |This flag is cleared when SPD mode is entered. 900 * |[15] |TAMPERWK |Tamper Wake-up Flag (Read Only) 901 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a Tamper event occurred. 902 * | | |This flag is cleared when SPD mode is entered. 903 * |[31] |CLRWK |Clear Wake-up Flag 904 * | | |0 = No clear. 905 * | | |1 = Clear all wake-up flag. 906 * | | |Note: This bit is auto cleared by hardware. 907 * @var CLK_T::SWKDBCTL 908 * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register 909 * --------------------------------------------------------------------------------------------------- 910 * |Bits |Field |Descriptions 911 * | :----: | :----: | :---- | 912 * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection 913 * | | |0000 = Sample wake-up input once per 1 clocks. 914 * | | |0001 = Sample wake-up input once per 2 clocks. 915 * | | |0010 = Sample wake-up input once per 4 clocks. 916 * | | |0011 = Sample wake-up input once per 8 clocks. 917 * | | |0100 = Sample wake-up input once per 16 clocks. 918 * | | |0101 = Sample wake-up input once per 32 clocks. 919 * | | |0110 = Sample wake-up input once per 64 clocks. 920 * | | |0111 = Sample wake-up input once per 128 clocks. 921 * | | |1000 = Sample wake-up input once per 256 clocks. 922 * | | |1001 = Sample wake-up input once per 2*256 clocks. 923 * | | |1010 = Sample wake-up input once per 4*256 clocks. 924 * | | |1011 = Sample wake-up input once per 8*256 clocks. 925 * | | |1100 = Sample wake-up input once per 16*256 clocks. 926 * | | |1101 = Sample wake-up input once per 32*256 clocks. 927 * | | |1110 = Sample wake-up input once per 64*256 clocks. 928 * | | |1111 = Sample wake-up input once per 128*256 clocks. 929 * | | |Note: De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC). 930 * @var CLK_T::PASWKCTL 931 * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register 932 * --------------------------------------------------------------------------------------------------- 933 * |Bits |Field |Descriptions 934 * | :----: | :----: | :---- | 935 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 936 * | | |0 = GPA group pin wake-up function disabled. 937 * | | |1 = GPA group pin wake-up function Enabled. 938 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 939 * | | |0 = GPA group pin rising edge wake-up function Disabled. 940 * | | |1 = GPA group pin rising edge wake-up function Enabled. 941 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 942 * | | |0 = GPA group pin falling edge wake-up function Disabled. 943 * | | |1 = GPA group pin falling edge wake-up function Enabled. 944 * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select 945 * | | |0000 = GPA.0 wake-up function enabled. 946 * | | |0001 = GPA.1 wake-up function enabled. 947 * | | |0010 = GPA.2 wake-up function enabled. 948 * | | |0011 = GPA.3 wake-up function enabled. 949 * | | |0100 = GPA.4 wake-up function enabled. 950 * | | |0101 = GPA.5 wake-up function enabled. 951 * | | |0110 = GPA.6 wake-up function enabled. 952 * | | |0111 = GPA.7 wake-up function enabled. 953 * | | |1000 = GPA.8 wake-up function enabled. 954 * | | |1001 = GPA.9 wake-up function enabled. 955 * | | |1010 = GPA.10 wake-up function enabled. 956 * | | |1011 = GPA.11 wake-up function enabled. 957 * | | |1100 = GPA.12 wake-up function enabled. 958 * | | |1101 = GPA.13 wake-up function enabled. 959 * | | |1110 = GPA.14 wake-up function enabled. 960 * | | |1111 = GPA.15 wake-up function enabled. 961 * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit 962 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. 963 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. 964 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC). 965 * | | |0 = Standby power-down wake-up pin De-bounce function Disable. 966 * | | |1 = Standby power-down wake-up pin De-bounce function Enable. 967 * | | |The de-bounce function is valid only for edge triggered. 968 * @var CLK_T::PBSWKCTL 969 * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register 970 * --------------------------------------------------------------------------------------------------- 971 * |Bits |Field |Descriptions 972 * | :----: | :----: | :---- | 973 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 974 * | | |0 = GPB group pin wake-up function Disabled. 975 * | | |1 = GPB group pin wake-up function Enabled. 976 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 977 * | | |0 = GPB group pin rising edge wake-up function Disabled. 978 * | | |1 = GPB group pin rising edge wake-up function Enabled. 979 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 980 * | | |0 = GPB group pin falling edge wake-up function Disabled. 981 * | | |1 = GPB group pin falling edge wake-up function Enabled. 982 * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select 983 * | | |0000 = GPB.0 wake-up function enabled. 984 * | | |0001 = GPB.1 wake-up function enabled. 985 * | | |0010 = GPB.2 wake-up function enabled. 986 * | | |0011 = GPB.3 wake-up function enabled. 987 * | | |0100 = GPB.4 wake-up function enabled. 988 * | | |0101 = GPB.5 wake-up function enabled. 989 * | | |0110 = GPB.6 wake-up function enabled. 990 * | | |0111 = GPB.7 wake-up function enabled. 991 * | | |1000 = GPB.8 wake-up function enabled. 992 * | | |1001 = GPB.9 wake-up function enabled. 993 * | | |1010 = GPB.10 wake-up function enabled. 994 * | | |1011 = GPB.11 wake-up function enabled. 995 * | | |1100 = GPB.12 wake-up function enabled. 996 * | | |1101 = GPB.13 wake-up function enabled. 997 * | | |1110 = GPB.14 wake-up function enabled. 998 * | | |1111 = GPB.15 wake-up function enabled. 999 * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit 1000 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. 1001 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. 1002 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC). 1003 * | | |0 = Standby power-down wake-up pin De-bounce function Disable. 1004 * | | |1 = Standby power-down wake-up pin De-bounce function Enable. 1005 * | | |The de-bounce function is valid only for edge triggered. 1006 * @var CLK_T::PCSWKCTL 1007 * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register 1008 * --------------------------------------------------------------------------------------------------- 1009 * |Bits |Field |Descriptions 1010 * | :----: | :----: | :---- | 1011 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1012 * | | |0 = GPC group pin wake-up function Disabled. 1013 * | | |1 = GPC group pin wake-up function Enabled. 1014 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1015 * | | |0 = GPC group pin rising edge wake-up function Disabled. 1016 * | | |1 = GPC group pin rising edge wake-up function Enabled. 1017 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1018 * | | |0 = GPC group pin falling edge wake-up function Disabled. 1019 * | | |1 = GPC group pin falling edge wake-up function Enabled. 1020 * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select 1021 * | | |0000 = GPC.0 wake-up function enabled. 1022 * | | |0001 = GPC.1 wake-up function enabled. 1023 * | | |0010 = GPC.2 wake-up function enabled. 1024 * | | |0011 = GPC.3 wake-up function enabled. 1025 * | | |0100 = GPC.4 wake-up function enabled. 1026 * | | |0101 = GPC.5 wake-up function enabled. 1027 * | | |0110 = GPC.6 wake-up function enabled. 1028 * | | |0111 = GPC.7 wake-up function enabled. 1029 * | | |1000 = GPC.8 wake-up function enabled. 1030 * | | |1001 = GPC.9 wake-up function enabled. 1031 * | | |1010 = GPC.10 wake-up function enabled. 1032 * | | |1011 = GPC.11 wake-up function enabled. 1033 * | | |1100 = GPC.12 wake-up function enabled. 1034 * | | |1101 = GPC.13 wake-up function enabled. 1035 * | | |1110 = Reserved. 1036 * | | |1111 = Reserved. 1037 * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit 1038 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. 1039 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. 1040 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 1041 * | | |0 = Standby power-down wake-up pin De-bounce function Disable. 1042 * | | |1 = Standby power-down wake-up pin De-bounce function Enable. 1043 * | | |The de-bounce function is valid only for edge triggered. 1044 * @var CLK_T::PDSWKCTL 1045 * Offset: 0xAC GPD Standby Power-down Wake-up Control Register 1046 * --------------------------------------------------------------------------------------------------- 1047 * |Bits |Field |Descriptions 1048 * | :----: | :----: | :---- | 1049 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1050 * | | |0 = GPD group pin wake-up function Disabled. 1051 * | | |1 = GPD group pin wake-up function Enabled. 1052 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1053 * | | |0 = GPD group pin rising edge wake-up function Disabled. 1054 * | | |1 = GPD group pin rising edge wake-up function Enabled. 1055 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1056 * | | |0 = GPD group pin falling edge wake-up function Disabled. 1057 * | | |1 = GPD group pin falling edge wake-up function Enabled. 1058 * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select 1059 * | | |0000 = GPD.0 wake-up function enabled. 1060 * | | |0001 = GPD.1 wake-up function enabled. 1061 * | | |0010 = GPD.2 wake-up function enabled. 1062 * | | |0011 = GPD.3 wake-up function enabled. 1063 * | | |0100 = GPD.4 wake-up function enabled. 1064 * | | |0101 = GPD.5 wake-up function enabled. 1065 * | | |0110 = GPD.6 wake-up function enabled. 1066 * | | |0111 = GPD.7 wake-up function enabled. 1067 * | | |1000 = GPD.8 wake-up function enabled. 1068 * | | |1001 = GPD.9 wake-up function enabled. 1069 * | | |1010 = GPD.10 wake-up function enabled. 1070 * | | |1011 = GPD.11 wake-up function enabled. 1071 * | | |1100 = GPD.12 wake-up function enabled. 1072 * | | |1101 = Reserved. 1073 * | | |1110 = GPD.14 wake-up function enabled. 1074 * | | |1111 = Reserved. 1075 * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit 1076 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. 1077 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. 1078 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC). 1079 * | | |0 = Standby power-down wake-up pin De-bounce function Disable. 1080 * | | |1 = Standby power-down wake-up pin De-bounce function Enable. 1081 * | | |The de-bounce function is valid only for edge triggered. 1082 * @var CLK_T::IOPDCTL 1083 * Offset: 0xB0 GPIO Standby Power-down Control Register 1084 * --------------------------------------------------------------------------------------------------- 1085 * |Bits |Field |Descriptions 1086 * | :----: | :----: | :---- | 1087 * |[0] |IOHR |GPIO Hold Release 1088 * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status. 1089 * | | |After chip was waked up from standby Power-down mode, the I/O still keeps hold status until user sets this bit to release I/O hold status. 1090 * | | |Note: This bit is auto cleared by hardware. 1091 * @var CLK_T::HXTFSEL 1092 * Offset: 0xB4 HXT Filter Select Control Register 1093 * --------------------------------------------------------------------------------------------------- 1094 * |Bits |Field |Descriptions 1095 * | :----: | :----: | :---- | 1096 * |[0] |HXTFSEL |HXT Filter Select 1097 * | | |0 = HXT frequency is > 12MHz. 1098 * | | |1 = HXT frequency is <= 12MHz. 1099 * | | |Note: This bit is auto cleared by hardware. 1100 */ 1101 1102 1103 __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ 1104 __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ 1105 __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ 1106 __IO uint32_t APBCLK1; /*!< [0x000C] APB Devices Clock Enable Control Register 1 */ 1107 __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ 1108 __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ 1109 __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ 1110 __IO uint32_t CLKSEL3; /*!< [0x001C] Clock Source Select Control Register 3 */ 1111 __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ 1112 __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ 1113 __I uint32_t RESERVE0[2]; 1114 __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ 1115 __I uint32_t RESERVE7[1]; 1116 __I uint32_t RESERVE1[2]; 1117 __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ 1118 __I uint32_t RESERVE2[3]; 1119 __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ 1120 __I uint32_t RESERVE3[3]; 1121 __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ 1122 __I uint32_t RESERVE4[3]; 1123 __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ 1124 __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ 1125 __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Detector Upper Boundary Register */ 1126 __IO uint32_t CDLOWB; /*!< [0x007C] Clock Frequency Detector Low Boundary Register */ 1127 __I uint32_t RESERVE5[4]; 1128 __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ 1129 __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ 1130 __I uint32_t RESERVE6[1]; 1131 __IO uint32_t SWKDBCTL; /*!< [0x009C] Standby Power-down Wake-up De-bounce Control Register */ 1132 __IO uint32_t PASWKCTL; /*!< [0x00A0] GPA Standby Power-down Wake-up Control Register */ 1133 __IO uint32_t PBSWKCTL; /*!< [0x00A4] GPB Standby Power-down Wake-up Control Register */ 1134 __IO uint32_t PCSWKCTL; /*!< [0x00A8] GPC Standby Power-down Wake-up Control Register */ 1135 __IO uint32_t PDSWKCTL; /*!< [0x00AC] GPD Standby Power-down Wake-up Control Register */ 1136 __IO uint32_t IOPDCTL; /*!< [0x00B0] GPIO Standby Power-down Control Register */ 1137 __IO uint32_t HXTFSEL; /*!< [0x00B4] HXT Filter Select Control Register */ 1138 1139 } CLK_T; 1140 1141 /** 1142 @addtogroup CLK_CONST CLK Bit Field Definition 1143 Constant Definitions for CLK Controller 1144 @{ 1145 */ 1146 1147 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ 1148 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ 1149 1150 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ 1151 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ 1152 1153 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ 1154 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ 1155 1156 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ 1157 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ 1158 1159 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ 1160 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ 1161 1162 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ 1163 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ 1164 1165 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ 1166 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ 1167 1168 #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ 1169 #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ 1170 1171 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ 1172 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ 1173 1174 #define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ 1175 #define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ 1176 1177 #define CLK_PWRCTL_HIRC48EN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48EN Position */ 1178 #define CLK_PWRCTL_HIRC48EN_Msk (0x1ul << CLK_PWRCTL_HIRC48EN_Pos) /*!< CLK_T::PWRCTL: HIRC48EN Mask */ 1179 1180 #define CLK_PWRCTL_MIRC1P2MEN_Pos (20) /*!< CLK_T::PWRCTL: MIRC1P2MEN Position */ 1181 #define CLK_PWRCTL_MIRC1P2MEN_Msk (0x1ul << CLK_PWRCTL_MIRC1P2MEN_Pos) /*!< CLK_T::PWRCTL: MIRC1P2MEN Mask */ 1182 1183 #define CLK_PWRCTL_MIRCEN_Pos (21) /*!< CLK_T::PWRCTL: MIRCEN Position */ 1184 #define CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos) /*!< CLK_T::PWRCTL: MIRCEN Mask */ 1185 1186 #define CLK_AHBCLK_PDMA0CKEN_Pos (0) /*!< CLK_T::AHBCLK: PDMA0CKEN Position */ 1187 #define CLK_AHBCLK_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA0CKEN Mask */ 1188 1189 #define CLK_AHBCLK_PDMA1CKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMA1CKEN Position */ 1190 #define CLK_AHBCLK_PDMA1CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA1CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA1CKEN Mask */ 1191 1192 #define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ 1193 #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ 1194 1195 #define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ 1196 #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ 1197 1198 #define CLK_AHBCLK_EXSTCKEN_Pos (4) /*!< CLK_T::AHBCLK: EXSTCKEN Position */ 1199 #define CLK_AHBCLK_EXSTCKEN_Msk (0x1ul << CLK_AHBCLK_EXSTCKEN_Pos) /*!< CLK_T::AHBCLK: EXSTCKEN Mask */ 1200 1201 #define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ 1202 #define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ 1203 1204 #define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ 1205 #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ 1206 1207 #define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ 1208 #define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ 1209 1210 #define CLK_AHBCLK_KSCKEN_Pos (13) /*!< CLK_T::AHBCLK: KSCKEN Position */ 1211 #define CLK_AHBCLK_KSCKEN_Msk (0x1ul << CLK_AHBCLK_KSCKEN_Pos) /*!< CLK_T::AHBCLK: KSCKEN Mask */ 1212 1213 #define CLK_AHBCLK_TRACECKEN_Pos (14) /*!< CLK_T::AHBCLK: TRACECKEN Position */ 1214 #define CLK_AHBCLK_TRACECKEN_Msk (0x1ul << CLK_AHBCLK_TRACECKEN_Pos) /*!< CLK_T::AHBCLK: TRACECKEN Mask */ 1215 1216 #define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ 1217 #define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ 1218 1219 #define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ 1220 #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ 1221 1222 #define CLK_AHBCLK_SRAM0CKEN_Pos (20) /*!< CLK_T::AHBCLK: SRAM0CKEN Position */ 1223 #define CLK_AHBCLK_SRAM0CKEN_Msk (0x1ul << CLK_AHBCLK_SRAM0CKEN_Pos) /*!< CLK_T::AHBCLK: SRAM0CKEN Mask */ 1224 1225 #define CLK_AHBCLK_SRAM1CKEN_Pos (21) /*!< CLK_T::AHBCLK: SRAM1CKEN Position */ 1226 #define CLK_AHBCLK_SRAM1CKEN_Msk (0x1ul << CLK_AHBCLK_SRAM1CKEN_Pos) /*!< CLK_T::AHBCLK: SRAM1CKEN Mask */ 1227 1228 #define CLK_AHBCLK_SRAM2CKEN_Pos (22) /*!< CLK_T::AHBCLK: SRAM2CKEN Position */ 1229 #define CLK_AHBCLK_SRAM2CKEN_Msk (0x1ul << CLK_AHBCLK_SRAM2CKEN_Pos) /*!< CLK_T::AHBCLK: SRAM2CKEN Mask */ 1230 1231 #define CLK_AHBCLK_GPACKEN_Pos (24) /*!< CLK_T::AHBCLK: GPACKEN Position */ 1232 #define CLK_AHBCLK_GPACKEN_Msk (0x1ul << CLK_AHBCLK_GPACKEN_Pos) /*!< CLK_T::AHBCLK: GPACKEN Mask */ 1233 1234 #define CLK_AHBCLK_GPBCKEN_Pos (25) /*!< CLK_T::AHBCLK: GPBCKEN Position */ 1235 #define CLK_AHBCLK_GPBCKEN_Msk (0x1ul << CLK_AHBCLK_GPBCKEN_Pos) /*!< CLK_T::AHBCLK: GPBCKEN Mask */ 1236 1237 #define CLK_AHBCLK_GPCCKEN_Pos (26) /*!< CLK_T::AHBCLK: GPCCKEN Position */ 1238 #define CLK_AHBCLK_GPCCKEN_Msk (0x1ul << CLK_AHBCLK_GPCCKEN_Pos) /*!< CLK_T::AHBCLK: GPCCKEN Mask */ 1239 1240 #define CLK_AHBCLK_GPDCKEN_Pos (27) /*!< CLK_T::AHBCLK: GPDCKEN Position */ 1241 #define CLK_AHBCLK_GPDCKEN_Msk (0x1ul << CLK_AHBCLK_GPDCKEN_Pos) /*!< CLK_T::AHBCLK: GPDCKEN Mask */ 1242 1243 #define CLK_AHBCLK_GPECKEN_Pos (28) /*!< CLK_T::AHBCLK: GPECKEN Position */ 1244 #define CLK_AHBCLK_GPECKEN_Msk (0x1ul << CLK_AHBCLK_GPECKEN_Pos) /*!< CLK_T::AHBCLK: GPECKEN Mask */ 1245 1246 #define CLK_AHBCLK_GPFCKEN_Pos (29) /*!< CLK_T::AHBCLK: GPFCKEN Position */ 1247 #define CLK_AHBCLK_GPFCKEN_Msk (0x1ul << CLK_AHBCLK_GPFCKEN_Pos) /*!< CLK_T::AHBCLK: GPFCKEN Mask */ 1248 1249 #define CLK_AHBCLK_GPGCKEN_Pos (30) /*!< CLK_T::AHBCLK: GPGCKEN Position */ 1250 #define CLK_AHBCLK_GPGCKEN_Msk (0x1ul << CLK_AHBCLK_GPGCKEN_Pos) /*!< CLK_T::AHBCLK: GPGCKEN Mask */ 1251 1252 #define CLK_AHBCLK_GPHCKEN_Pos (31) /*!< CLK_T::AHBCLK: GPHCKEN Position */ 1253 #define CLK_AHBCLK_GPHCKEN_Msk (0x1ul << CLK_AHBCLK_GPHCKEN_Pos) /*!< CLK_T::AHBCLK: GPHCKEN Mask */ 1254 1255 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ 1256 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ 1257 1258 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ 1259 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ 1260 1261 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ 1262 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ 1263 1264 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ 1265 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ 1266 1267 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ 1268 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ 1269 1270 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ 1271 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ 1272 1273 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ 1274 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ 1275 1276 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ 1277 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ 1278 1279 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ 1280 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ 1281 1282 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ 1283 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ 1284 1285 #define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ 1286 #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ 1287 1288 #define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ 1289 #define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ 1290 1291 #define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ 1292 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ 1293 1294 #define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ 1295 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ 1296 1297 #define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ 1298 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ 1299 1300 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ 1301 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ 1302 1303 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ 1304 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ 1305 1306 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ 1307 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ 1308 1309 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ 1310 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ 1311 1312 #define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ 1313 #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ 1314 1315 #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ 1316 #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ 1317 1318 #define CLK_APBCLK0_TAMPERCKEN_Pos (22) /*!< CLK_T::APBCLK0: TAMPERCKEN Position */ 1319 #define CLK_APBCLK0_TAMPERCKEN_Msk (0x1ul << CLK_APBCLK0_TAMPERCKEN_Pos) /*!< CLK_T::APBCLK0: TAMPERCKEN Mask */ 1320 1321 #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ 1322 #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ 1323 1324 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ 1325 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ 1326 1327 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ 1328 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ 1329 1330 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ 1331 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ 1332 1333 #define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ 1334 #define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ 1335 1336 #define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ 1337 #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ 1338 1339 #define CLK_APBCLK0_EWDTCKEN_Pos (31) /*!< CLK_T::APBCLK0: EWDTCKEN Position */ 1340 #define CLK_APBCLK0_EWDTCKEN_Msk (0x1ul << CLK_APBCLK0_EWDTCKEN_Pos) /*!< CLK_T::APBCLK0: EWDTCKEN Mask */ 1341 1342 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ 1343 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ 1344 1345 #define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ 1346 #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ 1347 1348 #define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ 1349 #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ 1350 1351 #define CLK_APBCLK1_TMR4CKEN_Pos (4) /*!< CLK_T::APBCLK1: TMR4CKEN Position */ 1352 #define CLK_APBCLK1_TMR4CKEN_Msk (0x1ul << CLK_APBCLK1_TMR4CKEN_Pos) /*!< CLK_T::APBCLK1: TMR4CKEN Mask */ 1353 1354 #define CLK_APBCLK1_TMR5CKEN_Pos (5) /*!< CLK_T::APBCLK1: TMR5CKEN Position */ 1355 #define CLK_APBCLK1_TMR5CKEN_Msk (0x1ul << CLK_APBCLK1_TMR5CKEN_Pos) /*!< CLK_T::APBCLK1: TMR5CKEN Mask */ 1356 1357 #define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ 1358 #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ 1359 1360 #define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ 1361 #define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ 1362 1363 #define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ 1364 #define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ 1365 1366 #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ 1367 #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ 1368 1369 #define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ 1370 #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ 1371 1372 #define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ 1373 #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ 1374 1375 #define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ 1376 #define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ 1377 1378 #define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ 1379 #define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ 1380 1381 #define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ 1382 #define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ 1383 1384 #define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ 1385 #define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ 1386 1387 #define CLK_APBCLK1_LCDCKEN_Pos (24) /*!< CLK_T::APBCLK1: LCDCKEN Position */ 1388 #define CLK_APBCLK1_LCDCKEN_Msk (0x1ul << CLK_APBCLK1_LCDCKEN_Pos) /*!< CLK_T::APBCLK1: LCKCKEN Mask */ 1389 1390 #define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ 1391 #define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ 1392 1393 #define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ 1394 #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ 1395 1396 #define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ 1397 #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ 1398 1399 #define CLK_APBCLK1_LCDCPCKEN_Pos (28) /*!< CLK_T::APBCLK1: LCDCPCKEN Position */ 1400 #define CLK_APBCLK1_LCDCPCKEN_Msk (0x1ul << CLK_APBCLK1_LCDCPCKEN_Pos) /*!< CLK_T::APBCLK1: LCDCPCKEN Mask */ 1401 1402 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ 1403 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ 1404 1405 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ 1406 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ 1407 1408 #define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */ 1409 #define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */ 1410 1411 #define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ 1412 #define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ 1413 1414 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ 1415 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ 1416 1417 #define CLK_CLKSEL1_LCDSEL_Pos (2) /*!< CLK_T::CLKSEL1: LCDSEL Position */ 1418 #define CLK_CLKSEL1_LCDSEL_Msk (0x1ul << CLK_CLKSEL1_LCDSEL_Pos) /*!< CLK_T::CLKSEL1: LCDSEL Mask */ 1419 1420 #define CLK_CLKSEL1_LCDCPSEL_Pos (3) /*!< CLK_T::CLKSEL1: LCDCPSEL Position */ 1421 #define CLK_CLKSEL1_LCDCPSEL_Msk (0x1ul << CLK_CLKSEL1_LCDCPSEL_Pos) /*!< CLK_T::CLKSEL1: LCDCPSEL Mask */ 1422 1423 #define CLK_CLKSEL1_EWDTSEL_Pos (4) /*!< CLK_T::CLKSEL1: EWDTSEL Position */ 1424 #define CLK_CLKSEL1_EWDTSEL_Msk (0x3ul << CLK_CLKSEL1_EWDTSEL_Pos) /*!< CLK_T::CLKSEL1: EWDTSEL Mask */ 1425 1426 #define CLK_CLKSEL1_EWWDTSEL_Pos (6) /*!< CLK_T::CLKSEL1: EWWDTSEL Position */ 1427 #define CLK_CLKSEL1_EWWDTSEL_Msk (0x3ul << CLK_CLKSEL1_EWWDTSEL_Pos) /*!< CLK_T::CLKSEL1: EWWDTSEL Mask */ 1428 1429 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ 1430 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ 1431 1432 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ 1433 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ 1434 1435 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ 1436 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ 1437 1438 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ 1439 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ 1440 1441 #define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ 1442 #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ 1443 1444 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ 1445 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ 1446 1447 #define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ 1448 #define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ 1449 1450 #define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ 1451 #define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ 1452 1453 #define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ 1454 #define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ 1455 1456 #define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ 1457 #define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ 1458 1459 #define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ 1460 #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ 1461 1462 #define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ 1463 #define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ 1464 1465 #define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ 1466 #define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ 1467 1468 #define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ 1469 #define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ 1470 1471 #define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ 1472 #define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ 1473 1474 #define CLK_CLKSEL2_UART0SEL_Pos (16) /*!< CLK_T::CLKSEL2: UART0SEL Position */ 1475 #define CLK_CLKSEL2_UART0SEL_Msk (0x7ul << CLK_CLKSEL2_UART0SEL_Pos) /*!< CLK_T::CLKSEL2: UART0SEL Mask */ 1476 1477 #define CLK_CLKSEL2_UART1SEL_Pos (20) /*!< CLK_T::CLKSEL2: UART1SEL Position */ 1478 #define CLK_CLKSEL2_UART1SEL_Msk (0x7ul << CLK_CLKSEL2_UART1SEL_Pos) /*!< CLK_T::CLKSEL2: UART1SEL Mask */ 1479 1480 #define CLK_CLKSEL2_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL2: UART2SEL Position */ 1481 #define CLK_CLKSEL2_UART2SEL_Msk (0x7ul << CLK_CLKSEL2_UART2SEL_Pos) /*!< CLK_T::CLKSEL2: UART2SEL Mask */ 1482 1483 #define CLK_CLKSEL2_UART3SEL_Pos (28) /*!< CLK_T::CLKSEL2: UART3SEL Position */ 1484 #define CLK_CLKSEL2_UART3SEL_Msk (0x7ul << CLK_CLKSEL2_UART3SEL_Pos) /*!< CLK_T::CLKSEL2: UART3SEL Mask */ 1485 1486 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ 1487 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ 1488 1489 #define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ 1490 #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ 1491 1492 #define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ 1493 #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ 1494 1495 #define CLK_CLKSEL3_TMR4SEL_Pos (8) /*!< CLK_T::CLKSEL3: TMR4SEL Position */ 1496 #define CLK_CLKSEL3_TMR4SEL_Msk (0x7ul << CLK_CLKSEL3_TMR4SEL_Pos) /*!< CLK_T::CLKSEL3: TMR4SEL Mask */ 1497 1498 #define CLK_CLKSEL3_TMR5SEL_Pos (12) /*!< CLK_T::CLKSEL3: TMR5SEL Position */ 1499 #define CLK_CLKSEL3_TMR5SEL_Msk (0x7ul << CLK_CLKSEL3_TMR5SEL_Pos) /*!< CLK_T::CLKSEL3: TMR5SEL Mask */ 1500 1501 #define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ 1502 #define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ 1503 1504 #define CLK_CLKSEL3_UART4SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART4SEL Position */ 1505 #define CLK_CLKSEL3_UART4SEL_Msk (0x7ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ 1506 1507 #define CLK_CLKSEL3_UART5SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART5SEL Position */ 1508 #define CLK_CLKSEL3_UART5SEL_Msk (0x7ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ 1509 1510 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ 1511 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ 1512 1513 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ 1514 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ 1515 1516 #define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ 1517 #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ 1518 1519 #define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ 1520 #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ 1521 1522 #define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ 1523 #define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ 1524 1525 #define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ 1526 #define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ 1527 1528 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ 1529 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ 1530 1531 #define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ 1532 #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ 1533 1534 #define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ 1535 #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ 1536 1537 #define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ 1538 #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ 1539 1540 #define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ 1541 #define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ 1542 1543 #define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ 1544 #define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ 1545 1546 #define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ 1547 #define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ 1548 1549 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ 1550 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ 1551 1552 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ 1553 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ 1554 1555 #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ 1556 #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ 1557 1558 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ 1559 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ 1560 1561 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ 1562 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ 1563 1564 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ 1565 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ 1566 1567 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ 1568 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ 1569 1570 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ 1571 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ 1572 1573 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ 1574 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ 1575 1576 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ 1577 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ 1578 1579 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ 1580 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ 1581 1582 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ 1583 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ 1584 1585 #define CLK_STATUS_MIRCSTB_Pos (5) /*!< CLK_T::STATUS: MIRCSTB Position */ 1586 #define CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos) /*!< CLK_T::STATUS: MIRCSTB Mask */ 1587 1588 #define CLK_STATUS_HIRC48STB_Pos (6) /*!< CLK_T::STATUS: HIRC48STB Position */ 1589 #define CLK_STATUS_HIRC48STB_Msk (0x1ul << CLK_STATUS_HIRC48STB_Pos) /*!< CLK_T::STATUS: HIRC48STB Mask */ 1590 1591 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ 1592 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ 1593 1594 #define CLK_STATUS_EXTLXTSTB_Pos (8) /*!< CLK_T::STATUS: EXTLXTSTB Position */ 1595 #define CLK_STATUS_EXTLXTSTB_Msk (0x1ul << CLK_STATUS_EXTLXTSTB_Pos) /*!< CLK_T::STATUS: EXTLXTSTB Mask */ 1596 1597 #define CLK_STATUS_LIRC32STB_Pos (9) /*!< CLK_T::STATUS: LIRC32STB Position */ 1598 #define CLK_STATUS_LIRC32STB_Msk (0x1ul << CLK_STATUS_LIRC32STB_Pos) /*!< CLK_T::STATUS: LIRC32STB Mask */ 1599 1600 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ 1601 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ 1602 1603 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ 1604 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ 1605 1606 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ 1607 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ 1608 1609 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ 1610 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ 1611 1612 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ 1613 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ 1614 1615 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ 1616 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ 1617 1618 #define CLK_CLKDCTL_HXTFDSEL_Pos (6) /*!< CLK_T::CLKDCTL: HXTFDSEL Position */ 1619 #define CLK_CLKDCTL_HXTFDSEL_Msk (0x1ul << CLK_CLKDCTL_HXTFDSEL_Pos) /*!< CLK_T::CLKDCTL: HXTFDSEL Mask */ 1620 1621 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ 1622 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ 1623 1624 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ 1625 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ 1626 1627 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ 1628 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ 1629 1630 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ 1631 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ 1632 1633 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ 1634 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ 1635 1636 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ 1637 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ 1638 1639 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ 1640 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ 1641 1642 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ 1643 #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ 1644 1645 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ 1646 #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ 1647 1648 #define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ 1649 #define CLK_PMUCTL_PDMSEL_Msk (0x7ul<< CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ 1650 1651 #define CLK_PMUCTL_VDROPEN_Pos (4) /*!< CLK_T::PMUCTL: VDROPEN Position */ 1652 #define CLK_PMUCTL_VDROPEN_Msk (0x1ul<< CLK_PMUCTL_VDROPEN_Pos) /*!< CLK_T::PMUCTL: VDROPEN Mask */ 1653 1654 #define CLK_PMUCTL_WRBUSY_Pos (7) /*!< CLK_T::PMUCTL: WRBUSY Position */ 1655 #define CLK_PMUCTL_WRBUSY_Msk (0x1ul<< CLK_PMUCTL_WRBUSY_Pos) /*!< CLK_T::PMUCTL: WRBUSY Mask */ 1656 1657 #define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ 1658 #define CLK_PMUCTL_WKTMREN_Msk (0x1ul<< CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ 1659 1660 #define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ 1661 #define CLK_PMUCTL_WKTMRIS_Msk (0x7ul<< CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ 1662 1663 #define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ 1664 #define CLK_PMUCTL_WKPINEN_Msk (0x3ul<< CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ 1665 1666 #define CLK_PMUCTL_WKPINEN0_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN0 Position */ 1667 #define CLK_PMUCTL_WKPINEN0_Msk (0x3ul<< CLK_PMUCTL_WKPINEN0_Pos) /*!< CLK_T::PMUCTL: WKPINEN0 Mask */ 1668 1669 #define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ 1670 #define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul<< CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ 1671 1672 #define CLK_PMUCTL_TAMPERWK_Pos (19) /*!< CLK_T::PMUCTL: TAMPERWK Position */ 1673 #define CLK_PMUCTL_TAMPERWK_Msk (0x1ul<< CLK_PMUCTL_TAMPERWK_Pos) /*!< CLK_T::PMUCTL: TAMPERWK Mask */ 1674 1675 #define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ 1676 #define CLK_PMUCTL_RTCWKEN_Msk (0x1ul<< CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ 1677 1678 #define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */ 1679 #define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */ 1680 1681 #define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */ 1682 #define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */ 1683 1684 #define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */ 1685 #define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */ 1686 1687 #define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */ 1688 #define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */ 1689 1690 #define CLK_PMUSTS_PINWK0_Pos (0) /*!< CLK_T::PMUSTS: PINWK0 Position */ 1691 #define CLK_PMUSTS_PINWK0_Msk (0x1ul << CLK_PMUSTS_PINWK0_Pos) /*!< CLK_T::PMUSTS: PINWK0 Mask */ 1692 1693 #define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ 1694 #define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ 1695 1696 #define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ 1697 #define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ 1698 1699 #define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ 1700 #define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ 1701 1702 #define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */ 1703 #define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */ 1704 1705 #define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */ 1706 #define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */ 1707 1708 #define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */ 1709 #define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */ 1710 1711 #define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */ 1712 #define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */ 1713 1714 #define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ 1715 #define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ 1716 1717 #define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ 1718 #define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ 1719 1720 #define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ 1721 #define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ 1722 1723 #define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ 1724 #define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ 1725 1726 #define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ 1727 #define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ 1728 1729 #define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ 1730 #define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ 1731 1732 #define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ 1733 #define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ 1734 1735 #define CLK_PMUSTS_TAMPERWK_Pos (15) /*!< CLK_T::PMUSTS: TAMPERWK Position */ 1736 #define CLK_PMUSTS_TAMPERWK_Msk (0x1ul << CLK_PMUSTS_TAMPERWK_Pos) /*!< CLK_T::PMUSTS: TAMPERWK Mask */ 1737 1738 #define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ 1739 #define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ 1740 1741 #define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ 1742 #define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xFul<< CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ 1743 1744 #define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ 1745 #define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ 1746 1747 #define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ 1748 #define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ 1749 1750 #define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ 1751 #define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ 1752 1753 #define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ 1754 #define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ 1755 1756 #define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ 1757 #define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ 1758 1759 #define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ 1760 #define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ 1761 1762 #define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ 1763 #define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ 1764 1765 #define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ 1766 #define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ 1767 1768 #define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ 1769 #define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ 1770 1771 #define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ 1772 #define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ 1773 1774 #define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ 1775 #define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ 1776 1777 #define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ 1778 #define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ 1779 1780 #define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ 1781 #define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ 1782 1783 #define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ 1784 #define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ 1785 1786 #define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ 1787 #define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ 1788 1789 #define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ 1790 #define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ 1791 1792 #define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ 1793 #define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ 1794 1795 #define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ 1796 #define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ 1797 1798 #define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ 1799 #define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ 1800 1801 #define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ 1802 #define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ 1803 1804 #define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ 1805 #define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ 1806 1807 #define CLK_HXTFSEL_HXTFSEL_Pos (0) /*!< CLK_T::HXTFSEL: HXTFSEL Position */ 1808 #define CLK_HXTFSEL_HXTFSEL_Msk (0x1ul << CLK_HXTFSEL_HXTFSEL_Pos) /*!< CLK_T::HXTFSEL: HXTFSEL Mask */ 1809 1810 1811 /**@}*/ /* CLK_CONST */ 1812 /**@}*/ /* end of CLK register group */ 1813 /**@}*/ /* end of REGISTER group */ 1814 1815 #endif /* __CLK_REG_H__ */ 1816
