1 /**************************************************************************//**
2 * @file clk.c
3 * @version V3.00
4 * @brief M460 series CLK driver source file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9
10 #include "NuMicro.h"
11
12 /** @addtogroup Standard_Driver Standard Driver
13 @{
14 */
15
16 /** @addtogroup CLK_Driver CLK Driver
17 @{
18 */
19
20 /** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
21 @{
22 */
23
24 /**
25 * @brief Disable clock divider output function
26 * @param None
27 * @return None
28 * @details This function disable clock divider output function.
29 */
CLK_DisableCKO(void)30 void CLK_DisableCKO(void)
31 {
32 /* Disable CKO clock source */
33 CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk);
34 }
35
36 /**
37 * @brief This function enable clock divider output module clock,
38 * enable clock divider output function and set frequency selection.
39 * @param[in] u32ClkSrc is frequency divider function clock source. Including :
40 * - \ref CLK_CLKSEL1_CLKOSEL_HXT
41 * - \ref CLK_CLKSEL1_CLKOSEL_LXT
42 * - \ref CLK_CLKSEL1_CLKOSEL_HCLK
43 * - \ref CLK_CLKSEL1_CLKOSEL_HIRC
44 * - \ref CLK_CLKSEL1_CLKOSEL_LIRC
45 * - \ref CLK_CLKSEL1_CLKOSEL_PLLFN_DIV2
46 * - \ref CLK_CLKSEL1_CLKOSEL_PLL_DIV2
47 * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15.
48 * @param[in] u32ClkDivBy1En is clock divided by one enabled.
49 * @return None
50 * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n
51 * The formula is: \n
52 * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n
53 * This function is just used to set CKO clock.
54 * User must enable I/O for CKO clock output pin by themselves. \n
55 */
CLK_EnableCKO(uint32_t u32ClkSrc,uint32_t u32ClkDiv,uint32_t u32ClkDivBy1En)56 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
57 {
58 /* CKO = clock source / 2^(u32ClkDiv + 1) */
59 CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
60
61 /* Enable CKO clock source */
62 CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk;
63
64 /* Select CKO clock source */
65 CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc);
66 }
67
68 /**
69 * @brief Enter to Power-down mode
70 * @param None
71 * @return None
72 * @details This function is used to let system enter to Power-down mode. \n
73 * The register write-protection function should be disabled before using this function.
74 */
CLK_PowerDown(void)75 void CLK_PowerDown(void)
76 {
77 volatile uint32_t u32SysTickTICKINT = 0, u32HIRCTCTL = 0, u32IRCTCTL = 0;
78
79 /* Set the processor uses deep sleep as its low power mode */
80 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
81
82 /* Set system Power-down enabled */
83 CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk);
84
85 /* Store SysTick interrupt and HIRC auto trim setting */
86 u32SysTickTICKINT = SysTick->CTRL & SysTick_CTRL_TICKINT_Msk;
87 u32HIRCTCTL = SYS->HIRCTCTL;
88 u32IRCTCTL = SYS->IRCTCTL;
89
90 /* Disable SysTick interrupt and HIRC auto trim */
91 SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
92 SYS->HIRCTCTL &= (~SYS_HIRCTCTL_FREQSEL_Msk);
93 SYS->IRCTCTL &= (~SYS_IRCTCTL_FREQSEL_Msk);
94
95 /* Chip enter Power-down mode after CPU run WFI instruction */
96 __WFI();
97
98 /* Restore SysTick interrupt and HIRC auto trim setting */
99 if(u32SysTickTICKINT) SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
100 SYS->HIRCTCTL = u32HIRCTCTL;
101 SYS->IRCTCTL = u32IRCTCTL;
102 }
103
104 /**
105 * @brief Enter to Idle mode
106 * @param None
107 * @return None
108 * @details This function let system enter to Idle mode. \n
109 * The register write-protection function should be disabled before using this function.
110 */
CLK_Idle(void)111 void CLK_Idle(void)
112 {
113 /* Set the processor uses sleep as its low power mode */
114 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
115
116 /* Set chip in idle mode because of WFI command */
117 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
118
119 /* Chip enter idle mode after CPU run WFI instruction */
120 __WFI();
121 }
122
123 /**
124 * @brief Get external high speed crystal clock frequency
125 * @param None
126 * @return External high frequency crystal frequency
127 * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
128 */
CLK_GetHXTFreq(void)129 uint32_t CLK_GetHXTFreq(void)
130 {
131 uint32_t u32Freq;
132
133 if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
134 {
135 u32Freq = __HXT;
136 }
137 else
138 {
139 u32Freq = 0UL;
140 }
141
142 return u32Freq;
143 }
144
145
146 /**
147 * @brief Get external low speed crystal clock frequency
148 * @param None
149 * @return External low speed crystal clock frequency
150 * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
151 */
CLK_GetLXTFreq(void)152 uint32_t CLK_GetLXTFreq(void)
153 {
154 uint32_t u32Freq;
155
156 if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk)
157 {
158 u32Freq = __LXT;
159 }
160 else
161 {
162 u32Freq = 0UL;
163 }
164
165 return u32Freq;
166 }
167
168 /**
169 * @brief Get PCLK0 frequency
170 * @param None
171 * @return PCLK0 frequency
172 * @details This function get PCLK0 frequency. The frequency unit is Hz.
173 */
CLK_GetPCLK0Freq(void)174 uint32_t CLK_GetPCLK0Freq(void)
175 {
176 uint32_t u32Freq;
177 SystemCoreClockUpdate();
178
179 if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV1)
180 {
181 u32Freq = SystemCoreClock;
182 }
183 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV2)
184 {
185 u32Freq = SystemCoreClock>>1;
186 }
187 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV4)
188 {
189 u32Freq = SystemCoreClock>>2;
190 }
191 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV8)
192 {
193 u32Freq = SystemCoreClock>>3;
194 }
195 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV16)
196 {
197 u32Freq = SystemCoreClock>>4;
198 }
199 else
200 {
201 u32Freq = SystemCoreClock;
202 }
203
204 return u32Freq;
205 }
206
207
208 /**
209 * @brief Get PCLK1 frequency
210 * @param None
211 * @return PCLK1 frequency
212 * @details This function get PCLK1 frequency. The frequency unit is Hz.
213 */
CLK_GetPCLK1Freq(void)214 uint32_t CLK_GetPCLK1Freq(void)
215 {
216 uint32_t u32Freq;
217 SystemCoreClockUpdate();
218
219 if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV1)
220 {
221 u32Freq = SystemCoreClock;
222 }
223 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV2)
224 {
225 u32Freq = SystemCoreClock>>1;
226 }
227 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV4)
228 {
229 u32Freq = SystemCoreClock>>2;
230 }
231 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV8)
232 {
233 u32Freq = SystemCoreClock>>3;
234 }
235 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV16)
236 {
237 u32Freq = SystemCoreClock>>4;
238 }
239 else
240 {
241 u32Freq = SystemCoreClock;
242 }
243
244 return u32Freq;
245 }
246
247
248 /**
249 * @brief Get HCLK frequency
250 * @param None
251 * @return HCLK frequency
252 * @details This function get HCLK frequency. The frequency unit is Hz.
253 */
CLK_GetHCLKFreq(void)254 uint32_t CLK_GetHCLKFreq(void)
255 {
256 SystemCoreClockUpdate();
257 return SystemCoreClock;
258 }
259
260
261 /**
262 * @brief Get CPU frequency
263 * @param None
264 * @return CPU frequency
265 * @details This function get CPU frequency. The frequency unit is Hz.
266 */
CLK_GetCPUFreq(void)267 uint32_t CLK_GetCPUFreq(void)
268 {
269 SystemCoreClockUpdate();
270 return SystemCoreClock;
271 }
272
273
274 /**
275 * @brief Set HCLK frequency
276 * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 50MHz ~ 200MHz.
277 * @return HCLK frequency
278 * @details This function is used to set HCLK frequency by using PLL. The frequency unit is Hz. \n
279 * Power level and flash access cycle are also set according to HCLK frequency. \n
280 * The register write-protection function should be disabled before using this function.
281 */
CLK_SetCoreClock(uint32_t u32Hclk)282 uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
283 {
284 uint32_t u32HIRCSTB;
285
286 /* Read HIRC clock source stable flag */
287 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
288
289 /* Check HCLK frequency range is 50MHz ~ 200MHz */
290 if(u32Hclk > FREQ_200MHZ)
291 {
292 u32Hclk = FREQ_200MHZ;
293 }
294 else if(u32Hclk < FREQ_50MHZ)
295 {
296 u32Hclk = FREQ_50MHZ;
297 }
298
299 /* Switch HCLK clock source to HIRC clock for safe */
300 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
301 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
302 CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
303 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
304
305 /* Configure PLL setting if HXT clock is stable */
306 if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk)
307 {
308 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);
309 }
310 /* Configure PLL setting if HXT clock is not stable */
311 else
312 {
313 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);
314
315 /* Read HIRC clock source stable flag */
316 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
317 }
318
319 /* Select HCLK clock source to PLL,
320 select HCLK clock source divider as 1,
321 adjust power level, flash access cycle and update system core clock
322 */
323 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
324
325 /* Disable HIRC if HIRC is disabled before setting core clock */
326 if(u32HIRCSTB == 0UL)
327 {
328 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
329 }
330
331 /* Return actually HCLK frequency is PLL frequency divide 1 */
332 return u32Hclk;
333 }
334
335 /**
336 * @brief Set HCLK clock source and HCLK clock divider
337 * @param[in] u32ClkSrc is HCLK clock source. Including :
338 * - \ref CLK_CLKSEL0_HCLKSEL_HXT
339 * - \ref CLK_CLKSEL0_HCLKSEL_LXT
340 * - \ref CLK_CLKSEL0_HCLKSEL_PLL
341 * - \ref CLK_CLKSEL0_HCLKSEL_LIRC
342 * - \ref CLK_CLKSEL0_HCLKSEL_HIRC
343 * @param[in] u32ClkDiv is HCLK clock divider. Including :
344 * - \ref CLK_CLKDIV0_HCLK(x)
345 * @return None
346 * @details This function set HCLK clock source and HCLK clock divider. \n
347 * Power level and flash access cycle are also set according to HCLK operation frequency. \n
348 * The register write-protection function should be disabled before using this function.
349 */
CLK_SetHCLK(uint32_t u32ClkSrc,uint32_t u32ClkDiv)350 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
351 {
352 uint32_t u32HIRCSTB, u32TimeOutCount;
353
354 /* Read HIRC clock source stable flag */
355 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
356
357 /* Switch to HIRC for safe. Avoid HCLK too high when applying new divider. */
358 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
359 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
360 CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
361
362 /* Switch to power level 0 for safe */
363 SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL0;
364 u32TimeOutCount = SystemCoreClock; /* 1 second time-out */
365 while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk)
366 {
367 if(u32TimeOutCount-- == 0) break;
368 }
369
370 /* Set Flash Access Cycle to 8 for safe */
371 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (8);
372
373 /* Apply new Divider */
374 CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
375
376 /* Switch HCLK to new HCLK source */
377 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
378
379 /* Update System Core Clock */
380 SystemCoreClockUpdate();
381
382 /* Set power level according to new HCLK */
383 if(SystemCoreClock <= FREQ_180MHZ)
384 {
385 SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL1;
386 }
387 u32TimeOutCount = SystemCoreClock; /* 1 second time-out */
388 while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk)
389 {
390 if(u32TimeOutCount-- == 0) break;
391 }
392
393 /* Switch flash access cycle to suitable value base on HCLK */
394 if (SystemCoreClock >= FREQ_175MHZ)
395 {
396 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (8);
397 }
398 else if (SystemCoreClock >= FREQ_150MHZ)
399 {
400 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (7);
401 }
402 else if (SystemCoreClock >= FREQ_125MHZ)
403 {
404 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (6);
405 }
406 else if (SystemCoreClock >= FREQ_100MHZ)
407 {
408 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (5);
409 }
410 else if (SystemCoreClock >= FREQ_75MHZ)
411 {
412 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (4);
413 }
414 else if (SystemCoreClock >= FREQ_50MHZ)
415 {
416 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (3);
417 }
418 else if (SystemCoreClock >= FREQ_25MHZ)
419 {
420 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (2);
421 }
422 else /* SystemCoreClock < FREQ_25MHZ */
423 {
424 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (1);
425 }
426
427 /* Disable HIRC if HIRC is disabled before switching HCLK source */
428 if(u32HIRCSTB == 0UL)
429 {
430 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
431 }
432 }
433
434 /**
435 * @brief This function set selected module clock source and module clock divider
436 * @param[in] u32ModuleIdx is module index.
437 * @param[in] u32ClkSrc is module clock source.
438 * @param[in] u32ClkDiv is module clock divider.
439 * @return None
440 * @details Valid parameter combinations listed in following table:
441 *
442 * |Module index |Clock source |Divider |
443 * | :---------------- | :----------------------------------- | :-------------------------- |
444 * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48M |\ref CLK_CLKDIV0_USB(x) |
445 * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL_DIV2 |\ref CLK_CLKDIV0_USB(x) |
446 * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48M |\ref CLK_CLKDIV0_USB(x) |
447 * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL_DIV2 |\ref CLK_CLKDIV0_USB(x) |
448 * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48M |\ref CLK_CLKDIV0_USB(x) |
449 * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL_DIV2 |\ref CLK_CLKDIV0_USB(x) |
450 * |\ref EADC0_MODULE |\ref CLK_CLKSEL0_EADC0SEL_PLLFN_DIV2 |\ref CLK_CLKDIV0_EADC0(x) |
451 * |\ref EADC0_MODULE |\ref CLK_CLKSEL0_EADC0SEL_PLL_DIV2 |\ref CLK_CLKDIV0_EADC0(x) |
452 * |\ref EADC0_MODULE |\ref CLK_CLKSEL0_EADC0SEL_HCLK |\ref CLK_CLKDIV0_EADC0(x) |
453 * |\ref EADC1_MODULE |\ref CLK_CLKSEL0_EADC1SEL_PLLFN_DIV2 |\ref CLK_CLKDIV2_EADC1(x) |
454 * |\ref EADC1_MODULE |\ref CLK_CLKSEL0_EADC1SEL_PLL_DIV2 |\ref CLK_CLKDIV2_EADC1(x) |
455 * |\ref EADC1_MODULE |\ref CLK_CLKSEL0_EADC1SEL_HCLK |\ref CLK_CLKDIV2_EADC1(x) |
456 * |\ref EADC2_MODULE |\ref CLK_CLKSEL0_EADC2SEL_PLLFN_DIV2 |\ref CLK_CLKDIV5_EADC2(x) |
457 * |\ref EADC2_MODULE |\ref CLK_CLKSEL0_EADC2SEL_PLL_DIV2 |\ref CLK_CLKDIV5_EADC2(x) |
458 * |\ref EADC2_MODULE |\ref CLK_CLKSEL0_EADC2SEL_HCLK |\ref CLK_CLKDIV5_EADC2(x) |
459 * |\ref CCAP_MODULE | x | x |
460 * |\ref CCAP_MODULE | x | x |
461 * |\ref CCAP_MODULE | x | x |
462 * |\ref CCAP_MODULE | x | x |
463 * |\ref SEN_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HXT |\ref CLK_CLKDIV3_VSENSE(x) |
464 * |\ref SEN_MODULE |\ref CLK_CLKSEL0_CCAPSEL_PLL_DIV2 |\ref CLK_CLKDIV3_VSENSE(x) |
465 * |\ref SEN_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HCLK |\ref CLK_CLKDIV3_VSENSE(x) |
466 * |\ref SEN_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HIRC |\ref CLK_CLKDIV3_VSENSE(x) |
467 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) |
468 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL_DIV2 |\ref CLK_CLKDIV0_SDH0(x) |
469 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) |
470 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) |
471 * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HXT |\ref CLK_CLKDIV3_SDH1(x) |
472 * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_PLL_DIV2 |\ref CLK_CLKDIV3_SDH1(x) |
473 * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HIRC |\ref CLK_CLKDIV3_SDH1(x) |
474 * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HCLK |\ref CLK_CLKDIV3_SDH1(x) |
475 * |\ref CANFD0_MODULE |\ref CLK_CLKSEL0_CANFD0SEL_HXT |\ref CLK_CLKDIV5_CANFD0(x) |
476 * |\ref CANFD0_MODULE |\ref CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 |\ref CLK_CLKDIV5_CANFD0(x) |
477 * |\ref CANFD0_MODULE |\ref CLK_CLKSEL0_CANFD0SEL_HCLK |\ref CLK_CLKDIV5_CANFD0(x) |
478 * |\ref CANFD0_MODULE |\ref CLK_CLKSEL0_CANFD0SEL_HIRC |\ref CLK_CLKDIV5_CANFD0(x) |
479 * |\ref CANFD1_MODULE |\ref CLK_CLKSEL0_CANFD1SEL_HXT |\ref CLK_CLKDIV5_CANFD1(x) |
480 * |\ref CANFD1_MODULE |\ref CLK_CLKSEL0_CANFD1SEL_PLL_DIV2 |\ref CLK_CLKDIV5_CANFD1(x) |
481 * |\ref CANFD1_MODULE |\ref CLK_CLKSEL0_CANFD1SEL_HCLK |\ref CLK_CLKDIV5_CANFD1(x) |
482 * |\ref CANFD1_MODULE |\ref CLK_CLKSEL0_CANFD1SEL_HIRC |\ref CLK_CLKDIV5_CANFD1(x) |
483 * |\ref CANFD2_MODULE |\ref CLK_CLKSEL0_CANFD2SEL_HXT |\ref CLK_CLKDIV5_CANFD2(x) |
484 * |\ref CANFD2_MODULE |\ref CLK_CLKSEL0_CANFD2SEL_PLL_DIV2 |\ref CLK_CLKDIV5_CANFD2(x) |
485 * |\ref CANFD2_MODULE |\ref CLK_CLKSEL0_CANFD2SEL_HCLK |\ref CLK_CLKDIV5_CANFD2(x) |
486 * |\ref CANFD2_MODULE |\ref CLK_CLKSEL0_CANFD2SEL_HIRC |\ref CLK_CLKDIV5_CANFD2(x) |
487 * |\ref CANFD3_MODULE |\ref CLK_CLKSEL0_CANFD3SEL_HXT |\ref CLK_CLKDIV5_CANFD3(x) |
488 * |\ref CANFD3_MODULE |\ref CLK_CLKSEL0_CANFD3SEL_PLL_DIV2 |\ref CLK_CLKDIV5_CANFD3(x) |
489 * |\ref CANFD3_MODULE |\ref CLK_CLKSEL0_CANFD3SEL_HCLK |\ref CLK_CLKDIV5_CANFD3(x) |
490 * |\ref CANFD3_MODULE |\ref CLK_CLKSEL0_CANFD3SEL_HIRC |\ref CLK_CLKDIV5_CANFD3(x) |
491 * |\ref EMAC0_MODULE | x | x |
492 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
493 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
494 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
495 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
496 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
497 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
498 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
499 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LIRC | x |
500 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_PLLFN_DIV2 | x |
501 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_PLL_DIV2 | x |
502 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
503 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
504 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |
505 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x |
506 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
507 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
508 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
509 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
510 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |
511 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x |
512 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
513 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
514 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
515 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
516 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |
517 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x |
518 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
519 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
520 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
521 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
522 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |
523 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x |
524 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
525 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
526 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) |
527 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL_DIV2 |\ref CLK_CLKDIV0_UART0(x) |
528 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) |
529 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) |
530 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) |
531 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL_DIV2 |\ref CLK_CLKDIV0_UART1(x) |
532 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) |
533 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) |
534 * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x |
535 * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
536 * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_HCLK | x |
537 * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PCLK0 | x |
538 * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_HCLK | x |
539 * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PCLK1 | x |
540 * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x |
541 * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL_DIV2 | x |
542 * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x |
543 * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x |
544 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |
545 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL_DIV2 | x |
546 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x |
547 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |
548 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC48M | x |
549 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLLFN_DIV2 | x |
550 * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_HCLK | x |
551 * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x |
552 * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_HCLK | x |
553 * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x |
554 * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_HXT | x |
555 * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_PLL_DIV2 | x |
556 * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_PCLK1 | x |
557 * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_HIRC | x |
558 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x |
559 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL_DIV2 | x |
560 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x |
561 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x |
562 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC48M | x |
563 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLLFN_DIV2 | x |
564 * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_HXT |\ref CLK_CLKDIV2_I2S1(x) |
565 * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_PLL_DIV2 |\ref CLK_CLKDIV2_I2S1(x) |
566 * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_PCLK1 |\ref CLK_CLKDIV2_I2S1(x) |
567 * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_HIRC |\ref CLK_CLKDIV2_I2S1(x) |
568 * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_HIRC48M |\ref CLK_CLKDIV2_I2S1(x) |
569 * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_PLLFN_DIV2 |\ref CLK_CLKDIV2_I2S1(x) |
570 * |\ref UART8_MODULE |\ref CLK_CLKSEL2_UART8SEL_HXT |\ref CLK_CLKDIV5_UART8(x) |
571 * |\ref UART8_MODULE |\ref CLK_CLKSEL2_UART8SEL_PLL_DIV2 |\ref CLK_CLKDIV5_UART8(x) |
572 * |\ref UART8_MODULE |\ref CLK_CLKSEL2_UART8SEL_LXT |\ref CLK_CLKDIV5_UART8(x) |
573 * |\ref UART8_MODULE |\ref CLK_CLKSEL2_UART8SEL_HIRC |\ref CLK_CLKDIV5_UART8(x) |
574 * |\ref UART9_MODULE |\ref CLK_CLKSEL2_UART9SEL_HXT |\ref CLK_CLKDIV5_UART9(x) |
575 * |\ref UART9_MODULE |\ref CLK_CLKSEL2_UART9SEL_PLL_DIV2 |\ref CLK_CLKDIV5_UART9(x) |
576 * |\ref UART9_MODULE |\ref CLK_CLKSEL2_UART9SEL_LXT |\ref CLK_CLKDIV5_UART9(x) |
577 * |\ref UART9_MODULE |\ref CLK_CLKSEL2_UART9SEL_HIRC |\ref CLK_CLKDIV5_UART9(x) |
578 * |\ref TRNG_MODULE |\ref CLK_CLKSEL2_TRNGSEL_LXT | x |
579 * |\ref TRNG_MODULE |\ref CLK_CLKSEL2_TRNGSEL_LIRC | x |
580 * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_HXT |\ref CLK_CLKDIV1_PSIO(x) |
581 * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_LXT |\ref CLK_CLKDIV1_PSIO(x) |
582 * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_PCLK1 |\ref CLK_CLKDIV1_PSIO(x) |
583 * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_PLL_DIV2 |\ref CLK_CLKDIV1_PSIO(x) |
584 * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_LIRC |\ref CLK_CLKDIV1_PSIO(x) |
585 * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_HIRC |\ref CLK_CLKDIV1_PSIO(x) |
586 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
587 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL_DIV2 |\ref CLK_CLKDIV1_SC0(x) |
588 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |
589 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
590 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) |
591 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL_DIV2 |\ref CLK_CLKDIV1_SC1(x) |
592 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) |
593 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) |
594 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) |
595 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL_DIV2 |\ref CLK_CLKDIV1_SC2(x) |
596 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) |
597 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) |
598 * |\ref KPI_MODULE |\ref CLK_CLKSEL3_KPISEL_HXT |\ref CLK_CLKDIV2_KPI(x) |
599 * |\ref KPI_MODULE |\ref CLK_CLKSEL3_KPISEL_LIRC |\ref CLK_CLKDIV2_KPI(x) |
600 * |\ref KPI_MODULE |\ref CLK_CLKSEL3_KPISEL_HIRC |\ref CLK_CLKDIV2_KPI(x) |
601 * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_HXT | x |
602 * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_PLL_DIV2 | x |
603 * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_PCLK1 | x |
604 * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_HIRC | x |
605 * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_HIRC48M | x |
606 * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_PLLFN_DIV2 | x |
607 * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_HXT | x |
608 * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_PLL_DIV2 | x |
609 * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_PCLK0 | x |
610 * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_HIRC | x |
611 * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_HIRC48M | x |
612 * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_PLLFN_DIV2 | x |
613 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT |\ref CLK_CLKDIV2_I2S0(x) |
614 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL_DIV2 |\ref CLK_CLKDIV2_I2S0(x) |
615 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK0 |\ref CLK_CLKDIV2_I2S0(x) |
616 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC |\ref CLK_CLKDIV2_I2S0(x) |
617 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC48M |\ref CLK_CLKDIV2_I2S0(x) |
618 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLLFN_DIV2 |\ref CLK_CLKDIV2_I2S0(x) |
619 * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HXT |\ref CLK_CLKDIV4_UART6(x) |
620 * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART6(x) |
621 * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_LXT |\ref CLK_CLKDIV4_UART6(x) |
622 * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HIRC |\ref CLK_CLKDIV4_UART6(x) |
623 * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HXT |\ref CLK_CLKDIV4_UART7(x) |
624 * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART7(x) |
625 * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_LXT |\ref CLK_CLKDIV4_UART7(x) |
626 * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HIRC |\ref CLK_CLKDIV4_UART7(x) |
627 * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) |
628 * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART2(x) |
629 * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) |
630 * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) |
631 * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) |
632 * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART3(x) |
633 * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) |
634 * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) |
635 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) |
636 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART4(x) |
637 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) |
638 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) |
639 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) |
640 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART5(x) |
641 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) |
642 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) |
643 * |\ref RTC_MODULE |\ref RTC_LXTCTL_RTCCKSEL_LXT | x |
644 * |\ref RTC_MODULE |\ref RTC_LXTCTL_RTCCKSEL_LIRC | x |
645 * |\ref SPI4_MODULE |\ref CLK_CLKSEL4_SPI4SEL_HXT | x |
646 * |\ref SPI4_MODULE |\ref CLK_CLKSEL4_SPI4SEL_PLL_DIV2 | x |
647 * |\ref SPI4_MODULE |\ref CLK_CLKSEL4_SPI4SEL_PCLK1 | x |
648 * |\ref SPI4_MODULE |\ref CLK_CLKSEL4_SPI4SEL_HIRC | x |
649 * |\ref SPI5_MODULE |\ref CLK_CLKSEL4_SPI5SEL_HXT | x |
650 * |\ref SPI5_MODULE |\ref CLK_CLKSEL4_SPI5SEL_PLL_DIV2 | x |
651 * |\ref SPI5_MODULE |\ref CLK_CLKSEL4_SPI5SEL_PCLK0 | x |
652 * |\ref SPI5_MODULE |\ref CLK_CLKSEL4_SPI5SEL_HIRC | x |
653 * |\ref SPI6_MODULE |\ref CLK_CLKSEL4_SPI6SEL_HXT | x |
654 * |\ref SPI6_MODULE |\ref CLK_CLKSEL4_SPI6SEL_PLL_DIV2 | x |
655 * |\ref SPI6_MODULE |\ref CLK_CLKSEL4_SPI6SEL_PCLK1 | x |
656 * |\ref SPI6_MODULE |\ref CLK_CLKSEL4_SPI6SEL_HIRC | x |
657 * |\ref SPI7_MODULE |\ref CLK_CLKSEL4_SPI7SEL_HXT | x |
658 * |\ref SPI7_MODULE |\ref CLK_CLKSEL4_SPI7SEL_PLL_DIV2 | x |
659 * |\ref SPI7_MODULE |\ref CLK_CLKSEL4_SPI7SEL_PCLK0 | x |
660 * |\ref SPI7_MODULE |\ref CLK_CLKSEL4_SPI7SEL_HIRC | x |
661 * |\ref SPI8_MODULE |\ref CLK_CLKSEL4_SPI8SEL_HXT | x |
662 * |\ref SPI8_MODULE |\ref CLK_CLKSEL4_SPI8SEL_PLL_DIV2 | x |
663 * |\ref SPI8_MODULE |\ref CLK_CLKSEL4_SPI8SEL_PCLK1 | x |
664 * |\ref SPI8_MODULE |\ref CLK_CLKSEL4_SPI8SEL_HIRC | x |
665 * |\ref SPI9_MODULE |\ref CLK_CLKSEL4_SPI9SEL_HXT | x |
666 * |\ref SPI9_MODULE |\ref CLK_CLKSEL4_SPI9SEL_PLL_DIV2 | x |
667 * |\ref SPI9_MODULE |\ref CLK_CLKSEL4_SPI9SEL_PCLK0 | x |
668 * |\ref SPI9_MODULE |\ref CLK_CLKSEL4_SPI9SEL_HIRC | x |
669 * |\ref SPI10_MODULE |\ref CLK_CLKSEL4_SPI10SEL_HXT | x |
670 * |\ref SPI10_MODULE |\ref CLK_CLKSEL4_SPI10SEL_PLL_DIV2 | x |
671 * |\ref SPI10_MODULE |\ref CLK_CLKSEL4_SPI10SEL_PCLK1 | x |
672 * |\ref SPI10_MODULE |\ref CLK_CLKSEL4_SPI10SEL_HIRC | x |
673 *
674 */
CLK_SetModuleClock(uint32_t u32ModuleIdx,uint32_t u32ClkSrc,uint32_t u32ClkDiv)675 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
676 {
677 uint32_t u32Sel = 0UL, u32Div = 0UL;
678 uint32_t au32SelTbl[5] = {0x0UL, 0x4UL, 0x8UL, 0xCUL, 0x4CUL}; /* CLK_CLKSEL0~4 */
679 uint32_t au32DivTbl[6] = {0x0UL, 0x4UL, 0x8UL, 0xCUL, 0x10UL, 0x1C}; /* CLK_CLKDIV0~5 */
680 uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;
681
682 if(u32ModuleIdx == RTC_MODULE) /* RTC clock source configuration */
683 {
684 if(u32RTCCKEN == 0UL)
685 {
686 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */
687 }
688
689 /* Select RTC clock source */
690 RTC->LXTCTL = (RTC->LXTCTL & (~RTC_LXTCTL_RTCCKSEL_Msk)) | (u32ClkSrc);
691
692 if(u32RTCCKEN == 0UL)
693 {
694 CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */
695 }
696 }
697 else /* Others clock source configuration */
698 {
699 /* Configure clock source divider */
700 switch(u32ModuleIdx)
701 {
702 /* For 8 bits divider */
703 case EADC0_MODULE: CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_EADC0DIV_Msk)) | (u32ClkDiv); break;
704 case SDH0_MODULE: CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_SDH0DIV_Msk)) | (u32ClkDiv); break;
705 case SC0_MODULE: CLK->CLKDIV1 = (CLK->CLKDIV1 & (~CLK_CLKDIV1_SC0DIV_Msk)) | (u32ClkDiv); break;
706 case SC1_MODULE: CLK->CLKDIV1 = (CLK->CLKDIV1 & (~CLK_CLKDIV1_SC1DIV_Msk)) | (u32ClkDiv); break;
707 case SC2_MODULE: CLK->CLKDIV1 = (CLK->CLKDIV1 & (~CLK_CLKDIV1_SC2DIV_Msk)) | (u32ClkDiv); break;
708 case PSIO_MODULE: CLK->CLKDIV1 = (CLK->CLKDIV1 & (~CLK_CLKDIV1_PSIODIV_Msk)) | (u32ClkDiv); break;
709 case KPI_MODULE: CLK->CLKDIV2 = (CLK->CLKDIV2 & (~CLK_CLKDIV2_KPIDIV_Msk)) | (u32ClkDiv); break;
710 case EADC1_MODULE: CLK->CLKDIV2 = (CLK->CLKDIV2 & (~CLK_CLKDIV2_EADC1DIV_Msk)) | (u32ClkDiv); break;
711 case SEN_MODULE: CLK->CLKDIV3 = (CLK->CLKDIV3 & (~CLK_CLKDIV3_VSENSEDIV_Msk)) | (u32ClkDiv); break;
712 case SDH1_MODULE: CLK->CLKDIV3 = (CLK->CLKDIV3 & (~CLK_CLKDIV3_SDH1DIV_Msk)) | (u32ClkDiv); break;
713 case EADC2_MODULE: CLK->CLKDIV5 = (CLK->CLKDIV5 & (~CLK_CLKDIV5_EADC2DIV_Msk)) | (u32ClkDiv); break;
714
715 /* Others */
716 default:
717 {
718 if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
719 {
720 /* Get clock divider control register address */
721 u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
722 /* Apply new divider */
723 M32(u32Div) = (M32(u32Div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
724 }
725 }
726 break;
727 }
728
729 /* Configure clock source */
730 if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
731 {
732 /* Get clock select control register address */
733 u32Sel = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
734 /* Set new clock selection setting */
735 M32(u32Sel) = (M32(u32Sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
736 }
737 }
738
739 }
740
741 /**
742 * @brief Set SysTick clock source
743 * @param[in] u32ClkSrc is module clock source. Including:
744 * - \ref CLK_CLKSEL0_STCLKSEL_HXT
745 * - \ref CLK_CLKSEL0_STCLKSEL_LXT
746 * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
747 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
748 * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
749 * @return None
750 * @details This function set SysTick clock source. \n
751 * The register write-protection function should be disabled before using this function.
752 */
CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)753 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
754 {
755 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
756 }
757
758 /**
759 * @brief Enable clock source
760 * @param[in] u32ClkMask is clock source mask. Including :
761 * - \ref CLK_PWRCTL_HXTEN_Msk
762 * - \ref CLK_PWRCTL_LXTEN_Msk
763 * - \ref CLK_PWRCTL_HIRCEN_Msk
764 * - \ref CLK_PWRCTL_LIRCEN_Msk
765 * - \ref CLK_PWRCTL_HIRC48MEN_Msk
766 * @return None
767 * @details This function enable clock source. \n
768 * The register write-protection function should be disabled before using this function.
769 */
CLK_EnableXtalRC(uint32_t u32ClkMask)770 void CLK_EnableXtalRC(uint32_t u32ClkMask)
771 {
772 CLK->PWRCTL |= u32ClkMask;
773 }
774
775 /**
776 * @brief Disable clock source
777 * @param[in] u32ClkMask is clock source mask. Including :
778 * - \ref CLK_PWRCTL_HXTEN_Msk
779 * - \ref CLK_PWRCTL_LXTEN_Msk
780 * - \ref CLK_PWRCTL_HIRCEN_Msk
781 * - \ref CLK_PWRCTL_LIRCEN_Msk
782 * - \ref CLK_PWRCTL_HIRC48MEN_Msk
783 * @return None
784 * @details This function disable clock source. \n
785 * The register write-protection function should be disabled before using this function.
786 */
CLK_DisableXtalRC(uint32_t u32ClkMask)787 void CLK_DisableXtalRC(uint32_t u32ClkMask)
788 {
789 CLK->PWRCTL &= ~u32ClkMask;
790 }
791
792 /**
793 * @brief Enable module clock
794 * @param[in] u32ModuleIdx is module index. Including :
795 * - \ref PDMA0_MODULE
796 * - \ref PDMA1_MODULE
797 * - \ref ISP_MODULE
798 * - \ref EBI_MODULE
799 * - \ref ST_MODULE
800 * - \ref EMAC0_MODULE
801 * - \ref SDH0_MODULE
802 * - \ref SDH1_MODULE
803 * - \ref CRC_MODULE
804 * - \ref CCAP_MODULE
805 * - \ref SEN_MODULE
806 * - \ref HSUSBD_MODULE
807 * - \ref HSOTG_MODULE
808 * - \ref HBI_MODULE
809 * - \ref CRPT_MODULE
810 * - \ref KS_MODULE
811 * - \ref SPIM_MODULE
812 * - \ref FMCIDLE_MODULE
813 * - \ref USBH_MODULE
814 * - \ref OTG_MODULE
815 * - \ref USBD_MODULE
816 * - \ref TRACE_MODULE
817 * - \ref GPA_MODULE
818 * - \ref GPB_MODULE
819 * - \ref GPC_MODULE
820 * - \ref GPD_MODULE
821 * - \ref GPE_MODULE
822 * - \ref GPF_MODULE
823 * - \ref GPG_MODULE
824 * - \ref GPH_MODULE
825 * - \ref GPI_MODULE
826 * - \ref GPJ_MODULE
827 * - \ref CANFD0_MODULE
828 * - \ref CANFD1_MODULE
829 * - \ref CANFD2_MODULE
830 * - \ref CANFD3_MODULE
831 * - \ref WDT_MODULE
832 * - \ref WWDT_MODULE
833 * - \ref RTC_MODULE
834 * - \ref TMR0_MODULE
835 * - \ref TMR1_MODULE
836 * - \ref TMR2_MODULE
837 * - \ref TMR3_MODULE
838 * - \ref CLKO_MODULE
839 * - \ref ACMP01_MODULE
840 * - \ref ACMP23_MODULE
841 * - \ref I2C0_MODULE
842 * - \ref I2C1_MODULE
843 * - \ref I2C2_MODULE
844 * - \ref I2C3_MODULE
845 * - \ref I2C4_MODULE
846 * - \ref QSPI0_MODULE
847 * - \ref QSPI1_MODULE
848 * - \ref SPI0_MODULE
849 * - \ref SPI1_MODULE
850 * - \ref SPI2_MODULE
851 * - \ref SPI3_MODULE
852 * - \ref SPI4_MODULE
853 * - \ref SPI5_MODULE
854 * - \ref SPI6_MODULE
855 * - \ref SPI7_MODULE
856 * - \ref SPI8_MODULE
857 * - \ref SPI9_MODULE
858 * - \ref SPI10_MODULE
859 * - \ref UART0_MODULE
860 * - \ref UART1_MODULE
861 * - \ref UART2_MODULE
862 * - \ref UART3_MODULE
863 * - \ref UART4_MODULE
864 * - \ref UART5_MODULE
865 * - \ref UART6_MODULE
866 * - \ref UART7_MODULE
867 * - \ref UART8_MODULE
868 * - \ref UART9_MODULE
869 * - \ref EADC0_MODULE
870 * - \ref EADC1_MODULE
871 * - \ref EADC2_MODULE
872 * - \ref I2S0_MODULE
873 * - \ref I2S1_MODULE
874 * - \ref SC0_MODULE
875 * - \ref SC1_MODULE
876 * - \ref SC2_MODULE
877 * - \ref USCI0_MODULE
878 * - \ref PSIO_MODULE
879 * - \ref DAC_MODULE
880 * - \ref EPWM0_MODULE
881 * - \ref EPWM1_MODULE
882 * - \ref BPWM0_MODULE
883 * - \ref BPWM1_MODULE
884 * - \ref EQEI0_MODULE
885 * - \ref EQEI1_MODULE
886 * - \ref EQEI2_MODULE
887 * - \ref EQEI3_MODULE
888 * - \ref TRNG_MODULE
889 * - \ref ECAP0_MODULE
890 * - \ref ECAP1_MODULE
891 * - \ref ECAP2_MODULE
892 * - \ref ECAP3_MODULE
893 * - \ref TRNG_MODULE
894 * - \ref KPI_MODULE
895 * @return None
896 * @details This function is used to enable module clock.
897 */
CLK_EnableModuleClock(uint32_t u32ModuleIdx)898 void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
899 {
900 uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
901
902 /* Index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2, 0x4:AHBCLK1 */
903 uint32_t au32ClkEnTbl[5] = {0x0UL, 0x4UL, 0x8UL, 0x34UL, 0x54UL};
904
905 u32TmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
906 u32TmpAddr = (uint32_t)&CLK->AHBCLK0 + au32ClkEnTbl[MODULE_APBCLK(u32ModuleIdx)];
907
908 *(volatile uint32_t *)u32TmpAddr |= u32TmpVal;
909 }
910
911 /**
912 * @brief Disable module clock
913 * @param[in] u32ModuleIdx is module index. Including :
914 * - \ref PDMA0_MODULE
915 * - \ref PDMA1_MODULE
916 * - \ref ISP_MODULE
917 * - \ref EBI_MODULE
918 * - \ref ST_MODULE
919 * - \ref EMAC0_MODULE
920 * - \ref SDH0_MODULE
921 * - \ref SDH1_MODULE
922 * - \ref CRC_MODULE
923 * - \ref CCAP_MODULE
924 * - \ref SEN_MODULE
925 * - \ref HSUSBD_MODULE
926 * - \ref HSOTG_MODULE
927 * - \ref HBI_MODULE
928 * - \ref CRPT_MODULE
929 * - \ref KS_MODULE
930 * - \ref SPIM_MODULE
931 * - \ref FMCIDLE_MODULE
932 * - \ref USBH_MODULE
933 * - \ref OTG_MODULE
934 * - \ref USBD_MODULE
935 * - \ref TRACE_MODULE
936 * - \ref GPA_MODULE
937 * - \ref GPB_MODULE
938 * - \ref GPC_MODULE
939 * - \ref GPD_MODULE
940 * - \ref GPE_MODULE
941 * - \ref GPF_MODULE
942 * - \ref GPG_MODULE
943 * - \ref GPH_MODULE
944 * - \ref GPI_MODULE
945 * - \ref GPJ_MODULE
946 * - \ref CANFD0_MODULE
947 * - \ref CANFD1_MODULE
948 * - \ref CANFD2_MODULE
949 * - \ref CANFD3_MODULE
950 * - \ref WDT_MODULE
951 * - \ref WWDT_MODULE
952 * - \ref RTC_MODULE
953 * - \ref TMR0_MODULE
954 * - \ref TMR1_MODULE
955 * - \ref TMR2_MODULE
956 * - \ref TMR3_MODULE
957 * - \ref CLKO_MODULE
958 * - \ref ACMP01_MODULE
959 * - \ref ACMP23_MODULE
960 * - \ref I2C0_MODULE
961 * - \ref I2C1_MODULE
962 * - \ref I2C2_MODULE
963 * - \ref I2C3_MODULE
964 * - \ref I2C4_MODULE
965 * - \ref QSPI0_MODULE
966 * - \ref QSPI1_MODULE
967 * - \ref SPI0_MODULE
968 * - \ref SPI1_MODULE
969 * - \ref SPI2_MODULE
970 * - \ref SPI3_MODULE
971 * - \ref SPI4_MODULE
972 * - \ref SPI5_MODULE
973 * - \ref SPI6_MODULE
974 * - \ref SPI7_MODULE
975 * - \ref SPI8_MODULE
976 * - \ref SPI9_MODULE
977 * - \ref SPI10_MODULE
978 * - \ref UART0_MODULE
979 * - \ref UART1_MODULE
980 * - \ref UART2_MODULE
981 * - \ref UART3_MODULE
982 * - \ref UART4_MODULE
983 * - \ref UART5_MODULE
984 * - \ref UART6_MODULE
985 * - \ref UART7_MODULE
986 * - \ref UART8_MODULE
987 * - \ref UART9_MODULE
988 * - \ref EADC0_MODULE
989 * - \ref EADC1_MODULE
990 * - \ref EADC2_MODULE
991 * - \ref I2S0_MODULE
992 * - \ref I2S1_MODULE
993 * - \ref SC0_MODULE
994 * - \ref SC1_MODULE
995 * - \ref SC2_MODULE
996 * - \ref USCI0_MODULE
997 * - \ref PSIO_MODULE
998 * - \ref DAC_MODULE
999 * - \ref EPWM0_MODULE
1000 * - \ref EPWM1_MODULE
1001 * - \ref BPWM0_MODULE
1002 * - \ref BPWM1_MODULE
1003 * - \ref EQEI0_MODULE
1004 * - \ref EQEI1_MODULE
1005 * - \ref EQEI2_MODULE
1006 * - \ref EQEI3_MODULE
1007 * - \ref TRNG_MODULE
1008 * - \ref ECAP0_MODULE
1009 * - \ref ECAP1_MODULE
1010 * - \ref ECAP2_MODULE
1011 * - \ref ECAP3_MODULE
1012 * - \ref TRNG_MODULE
1013 * - \ref KPI_MODULE
1014 * @return None
1015 * @details This function is used to disable module clock.
1016 */
CLK_DisableModuleClock(uint32_t u32ModuleIdx)1017 void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
1018 {
1019 uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
1020
1021 /* Index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2, 0x4:AHBCLK1 */
1022 uint32_t au32ClkEnTbl[5] = {0x0UL, 0x4UL, 0x8UL, 0x34UL, 0x54UL};
1023
1024 u32TmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
1025 u32TmpAddr = (uint32_t)&CLK->AHBCLK0 + au32ClkEnTbl[MODULE_APBCLK(u32ModuleIdx)];
1026
1027 *(uint32_t *)u32TmpAddr &= u32TmpVal;
1028 }
1029
1030
1031 /**
1032 * @brief Set PLL frequency
1033 * @param[in] u32PllClkSrc is PLL clock source. Including :
1034 * - \ref CLK_PLLCTL_PLLSRC_HXT
1035 * - \ref CLK_PLLCTL_PLLSRC_HIRC
1036 * @param[in] u32PllFreq is PLL frequency. The range of u32PllFreq is 50 MHz ~ 500 MHz.
1037 * @return PLL frequency
1038 * @details This function is used to configure CLK_PLLCTL register to set specified PLL frequency. \n
1039 * The register write-protection function should be disabled before using this function.
1040 */
CLK_EnablePLL(uint32_t u32PllClkSrc,uint32_t u32PllFreq)1041 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
1042 {
1043 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32PllClk;
1044 uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
1045
1046 /* Check if HCLK is PLL before configure PLL */
1047 if( (CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk) == CLK_CLKSEL0_HCLKSEL_PLL )
1048 {
1049 /* Return PLL frequency directly if HCLK is PLL */
1050 return CLK_GetPLLClockFreq();
1051 }
1052 else
1053 {
1054 /* Disable PLL first to avoid unstable when setting PLL */
1055 CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
1056 }
1057
1058 /* PLL source clock is from HXT */
1059 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
1060 {
1061 /* Enable HXT clock */
1062 CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
1063
1064 /* Wait for HXT clock ready */
1065 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
1066
1067 /* Select PLL source clock from HXT */
1068 u32PllSrcClk = __HXT;
1069 }
1070
1071 /* PLL source clock is from HIRC */
1072 else
1073 {
1074 /* Enable HIRC clock */
1075 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
1076
1077 /* Wait for HIRC clock ready */
1078 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
1079
1080 /* Select PLL source clock from HIRC */
1081 u32PllSrcClk = __HIRC;
1082 }
1083
1084 /* Check PLL frequency range */
1085 /* Constraint 1: 50MHz < FOUT < 500MHz */
1086 if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ))
1087 {
1088 /* Select "NO" according to request frequency */
1089 if((u32PllFreq < FREQ_100MHZ) && (u32PllFreq >= FREQ_50MHZ))
1090 {
1091 u32NO = 3UL;
1092 u32PllFreq = u32PllFreq << 2;
1093 }
1094 else if((u32PllFreq < FREQ_200MHZ) && (u32PllFreq >= FREQ_100MHZ))
1095 {
1096 u32NO = 1UL;
1097 u32PllFreq = u32PllFreq << 1;
1098 }
1099 else
1100 {
1101 u32NO = 0UL;
1102 }
1103
1104 /* u32NR start from 3 to avoid calculation overflow */
1105 u32NR = 3UL;
1106
1107 /* Find best solution */
1108 u32Min = (uint32_t) - 1; /* initial u32Min to max value of uint32_t (0xFFFFFFFF) */
1109 u32MinNR = 0UL;
1110 u32MinNF = 0UL;
1111
1112 for(; u32NR <= 32UL; u32NR++) /* max NR = 32 since NR = INDIV+1 and INDIV = 0~31 */
1113 {
1114 u32Tmp = u32PllSrcClk / u32NR; /* FREF = FIN/NR */
1115 if((u32Tmp >= FREQ_4MHZ) && (u32Tmp <= FREQ_8MHZ)) /* Constraint 2: 4MHz < FREF < 8MHz. */
1116 {
1117 for(u32NF = 2UL; u32NF <= 513UL; u32NF++) /* NF = 2~513 since NF = FBDIV+2 and FBDIV = 0~511 */
1118 {
1119 u32Tmp2 = (u32Tmp * u32NF) << 1; /* FVCO = FREF*2*NF */
1120 if((u32Tmp2 >= FREQ_200MHZ) && (u32Tmp2 <= FREQ_500MHZ)) /* Constraint 3: 200MHz < FVCO < 500MHz */
1121 {
1122 u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
1123 if(u32Tmp3 < u32Min)
1124 {
1125 u32Min = u32Tmp3;
1126 u32MinNR = u32NR;
1127 u32MinNF = u32NF;
1128
1129 /* Break when get good results */
1130 if(u32Min == 0UL)
1131 {
1132 break;
1133 }
1134 }
1135 }
1136 }
1137 }
1138 }
1139
1140 /* Enable and apply new PLL setting. */
1141 CLK->PLLCTL = u32PllClkSrc |
1142 (u32NO << CLK_PLLCTL_OUTDIV_Pos) |
1143 ((u32MinNR - 1UL) << CLK_PLLCTL_INDIV_Pos) |
1144 ((u32MinNF - 2UL) << CLK_PLLCTL_FBDIV_Pos);
1145
1146 /* Actual PLL output clock frequency. FOUT = (FIN/NR)*2*NF*(1/NO) */
1147 u32PllClk = u32PllSrcClk / ((u32NO + 1UL) * u32MinNR) * (u32MinNF << 1);
1148 }
1149 else
1150 {
1151 /* Apply default PLL setting and return */
1152 CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_192MHz_HXT;
1153
1154 /* Actual PLL output clock frequency */
1155 u32PllClk = FREQ_192MHZ;
1156 }
1157
1158 /* Wait for PLL clock stable */
1159 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
1160
1161 /* Return actual PLL output clock frequency */
1162 return u32PllClk;
1163 }
1164
1165
1166 /**
1167 * @brief Disable PLL
1168 * @param None
1169 * @return None
1170 * @details This function set PLL in Power-down mode. \n
1171 * The register write-protection function should be disabled before using this function.
1172 */
CLK_DisablePLL(void)1173 void CLK_DisablePLL(void)
1174 {
1175 CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
1176 }
1177
1178
1179 /**
1180 * @brief This function check selected clock source status
1181 * @param[in] u32ClkMask is selected clock source. Including :
1182 * - \ref CLK_STATUS_HXTSTB_Msk
1183 * - \ref CLK_STATUS_LXTSTB_Msk
1184 * - \ref CLK_STATUS_HIRCSTB_Msk
1185 * - \ref CLK_STATUS_LIRCSTB_Msk
1186 * - \ref CLK_STATUS_PLLSTB_Msk
1187 * - \ref CLK_STATUS_PLLFNSTB_Msk
1188 * - \ref CLK_STATUS_HIRC48MSTB_Msk
1189 * @retval 0 clock is not stable
1190 * @retval 1 clock is stable
1191 * @details To wait for clock ready by specified clock source stable flag or timeout (>500ms)
1192 */
CLK_WaitClockReady(uint32_t u32ClkMask)1193 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
1194 {
1195 uint32_t u32TimeOutCnt = SystemCoreClock>>1; /* 500ms time-out */
1196 uint32_t u32Ret = 1U;
1197
1198 while((CLK->STATUS & u32ClkMask) != u32ClkMask)
1199 {
1200 if(--u32TimeOutCnt == 0)
1201 {
1202 u32Ret = 0U;
1203 break;
1204 }
1205 }
1206
1207 return u32Ret;
1208 }
1209
1210 /**
1211 * @brief Enable System Tick counter
1212 * @param[in] u32ClkSrc is System Tick clock source. Including:
1213 * - \ref CLK_CLKSEL0_STCLKSEL_HXT
1214 * - \ref CLK_CLKSEL0_STCLKSEL_LXT
1215 * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
1216 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
1217 * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
1218 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK
1219 * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
1220 * @return None
1221 * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
1222 * The register write-protection function should be disabled before using this function.
1223 */
CLK_EnableSysTick(uint32_t u32ClkSrc,uint32_t u32Count)1224 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
1225 {
1226 /* Set System Tick counter disabled */
1227 SysTick->CTRL = 0UL;
1228
1229 /* Set System Tick clock source */
1230 if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )
1231 {
1232 /* Disable System Tick clock source from external reference clock */
1233 CLK->AHBCLK0 &= ~CLK_AHBCLK0_STCKEN_Msk;
1234
1235 /* Select System Tick clock source from core clock */
1236 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
1237 }
1238 else
1239 {
1240 /* Enable System Tick clock source from external reference clock */
1241 CLK->AHBCLK0 |= CLK_AHBCLK0_STCKEN_Msk;
1242
1243 /* Select System Tick external reference clock source */
1244 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
1245
1246 /* Select System Tick clock source from external reference clock */
1247 SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
1248 }
1249
1250 /* Set System Tick reload value */
1251 SysTick->LOAD = u32Count;
1252
1253 /* Clear System Tick current value and counter flag */
1254 SysTick->VAL = 0UL;
1255
1256 /* Set System Tick interrupt enabled and counter enabled */
1257 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
1258 }
1259
1260 /**
1261 * @brief Disable System Tick counter
1262 * @param None
1263 * @return None
1264 * @details This function disable System Tick counter.
1265 */
CLK_DisableSysTick(void)1266 void CLK_DisableSysTick(void)
1267 {
1268 /* Set System Tick counter disabled */
1269 SysTick->CTRL = 0UL;
1270 }
1271
1272
1273 /**
1274 * @brief Power-down mode selected
1275 * @param[in] u32PDMode is power down mode index. Including :
1276 * - \ref CLK_PMUCTL_PDMSEL_PD
1277 * - \ref CLK_PMUCTL_PDMSEL_LLPD
1278 * - \ref CLK_PMUCTL_PDMSEL_FWPD
1279 * - \ref CLK_PMUCTL_PDMSEL_SPD
1280 * - \ref CLK_PMUCTL_PDMSEL_DPD
1281 * @return None
1282 * @details This function is used to set power-down mode.
1283 * The register write-protection function should be disabled before using this function.
1284 */
1285
CLK_SetPowerDownMode(uint32_t u32PDMode)1286 void CLK_SetPowerDownMode(uint32_t u32PDMode)
1287 {
1288 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode;
1289 }
1290
1291
1292 /**
1293 * @brief Set Wake-up pin trigger type at Deep Power down mode
1294 *
1295 * @param[in] u32TriggerType Wake-up pin trigger type
1296 * - \ref CLK_DPDWKPIN_RISING
1297 * - \ref CLK_DPDWKPIN_FALLING
1298 * - \ref CLK_DPDWKPIN_BOTHEDGE
1299 * - \ref CLK_DPDWKPIN1_RISING
1300 * - \ref CLK_DPDWKPIN1_FALLING
1301 * - \ref CLK_DPDWKPIN1_BOTHEDGE
1302 * - \ref CLK_DPDWKPIN2_RISING
1303 * - \ref CLK_DPDWKPIN2_FALLING
1304 * - \ref CLK_DPDWKPIN2_BOTHEDGE
1305 * - \ref CLK_DPDWKPIN3_RISING
1306 * - \ref CLK_DPDWKPIN3_FALLING
1307 * - \ref CLK_DPDWKPIN3_BOTHEDGE
1308 * - \ref CLK_DPDWKPIN4_RISING
1309 * - \ref CLK_DPDWKPIN4_FALLING
1310 * - \ref CLK_DPDWKPIN4_BOTHEDGE
1311 * @return None
1312 *
1313 * @details This function is used to enable Wake-up pin trigger type.
1314 * The register write-protection function should be disabled before using this function.
1315 */
1316
CLK_EnableDPDWKPin(uint32_t u32TriggerType)1317 void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
1318 {
1319 uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4;
1320
1321 /* Get DPD wake-up pin configuration */
1322 u32Pin1 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN1_Msk);
1323 u32Pin2 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN2_Msk);
1324 u32Pin3 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN3_Msk);
1325 u32Pin4 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN4_Msk);
1326
1327 /* Set DPD wake-up pin configuration */
1328 if(u32Pin1)
1329 {
1330 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType;
1331 }
1332 else if(u32Pin2)
1333 {
1334 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType;
1335 }
1336 else if(u32Pin3)
1337 {
1338 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType;
1339 }
1340 else if(u32Pin4)
1341 {
1342 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType;
1343 }
1344 else
1345 {
1346 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN0_Msk)) | u32TriggerType;
1347 }
1348
1349 }
1350
1351 /**
1352 * @brief Get power manager wake up source
1353 *
1354 * @param[in] None
1355 * @return None
1356 *
1357 * @details This function get power manager wake up source.
1358 */
1359
CLK_GetPMUWKSrc(void)1360 uint32_t CLK_GetPMUWKSrc(void)
1361 {
1362 return (CLK->PMUSTS);
1363 }
1364
1365 /**
1366 * @brief Set specified GPIO as wake up source at Stand-by Power down mode
1367 *
1368 * @param[in] u32Port GPIO port. It could be 0~3.
1369 * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
1370 * @param[in] u32TriggerType Wake-up pin trigger type
1371 * - \ref CLK_SPDWKPIN_RISING
1372 * - \ref CLK_SPDWKPIN_FALLING
1373 * @param[in] u32DebounceEn Standby Power-down mode wake-up pin de-bounce function
1374 * - \ref CLK_SPDWKPIN_DEBOUNCEEN
1375 * - \ref CLK_SPDWKPIN_DEBOUNCEDIS
1376 * @return None
1377 *
1378 * @details This function is used to set specified GPIO as wake up source at Stand-by Power down mode.
1379 */
CLK_EnableSPDWKPin(uint32_t u32Port,uint32_t u32Pin,uint32_t u32TriggerType,uint32_t u32DebounceEn)1380 void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
1381 {
1382 uint32_t u32tmpAddr = 0UL;
1383 uint32_t u32tmpVal = 0UL;
1384
1385 /* GPx Stand-by Power-down Wake-up Pin Select */
1386 u32tmpAddr = (uint32_t)&CLK->PASWKCTL;
1387 u32tmpAddr += (0x4UL * u32Port);
1388
1389 u32tmpVal = inpw((uint32_t *)u32tmpAddr);
1390 u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |
1391 (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
1392 outpw((uint32_t *)u32tmpAddr, u32tmpVal);
1393 }
1394
1395 /**
1396 * @brief Get PLL clock frequency
1397 * @param None
1398 * @return PLL frequency
1399 * @details This function get PLL frequency. The frequency unit is Hz.
1400 */
CLK_GetPLLClockFreq(void)1401 uint32_t CLK_GetPLLClockFreq(void)
1402 {
1403 uint32_t u32PllFreq = 0UL, u32PllReg;
1404 uint32_t u32FIN, u32NF, u32NR, u32NO;
1405 uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
1406
1407 u32PllReg = CLK->PLLCTL;
1408
1409 if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
1410 {
1411 u32PllFreq = 0UL; /* PLL is in power down mode or fix low */
1412 }
1413 else /* PLL is in normal mode */
1414 {
1415 /* PLL source clock */
1416 if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)
1417 {
1418 u32FIN = __HIRC; /* PLL source clock from HIRC */
1419 }
1420 else
1421 {
1422 u32FIN = __HXT; /* PLL source clock from HXT */
1423 }
1424
1425 /* Calculate PLL frequency */
1426 if(u32PllReg & CLK_PLLCTL_BP_Msk)
1427 {
1428 u32PllFreq = u32FIN; /* PLL is in bypass mode */
1429 }
1430 else
1431 {
1432 /* PLL is output enabled in normal work mode */
1433 u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
1434 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
1435 u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
1436
1437 /* u32FIN is shifted 2 bits to avoid overflow */
1438 u32PllFreq = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2);
1439 }
1440 }
1441
1442 return u32PllFreq;
1443 }
1444
1445 /**
1446 * @brief Get selected module clock source
1447 * @param[in] u32ModuleIdx is module index.
1448 * - \ref SDH0_MODULE
1449 * - \ref SDH1_MODULE
1450 * - \ref SEN_MODULE
1451 * - \ref USBH_MODULE
1452 * - \ref OTG_MODULE
1453 * - \ref USBD_MODULE
1454 * - \ref CANFD0_MODULE
1455 * - \ref CANFD1_MODULE
1456 * - \ref CANFD2_MODULE
1457 * - \ref CANFD3_MODULE
1458 * - \ref WDT_MODULE
1459 * - \ref WWDT_MODULE
1460 * - \ref RTC_MODULE
1461 * - \ref TMR0_MODULE
1462 * - \ref TMR1_MODULE
1463 * - \ref TMR2_MODULE
1464 * - \ref TMR3_MODULE
1465 * - \ref CLKO_MODULE
1466 * - \ref QSPI0_MODULE
1467 * - \ref QSPI1_MODULE
1468 * - \ref SPI0_MODULE
1469 * - \ref SPI1_MODULE
1470 * - \ref SPI2_MODULE
1471 * - \ref SPI3_MODULE
1472 * - \ref SPI4_MODULE
1473 * - \ref SPI5_MODULE
1474 * - \ref SPI6_MODULE
1475 * - \ref SPI7_MODULE
1476 * - \ref SPI8_MODULE
1477 * - \ref SPI9_MODULE
1478 * - \ref SPI10_MODULE
1479 * - \ref UART0_MODULE
1480 * - \ref UART1_MODULE
1481 * - \ref UART2_MODULE
1482 * - \ref UART3_MODULE
1483 * - \ref UART4_MODULE
1484 * - \ref UART5_MODULE
1485 * - \ref UART6_MODULE
1486 * - \ref UART7_MODULE
1487 * - \ref UART8_MODULE
1488 * - \ref UART9_MODULE
1489 * - \ref EPWM0_MODULE
1490 * - \ref EPWM1_MODULE
1491 * - \ref BPWM0_MODULE
1492 * - \ref BPWM1_MODULE
1493 * - \ref EADC0_MODULE
1494 * - \ref EADC1_MODULE
1495 * - \ref EADC2_MODULE
1496 * - \ref I2S0_MODULE
1497 * - \ref I2S1_MODULE
1498 * - \ref SC0_MODULE
1499 * - \ref SC1_MODULE
1500 * - \ref SC2_MODULE
1501 * - \ref PSIO_MODULE
1502 * - \ref TRNG_MODULE
1503 * - \ref KPI_MODULE
1504 * @return Selected module clock source setting
1505 * @details This function get selected module clock source.
1506 */
CLK_GetModuleClockSource(uint32_t u32ModuleIdx)1507 uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
1508 {
1509 uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
1510 uint32_t au32SelTbl[5] = {0x0UL, 0x4UL, 0x8UL, 0xCUL, 0x4CUL}; /* CLK_CLKSEL0~4 */
1511 uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;
1512
1513 /* Get clock source selection setting */
1514 if(u32ModuleIdx == RTC_MODULE)
1515 {
1516 if(u32RTCCKEN == 0UL)
1517 {
1518 /* Enable RTC clock to get LXT clock source */
1519 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
1520 }
1521
1522 u32TmpVal = ((RTC->LXTCTL & RTC_LXTCTL_RTCCKSEL_Msk) >> RTC_LXTCTL_RTCCKSEL_Pos);
1523
1524 if(u32RTCCKEN == 0UL)
1525 {
1526 /* Disable RTC clock if it is disabled before */
1527 CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk);
1528 }
1529
1530 }
1531 else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
1532 {
1533 /* Get clock select control register address */
1534 u32TmpAddr = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
1535
1536 /* Get clock source selection setting */
1537 u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx));
1538 }
1539
1540 return u32TmpVal;
1541
1542 }
1543
1544 /**
1545 * @brief Get selected module clock divider number
1546 * @param[in] u32ModuleIdx is module index.
1547 * - \ref SDH0_MODULE
1548 * - \ref SDH1_MODULE
1549 * - \ref SEN_MODULE
1550 * - \ref USBH_MODULE
1551 * - \ref OTG_MODULE
1552 * - \ref USBD_MODULE
1553 * - \ref CANFD0_MODULE
1554 * - \ref CANFD1_MODULE
1555 * - \ref CANFD2_MODULE
1556 * - \ref CANFD3_MODULE
1557 * - \ref UART0_MODULE
1558 * - \ref UART1_MODULE
1559 * - \ref UART2_MODULE
1560 * - \ref UART3_MODULE
1561 * - \ref UART4_MODULE
1562 * - \ref UART5_MODULE
1563 * - \ref UART6_MODULE
1564 * - \ref UART7_MODULE
1565 * - \ref UART8_MODULE
1566 * - \ref UART9_MODULE
1567 * - \ref EADC0_MODULE
1568 * - \ref EADC1_MODULE
1569 * - \ref EADC2_MODULE
1570 * - \ref I2S0_MODULE
1571 * - \ref I2S1_MODULE
1572 * - \ref SC0_MODULE
1573 * - \ref SC1_MODULE
1574 * - \ref SC2_MODULE
1575 * - \ref PSIO_MODULE
1576 * - \ref KPI_MODULE
1577 * @return Selected module clock divider number setting
1578 * @details This function get selected module clock divider number.
1579 */
CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)1580 uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
1581 {
1582 uint32_t u32DivVal = 0UL, u32DivAddr = 0UL;
1583 uint32_t au32DivTbl[6] = {0x0UL, 0x4UL, 0x8UL, 0xCUL, 0x10UL, 0x1C}; /* CLK_CLKDIV0~5 */
1584
1585 switch(u32ModuleIdx)
1586 {
1587 /* For 8 bits divider */
1588 case EADC0_MODULE: u32DivVal = (CLK->CLKDIV0 & CLK_CLKDIV0_EADC0DIV_Msk) >> CLK_CLKDIV0_EADC0DIV_Pos; break;
1589 case SDH0_MODULE: u32DivVal = (CLK->CLKDIV0 & CLK_CLKDIV0_SDH0DIV_Msk) >> CLK_CLKDIV0_SDH0DIV_Pos; break;
1590 case SC0_MODULE: u32DivVal = (CLK->CLKDIV1 & CLK_CLKDIV1_SC0DIV_Msk) >> CLK_CLKDIV1_SC0DIV_Pos; break;
1591 case SC1_MODULE: u32DivVal = (CLK->CLKDIV1 & CLK_CLKDIV1_SC1DIV_Msk) >> CLK_CLKDIV1_SC1DIV_Pos; break;
1592 case SC2_MODULE: u32DivVal = (CLK->CLKDIV1 & CLK_CLKDIV1_SC2DIV_Msk) >> CLK_CLKDIV1_SC2DIV_Pos; break;
1593 case PSIO_MODULE: u32DivVal = (CLK->CLKDIV1 & CLK_CLKDIV1_PSIODIV_Msk) >> CLK_CLKDIV1_PSIODIV_Pos; break;
1594 case KPI_MODULE: u32DivVal = (CLK->CLKDIV2 & CLK_CLKDIV2_KPIDIV_Msk) >> CLK_CLKDIV2_KPIDIV_Pos; break;
1595 case EADC1_MODULE: u32DivVal = (CLK->CLKDIV2 & CLK_CLKDIV2_EADC1DIV_Msk) >> CLK_CLKDIV2_EADC1DIV_Pos; break;
1596 case SEN_MODULE: u32DivVal = (CLK->CLKDIV3 & CLK_CLKDIV3_VSENSEDIV_Msk) >> CLK_CLKDIV3_VSENSEDIV_Pos; break;
1597 case SDH1_MODULE: u32DivVal = (CLK->CLKDIV3 & CLK_CLKDIV3_SDH1DIV_Msk) >> CLK_CLKDIV3_SDH1DIV_Pos; break;
1598 case EADC2_MODULE: u32DivVal = (CLK->CLKDIV5 & CLK_CLKDIV5_EADC2DIV_Msk) >> CLK_CLKDIV5_EADC2DIV_Pos; break;
1599
1600 /* Others */
1601 default:
1602 {
1603 /* Get clock divider control register address */
1604 u32DivAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
1605 /* Get clock divider number setting */
1606 u32DivVal = ((inpw((uint32_t *)u32DivAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx));
1607 }
1608 break;
1609 }
1610
1611 return u32DivVal;
1612 }
1613
1614 /**
1615 * @brief Disable PLLFN
1616 * @param None
1617 * @return None
1618 * @details This function set PLLFN in Power-down mode. \n
1619 * The register write-protection function should be disabled before using this function.
1620 */
CLK_DisablePLLFN(void)1621 void CLK_DisablePLLFN(void)
1622 {
1623 CLK->PLLFNCTL1 |= CLK_PLLFNCTL1_PD_Msk;
1624 }
1625
1626 /**
1627 * @brief Set PLLFN frequency
1628 * @param[in] u32PllClkSrc is PLLFN clock source. Including :
1629 * - \ref CLK_PLLFNCTL1_PLLSRC_HXT
1630 * - \ref CLK_PLLFNCTL1_PLLSRC_HIRC
1631 * @param[in] u32PllFreq is PLLFN frequency. The range of u32PllFreq is 50 MHz ~ 500 MHz.
1632 * @return PLL frequency
1633 * @details This function is used to configure PLLFNCTL0 and PLLFNCTL1 register to set specified PLLFN frequency. \n
1634 * The register write-protection function should be disabled before using this function.
1635 */
CLK_EnablePLLFN(uint32_t u32PllClkSrc,uint32_t u32PllFreq)1636 uint32_t CLK_EnablePLLFN(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
1637 {
1638 uint32_t u32FIN, u32FVCO, u32FREF, u32PllClk = 0UL;
1639 uint32_t u32NR = 0UL, u32NF = 0UL, u32NO, u32X = 0UL;
1640 float fNX_X = 0.0, fX = 0.0;
1641
1642 /* Disable PLLFN first to avoid unstable when setting PLLFN */
1643 CLK->PLLFNCTL1 |= CLK_PLLFNCTL1_PD_Msk;
1644
1645 /* PLLFN source clock is from HXT */
1646 if(u32PllClkSrc == CLK_PLLFNCTL1_PLLSRC_HXT)
1647 {
1648 /* Enable HXT clock */
1649 CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
1650
1651 /* Wait for HXT clock ready */
1652 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
1653
1654 /* Select PLLFN source clock from HXT */
1655 u32FIN = __HXT;
1656 }
1657
1658 /* PLL source clock is from HIRC */
1659 else
1660 {
1661 /* Enable HIRC clock */
1662 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
1663
1664 /* Wait for HIRC clock ready */
1665 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
1666
1667 /* Select PLLFN source clock from HIRC */
1668 u32FIN = __HIRC;
1669 }
1670
1671 /* Check PLL frequency range */
1672 /* Constraint 1: 50MHz < FOUT < 500MHz */
1673 if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ))
1674 {
1675 /* Select "NO" according to request frequency */
1676 if((u32PllFreq < FREQ_100MHZ) && (u32PllFreq >= FREQ_50MHZ))
1677 {
1678 u32NO = 3UL;
1679 u32FVCO = u32PllFreq << 2;
1680 }
1681 else if((u32PllFreq < FREQ_200MHZ) && (u32PllFreq >= FREQ_100MHZ))
1682 {
1683 u32NO = 1UL;
1684 u32FVCO = u32PllFreq << 1;
1685 }
1686 else
1687 {
1688 u32NO = 0UL;
1689 u32FVCO = u32PllFreq;
1690 }
1691
1692 /* u32NR start from 3 to avoid calculation overflow */
1693 u32NR = 3UL;
1694
1695 for(; u32NR <= 32UL; u32NR++) /* max NR = 32 since NR = INDIV+1 and INDIV = 0~31 */
1696 {
1697 u32FREF = u32FIN / u32NR; /* FREF = FIN/NR */
1698
1699 if((u32FREF >= FREQ_1MHZ) && (u32FREF <= FREQ_8MHZ)) /* Constraint 2: 1MHz <= FREF <= 8MHz. */
1700 {
1701 fNX_X = (float)((u32FVCO * u32NR)>>1)/u32FIN;
1702 u32NF = (uint32_t)fNX_X;
1703
1704 if((u32NF >= 12) && (u32NF <= 255)) /* Constraint 4: 12<= NF <= 255. */
1705 {
1706 fX = fNX_X - u32NF;
1707 u32X = (uint32_t)(fX*4096);
1708 break;
1709 }
1710 }
1711 }
1712
1713 if(u32NR <= 32UL)
1714 {
1715 /* Enable and apply new PLLFN setting. */
1716 CLK->PLLFNCTL0 = (u32X << CLK_PLLFNCTL0_FRDIV_Pos) |
1717 (u32NO << CLK_PLLFNCTL0_OUTDIV_Pos) |
1718 ((u32NR - 1UL) << CLK_PLLFNCTL0_INDIV_Pos) |
1719 ((u32NF - 2UL) << CLK_PLLFNCTL0_FBDIV_Pos);
1720 CLK->PLLFNCTL1 = u32PllClkSrc;
1721
1722 /* Actual PLL output clock frequency. FOUT = (FIN/NR)*2*(NF.X)*(1/NO) */
1723 u32PllClk = (uint32_t)((float)u32FIN / (((u32NO + 1UL) * u32NR)<<11) * ((u32NF<<12)+u32X));
1724 }
1725 }
1726
1727 if((u32PllFreq > FREQ_500MHZ) || (u32PllFreq < FREQ_50MHZ) || (u32NR==33) )
1728 {
1729 /* Apply default PLLFN setting and return */
1730 CLK->PLLFNCTL0 = CLK_PLLCTL_192MHz_HXT;
1731 CLK->PLLFNCTL1 = u32PllClkSrc;
1732
1733 /* Actual PLLFN output clock frequency */
1734 u32PllClk = FREQ_192MHZ;
1735 }
1736
1737 /* Wait for PLLFN clock stable */
1738 CLK_WaitClockReady(CLK_STATUS_PLLFNSTB_Msk);
1739
1740 /* Return actual PLLFN output clock frequency */
1741 return u32PllClk;
1742 }
1743
1744
1745 /**
1746 * @brief Get PLLFN clock frequency
1747 * @param None
1748 * @return PLLFN frequency
1749 * @details This function get PLLFN frequency. The frequency unit is Hz.
1750 */
CLK_GetPLLFNClockFreq(void)1751 uint32_t CLK_GetPLLFNClockFreq(void)
1752 {
1753 uint32_t u32PllFreq = 0UL, u32PllReg0, u32PllReg1;
1754 uint32_t u32FIN, u32NF, u32NR, u32NO, u32X;
1755 uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
1756
1757 /* Get PLLFN configuration */
1758 u32PllReg0 = CLK->PLLFNCTL0;
1759 u32PllReg1 = CLK->PLLFNCTL1;
1760
1761 if(u32PllReg1 & (CLK_PLLFNCTL1_PD_Msk|CLK_PLLFNCTL1_OE_Msk) )
1762 {
1763 u32PllFreq = 0UL; /* PLLFN is in power down mode or fix low */
1764 }
1765 else /* PLLFN is in normal mode */
1766 {
1767 /* PLLFN source clock */
1768 if(u32PllReg1 & CLK_PLLFNCTL1_PLLSRC_Msk)
1769 {
1770 u32FIN = __HIRC; /* PLLFN source clock from HIRC */
1771 }
1772 else
1773 {
1774 u32FIN = __HXT; /* PLLFN source clock from HXT */
1775 }
1776
1777 /* Calculate PLLFN frequency */
1778 if(u32PllReg1 & CLK_PLLFNCTL1_BP_Msk)
1779 {
1780 u32PllFreq = u32FIN; /* PLLFN is in bypass mode */
1781 }
1782 else
1783 {
1784 /* PLLFN is output enabled in normal work mode */
1785 u32NO = au8NoTbl[((u32PllReg0 & CLK_PLLFNCTL0_OUTDIV_Msk) >> CLK_PLLFNCTL0_OUTDIV_Pos)];
1786 u32NF = ((u32PllReg0 & CLK_PLLFNCTL0_FBDIV_Msk) >> CLK_PLLFNCTL0_FBDIV_Pos) + 2UL;
1787 u32NR = ((u32PllReg0 & CLK_PLLFNCTL0_INDIV_Msk) >> CLK_PLLFNCTL0_INDIV_Pos) + 1UL;
1788 u32X = ((u32PllReg0 & CLK_PLLFNCTL0_FRDIV_Msk) >> CLK_PLLFNCTL0_FRDIV_Pos);
1789
1790 u32PllFreq = (uint32_t)((float)u32FIN / ((u32NO * u32NR)<<11) * ( ((u32NF<<12)+u32X)));
1791 }
1792 }
1793
1794 return u32PllFreq;
1795 }
1796
1797
1798 /*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
1799
1800 /*@}*/ /* end of group CLK_Driver */
1801
1802 /*@}*/ /* end of group Standard_Driver */
1803
