1 /**************************************************************************//** 2 * @file clk_reg.h 3 * @version V1.00 4 * @brief CLK register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CLK_REG_H__ 10 #define __CLK_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- System Clock Controller -------------------------*/ 20 /** 21 @addtogroup CLK System Clock Controller(CLK) 22 Memory Mapped Structure for CLK Controller 23 @{ */ 24 25 typedef struct 26 { 27 28 /** 29 * @var CLK_T::PWRCTL 30 * Offset: 0x00 System Power-down Control Register 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[0] |HXTEN |HXT Enable Bit (Write Protect) 35 * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. 36 * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. 37 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 38 * | | |Note2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT). 39 * |[1] |LXTEN |LXT Enable Bit (Write Protect) 40 * | | |0 = 32.768 kHz external low speed crystal (extLXT) Disabled. 41 * | | |1 = 32.768 kHz external low speed crystal (extLXT) Enabled. 42 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 43 * | | |Note2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as extLXT by setting C32KS(RTC_LXTCTL[7]) to 1. 44 * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) 45 * | | |The HCLK default clock source is from HIRC and this bit default value is 1. 46 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. 47 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. 48 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 49 * | | |Note2: HIRC cannot be disabled and HIRCEN will always read as 1 if Flash access cycle auto-tuning function is enabled or HCLK clock source is selected from HIRC or PLL (clock source from HIRC). 50 * | | |Flash access cycle auto-tuning function can be disabled by setting FADIS (FMC_CYCCTL[8]). 51 * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) 52 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. 53 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. 54 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 55 * | | |Note2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC. 56 * | | |Note3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]). 57 * | | |If CWDTEN(CONFIG0[31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode and LIRCEN will always read as 1 58 * | | |In Power-down mode, LIRC clock is controlled by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN (CONFIG0[30]) setting. 59 * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) 60 * | | |0 = Power-down mode wake-up interrupt Disabled. 61 * | | |1 = Power-down mode wake-up interrupt Enabled. 62 * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from Power-down mode. 63 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 64 * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status 65 * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode. 66 * | | |The flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, SDH0, TMR0~3, I2C0~2, USCI0~1, RTC wake-up occurred. 67 * | | |Note1: Write 1 to clear the bit to 0. 68 * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 69 * |[7] |PDEN |System Power-down Enable (Write Protect) 70 * | | |When this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. 71 * | | |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. 72 * | | |In Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. 73 * | | |0 = Chip operating normally or chip in idle mode because of WFI command. 74 * | | |1 = Chip waits CPU sleep command WFI and then enters Power-down mode. 75 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 76 * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) 77 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally. 78 * | | |If gain control is enabled, crystal will consume more power than gain control off. 79 * | | |00 = HXT frequency is lower than from 8 MHz. 80 * | | |01 = HXT frequency is from 8 MHz to 12 MHz. 81 * | | |10 = HXT frequency is from 12 MHz to 16 MHz. 82 * | | |11 = HXT frequency is higher than 16 MHz. 83 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 84 * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) 85 * | | |0 = Select INV type. 86 * | | |1 = Select GM type. 87 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 88 * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) 89 * | | |0 = HXT Crystal TURBO mode disabled. 90 * | | |1 = HXT Crystal TURBO mode enabled. 91 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 92 * |[18] |HIRC48EN |HIRC48 Enable Bit (Write Protect) 93 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48) Disabled. 94 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48) Enabled. 95 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 96 * @var CLK_T::AHBCLK 97 * Offset: 0x04 AHB Devices Clock Enable Control Register 98 * --------------------------------------------------------------------------------------------------- 99 * |Bits |Field |Descriptions 100 * | :----: | :----: | :---- | 101 * |[0] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit (Secure) 102 * | | |0 = PDMA0 peripheral clock Disabled. 103 * | | |1 = PDMA0 peripheral clock Enabled. 104 * |[1] |PDMA1CKEN |PDMA1 Controller Clock Enable Bit 105 * | | |0 = PDMA1 peripheral clock Disabled. 106 * | | |1 = PDMA1 peripheral clock Enabled. 107 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit 108 * | | |0 = Flash ISP peripheral clock Disabled. 109 * | | |1 = Flash ISP peripheral clock Enabled. 110 * |[3] |EBICKEN |EBI Controller Clock Enable Bit 111 * | | |0 = EBI peripheral clock Disabled. 112 * | | |1 = EBI peripheral clock Enabled. 113 * |[6] |SDH0CKEN |SDHOST0 Controller Clock Enable Bit 114 * | | |0 = SDHOST0 peripheral clock Disabled. 115 * | | |1 = SDHOST0 peripheral clock Enabled. 116 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit 117 * | | |0 = CRC peripheral clock Disabled. 118 * | | |1 = CRC peripheral clock Enabled. 119 * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit 120 * | | |0 = Cryptographic Accelerator clock Disabled. 121 * | | |1 = Cryptographic Accelerator clock Enabled. 122 * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode 123 * | | |0 = FMC clock Disabled when chip is under IDLE mode. 124 * | | |1 = FMC clock Enabled when chip is under IDLE mode. 125 * |[16] |USBHCKEN |USB HOST 1.1 Controller Clock Enable Bit 126 * | | |0 = USB HOST 1.1 peripheral clock Disabled. 127 * | | |1 = USB HOST 1.1 peripheral clock Enabled. 128 * @var CLK_T::APBCLK0 129 * Offset: 0x08 APB Devices Clock Enable Control Register 0 130 * --------------------------------------------------------------------------------------------------- 131 * |Bits |Field |Descriptions 132 * | :----: | :----: | :---- | 133 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) 134 * | | |0 = Watchdog timer clock Disabled. 135 * | | |1 = Watchdog timer clock Enabled. 136 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 137 * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit 138 * | | |This bit is used to control the RTC APB clock only. 139 * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]) 140 * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC). 141 * | | |0 = RTC clock Disabled. 142 * | | |1 = RTC clock Enabled. 143 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit 144 * | | |0 = Timer0 clock Disabled. 145 * | | |1 = Timer0 clock Enabled. 146 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit 147 * | | |0 = Timer1 clock Disabled. 148 * | | |1 = Timer1 clock Enabled. 149 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit 150 * | | |0 = Timer2 clock Disabled. 151 * | | |1 = Timer2 clock Enabled. 152 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit 153 * | | |0 = Timer3 clock Disabled. 154 * | | |1 = Timer3 clock Enabled. 155 * |[6] |CLKOCKEN |CLKO Clock Enable Bit 156 * | | |0 = CLKO clock Disabled. 157 * | | |1 = CLKO clock Enabled. 158 * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit 159 * | | |0 = Analog comparator 0/1 clock Disabled. 160 * | | |1 = Analog comparator 0/1 clock Enabled. 161 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit 162 * | | |0 = I2C0 clock Disabled. 163 * | | |1 = I2C0 clock Enabled. 164 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit 165 * | | |0 = I2C1 clock Disabled. 166 * | | |1 = I2C1 clock Enabled. 167 * |[10] |I2C2CKEN |I2C2 Clock Enable Bit 168 * | | |0 = I2C2 clock Disabled. 169 * | | |1 = I2C2 clock Enabled. 170 * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit 171 * | | |0 = QSPI0 clock Disabled. 172 * | | |1 = QSPI0 clock Enabled. 173 * |[13] |SPI0CKEN |SPI0 Clock Enable Bit 174 * | | |0 = SPI0 clock Disabled. 175 * | | |1 = SPI0 clock Enabled. 176 * |[14] |SPI1CKEN |SPI1 Clock Enable Bit 177 * | | |0 = SPI1 clock Disabled. 178 * | | |1 = SPI1 clock Enabled. 179 * |[15] |SPI2CKEN |SPI2 Clock Enable Bit 180 * | | |0 = SPI2 clock Disabled. 181 * | | |1 = SPI2 clock Enabled. 182 * |[16] |UART0CKEN |UART0 Clock Enable Bit 183 * | | |0 = UART0 clock Disabled. 184 * | | |1 = UART0 clock Enabled. 185 * |[17] |UART1CKEN |UART1 Clock Enable Bit 186 * | | |0 = UART1 clock Disabled. 187 * | | |1 = UART1 clock Enabled. 188 * |[18] |UART2CKEN |UART2 Clock Enable Bit 189 * | | |0 = UART2 clock Disabled. 190 * | | |1 = UART2 clock Enabled. 191 * |[19] |UART3CKEN |UART3 Clock Enable Bit 192 * | | |0 = UART3 clock Disabled. 193 * | | |1 = UART3 clock Enabled. 194 * |[20] |UART4CKEN |UART4 Clock Enable Bit 195 * | | |0 = UART4 clock Disabled. 196 * | | |1 = UART4 clock Enabled. 197 * |[21] |UART5CKEN |UART5 Clock Enable Bit 198 * | | |0 = UART5 clock Disabled. 199 * | | |1 = UART5 clock Enabled. 200 * |[24] |CAN0CKEN |CAN0 Clock Enable Bit 201 * | | |0 = CAN0 clock Disabled. 202 * | | |1 = CAN0 clock Enabled. 203 * |[26] |OTGCKEN |USB OTG Clock Enable Bit 204 * | | |0 = USB OTG clock Disabled. 205 * | | |1 = USB OTG clock Enabled. 206 * |[27] |USBDCKEN |USB Device Clock Enable Bit 207 * | | |0 = USB Device clock Disabled. 208 * | | |1 = USB Device clock Enabled. 209 * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit 210 * | | |0 = EADC clock Disabled. 211 * | | |1 = EADC clock Enabled. 212 * |[29] |I2S0CKEN |I2S0 Clock Enable Bit 213 * | | |0 = I2S0 Clock Disabled. 214 * | | |1 = I2S0 Clock Enabled. 215 * @var CLK_T::APBCLK1 216 * Offset: 0x0C APB Devices Clock Enable Control Register 1 217 * --------------------------------------------------------------------------------------------------- 218 * |Bits |Field |Descriptions 219 * | :----: | :----: | :---- | 220 * |[0] |SC0CKEN |Smart Card 0 (SC0) Clock Enable Bit 221 * | | |0 = SC0 clock Disabled. 222 * | | |1 = SC0 clock Enabled. 223 * |[1] |SC1CKEN |Smart Card 1 (SC1) Clock Enable Bit 224 * | | |0 = SC1 clock Disabled. 225 * | | |1 = SC1 clock Enabled. 226 * |[2] |SC2CKEN |Smart Card 2 (SC2) Clock Enable Bit 227 * | | |0 = SC2 clock Disabled. 228 * | | |1 = SC2 clock Enabled. 229 * |[6] |SPI3CKEN |SPI3 Clock Enable Bit 230 * | | |0 = SPI3 clock Disabled. 231 * | | |1 = SPI3 clock Enabled. 232 * |[8] |USCI0CKEN |USCI0 Clock Enable Bit 233 * | | |0 = USCI0 clock Disabled. 234 * | | |1 = USCI0 clock Enabled. 235 * |[9] |USCI1CKEN |USCI1 Clock Enable Bit 236 * | | |0 = USCI1 clock Disabled. 237 * | | |1 = USCI1 clock Enabled. 238 * |[12] |DACCKEN |DAC Clock Enable Bit 239 * | | |0 = DAC clock Disabled. 240 * | | |1 = DAC clock Enabled. 241 * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit 242 * | | |0 = EPWM0 clock Disabled. 243 * | | |1 = EPWM0 clock Enabled. 244 * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit 245 * | | |0 = EPWM1 clock Disabled. 246 * | | |1 = EPWM1 clock Enabled. 247 * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit 248 * | | |0 = BPWM0 clock Disabled. 249 * | | |1 = BPWM0 clock Enabled. 250 * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit 251 * | | |0 = BPWM1 clock Disabled. 252 * | | |1 = BPWM1 clock Enabled. 253 * |[22] |QEI0CKEN |QEI0 Clock Enable Bit 254 * | | |0 = QEI0 clock Disabled. 255 * | | |1 = QEI0 clock Enabled. 256 * |[23] |QEI1CKEN |QEI1 Clock Enable Bit 257 * | | |0 = QEI1 clock Disabled. 258 * | | |1 = QEI1 clock Enabled. 259 * |[25] |TRNGCKEN |TRNG Clock Enable Bit 260 * | | |0 = TRNG clock Disabled. 261 * | | |1 = TRNG clock Enabled. 262 * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit 263 * | | |0 = ECAP0 clock Disabled. 264 * | | |1 = ECAP0 clock Enabled. 265 * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit 266 * | | |0 = ECAP1 clock Disabled. 267 * | | |1 = ECAP1 clock Enabled. 268 * @var CLK_T::CLKSEL0 269 * Offset: 0x10 Clock Source Select Control Register 0 270 * --------------------------------------------------------------------------------------------------- 271 * |Bits |Field |Descriptions 272 * | :----: | :----: | :---- | 273 * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) 274 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. 275 * | | |000 = Clock source from HXT. 276 * | | |001 = Clock source from LXT. 277 * | | |010 = Clock source from PLL. 278 * | | |011 = Clock source from LIRC. 279 * | | |100 = Reserved. 280 * | | |101 = Clock source from HIRC48. 281 * | | |111 = Clock source from HIRC. 282 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 283 * |[5:3] |STCLKSEL |SysTick Clock Source Selection (Write Protect) 284 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. 285 * | | |000 = Clock source from HXT. 286 * | | |001 = Clock source from LXT. 287 * | | |010 = Clock source from HXT/2. 288 * | | |011 = Clock source from HCLK/2. 289 * | | |111 = Clock source from HIRC/2. 290 * | | |Others = Reserved. 291 * | | |Note1: if SysTick clock source is not from HCLK (i.e SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2. 292 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 293 * |[8] |USBSEL |USB Clock Source Selection (Write Protect) 294 * | | |0 = Clock source from HIRC48. 295 * | | |1 = Clock source from PLL. 296 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 297 * |[21:20] |SDH0SEL |SDHOST0 Peripheral Clock Source Selection (Write Protect) 298 * | | |00 = Clock source from HXT clock. 299 * | | |01 = Clock source from PLL clock. 300 * | | |10 = Clock source from HCLK. 301 * | | |11 = Clock source from HIRC clock. 302 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 303 * @var CLK_T::CLKSEL1 304 * Offset: 0x14 Clock Source Select Control Register 1 305 * --------------------------------------------------------------------------------------------------- 306 * |Bits |Field |Descriptions 307 * | :----: | :----: | :---- | 308 * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) 309 * | | |Others = Reserved. 310 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 311 * | | |10 = Clock source from HCLK/2048. 312 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 313 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 314 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection 315 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 316 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 317 * | | |010 = Clock source from PCLK0. 318 * | | |011 = Clock source from external clock TM0 pin. 319 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 320 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 321 * | | |Others = Reserved. 322 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection 323 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 324 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 325 * | | |010 = Clock source from PCLK0. 326 * | | |011 = Clock source from external clock TM1 pin. 327 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 328 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 329 * | | |Others = Reserved. 330 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection 331 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 332 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 333 * | | |010 = Clock source from PCLK1. 334 * | | |011 = Clock source from external clock TM2 pin. 335 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 336 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 337 * | | |Others = Reserved. 338 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection 339 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 340 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 341 * | | |010 = Clock source from PCLK1. 342 * | | |011 = Clock source from external clock TM3 pin. 343 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 344 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 345 * | | |Others = Reserved. 346 * |[25:24] |UART0SEL |UART0 Clock Source Selection 347 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 348 * | | |01 = Clock source from PLL. 349 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 350 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 351 * |[27:26] |UART1SEL |UART1 Clock Source Selection 352 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 353 * | | |01 = Clock source from PLL. 354 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 355 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 356 * |[29:28] |CLKOSEL |Clock Output Clock Source Selection 357 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 358 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 359 * | | |10 = Clock source from HCLK. 360 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 361 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection (Write Protect) 362 * | | |10 = Clock source from HCLK/2048. 363 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 364 * | | |Others = Reserved. 365 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 366 * @var CLK_T::CLKSEL2 367 * Offset: 0x18 Clock Source Select Control Register 2 368 * --------------------------------------------------------------------------------------------------- 369 * |Bits |Field |Descriptions 370 * | :----: | :----: | :---- | 371 * |[0] |EPWM0SEL |EPWM0 Clock Source Selection (Read Only) 372 * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. 373 * | | |1 = Clock source from PCLK0. 374 * |[1] |EPWM1SEL |EPWM1 Clock Source Selection (Read Only) 375 * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. 376 * | | |1 = Clock source from PCLK1. 377 * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection 378 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 379 * | | |01 = Clock source from PLL. 380 * | | |10 = Clock source from PCLK0. 381 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 382 * |[5:4] |SPI0SEL |SPI0 Clock Source Selection 383 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 384 * | | |01 = Clock source from PLL. 385 * | | |10 = Clock source from PCLK1. 386 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 387 * |[7:6] |SPI1SEL |SPI1 Clock Source Selection 388 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 389 * | | |01 = Clock source from PLL. 390 * | | |10 = Clock source from PCLK0. 391 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 392 * |[8] |BPWM0SEL |BPWM0 Clock Source Selection (Read Only) 393 * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. 394 * | | |1 = Clock source from PCLK0. 395 * |[9] |BPWM1SEL |BPWM1 Clock Source Selection (Read Only) 396 * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. 397 * | | |1 = Clock source from PCLK1. 398 * |[11:10] |SPI2SEL |SPI2 Clock Source Selection 399 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 400 * | | |01 = Clock source from PLL. 401 * | | |10 = Clock source from PCLK1. 402 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 403 * |[13:12] |SPI3SEL |SPI3 Clock Source Selection 404 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 405 * | | |01 = Clock source from PLL. 406 * | | |10 = Clock source from PCLK0. 407 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 408 * @var CLK_T::CLKSEL3 409 * Offset: 0x1C Clock Source Select Control Register 3 410 * --------------------------------------------------------------------------------------------------- 411 * |Bits |Field |Descriptions 412 * | :----: | :----: | :---- | 413 * |[1:0] |SC0SEL |Smart Card 0 (SC0) Clock Source Selection 414 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 415 * | | |01 = Clock source from PLL. 416 * | | |10 = Clock source from PCLK0. 417 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 418 * |[3:2] |SC1SEL |Smart Card 1 (SC1) Clock Source Selection 419 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 420 * | | |01 = Clock source from PLL. 421 * | | |10 = Clock source from PCLK1. 422 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 423 * |[5:4] |SC2SEL |Smart Card 2 (SC2) Clock Source Selection 424 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 425 * | | |01 = Clock source from PLL. 426 * | | |10 = Clock source from PCLK0. 427 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 428 * |[8] |RTCSEL |RTC Clock Source Selection 429 * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 430 * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 431 * |[17:16] |I2S0SEL |I2S0 Clock Source Selection 432 * | | |00 = Clock source from HXT clock. 433 * | | |01 = Clock source from PLL clock. 434 * | | |10 = Clock source from PCLK0. 435 * | | |11 = Clock source from HIRC clock. 436 * |[25:24] |UART2SEL |UART2 Clock Source Selection 437 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 438 * | | |01 = Clock source from PLL. 439 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 440 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 441 * |[27:26] |UART3SEL |UART3 Clock Source Selection 442 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 443 * | | |01 = Clock source from PLL. 444 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 445 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 446 * |[29:28] |UART4SEL |UART4 Clock Source Selection 447 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 448 * | | |01 = Clock source from PLL. 449 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 450 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 451 * |[31:30] |UART5SEL |UART5 Clock Source Selection 452 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 453 * | | |01 = Clock source from PLL. 454 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 455 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 456 * @var CLK_T::CLKDIV0 457 * Offset: 0x20 Clock Divider Number Register 0 458 * --------------------------------------------------------------------------------------------------- 459 * |Bits |Field |Descriptions 460 * | :----: | :----: | :---- | 461 * |[3:0] |HCLKDIV |HCLK Clock Divide Number from HCLK Clock Source 462 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). 463 * |[7:4] |USBDIV |USB Clock Divide Number from PLL Clock 464 * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1). 465 * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source 466 * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). 467 * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source 468 * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). 469 * |[23:16] |EADCDIV |EADC Clock Divide Number from EADC Clock Source 470 * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). 471 * |[31:24] |SDH0DIV |SDHOST0 Clock Divide Number from SDHOST0 Clock Source 472 * | | |SDHOST0 clock frequency = (SDHOST0 clock source frequency) / (SDH0DIV + 1). 473 * @var CLK_T::CLKDIV1 474 * Offset: 0x24 Clock Divider Number Register 1 475 * --------------------------------------------------------------------------------------------------- 476 * |Bits |Field |Descriptions 477 * | :----: | :----: | :---- | 478 * |[7:0] |SC0DIV |Smart Card 0 (SC0) Clock Divide Number from SC0 Clock Source 479 * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). 480 * |[15:8] |SC1DIV |Smart Card 1 (SC1) Clock Divide Number from SC1 Clock Source 481 * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). 482 * |[23:16] |SC2DIV |Smart Card 2 (SC2) Clock Divide Number from SC2 Clock Source 483 * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1). 484 * @var CLK_T::CLKDIV4 485 * Offset: 0x30 Clock Divider Number Register 4 486 * --------------------------------------------------------------------------------------------------- 487 * |Bits |Field |Descriptions 488 * | :----: | :----: | :---- | 489 * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source 490 * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). 491 * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source 492 * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). 493 * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source 494 * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). 495 * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source 496 * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). 497 * @var CLK_T::PCLKDIV 498 * Offset: 0x34 APB Clock Divider Register 499 * --------------------------------------------------------------------------------------------------- 500 * |Bits |Field |Descriptions 501 * | :----: | :----: | :---- | 502 * |[2:0] |APB0DIV |APB0 Clock Divider 503 * | | |APB0 clock can be divided from HCLK. 504 * | | |000 = PCLK0 frequency is HCLK. 505 * | | |001 = PCLK0 frequency is 1/2 HCLK. 506 * | | |010 = PCLK0 frequency is 1/4 HCLK. 507 * | | |011 = PCLK0 frequency is 1/8 HCLK. 508 * | | |100 = PCLK0 frequency is 1/16 HCLK. 509 * | | |101 = PCLK0 frequency is 1/32 HCLK. 510 * | | |Others = Reserved. 511 * |[6:4] |APB1DIV |APB1 Clock Divider 512 * | | |APB1 clock can be divided from HCLK. 513 * | | |000 = PCLK1 frequency is HCLK. 514 * | | |001 = PCLK1 frequency is 1/2 HCLK. 515 * | | |010 = PCLK1 frequency is 1/4 HCLK. 516 * | | |011 = PCLK1 frequency is 1/8 HCLK. 517 * | | |100 = PCLK1 frequency is 1/16 HCLK. 518 * | | |101 = PCLK1 frequency is 1/32 HCLK. 519 * | | |Others = Reserved. 520 * @var CLK_T::PLLCTL 521 * Offset: 0x40 PLL Control Register 522 * --------------------------------------------------------------------------------------------------- 523 * |Bits |Field |Descriptions 524 * | :----: | :----: | :---- | 525 * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) 526 * | | |Refer to the PLL formulas. 527 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 528 * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) 529 * | | |Refer to the PLL formulas. 530 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 531 * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) 532 * | | |Refer to the PLL formulas. 533 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 534 * |[16] |PD |Power-down Mode (Write Protect) 535 * | | |0 = PLL is enable (in normal mode). 536 * | | |1 = PLL is disable (in Power-down mode) (default). 537 * | | |Note1: If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. 538 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 539 * |[17] |BP |PLL Bypass Control (Write Protect) 540 * | | |0 = PLL is in normal mode (default). 541 * | | |1 = PLL clock output is same as PLL input clock FIN. 542 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 543 * |[18] |OE |PLL OE (FOUT Enable) Control (Write Protect) 544 * | | |0 = PLL FOUT Enabled. 545 * | | |1 = PLL FOUT is fixed low. 546 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 547 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) 548 * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). 549 * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). 550 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 551 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) 552 * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). 553 * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). 554 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 555 * @var CLK_T::STATUS 556 * Offset: 0x50 Clock Status Monitor Register 557 * --------------------------------------------------------------------------------------------------- 558 * |Bits |Field |Descriptions 559 * | :----: | :----: | :---- | 560 * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) 561 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. 562 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. 563 * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) 564 * | | |LXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]). 565 * | | |If C32KS is set to 0 the LXT stable flag is set when extLXT clock source is stable. 566 * | | |If C32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable. 567 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. 568 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. 569 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) 570 * | | |0 = Internal PLL clock is not stable or disabled. 571 * | | |1 = Internal PLL clock is stable and enabled. 572 * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) 573 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. 574 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. 575 * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) 576 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. 577 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. 578 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) 579 * | | |This bit is updated when software switches system clock source. 580 * | | |If switch target clock is stable, this bit will be set to 0. 581 * | | |If switch target clock is not stable, this bit will be set to 1. 582 * | | |0 = Clock switching success. 583 * | | |1 = Clock switching failure. 584 * | | |Note: This bit is read only. 585 * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. 586 * |[8] |EXTLXTSTB |EXTLXT Clock Source Stable Flag (Read Only) 587 * | | |0 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is not stable or disabled. 588 * | | |1 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is stable and enabled. 589 * |[9] |LIRC32STB |LIRC32 Clock Source Stable Flag (Read Only) 590 * | | |0 = 32 kHz internal low speed RC oscillator (LIRC32) clock is not stable or disabled. 591 * | | |1 = 32 kHz internal low speed RC oscillator (LIRC32) clock is stable and enabled. 592 * @var CLK_T::CLKOCTL 593 * Offset: 0x60 Clock Output Control Register 594 * --------------------------------------------------------------------------------------------------- 595 * |Bits |Field |Descriptions 596 * | :----: | :----: | :---- | 597 * |[3:0] |FREQSEL |Clock Output Frequency Selection 598 * | | |The formula of output frequency is Fout = Fin/2^(N+1). 599 * | | |Fin is the input clock frequency. 600 * | | |Fout is the frequency of divider output clock. 601 * | | |N is the 4-bit value of FREQSEL[3:0]. 602 * |[4] |CLKOEN |Clock Output Enable Bit 603 * | | |0 = Clock Output function Disabled. 604 * | | |1 = Clock Output function Enabled. 605 * |[5] |DIV1EN |Clock Output Divide One Enable Bit 606 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. 607 * | | |1 = Clock Output will output clock with source frequency. 608 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit 609 * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. 610 * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. 611 * @var CLK_T::CLKDCTL 612 * Offset: 0x70 Clock Fail Detector Control Register 613 * --------------------------------------------------------------------------------------------------- 614 * |Bits |Field |Descriptions 615 * | :----: | :----: | :---- | 616 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit 617 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. 618 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. 619 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit 620 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. 621 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. 622 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit 623 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. 624 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. 625 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit 626 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. 627 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. 628 * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit 629 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled. 630 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled. 631 * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit 632 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled. 633 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled. 634 * @var CLK_T::CLKDSTS 635 * Offset: 0x74 Clock Fail Detector Status Register 636 * --------------------------------------------------------------------------------------------------- 637 * |Bits |Field |Descriptions 638 * | :----: | :----: | :---- | 639 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) 640 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. 641 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. 642 * | | |Note1: Write 1 to clear the bit to 0. 643 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 644 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) 645 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. 646 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. 647 * | | |Note1: Write 1 to clear the bit to 0. 648 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 649 * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag (Write Protect) 650 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. 651 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. 652 * | | |Note1: Write 1 to clear the bit to 0. 653 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 654 * @var CLK_T::CDUPB 655 * Offset: 0x78 Clock Frequency Detector Upper Boundary Register 656 * --------------------------------------------------------------------------------------------------- 657 * |Bits |Field |Descriptions 658 * | :----: | :----: | :---- | 659 * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary 660 * | | |The bits define the high value of frequency monitor window. 661 * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. 662 * @var CLK_T::CDLOWB 663 * Offset: 0x7C Clock Frequency Detector Lower Boundary Register 664 * --------------------------------------------------------------------------------------------------- 665 * |Bits |Field |Descriptions 666 * | :----: | :----: | :---- | 667 * |[9:0] |LOWERBD |HXT Clock Frequency Detector Lower Boundary 668 * | | |The bits define the low value of frequency monitor window. 669 * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. 670 * @var CLK_T::PMUCTL 671 * Offset: 0x90 Power Manager Control Register 672 * --------------------------------------------------------------------------------------------------- 673 * |Bits |Field |Descriptions 674 * | :----: | :----: | :---- | 675 * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) 676 * | | |These bits control chip Power-down mode grade selection when CPU execute WFI/WFE instruction. 677 * | | |000 = Power-down mode is selected (PD). 678 * | | |001 = Low leakage Power-down mode is selected (LLPD). 679 * | | |010 = Fast wake-up Power-down (FWPD). 680 * | | |011 = Ultra low leakage Power-down mode is selected (ULLPD). 681 * | | |100 = Standby Power-down mode is selected (SPD). 682 * | | |101 = Reserved. 683 * | | |110 = Deep Power-down mode is selected (DPD). 684 * | | |111 = Reserved. 685 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 686 * |[8] |WKTMREN |Wake-up Timer Enable Bit (Write Protect) 687 * | | |0 = Wake-up timer Disable in Deep Power-down mode or Standby Power-down mode. 688 * | | |1 = Wake-up timer Enabled in Deep Power-down mode or Standby Power-down mode. 689 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 690 * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) 691 * | | |These bits control wake-up timer time-out interval when chip under Deep Power-down mode or Standby Power-down mode. 692 * | | |000 = Time-out interval is 128 LIRC clocks (12.8ms). 693 * | | |001 = Time-out interval is 256 LIRC clocks (25.6ms). 694 * | | |010 = Time-out interval is 512 LIRC clocks (51.2ms). 695 * | | |011 = Time-out interval is 1024 LIRC clocks (102.4ms). 696 * | | |100 = Time-out interval is 4096 LIRC clocks (409.6ms). 697 * | | |101 = Time-out interval is 8192 LIRC clocks (819.2ms). 698 * | | |110 = Time-out interval is 16384 LIRC clocks (1638.4ms). 699 * | | |111 = Time-out interval is 65536 LIRC clocks (6553.6ms). 700 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 701 * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect) 702 * | | |00 = Wake-up pin Disable in Deep Power-down mode. 703 * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. 704 * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. 705 * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. 706 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 707 * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) 708 * | | |0 = ACMP wake-up Disable in Standby Power-down mode. 709 * | | |1 = ACMP wake-up Enabled in Standby Power-down mode. 710 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 711 * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) 712 * | | |This is a protected register. Please refer to open lock sequence to program it. 713 * | | |0 = RTC wake-up Disable in Deep Power-down mode or Standby Power-down mode. 714 * | | |1 = RTC wake-up Enabled in Deep Power-down mode or Standby Power-down mode. 715 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 716 * @var CLK_T::PMUSTS 717 * @var CLK_T::PMUSTS 718 * Offset: 0x94 Power Manager Status Register 719 * --------------------------------------------------------------------------------------------------- 720 * |Bits |Field |Descriptions 721 * | :----: | :----: | :---- | 722 * |[0] |PINWK |Pin Wake-up Flag (Read Only) 723 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0). 724 * | | |This flag is cleared when DPD mode is entered. 725 * |[1] |TMRWK |Timer Wake-up Flag (Read Only) 726 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. 727 * | | |This flag is cleared when DPD or SPD mode is entered. 728 * |[2] |RTCWK |RTC Wake-up Flag (Read Only) 729 * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. 730 * | | |This flag is cleared when DPD or SPD mode is entered. 731 * |[8] |GPAWK |GPA Wake-up Flag (Read Only) 732 * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins. 733 * | | |This flag is cleared when SPD mode is entered. 734 * |[9] |GPBWK |GPB Wake-up Flag (Read Only) 735 * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins. 736 * | | |This flag is cleared when SPD mode is entered. 737 * |[10] |GPCWK |GPC Wake-up Flag (Read Only) 738 * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins. 739 * | | |This flag is cleared when SPD mode is entered. 740 * |[11] |GPDWK |GPD Wake-up Flag (Read Only) 741 * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins. 742 * | | |This flag is cleared when SPD mode is entered. 743 * |[12] |LVRWK |LVR Wake-up Flag (Read Only) 744 * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a LVR happened. 745 * | | |This flag is cleared when SPD mode is entered. 746 * |[13] |BODWK |BOD Wake-up Flag (Read Only) 747 * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a BOD happened. 748 * | | |This flag is cleared when SPD mode is entered. 749 * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) 750 * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a ACMP transition. 751 * | | |This flag is cleared when SPD mode is entered. 752 * |[31] |CLRWK |Clear Wake-up Flag 753 * | | |0 = No clear. 754 * | | |1 = Clear all wake-up flag. 755 * | | |Note: This bit is auto cleared by hardware. 756 * @var CLK_T::SWKDBCTL 757 * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register 758 * --------------------------------------------------------------------------------------------------- 759 * |Bits |Field |Descriptions 760 * | :----: | :----: | :---- | 761 * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection 762 * | | |0000 = Sample wake-up input once per 1 clocks. 763 * | | |0001 = Sample wake-up input once per 2 clocks. 764 * | | |0010 = Sample wake-up input once per 4 clocks. 765 * | | |0011 = Sample wake-up input once per 8 clocks. 766 * | | |0100 = Sample wake-up input once per 16 clocks. 767 * | | |0101 = Sample wake-up input once per 32 clocks. 768 * | | |0110 = Sample wake-up input once per 64 clocks. 769 * | | |0111 = Sample wake-up input once per 128 clocks. 770 * | | |1000 = Sample wake-up input once per 256 clocks. 771 * | | |1001 = Sample wake-up input once per 2*256 clocks. 772 * | | |1010 = Sample wake-up input once per 4*256 clocks. 773 * | | |1011 = Sample wake-up input once per 8*256 clocks. 774 * | | |1100 = Sample wake-up input once per 16*256 clocks. 775 * | | |1101 = Sample wake-up input once per 32*256 clocks. 776 * | | |1110 = Sample wake-up input once per 64*256 clocks. 777 * | | |1111 = Sample wake-up input once per 128*256 clocks. 778 * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). 779 * @var CLK_T::PASWKCTL 780 * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register 781 * --------------------------------------------------------------------------------------------------- 782 * |Bits |Field |Descriptions 783 * | :----: | :----: | :---- | 784 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 785 * | | |0 = GPA group pin wake-up function ddisabled. 786 * | | |1 = GPA group pin wake-up function Enabled. 787 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 788 * | | |0 = GPA group pin rising edge wake-up function Disabled. 789 * | | |1 = GPA group pin rising edge wake-up function Enabled. 790 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 791 * | | |0 = GPA group pin falling edge wake-up function Disabled. 792 * | | |1 = GPA group pin falling edge wake-up function Enabled. 793 * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select 794 * | | |0000 = GPA.0 wake-up function enabled. 795 * | | |0001 = GPA.1 wake-up function enabled. 796 * | | |0010 = GPA.2 wake-up function enabled. 797 * | | |0011 = GPA.3 wake-up function enabled. 798 * | | |0100 = GPA.4 wake-up function enabled. 799 * | | |0101 = GPA.5 wake-up function enabled. 800 * | | |0110 = GPA.6 wake-up function enabled. 801 * | | |0111 = GPA.7 wake-up function enabled. 802 * | | |1000 = GPA.8 wake-up function enabled. 803 * | | |1001 = GPA.9 wake-up function enabled. 804 * | | |1010 = GPA.10 wake-up function enabled. 805 * | | |1011 = GPA.11 wake-up function enabled. 806 * | | |1100 = GPA.12 wake-up function enabled. 807 * | | |1101 = GPA.13 wake-up function enabled. 808 * | | |1110 = GPA.14 wake-up function enabled. 809 * | | |1111 = GPA.15 wake-up function enabled. 810 * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit 811 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. 812 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. 813 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 814 * | | |0 = Standby power-down wake-up pin De-bounce function Disable. 815 * | | |1 = Standby power-down wake-up pin De-bounce function Enable. 816 * | | |The de-bounce function is valid only for edge triggered. 817 * @var CLK_T::PBSWKCTL 818 * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register 819 * --------------------------------------------------------------------------------------------------- 820 * |Bits |Field |Descriptions 821 * | :----: | :----: | :---- | 822 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 823 * | | |0 = GPB group pin wake-up function Disabled. 824 * | | |1 = GPB group pin wake-up function Enabled. 825 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 826 * | | |0 = GPB group pin rising edge wake-up function Disabled. 827 * | | |1 = GPB group pin rising edge wake-up function Enabled. 828 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 829 * | | |0 = GPB group pin falling edge wake-up function Disabled. 830 * | | |1 = GPB group pin falling edge wake-up function Enabled. 831 * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select 832 * | | |0000 = GPB.0 wake-up function enabled. 833 * | | |0001 = GPB.1 wake-up function enabled. 834 * | | |0010 = GPB.2 wake-up function enabled. 835 * | | |0011 = GPB.3 wake-up function enabled. 836 * | | |0100 = GPB.4 wake-up function enabled. 837 * | | |0101 = GPB.5 wake-up function enabled. 838 * | | |0110 = GPB.6 wake-up function enabled. 839 * | | |0111 = GPB.7 wake-up function enabled. 840 * | | |1000 = GPB.8 wake-up function enabled. 841 * | | |1001 = GPB.9 wake-up function enabled. 842 * | | |1010 = GPB.10 wake-up function enabled. 843 * | | |1011 = GPB.11 wake-up function enabled. 844 * | | |1100 = GPB.12 wake-up function enabled. 845 * | | |1101 = GPB.13 wake-up function enabled. 846 * | | |1110 = GPB.14 wake-up function enabled. 847 * | | |1111 = GPB.15 wake-up function enabled. 848 * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit 849 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. 850 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. 851 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 852 * | | |0 = Standby power-down wake-up pin De-bounce function Disable. 853 * | | |1 = Standby power-down wake-up pin De-bounce function Enable. 854 * | | |The de-bounce function is valid only for edge triggered. 855 * @var CLK_T::PCSWKCTL 856 * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register 857 * --------------------------------------------------------------------------------------------------- 858 * |Bits |Field |Descriptions 859 * | :----: | :----: | :---- | 860 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 861 * | | |0 = GPC group pin wake-up function Disabled. 862 * | | |1 = GPC group pin wake-up function Enabled. 863 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 864 * | | |0 = GPC group pin rising edge wake-up function Disabled. 865 * | | |1 = GPC group pin rising edge wake-up function Enabled. 866 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 867 * | | |0 = GPC group pin falling edge wake-up function Disabled. 868 * | | |1 = GPC group pin falling edge wake-up function Enabled. 869 * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select 870 * | | |0000 = GPC.0 wake-up function enabled. 871 * | | |0001 = GPC.1 wake-up function enabled. 872 * | | |0010 = GPC.2 wake-up function enabled. 873 * | | |0011 = GPC.3 wake-up function enabled. 874 * | | |0100 = GPC.4 wake-up function enabled. 875 * | | |0101 = GPC.5 wake-up function enabled. 876 * | | |0110 = GPC.6 wake-up function enabled. 877 * | | |0111 = GPC.7 wake-up function enabled. 878 * | | |1000 = GPC.8 wake-up function enabled. 879 * | | |1001 = GPC.9 wake-up function enabled. 880 * | | |1010 = GPC.10 wake-up function enabled. 881 * | | |1011 = GPC.11 wake-up function enabled. 882 * | | |1100 = GPC.12 wake-up function enabled. 883 * | | |1101 = GPC.13 wake-up function enabled. 884 * | | |1110 = Reserved. 885 * | | |1111 = Reserved. 886 * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit 887 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. 888 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. 889 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 890 * | | |0 = Standby power-down wake-up pin De-bounce function Disable. 891 * | | |1 = Standby power-down wake-up pin De-bounce function Enable. 892 * | | |The de-bounce function is valid only for edge triggered. 893 * @var CLK_T::PDSWKCTL 894 * Offset: 0xAC GPD Standby Power-down Wake-up Control Register 895 * --------------------------------------------------------------------------------------------------- 896 * |Bits |Field |Descriptions 897 * | :----: | :----: | :---- | 898 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 899 * | | |0 = GPD group pin wake-up function Disabled. 900 * | | |1 = GPD group pin wake-up function Enabled. 901 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 902 * | | |0 = GPD group pin rising edge wake-up function Disabled. 903 * | | |1 = GPD group pin rising edge wake-up function Enabled. 904 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 905 * | | |0 = GPD group pin falling edge wake-up function Disabled. 906 * | | |1 = GPD group pin falling edge wake-up function Enabled. 907 * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select 908 * | | |0000 = GPD.0 wake-up function enabled. 909 * | | |0001 = GPD.1 wake-up function enabled. 910 * | | |0010 = GPD.2 wake-up function enabled. 911 * | | |0011 = GPD.3 wake-up function enabled. 912 * | | |0100 = GPD.4 wake-up function enabled. 913 * | | |0101 = GPD.5 wake-up function enabled. 914 * | | |0110 = GPD.6 wake-up function enabled. 915 * | | |0111 = GPD.7 wake-up function enabled. 916 * | | |1000 = GPD.8 wake-up function enabled. 917 * | | |1001 = GPD.9 wake-up function enabled. 918 * | | |1010 = GPD.10 wake-up function enabled. 919 * | | |1011 = GPD.11 wake-up function enabled. 920 * | | |1100 = GPD.12 wake-up function enabled. 921 * | | |1101 = GPD.13 wake-up function enabled. 922 * | | |1110 = GPD.14 wake-up function enabled. 923 * | | |1111 = Reserved. 924 * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit 925 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. 926 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. 927 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 928 * | | |0 = Standby power-down wake-up pin De-bounce function Disable. 929 * | | |1 = Standby power-down wake-up pin De-bounce function Enable. 930 * | | |The de-bounce function is valid only for edge triggered. 931 * @var CLK_T::IOPDCTL 932 * Offset: 0xB0 GPIO Standby Power-down Control Register 933 * --------------------------------------------------------------------------------------------------- 934 * |Bits |Field |Descriptions 935 * | :----: | :----: | :---- | 936 * |[0] |IOHR |GPIO Hold Release 937 * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status. 938 * | | |After chip was waked up from standby Power-down mode, the I/O still keeps hold status until user sets this bit to release I/O hold status. 939 * | | |Note: This bit is auto cleared by hardware. 940 * @var CLK_T::HXTFSEL 941 * Offset: 0xB4 HXT Filter Select Control Register 942 * --------------------------------------------------------------------------------------------------- 943 * |Bits |Field |Descriptions 944 * | :----: | :----: | :---- | 945 * |[0] |HXTFSEL |HXT Filter Select 946 * | | |0 = HXT frequency is > 12MHz. 947 * | | |1 = HXT frequency is <= 12MHz. 948 * | | |Note: This bit is auto cleared by hardware. 949 */ 950 951 952 __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ 953 __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ 954 __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ 955 __IO uint32_t APBCLK1; /*!< [0x000C] APB Devices Clock Enable Control Register 1 */ 956 __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ 957 __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ 958 __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ 959 __IO uint32_t CLKSEL3; /*!< [0x001C] Clock Source Select Control Register 3 */ 960 __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ 961 __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ 962 __I uint32_t RESERVE0[2]; 963 __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ 964 __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ 965 __I uint32_t RESERVE1[2]; 966 __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ 967 __I uint32_t RESERVE2[3]; 968 __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ 969 __I uint32_t RESERVE3[3]; 970 __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ 971 __I uint32_t RESERVE4[3]; 972 __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ 973 __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ 974 __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Detector Upper Boundary Register */ 975 __IO uint32_t CDLOWB; /*!< [0x007C] Clock Frequency Detector Low Boundary Register */ 976 __I uint32_t RESERVE5[4]; 977 __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ 978 __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ 979 __I uint32_t RESERVE6[1]; 980 __IO uint32_t SWKDBCTL; /*!< [0x009C] Standby Power-down Wake-up De-bounce Control Register */ 981 __IO uint32_t PASWKCTL; /*!< [0x00A0] GPA Standby Power-down Wake-up Control Register */ 982 __IO uint32_t PBSWKCTL; /*!< [0x00A4] GPB Standby Power-down Wake-up Control Register */ 983 __IO uint32_t PCSWKCTL; /*!< [0x00A8] GPC Standby Power-down Wake-up Control Register */ 984 __IO uint32_t PDSWKCTL; /*!< [0x00AC] GPD Standby Power-down Wake-up Control Register */ 985 __IO uint32_t IOPDCTL; /*!< [0x00B0] GPIO Standby Power-down Control Register */ 986 __IO uint32_t HXTFSEL; /*!< [0x00B4] HXT Filter Select Control Register */ 987 988 } CLK_T; 989 990 /** 991 @addtogroup CLK_CONST CLK Bit Field Definition 992 Constant Definitions for CLK Controller 993 @{ */ 994 995 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ 996 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ 997 998 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ 999 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ 1000 1001 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ 1002 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ 1003 1004 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ 1005 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ 1006 1007 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ 1008 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ 1009 1010 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ 1011 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ 1012 1013 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ 1014 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ 1015 1016 #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ 1017 #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ 1018 1019 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ 1020 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ 1021 1022 #define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ 1023 #define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ 1024 1025 #define CLK_PWRCTL_HIRC48EN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48EN Position */ 1026 #define CLK_PWRCTL_HIRC48EN_Msk (0x1ul << CLK_PWRCTL_HIRC48EN_Pos) /*!< CLK_T::PWRCTL: HIRC48EN Mask */ 1027 1028 #define CLK_AHBCLK_PDMA0CKEN_Pos (0) /*!< CLK_T::AHBCLK: PDMA0CKEN Position */ 1029 #define CLK_AHBCLK_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA0CKEN Mask */ 1030 1031 #define CLK_AHBCLK_PDMA1CKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMA1CKEN Position */ 1032 #define CLK_AHBCLK_PDMA1CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA1CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA1CKEN Mask */ 1033 1034 #define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ 1035 #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ 1036 1037 #define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ 1038 #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ 1039 1040 #define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ 1041 #define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ 1042 1043 #define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ 1044 #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ 1045 1046 #define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ 1047 #define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ 1048 1049 #define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ 1050 #define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ 1051 1052 #define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ 1053 #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ 1054 1055 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ 1056 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ 1057 1058 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ 1059 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ 1060 1061 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ 1062 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ 1063 1064 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ 1065 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ 1066 1067 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ 1068 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ 1069 1070 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ 1071 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ 1072 1073 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ 1074 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ 1075 1076 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ 1077 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ 1078 1079 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ 1080 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ 1081 1082 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ 1083 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ 1084 1085 #define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ 1086 #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ 1087 1088 #define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ 1089 #define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ 1090 1091 #define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ 1092 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ 1093 1094 #define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ 1095 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ 1096 1097 #define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ 1098 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ 1099 1100 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ 1101 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ 1102 1103 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ 1104 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ 1105 1106 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ 1107 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ 1108 1109 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ 1110 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ 1111 1112 #define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ 1113 #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ 1114 1115 #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ 1116 #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ 1117 1118 #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ 1119 #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ 1120 1121 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ 1122 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ 1123 1124 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ 1125 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ 1126 1127 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ 1128 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ 1129 1130 #define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ 1131 #define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ 1132 1133 #define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ 1134 #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ 1135 1136 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ 1137 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ 1138 1139 #define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ 1140 #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ 1141 1142 #define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ 1143 #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ 1144 1145 #define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ 1146 #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ 1147 1148 #define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ 1149 #define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ 1150 1151 #define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ 1152 #define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ 1153 1154 #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ 1155 #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ 1156 1157 #define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ 1158 #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ 1159 1160 #define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ 1161 #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ 1162 1163 #define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ 1164 #define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ 1165 1166 #define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ 1167 #define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ 1168 1169 #define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ 1170 #define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ 1171 1172 #define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ 1173 #define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ 1174 1175 #define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ 1176 #define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ 1177 1178 #define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ 1179 #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ 1180 1181 #define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ 1182 #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ 1183 1184 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ 1185 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ 1186 1187 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ 1188 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ 1189 1190 #define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */ 1191 #define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */ 1192 1193 #define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ 1194 #define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ 1195 1196 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ 1197 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ 1198 1199 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ 1200 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ 1201 1202 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ 1203 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ 1204 1205 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ 1206 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ 1207 1208 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ 1209 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ 1210 1211 #define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ 1212 #define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ 1213 1214 #define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ 1215 #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ 1216 1217 #define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ 1218 #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ 1219 1220 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ 1221 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ 1222 1223 #define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ 1224 #define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ 1225 1226 #define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ 1227 #define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ 1228 1229 #define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ 1230 #define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ 1231 1232 #define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ 1233 #define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ 1234 1235 #define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ 1236 #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ 1237 1238 #define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ 1239 #define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ 1240 1241 #define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ 1242 #define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ 1243 1244 #define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ 1245 #define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ 1246 1247 #define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ 1248 #define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ 1249 1250 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ 1251 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ 1252 1253 #define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ 1254 #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ 1255 1256 #define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ 1257 #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ 1258 1259 #define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */ 1260 #define CLK_CLKSEL3_RTCSEL_Msk (0x3ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */ 1261 1262 #define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ 1263 #define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ 1264 1265 #define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ 1266 #define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ 1267 1268 #define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ 1269 #define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ 1270 1271 #define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ 1272 #define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ 1273 1274 #define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ 1275 #define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ 1276 1277 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ 1278 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ 1279 1280 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ 1281 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ 1282 1283 #define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ 1284 #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ 1285 1286 #define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ 1287 #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ 1288 1289 #define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ 1290 #define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ 1291 1292 #define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ 1293 #define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ 1294 1295 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ 1296 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ 1297 1298 #define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ 1299 #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ 1300 1301 #define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ 1302 #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ 1303 1304 #define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ 1305 #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ 1306 1307 #define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ 1308 #define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ 1309 1310 #define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ 1311 #define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ 1312 1313 #define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ 1314 #define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ 1315 1316 #define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ 1317 #define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ 1318 1319 #define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ 1320 #define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ 1321 1322 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ 1323 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ 1324 1325 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ 1326 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ 1327 1328 #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ 1329 #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ 1330 1331 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ 1332 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ 1333 1334 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ 1335 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ 1336 1337 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ 1338 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ 1339 1340 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ 1341 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ 1342 1343 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ 1344 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ 1345 1346 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ 1347 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ 1348 1349 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ 1350 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ 1351 1352 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ 1353 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ 1354 1355 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ 1356 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ 1357 1358 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ 1359 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ 1360 1361 #define CLK_STATUS_HIRC48STB_Pos (6) /*!< CLK_T::STATUS: HIRC48STB Position */ 1362 #define CLK_STATUS_HIRC48STB_Msk (0x1ul << CLK_STATUS_HIRC48STB_Pos) /*!< CLK_T::STATUS: HIRC48STB Mask */ 1363 1364 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ 1365 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ 1366 1367 #define CLK_STATUS_EXTLXTSTB_Pos (8) /*!< CLK_T::STATUS: EXTLXTSTB Position */ 1368 #define CLK_STATUS_EXTLXTSTB_Msk (0x1ul << CLK_STATUS_EXTLXTSTB_Pos) /*!< CLK_T::STATUS: EXTLXTSTB Mask */ 1369 1370 #define CLK_STATUS_LIRC32STB_Pos (9) /*!< CLK_T::STATUS: LIRC32STB Position */ 1371 #define CLK_STATUS_LIRC32STB_Msk (0x1ul << CLK_STATUS_LIRC32STB_Pos) /*!< CLK_T::STATUS: LIRC32STB Mask */ 1372 1373 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ 1374 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ 1375 1376 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ 1377 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ 1378 1379 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ 1380 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ 1381 1382 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ 1383 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ 1384 1385 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ 1386 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ 1387 1388 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ 1389 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ 1390 1391 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ 1392 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ 1393 1394 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ 1395 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ 1396 1397 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ 1398 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ 1399 1400 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ 1401 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ 1402 1403 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ 1404 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ 1405 1406 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ 1407 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ 1408 1409 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ 1410 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ 1411 1412 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ 1413 #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ 1414 1415 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ 1416 #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ 1417 1418 #define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ 1419 #define CLK_PMUCTL_PDMSEL_Msk (0x7ul<< CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ 1420 1421 #define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ 1422 #define CLK_PMUCTL_WKTMREN_Msk (0x1ul<< CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ 1423 1424 #define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ 1425 #define CLK_PMUCTL_WKTMRIS_Msk (0x7ul<< CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ 1426 1427 #define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ 1428 #define CLK_PMUCTL_WKPINEN_Msk (0x3ul<< CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ 1429 1430 #define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ 1431 #define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul<< CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ 1432 1433 #define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ 1434 #define CLK_PMUCTL_RTCWKEN_Msk (0x1ul<< CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ 1435 1436 #define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ 1437 #define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ 1438 1439 #define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ 1440 #define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ 1441 1442 #define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ 1443 #define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ 1444 1445 #define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ 1446 #define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ 1447 1448 #define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ 1449 #define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ 1450 1451 #define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ 1452 #define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ 1453 1454 #define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ 1455 #define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ 1456 1457 #define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ 1458 #define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ 1459 1460 #define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ 1461 #define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ 1462 1463 #define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ 1464 #define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ 1465 1466 #define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ 1467 #define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ 1468 1469 #define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ 1470 #define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xFul<< CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ 1471 1472 #define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ 1473 #define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ 1474 1475 #define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ 1476 #define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ 1477 1478 #define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ 1479 #define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ 1480 1481 #define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ 1482 #define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ 1483 1484 #define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ 1485 #define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ 1486 1487 #define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ 1488 #define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ 1489 1490 #define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ 1491 #define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ 1492 1493 #define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ 1494 #define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ 1495 1496 #define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ 1497 #define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ 1498 1499 #define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ 1500 #define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ 1501 1502 #define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ 1503 #define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ 1504 1505 #define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ 1506 #define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ 1507 1508 #define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ 1509 #define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ 1510 1511 #define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ 1512 #define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ 1513 1514 #define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ 1515 #define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ 1516 1517 #define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ 1518 #define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ 1519 1520 #define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ 1521 #define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ 1522 1523 #define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ 1524 #define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ 1525 1526 #define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ 1527 #define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ 1528 1529 #define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ 1530 #define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ 1531 1532 #define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ 1533 #define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ 1534 1535 #define CLK_HXTFSEL_HXTFSEL_Pos (0) /*!< CLK_T::HXTFSEL: HXTFSEL Position */ 1536 #define CLK_HXTFSEL_HXTFSEL_Msk (0x1ul << CLK_HXTFSEL_HXTFSEL_Pos) /*!< CLK_T::HXTFSEL: HXTFSEL Mask */ 1537 1538 1539 /**@}*/ /* CLK_CONST */ 1540 /**@}*/ /* end of CLK register group */ 1541 /**@}*/ /* end of REGISTER group */ 1542 1543 #endif /* __CLK_REG_H__ */ 1544
