1 /* 2 * Copyright (c) 2022-2023, Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_ 8 #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_ 9 10 #include <stdint.h> 11 12 #include <zephyr/sys/sys_io.h> 13 14 /* Clock manager register offsets */ 15 #define CLKMGR_CTRL 0x00 16 #define CLKMGR_STAT 0x04 17 #define CLKMGR_INTRCLR 0x14 18 19 /* Clock manager main PLL group register offsets */ 20 #define CLKMGR_MAINPLL_OFFSET 0x24 21 #define CLKMGR_MAINPLL_EN 0x00 22 #define CLKMGR_MAINPLL_BYPASS 0x0C 23 #define CLKMGR_MAINPLL_MPUCLK 0x18 24 #define CLKMGR_MAINPLL_BYPASSS 0x10 25 #define CLKMGR_MAINPLL_NOCCLK 0x1C 26 #define CLKMGR_MAINPLL_NOCDIV 0x20 27 #define CLKMGR_MAINPLL_PLLGLOB 0x24 28 #define CLKMGR_MAINPLL_FDBCK 0x28 29 #define CLKMGR_MAINPLL_MEM 0x2C 30 #define CLKMGR_MAINPLL_MEMSTAT 0x30 31 #define CLKMGR_MAINPLL_VCOCALIB 0x34 32 #define CLKMGR_MAINPLL_PLLC0 0x38 33 #define CLKMGR_MAINPLL_PLLC1 0x3C 34 #define CLKMGR_MAINPLL_PLLC2 0x40 35 #define CLKMGR_MAINPLL_PLLC3 0x44 36 #define CLKMGR_MAINPLL_PLLM 0x48 37 #define CLKMGR_MAINPLL_LOSTLOCK 0x54 38 39 /* Clock manager peripheral PLL group register offsets */ 40 #define CLKMGR_PERPLL_OFFSET 0x7C 41 #define CLKMGR_PERPLL_EN 0x00 42 #define CLKMGR_PERPLL_BYPASS 0x0C 43 #define CLKMGR_PERPLL_BYPASSS 0x10 44 #define CLKMGR_PERPLL_EMACCTL 0x18 45 #define CLKMGR_PERPLL_GPIODIV 0x1C 46 #define CLKMGR_PERPLL_PLLGLOB 0x20 47 #define CLKMGR_PERPLL_FDBCK 0x24 48 #define CLKMGR_PERPLL_MEM 0x28 49 #define CLKMGR_PERPLL_MEMSTAT 0x2C 50 #define CLKMGR_PERPLL_VCOCALIB 0x30 51 #define CLKMGR_PERPLL_PLLC0 0x34 52 #define CLKMGR_PERPLL_PLLC1 0x38 53 #define CLKMGR_PERPLL_PLLC2 0x3C 54 #define CLKMGR_PERPLL_PLLC3 0x40 55 #define CLKMGR_PERPLL_PLLM 0x44 56 #define CLKMGR_PERPLL_LOSTLOCK 0x50 57 58 /* Clock manager control/intel group register offsets */ 59 #define CLKMGR_INTEL_OFFSET 0xD0 60 #define CLKMGR_INTEL_JTAG 0x00 61 #define CLKMGR_INTEL_EMACACTR 0x4 62 #define CLKMGR_INTEL_EMACBCTR 0x8 63 #define CLKMGR_INTEL_EMACPTPCTR 0x0C 64 #define CLKMGR_INTEL_GPIODBCTR 0x10 65 #define CLKMGR_INTEL_SDMMCCTR 0x14 66 #define CLKMGR_INTEL_S2FUSER0CTR 0x18 67 #define CLKMGR_INTEL_S2FUSER1CTR 0x1C 68 #define CLKMGR_INTEL_PSIREFCTR 0x20 69 #define CLKMGR_INTEL_EXTCNTRST 0x24 70 71 /* Clock manager macros */ 72 #define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001U 73 #define CLKMGR_STAT_BUSY_E_BUSY 0x1 74 #define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001U) >> 0) 75 #define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100U) >> 8) 76 #define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000U) >> 16) 77 #define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004U 78 #define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008U 79 #define CLKMGR_MAINPLL_L4SPDIV(x) (((x) >> 16) & 0x3) 80 #define CLKMGR_INTOSC_HZ 460000000U 81 82 /* Shared Macros */ 83 #define CLKMGR_PSRC(x) (((x) & 0x00030000U) >> 16) 84 #define CLKMGR_PSRC_MAIN 0 85 #define CLKMGR_PSRC_PER 1 86 87 #define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0 88 #define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1 89 #define CLKMGR_PLLGLOB_PSRC_F2S 0x2 90 91 #define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003FFU) 92 #define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001U 93 #define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002U 94 95 #define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003F00) >> 8) 96 #define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000F00) >> 8) 97 #define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) 98 99 #define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003FF) 100 #define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00FF0000) 101 102 #define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000U 103 #define CLKMGR_PLLC_DIV(x) ((x) & 0x7FF) 104 #define CLKMGR_INTEL_SDMMC_CNT(x) (((x) & 0x7FF) + 1) 105 106 /** 107 * @brief Initialize the low layer clock control driver 108 * 109 * @param base_addr : Clock control device MMIO base address 110 * 111 * @return void 112 */ 113 void clock_agilex5_ll_init(mm_reg_t base_addr); 114 115 /** 116 * @brief Get MPU(Micro Processor Unit) clock value 117 * 118 * @param void 119 * 120 * @return returns MPU clock value 121 */ 122 uint32_t get_mpu_clk(void); 123 124 /** 125 * @brief Get Watchdog peripheral clock value 126 * 127 * @param void 128 * 129 * @return returns Watchdog clock value 130 */ 131 uint32_t get_wdt_clk(void); 132 133 /** 134 * @brief Get UART peripheral clock value 135 * 136 * @param void 137 * 138 * @return returns UART clock value 139 */ 140 uint32_t get_uart_clk(void); 141 142 /** 143 * @brief Get MMC peripheral clock value 144 * 145 * @param void 146 * 147 * @return returns MMC clock value 148 */ 149 uint32_t get_mmc_clk(void); 150 151 /** 152 * @brief Get Timer peripheral clock value 153 * 154 * @param void 155 * 156 * @return returns Timer clock value 157 */ 158 uint32_t get_timer_clk(void); 159 160 #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_ */ 161
