1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CLOCKMANAGER_H 8 #define CLOCKMANAGER_H 9 10 #include "socfpga_handoff.h" 11 12 /* MACRO DEFINITION */ 13 #define SOCFPGA_GLOBAL_TIMER 0xffd01000 14 #define SOCFPGA_GLOBAL_TIMER_EN 0x3 15 16 #define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16) 17 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 18 #define CLKMGR_PLLDIV_FDIV_MASK GENMASK(16, 8) 19 #define CLKMGR_PLLDIV_FDIV_OFFSET 8 20 #define CLKMGR_PLLDIV_REFCLKDIV_MASK GENMASK(5, 0) 21 #define CLKMGR_PLLDIV_REFCLKDIV_OFFSET 0 22 #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24) 23 #define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24 24 25 #define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) 26 #define CLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 27 #define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8) 28 #define CLKMGR_PLLOUTDIV_C1CNT_OFFSET 8 29 #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24) 30 #define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24 31 #define CLKMGR_CLKSRC_MASK GENMASK(18, 16) 32 #define CLKMGR_CLKSRC_OFFSET 16 33 #define CLKMGR_NOCDIV_DIVIDER_MASK GENMASK(1, 0) 34 #define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 35 36 #define CLKMGR_INTOSC_HZ 400000000 37 #define CLKMGR_VCO_PSRC_EOSC1 0 38 #define CLKMGR_VCO_PSRC_INTOSC 1 39 #define CLKMGR_VCO_PSRC_F2S 2 40 #define CLKMGR_CLKSRC_MAIN 0 41 #define CLKMGR_CLKSRC_PER 1 42 43 #define CLKMGR_N5X_BASE 0xffd10000 44 #define CLKMGR_MAINPLL_NOCCLK 0x40 45 #define CLKMGR_MAINPLL_NOCDIV 0x44 46 #define CLKMGR_MAINPLL_PLLGLOB 0x48 47 #define CLKMGR_MAINPLL_PLLOUTDIV 0x54 48 #define CLKMGR_MAINPLL_PLLDIV 0x50 49 #define CLKMGR_PERPLL_PLLGLOB 0x9c 50 #define CLKMGR_PERPLL_PLLDIV 0xa4 51 #define CLKMGR_PERPLL_PLLOUTDIV 0xa8 52 53 /* FUNCTION DEFINITION */ 54 uint64_t clk_get_pll_output_hz(void); 55 uint64_t get_l4_clk(void); 56 uint32_t get_clk_freq(uint32_t psrc_reg); 57 uint32_t get_mpu_clk(void); 58 uint32_t get_cpu_clk(void); 59 60 #endif 61
