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Searched defs:CLKDIV3 (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h21384 …__IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h22357 …__IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h20915 …__IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK26F18/
DMK26F18.h23357 …__IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK65F18/
DMK65F18.h25174 …__IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK66F18/
DMK66F18.h25174 …__IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h20917 …__IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1… member