1 /* 2 * Copyright (c) 2022-2024, Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_ 8 #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_ 9 10 #include <stdint.h> 11 #include <assert.h> 12 13 #include <zephyr/sys/sys_io.h> 14 15 /* Clock control MMIO register base address */ 16 #define CLKCTRL_BASE_ADDR DT_REG_ADDR(DT_NODELABEL(clock)) 17 18 /* Clock manager/control register offsets */ 19 #define CLKCTRL_OFFSET 0x00 20 #define CLKCTRL_CTRL 0x00 21 #define CLKCTRL_STAT 0x04 22 #define CLKCTRL_TESTIOCTRL 0x08 23 #define CLKCTRL_INTRGEN 0x0C 24 #define CLKCTRL_INTRMSK 0x10 25 #define CLKCTRL_INTRCLR 0x14 26 #define CLKCTRL_INTRSTS 0x18 27 #define CLKCTRL_INTRSTK 0x1C 28 #define CLKCTRL_INTRRAW 0x20 29 30 #define CLKCTRL(x) (CLKCTRL_BASE_ADDR + CLKCTRL_##_reg) 31 32 /* Clock manager/control main PLL group register offsets */ 33 #define CLKCTRL_MAINPLL_OFFSET 0x24 34 #define CLKCTRL_MAINPLL_EN 0x00 35 #define CLKCTRL_MAINPLL_ENS 0x04 36 #define CLKCTRL_MAINPLL_ENR 0x08 37 #define CLKCTRL_MAINPLL_BYPASS 0x0C 38 #define CLKCTRL_MAINPLL_BYPASSS 0x10 39 #define CLKCTRL_MAINPLL_BYPASSR 0x14 40 #define CLKCTRL_MAINPLL_NOCCLK 0x1C 41 #define CLKCTRL_MAINPLL_NOCDIV 0x20 42 #define CLKCTRL_MAINPLL_PLLGLOB 0x24 43 #define CLKCTRL_MAINPLL_FDBCK 0x28 44 #define CLKCTRL_MAINPLL_MEM 0x2C 45 #define CLKCTRL_MAINPLL_MEMSTAT 0x30 46 #define CLKCTRL_MAINPLL_VCOCALIB 0x34 47 #define CLKCTRL_MAINPLL_PLLC0 0x38 48 #define CLKCTRL_MAINPLL_PLLC1 0x3C 49 #define CLKCTRL_MAINPLL_PLLC2 0x40 50 #define CLKCTRL_MAINPLL_PLLC3 0x44 51 #define CLKCTRL_MAINPLL_PLLM 0x48 52 #define CLKCTRL_MAINPLL_FHOP 0x4C 53 #define CLKCTRL_MAINPLL_SSC 0x50 54 #define CLKCTRL_MAINPLL_LOSTLOCK 0x54 55 56 #define CLKCTRL_MAINPLL_BASE_ADDR (CLKCTRL_BASE_ADDR + CLKCTRL_MAINPLL_OFFSET) 57 #define CLKCTRL_MAINPLL(_reg) (CLKCTRL_MAINPLL_BASE_ADDR + CLKCTRL_MAINPLL_##_reg) 58 59 /* Clock manager/control peripheral PLL group register offsets */ 60 #define CLKCTRL_PERPLL_OFFSET 0x7C 61 #define CLKCTRL_PERPLL_EN 0x00 62 #define CLKCTRL_PERPLL_ENS 0x04 63 #define CLKCTRL_PERPLL_ENR 0x08 64 #define CLKCTRL_PERPLL_BYPASS 0x0C 65 #define CLKCTRL_PERPLL_BYPASSS 0x10 66 #define CLKCTRL_PERPLL_BYPASSR 0x14 67 #define CLKCTRL_PERPLL_EMACCTL 0x18 68 #define CLKCTRL_PERPLL_GPIODIV 0x1C 69 #define CLKCTRL_PERPLL_PLLGLOB 0x20 70 #define CLKCTRL_PERPLL_FDBCK 0x24 71 #define CLKCTRL_PERPLL_MEM 0x28 72 #define CLKCTRL_PERPLL_MEMSTAT 0x2C 73 #define CLKCTRL_PERPLL_VCOCALIB 0x30 74 #define CLKCTRL_PERPLL_PLLC0 0x34 75 #define CLKCTRL_PERPLL_PLLC1 0x38 76 #define CLKCTRL_PERPLL_PLLC2 0x3C 77 #define CLKCTRL_PERPLL_PLLC3 0x40 78 #define CLKCTRL_PERPLL_PLLM 0x44 79 #define CLKCTRL_PERPLL_FHOP 0x48 80 #define CLKCTRL_PERPLL_SSC 0x4C 81 #define CLKCTRL_PERPLL_LOSTLOCK 0x50 82 83 #define CLKCTRL_PERPLL_BASE_ADDR (CLKCTRL_BASE_ADDR + CLKCTRL_PERPLL_OFFSET) 84 #define CLKCTRL_PERPLL(_reg) (CLKCTRL_PERPLL_BASE_ADDR + CLKCTRL_PERPLL_##_reg) 85 86 /* Clock manager/control controller group register offsets */ 87 #define CLKCTRL_CTLGRP_OFFSET 0xD0 88 #define CLKCTRL_CTLGRP_JTAG 0x00 89 #define CLKCTRL_CTLGRP_EMACACTR 0x04 90 #define CLKCTRL_CTLGRP_EMACBCTR 0x08 91 #define CLKCTRL_CTLGRP_EMACPTPCTR 0x0C 92 #define CLKCTRL_CTLGRP_GPIODBCTR 0x10 93 #define CLKCTRL_CTLGRP_S2FUSER0CTR 0x18 94 #define CLKCTRL_CTLGRP_S2FUSER1CTR 0x1C 95 #define CLKCTRL_CTLGRP_PSIREFCTR 0x20 96 #define CLKCTRL_CTLGRP_EXTCNTRST 0x24 97 #define CLKCTRL_CTLGRP_USB31CTR 0x28 98 #define CLKCTRL_CTLGRP_DSUCTR 0x2C 99 #define CLKCTRL_CTLGRP_CORE01CTR 0x30 100 #define CLKCTRL_CTLGRP_CORE23CTR 0x34 101 #define CLKCTRL_CTLGRP_CORE2CTR 0x38 102 #define CLKCTRL_CTLGRP_CORE3CTR 0x3C 103 #define CLKCTRL_CTLGRP_SRL_CON_PLLCTR 0x40 104 105 #define CLKCTRL_CTLGRP_BASE_ADDR (CLKCTRL_BASE_ADDR + CLKCTRL_CTLGRP_OFFSET) 106 #define CLKCTRL_CTLGRP(_reg) (CLKCTRL_CTLGRP_BASE_ADDR + CLKCTRL_CTLGRP_##_reg) 107 108 109 /* Clock manager/control macros */ 110 #define CLKCTRL_CTRL_BOOTMODE_SET_MSK 0x00000001U 111 #define CLKCTRL_STAT_BUSY_E_BUSY 0x1 112 #define CLKCTRL_STAT_BUSY(x) (((x) & 0x00000001U) >> 0) 113 #define CLKCTRL_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100U) >> 8) 114 #define CLKCTRL_STAT_PERPLLLOCKED(x) (((x) & 0x00010000U) >> 16) 115 #define CLKCTRL_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004U 116 #define CLKCTRL_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008U 117 #define CLKCTRL_MAINPLL_L4SPDIV(x) (((x) >> 16) & 0x3) 118 #define CLKCTRL_INTOSC_HZ 460000000U 119 120 #define CLKCTRL_CLKSRC_MASK GENMASK(18, 16) 121 #define CLKCTRL_CLKSRC_OFFSET 16 122 #define CLKCTRL_CLKSRC_MAIN 0 123 #define CLKCTRL_CLKSRC_PER 1 124 #define CLKCTRL_CLKSRC_OSC1 2 125 #define CLKCTRL_CLKSRC_INTOSC 3 126 #define CLKCTRL_CLKSRC_FPGA 4 127 #define CLKCTRL_PLLCX_DIV_MSK GENMASK(10, 0) 128 #define GET_CLKCTRL_CLKSRC(x) (((x) & CLKCTRL_CLKSRC_MASK) >> \ 129 CLKCTRL_CLKSRC_OFFSET) 130 131 /* Shared Macros */ 132 #define CLKCTRL_PSRC(x) (((x) & 0x00030000U) >> 16) 133 #define CLKCTRL_PSRC_MAIN 0 134 #define CLKCTRL_PSRC_PER 1 135 136 #define CLKCTRL_PLLGLOB_PSRC_EOSC1 0x0 137 #define CLKCTRL_PLLGLOB_PSRC_INTOSC 0x1 138 #define CLKCTRL_PLLGLOB_PSRC_F2S 0x2 139 140 #define CLKCTRL_PLLM_MDIV(x) ((x) & 0x000003FFU) 141 #define CLKCTRL_PLLGLOB_PD_SET_MSK 0x00000001U 142 #define CLKCTRL_PLLGLOB_RST_SET_MSK 0x00000002U 143 144 #define CLKCTRL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003F00) >> 8) 145 #define CLKCTRL_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000F00) >> 8) 146 #define CLKCTRL_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) 147 148 #define CLKCTRL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003FF) 149 #define CLKCTRL_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00FF0000) 150 151 #define CLKCTRL_CLR_LOSTLOCK_BYPASS 0x20000000U 152 #define CLKCTRL_PLLC_DIV(x) ((x) & 0x7FF) 153 #define CLKCTRL_CTRL_SDMMC_CNT(x) (((x) & 0x7FF) + 1) 154 155 #define CLKCTRL_CPU_ID_CORE0 0 156 #define CLKCTRL_CPU_ID_CORE1 1 157 #define CLKCTRL_CPU_ID_CORE2 2 158 #define CLKCTRL_CPU_ID_CORE3 3 159 160 161 #define CLKCTRL_MAINPLL_NOCDIV_L4MP_MASK GENMASK(5, 4) 162 #define CLKCTRL_MAINPLL_NOCDIV_L4MP_OFFSET 4 163 #define GET_CLKCTRL_MAINPLL_NOCDIV_L4MP(x) (((x) & CLKCTRL_MAINPLL_NOCDIV_L4MP_MASK) >> \ 164 CLKCTRL_MAINPLL_NOCDIV_L4MP_OFFSET) 165 166 #define CLKCTRL_MAINPLL_NOCDIV_L4SP_MASK GENMASK(7, 6) 167 #define CLKCTRL_MAINPLL_NOCDIV_L4SP_OFFSET 6 168 #define GET_CLKCTRL_MAINPLL_NOCDIV_L4SP(x) (((x) & CLKCTRL_MAINPLL_NOCDIV_L4SP_MASK) >> \ 169 CLKCTRL_MAINPLL_NOCDIV_L4SP_OFFSET) 170 171 172 #define CLKCTRL_MAINPLL_NOCDIV_SPHY_MASK GENMASK(17, 16) 173 #define CLKCTRL_MAINPLL_NOCDIV_SPHY_OFFSET 16 174 #define GET_CLKCTRL_MAINPLL_NOCDIV_SPHY(x) (((x) & CLKCTRL_MAINPLL_NOCDIV_SPHY_MASK) >> \ 175 CLKCTRL_MAINPLL_NOCDIV_SPHY_OFFSET) 176 177 #define CLKCTRL_MAINPLL_NOCDIV_L4SYSFREE_MASK GENMASK(3, 2) 178 #define CLKCTRL_MAINPLL_NOCDIV_L4SYSFREE_OFFSET 2 179 #define GET_CLKCTRL_MAINPLL_NOCDIV_L4SYSFREE(x) (((x) & CLKCTRL_MAINPLL_NOCDIV_L4SYSFREE_MASK) >> \ 180 CLKCTRL_MAINPLL_NOCDIV_L4SYSFREE_OFFSET) 181 182 /** 183 * @brief Get MPU(Micro Processor Unit) clock value 184 * 185 * @param void 186 * 187 * @return returns MPU clock value 188 */ 189 uint32_t get_mpu_clk(void); 190 191 /** 192 * @brief Get Watchdog peripheral clock value 193 * 194 * @param void 195 * 196 * @return returns Watchdog clock value 197 */ 198 uint32_t get_wdt_clk(void); 199 200 /** 201 * @brief Get UART peripheral clock value 202 * 203 * @param void 204 * 205 * @return returns UART clock value 206 */ 207 uint32_t get_uart_clk(void); 208 209 /** 210 * @brief Get MMC peripheral clock value 211 * 212 * @param void 213 * 214 * @return returns MMC clock value 215 */ 216 uint32_t get_sdmmc_clk(void); 217 218 /** 219 * @brief Get Timer peripheral clock value 220 * 221 * @param void 222 * 223 * @return returns Timer clock value 224 */ 225 uint32_t get_timer_clk(void); 226 227 /** 228 * @brief Get QSPI peripheral clock value 229 * 230 * @param void 231 * 232 * @return returns QSPI clock value 233 */ 234 uint32_t get_qspi_clk(void); 235 236 /** 237 * @brief Get I2C peripheral clock value 238 * 239 * @param void 240 * 241 * @return returns I2C clock value 242 */ 243 uint32_t get_i2c_clk(void); 244 245 /** 246 * @brief Get I3C peripheral clock value 247 * 248 * @param void 249 * 250 * @return returns I3C clock value 251 */ 252 uint32_t get_i3c_clk(void); 253 254 #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_ */ 255
