1 /****************************************************************************** 2 * Filename: hw_clkctl_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_CLKCTL_H__ 34 #define __HW_CLKCTL_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // CLKCTL component 40 // 41 //***************************************************************************** 42 // Description Register. 43 #define CLKCTL_O_DESC 0x00000000U 44 45 // Extended Description Register 0. 46 #define CLKCTL_O_DESCEX0 0x00000004U 47 48 // Extended Description Register 1. 49 #define CLKCTL_O_DESCEX1 0x00000008U 50 51 // Clock Configuration Register 0. 52 #define CLKCTL_O_CLKCFG0 0x0000000CU 53 54 // Clock Configuration Register 1. 55 #define CLKCTL_O_CLKCFG1 0x00000010U 56 57 // Clock Enable Set Register 0. 58 #define CLKCTL_O_CLKENSET0 0x00000014U 59 60 // Clock Enable Set Register 1. 61 #define CLKCTL_O_CLKENSET1 0x00000018U 62 63 // Clock Enable Clear Register 0. 64 #define CLKCTL_O_CLKENCLR0 0x00000020U 65 66 // Clock Enable Clear Register 1. 67 #define CLKCTL_O_CLKENCLR1 0x00000024U 68 69 // Internal. Only to be used through TI provided API. 70 #define CLKCTL_O_STBYPTR 0x0000003CU 71 72 // IDLE Configuration Register. 73 #define CLKCTL_O_IDLECFG 0x00000048U 74 75 //***************************************************************************** 76 // 77 // Register: CLKCTL_O_DESC 78 // 79 //***************************************************************************** 80 // Field: [31:16] MODID 81 // 82 // Module identifier used to uniquely identify this IP. 83 #define CLKCTL_DESC_MODID_W 16U 84 #define CLKCTL_DESC_MODID_M 0xFFFF0000U 85 #define CLKCTL_DESC_MODID_S 16U 86 87 // Field: [15:12] STDIPOFF 88 // 89 // Standard IP MMR block offset. Standard IP MMRs are the set of from 90 // aggregated IRQ registers till DTB. 91 // 92 // 0: Standard IP MMRs do not exist 93 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 94 // address) 95 #define CLKCTL_DESC_STDIPOFF_W 4U 96 #define CLKCTL_DESC_STDIPOFF_M 0x0000F000U 97 #define CLKCTL_DESC_STDIPOFF_S 12U 98 99 // Field: [11:8] INSTIDX 100 // 101 // IP Instance ID number. If multiple instances of IP exist in the device, this 102 // field can identify the instance number (0-15). 103 #define CLKCTL_DESC_INSTIDX_W 4U 104 #define CLKCTL_DESC_INSTIDX_M 0x00000F00U 105 #define CLKCTL_DESC_INSTIDX_S 8U 106 107 // Field: [7:4] MAJREV 108 // 109 // Major revision of IP 0-15 110 #define CLKCTL_DESC_MAJREV_W 4U 111 #define CLKCTL_DESC_MAJREV_M 0x000000F0U 112 #define CLKCTL_DESC_MAJREV_S 4U 113 114 // Field: [3:0] MINREV 115 // 116 // Minor revision of IP 0-15. 117 #define CLKCTL_DESC_MINREV_W 4U 118 #define CLKCTL_DESC_MINREV_M 0x0000000FU 119 #define CLKCTL_DESC_MINREV_S 0U 120 121 //***************************************************************************** 122 // 123 // Register: CLKCTL_O_DESCEX0 124 // 125 //***************************************************************************** 126 // Field: [30] LGPT3 127 // 128 // IP status on device 129 // ENUMs: 130 // IP_AVAIL IP is available 131 // IP_UNAVAIL IP is unavailable 132 #define CLKCTL_DESCEX0_LGPT3 0x40000000U 133 #define CLKCTL_DESCEX0_LGPT3_M 0x40000000U 134 #define CLKCTL_DESCEX0_LGPT3_S 30U 135 #define CLKCTL_DESCEX0_LGPT3_IP_AVAIL 0x40000000U 136 #define CLKCTL_DESCEX0_LGPT3_IP_UNAVAIL 0x00000000U 137 138 // Field: [29] LGPT2 139 // 140 // IP status on device 141 // ENUMs: 142 // IP_AVAIL IP is available 143 // IP_UNAVAIL IP is unavailable 144 #define CLKCTL_DESCEX0_LGPT2 0x20000000U 145 #define CLKCTL_DESCEX0_LGPT2_M 0x20000000U 146 #define CLKCTL_DESCEX0_LGPT2_S 29U 147 #define CLKCTL_DESCEX0_LGPT2_IP_AVAIL 0x20000000U 148 #define CLKCTL_DESCEX0_LGPT2_IP_UNAVAIL 0x00000000U 149 150 // Field: [28] LGPT1 151 // 152 // IP status on device 153 // ENUMs: 154 // IP_AVAIL IP is available 155 // IP_UNAVAIL IP is unavailable 156 #define CLKCTL_DESCEX0_LGPT1 0x10000000U 157 #define CLKCTL_DESCEX0_LGPT1_M 0x10000000U 158 #define CLKCTL_DESCEX0_LGPT1_S 28U 159 #define CLKCTL_DESCEX0_LGPT1_IP_AVAIL 0x10000000U 160 #define CLKCTL_DESCEX0_LGPT1_IP_UNAVAIL 0x00000000U 161 162 // Field: [27] LGPT0 163 // 164 // IP status on device 165 // ENUMs: 166 // IP_AVAIL IP is available 167 // IP_UNAVAIL IP is unavailable 168 #define CLKCTL_DESCEX0_LGPT0 0x08000000U 169 #define CLKCTL_DESCEX0_LGPT0_M 0x08000000U 170 #define CLKCTL_DESCEX0_LGPT0_S 27U 171 #define CLKCTL_DESCEX0_LGPT0_IP_AVAIL 0x08000000U 172 #define CLKCTL_DESCEX0_LGPT0_IP_UNAVAIL 0x00000000U 173 174 // Field: [17] DMA 175 // 176 // IP status on device 177 // ENUMs: 178 // IP_AVAIL IP is available 179 // IP_UNAVAIL IP is unavailable 180 #define CLKCTL_DESCEX0_DMA 0x00020000U 181 #define CLKCTL_DESCEX0_DMA_M 0x00020000U 182 #define CLKCTL_DESCEX0_DMA_S 17U 183 #define CLKCTL_DESCEX0_DMA_IP_AVAIL 0x00020000U 184 #define CLKCTL_DESCEX0_DMA_IP_UNAVAIL 0x00000000U 185 186 // Field: [16] LAES 187 // 188 // IP status on device 189 // ENUMs: 190 // IP_AVAIL IP is available 191 // IP_UNAVAIL IP is unavailable 192 #define CLKCTL_DESCEX0_LAES 0x00010000U 193 #define CLKCTL_DESCEX0_LAES_M 0x00010000U 194 #define CLKCTL_DESCEX0_LAES_S 16U 195 #define CLKCTL_DESCEX0_LAES_IP_AVAIL 0x00010000U 196 #define CLKCTL_DESCEX0_LAES_IP_UNAVAIL 0x00000000U 197 198 // Field: [14] ADC0 199 // 200 // IP status on device 201 // ENUMs: 202 // IP_AVAIL IP is available 203 // IP_UNAVAIL IP is unavailable 204 #define CLKCTL_DESCEX0_ADC0 0x00004000U 205 #define CLKCTL_DESCEX0_ADC0_M 0x00004000U 206 #define CLKCTL_DESCEX0_ADC0_S 14U 207 #define CLKCTL_DESCEX0_ADC0_IP_AVAIL 0x00004000U 208 #define CLKCTL_DESCEX0_ADC0_IP_UNAVAIL 0x00000000U 209 210 // Field: [10] SPI0 211 // 212 // IP status on device 213 // ENUMs: 214 // IP_AVAIL IP is available 215 // IP_UNAVAIL IP is unavailable 216 #define CLKCTL_DESCEX0_SPI0 0x00000400U 217 #define CLKCTL_DESCEX0_SPI0_M 0x00000400U 218 #define CLKCTL_DESCEX0_SPI0_S 10U 219 #define CLKCTL_DESCEX0_SPI0_IP_AVAIL 0x00000400U 220 #define CLKCTL_DESCEX0_SPI0_IP_UNAVAIL 0x00000000U 221 222 // Field: [6] I2C0 223 // 224 // IP status on device 225 // ENUMs: 226 // IP_AVAIL IP is available 227 // IP_UNAVAIL IP is unavailable 228 #define CLKCTL_DESCEX0_I2C0 0x00000040U 229 #define CLKCTL_DESCEX0_I2C0_M 0x00000040U 230 #define CLKCTL_DESCEX0_I2C0_S 6U 231 #define CLKCTL_DESCEX0_I2C0_IP_AVAIL 0x00000040U 232 #define CLKCTL_DESCEX0_I2C0_IP_UNAVAIL 0x00000000U 233 234 // Field: [2] UART0 235 // 236 // IP status on device 237 // ENUMs: 238 // IP_AVAIL IP is available 239 // IP_UNAVAIL IP is unavailable 240 #define CLKCTL_DESCEX0_UART0 0x00000004U 241 #define CLKCTL_DESCEX0_UART0_M 0x00000004U 242 #define CLKCTL_DESCEX0_UART0_S 2U 243 #define CLKCTL_DESCEX0_UART0_IP_AVAIL 0x00000004U 244 #define CLKCTL_DESCEX0_UART0_IP_UNAVAIL 0x00000000U 245 246 // Field: [1] LRFD 247 // 248 // IP status on device 249 // ENUMs: 250 // IP_AVAIL IP is available 251 // IP_UNAVAIL IP is unavailable 252 #define CLKCTL_DESCEX0_LRFD 0x00000002U 253 #define CLKCTL_DESCEX0_LRFD_M 0x00000002U 254 #define CLKCTL_DESCEX0_LRFD_S 1U 255 #define CLKCTL_DESCEX0_LRFD_IP_AVAIL 0x00000002U 256 #define CLKCTL_DESCEX0_LRFD_IP_UNAVAIL 0x00000000U 257 258 // Field: [0] GPIO 259 // 260 // IP status on device 261 // ENUMs: 262 // IP_AVAIL IP is available 263 // IP_UNAVAIL IP is unavailable 264 #define CLKCTL_DESCEX0_GPIO 0x00000001U 265 #define CLKCTL_DESCEX0_GPIO_M 0x00000001U 266 #define CLKCTL_DESCEX0_GPIO_S 0U 267 #define CLKCTL_DESCEX0_GPIO_IP_AVAIL 0x00000001U 268 #define CLKCTL_DESCEX0_GPIO_IP_UNAVAIL 0x00000000U 269 270 //***************************************************************************** 271 // 272 // Register: CLKCTL_O_DESCEX1 273 // 274 //***************************************************************************** 275 // Field: [31:30] FLASHSZ 276 // 277 // System flash availability 278 // ENUMs: 279 // SZ3 Flash size set to level 3 (Max size) 280 // SZ2 Flash size set to level 2 281 // SZ1 Flash size set to level 1 282 // SZ0 Flash size set to level 0 (Min size) 283 #define CLKCTL_DESCEX1_FLASHSZ_W 2U 284 #define CLKCTL_DESCEX1_FLASHSZ_M 0xC0000000U 285 #define CLKCTL_DESCEX1_FLASHSZ_S 30U 286 #define CLKCTL_DESCEX1_FLASHSZ_SZ3 0xC0000000U 287 #define CLKCTL_DESCEX1_FLASHSZ_SZ2 0x80000000U 288 #define CLKCTL_DESCEX1_FLASHSZ_SZ1 0x40000000U 289 #define CLKCTL_DESCEX1_FLASHSZ_SZ0 0x00000000U 290 291 // Field: [29:28] SRAMSZ 292 // 293 // System SRAM availability 294 // ENUMs: 295 // SZ3 SRAM size set to level 3 (Max size) 296 // SZ2 SRAM size set to level 2 297 // SZ1 SRAM size set to level 1 298 // SZ0 SRAM size set to level 0 (Min size) 299 #define CLKCTL_DESCEX1_SRAMSZ_W 2U 300 #define CLKCTL_DESCEX1_SRAMSZ_M 0x30000000U 301 #define CLKCTL_DESCEX1_SRAMSZ_S 28U 302 #define CLKCTL_DESCEX1_SRAMSZ_SZ3 0x30000000U 303 #define CLKCTL_DESCEX1_SRAMSZ_SZ2 0x20000000U 304 #define CLKCTL_DESCEX1_SRAMSZ_SZ1 0x10000000U 305 #define CLKCTL_DESCEX1_SRAMSZ_SZ0 0x00000000U 306 307 // Field: [15:8] ROPT 308 // 309 // System radio feature availability 310 // ENUMs: 311 // MAX All features available 312 #define CLKCTL_DESCEX1_ROPT_W 8U 313 #define CLKCTL_DESCEX1_ROPT_M 0x0000FF00U 314 #define CLKCTL_DESCEX1_ROPT_S 8U 315 #define CLKCTL_DESCEX1_ROPT_MAX 0x0000FF00U 316 317 //***************************************************************************** 318 // 319 // Register: CLKCTL_O_CLKCFG0 320 // 321 //***************************************************************************** 322 // Field: [30] LGPT3 323 // 324 // IP clock configuration 325 // ENUMs: 326 // CLK_EN Clock is enabled 327 // CLK_DIS Clock is disabled 328 #define CLKCTL_CLKCFG0_LGPT3 0x40000000U 329 #define CLKCTL_CLKCFG0_LGPT3_M 0x40000000U 330 #define CLKCTL_CLKCFG0_LGPT3_S 30U 331 #define CLKCTL_CLKCFG0_LGPT3_CLK_EN 0x40000000U 332 #define CLKCTL_CLKCFG0_LGPT3_CLK_DIS 0x00000000U 333 334 // Field: [29] LGPT2 335 // 336 // IP clock configuration 337 // ENUMs: 338 // CLK_EN Clock is enabled 339 // CLK_DIS Clock is disabled 340 #define CLKCTL_CLKCFG0_LGPT2 0x20000000U 341 #define CLKCTL_CLKCFG0_LGPT2_M 0x20000000U 342 #define CLKCTL_CLKCFG0_LGPT2_S 29U 343 #define CLKCTL_CLKCFG0_LGPT2_CLK_EN 0x20000000U 344 #define CLKCTL_CLKCFG0_LGPT2_CLK_DIS 0x00000000U 345 346 // Field: [28] LGPT1 347 // 348 // IP clock configuration 349 // ENUMs: 350 // CLK_EN Clock is enabled 351 // CLK_DIS Clock is disabled 352 #define CLKCTL_CLKCFG0_LGPT1 0x10000000U 353 #define CLKCTL_CLKCFG0_LGPT1_M 0x10000000U 354 #define CLKCTL_CLKCFG0_LGPT1_S 28U 355 #define CLKCTL_CLKCFG0_LGPT1_CLK_EN 0x10000000U 356 #define CLKCTL_CLKCFG0_LGPT1_CLK_DIS 0x00000000U 357 358 // Field: [27] LGPT0 359 // 360 // IP clock configuration 361 // ENUMs: 362 // CLK_EN Clock is enabled 363 // CLK_DIS Clock is disabled 364 #define CLKCTL_CLKCFG0_LGPT0 0x08000000U 365 #define CLKCTL_CLKCFG0_LGPT0_M 0x08000000U 366 #define CLKCTL_CLKCFG0_LGPT0_S 27U 367 #define CLKCTL_CLKCFG0_LGPT0_CLK_EN 0x08000000U 368 #define CLKCTL_CLKCFG0_LGPT0_CLK_DIS 0x00000000U 369 370 // Field: [17] DMA 371 // 372 // IP clock configuration 373 // ENUMs: 374 // CLK_EN Clock is enabled 375 // CLK_DIS Clock is disabled 376 #define CLKCTL_CLKCFG0_DMA 0x00020000U 377 #define CLKCTL_CLKCFG0_DMA_M 0x00020000U 378 #define CLKCTL_CLKCFG0_DMA_S 17U 379 #define CLKCTL_CLKCFG0_DMA_CLK_EN 0x00020000U 380 #define CLKCTL_CLKCFG0_DMA_CLK_DIS 0x00000000U 381 382 // Field: [16] LAES 383 // 384 // IP clock configuration 385 // ENUMs: 386 // CLK_EN Clock is enabled 387 // CLK_DIS Clock is disabled 388 #define CLKCTL_CLKCFG0_LAES 0x00010000U 389 #define CLKCTL_CLKCFG0_LAES_M 0x00010000U 390 #define CLKCTL_CLKCFG0_LAES_S 16U 391 #define CLKCTL_CLKCFG0_LAES_CLK_EN 0x00010000U 392 #define CLKCTL_CLKCFG0_LAES_CLK_DIS 0x00000000U 393 394 // Field: [14] ADC0 395 // 396 // IP clock configuration 397 // ENUMs: 398 // CLK_EN Clock is enabled 399 // CLK_DIS Clock is disabled 400 #define CLKCTL_CLKCFG0_ADC0 0x00004000U 401 #define CLKCTL_CLKCFG0_ADC0_M 0x00004000U 402 #define CLKCTL_CLKCFG0_ADC0_S 14U 403 #define CLKCTL_CLKCFG0_ADC0_CLK_EN 0x00004000U 404 #define CLKCTL_CLKCFG0_ADC0_CLK_DIS 0x00000000U 405 406 // Field: [10] SPI0 407 // 408 // IP clock configuration 409 // ENUMs: 410 // CLK_EN Clock is enabled 411 // CLK_DIS Clock is disabled 412 #define CLKCTL_CLKCFG0_SPI0 0x00000400U 413 #define CLKCTL_CLKCFG0_SPI0_M 0x00000400U 414 #define CLKCTL_CLKCFG0_SPI0_S 10U 415 #define CLKCTL_CLKCFG0_SPI0_CLK_EN 0x00000400U 416 #define CLKCTL_CLKCFG0_SPI0_CLK_DIS 0x00000000U 417 418 // Field: [6] I2C0 419 // 420 // IP clock configuration 421 // ENUMs: 422 // CLK_EN Clock is enabled 423 // CLK_DIS Clock is disabled 424 #define CLKCTL_CLKCFG0_I2C0 0x00000040U 425 #define CLKCTL_CLKCFG0_I2C0_M 0x00000040U 426 #define CLKCTL_CLKCFG0_I2C0_S 6U 427 #define CLKCTL_CLKCFG0_I2C0_CLK_EN 0x00000040U 428 #define CLKCTL_CLKCFG0_I2C0_CLK_DIS 0x00000000U 429 430 // Field: [2] UART0 431 // 432 // IP clock configuration 433 // ENUMs: 434 // CLK_EN Clock is enabled 435 // CLK_DIS Clock is disabled 436 #define CLKCTL_CLKCFG0_UART0 0x00000004U 437 #define CLKCTL_CLKCFG0_UART0_M 0x00000004U 438 #define CLKCTL_CLKCFG0_UART0_S 2U 439 #define CLKCTL_CLKCFG0_UART0_CLK_EN 0x00000004U 440 #define CLKCTL_CLKCFG0_UART0_CLK_DIS 0x00000000U 441 442 // Field: [1] LRFD 443 // 444 // IP clock configuration 445 // ENUMs: 446 // CLK_EN Clock is enabled 447 // CLK_DIS Clock is disabled 448 #define CLKCTL_CLKCFG0_LRFD 0x00000002U 449 #define CLKCTL_CLKCFG0_LRFD_M 0x00000002U 450 #define CLKCTL_CLKCFG0_LRFD_S 1U 451 #define CLKCTL_CLKCFG0_LRFD_CLK_EN 0x00000002U 452 #define CLKCTL_CLKCFG0_LRFD_CLK_DIS 0x00000000U 453 454 // Field: [0] GPIO 455 // 456 // IP clock configuration 457 // ENUMs: 458 // CLK_EN Clock is enabled 459 // CLK_DIS Clock is disabled 460 #define CLKCTL_CLKCFG0_GPIO 0x00000001U 461 #define CLKCTL_CLKCFG0_GPIO_M 0x00000001U 462 #define CLKCTL_CLKCFG0_GPIO_S 0U 463 #define CLKCTL_CLKCFG0_GPIO_CLK_EN 0x00000001U 464 #define CLKCTL_CLKCFG0_GPIO_CLK_DIS 0x00000000U 465 466 //***************************************************************************** 467 // 468 // Register: CLKCTL_O_CLKCFG1 469 // 470 //***************************************************************************** 471 //***************************************************************************** 472 // 473 // Register: CLKCTL_O_CLKENSET0 474 // 475 //***************************************************************************** 476 // Field: [30] LGPT3 477 // 478 // Configure IP clock enable 479 // ENUMs: 480 // CLK_SET Set IP clock enable 481 // CLK_UNCHGD IP clock enable is unchanged 482 #define CLKCTL_CLKENSET0_LGPT3 0x40000000U 483 #define CLKCTL_CLKENSET0_LGPT3_M 0x40000000U 484 #define CLKCTL_CLKENSET0_LGPT3_S 30U 485 #define CLKCTL_CLKENSET0_LGPT3_CLK_SET 0x40000000U 486 #define CLKCTL_CLKENSET0_LGPT3_CLK_UNCHGD 0x00000000U 487 488 // Field: [29] LGPT2 489 // 490 // Configure IP clock enable 491 // ENUMs: 492 // CLK_SET Set IP clock enable 493 // CLK_UNCHGD IP clock enable is unchanged 494 #define CLKCTL_CLKENSET0_LGPT2 0x20000000U 495 #define CLKCTL_CLKENSET0_LGPT2_M 0x20000000U 496 #define CLKCTL_CLKENSET0_LGPT2_S 29U 497 #define CLKCTL_CLKENSET0_LGPT2_CLK_SET 0x20000000U 498 #define CLKCTL_CLKENSET0_LGPT2_CLK_UNCHGD 0x00000000U 499 500 // Field: [28] LGPT1 501 // 502 // Configure IP clock enable 503 // ENUMs: 504 // CLK_SET Set IP clock enable 505 // CLK_UNCHGD IP clock enable is unchanged 506 #define CLKCTL_CLKENSET0_LGPT1 0x10000000U 507 #define CLKCTL_CLKENSET0_LGPT1_M 0x10000000U 508 #define CLKCTL_CLKENSET0_LGPT1_S 28U 509 #define CLKCTL_CLKENSET0_LGPT1_CLK_SET 0x10000000U 510 #define CLKCTL_CLKENSET0_LGPT1_CLK_UNCHGD 0x00000000U 511 512 // Field: [27] LGPT0 513 // 514 // Configure IP clock enable 515 // ENUMs: 516 // CLK_SET Set IP clock enable 517 // CLK_UNCHGD IP clock enable is unchanged 518 #define CLKCTL_CLKENSET0_LGPT0 0x08000000U 519 #define CLKCTL_CLKENSET0_LGPT0_M 0x08000000U 520 #define CLKCTL_CLKENSET0_LGPT0_S 27U 521 #define CLKCTL_CLKENSET0_LGPT0_CLK_SET 0x08000000U 522 #define CLKCTL_CLKENSET0_LGPT0_CLK_UNCHGD 0x00000000U 523 524 // Field: [17] DMA 525 // 526 // Configure IP clock enable 527 // ENUMs: 528 // CLK_SET Set IP clock enable 529 // CLK_UNCHGD IP clock enable is unchanged 530 #define CLKCTL_CLKENSET0_DMA 0x00020000U 531 #define CLKCTL_CLKENSET0_DMA_M 0x00020000U 532 #define CLKCTL_CLKENSET0_DMA_S 17U 533 #define CLKCTL_CLKENSET0_DMA_CLK_SET 0x00020000U 534 #define CLKCTL_CLKENSET0_DMA_CLK_UNCHGD 0x00000000U 535 536 // Field: [16] LAES 537 // 538 // Configure IP clock enable 539 // ENUMs: 540 // CLK_SET Set IP clock enable 541 // CLK_UNCHGD IP clock enable is unchanged 542 #define CLKCTL_CLKENSET0_LAES 0x00010000U 543 #define CLKCTL_CLKENSET0_LAES_M 0x00010000U 544 #define CLKCTL_CLKENSET0_LAES_S 16U 545 #define CLKCTL_CLKENSET0_LAES_CLK_SET 0x00010000U 546 #define CLKCTL_CLKENSET0_LAES_CLK_UNCHGD 0x00000000U 547 548 // Field: [14] ADC0 549 // 550 // Configure IP clock enable 551 // ENUMs: 552 // CLK_SET Set IP clock enable 553 // CLK_UNCHGD IP clock enable is unchanged 554 #define CLKCTL_CLKENSET0_ADC0 0x00004000U 555 #define CLKCTL_CLKENSET0_ADC0_M 0x00004000U 556 #define CLKCTL_CLKENSET0_ADC0_S 14U 557 #define CLKCTL_CLKENSET0_ADC0_CLK_SET 0x00004000U 558 #define CLKCTL_CLKENSET0_ADC0_CLK_UNCHGD 0x00000000U 559 560 // Field: [10] SPI0 561 // 562 // Configure IP clock enable 563 // ENUMs: 564 // CLK_SET Set IP clock enable 565 // CLK_UNCHGD IP clock enable is unchanged 566 #define CLKCTL_CLKENSET0_SPI0 0x00000400U 567 #define CLKCTL_CLKENSET0_SPI0_M 0x00000400U 568 #define CLKCTL_CLKENSET0_SPI0_S 10U 569 #define CLKCTL_CLKENSET0_SPI0_CLK_SET 0x00000400U 570 #define CLKCTL_CLKENSET0_SPI0_CLK_UNCHGD 0x00000000U 571 572 // Field: [6] I2C0 573 // 574 // Configure IP clock enable 575 // ENUMs: 576 // CLK_SET Set IP clock enable 577 // CLK_UNCHGD IP clock enable is unchanged 578 #define CLKCTL_CLKENSET0_I2C0 0x00000040U 579 #define CLKCTL_CLKENSET0_I2C0_M 0x00000040U 580 #define CLKCTL_CLKENSET0_I2C0_S 6U 581 #define CLKCTL_CLKENSET0_I2C0_CLK_SET 0x00000040U 582 #define CLKCTL_CLKENSET0_I2C0_CLK_UNCHGD 0x00000000U 583 584 // Field: [2] UART0 585 // 586 // Configure IP clock enable 587 // ENUMs: 588 // CLK_SET Set IP clock enable 589 // CLK_UNCHGD IP clock enable is unchanged 590 #define CLKCTL_CLKENSET0_UART0 0x00000004U 591 #define CLKCTL_CLKENSET0_UART0_M 0x00000004U 592 #define CLKCTL_CLKENSET0_UART0_S 2U 593 #define CLKCTL_CLKENSET0_UART0_CLK_SET 0x00000004U 594 #define CLKCTL_CLKENSET0_UART0_CLK_UNCHGD 0x00000000U 595 596 // Field: [1] LRFD 597 // 598 // Configure IP clock enable 599 // ENUMs: 600 // CLK_SET Set IP clock enable 601 // CLK_UNCHGD IP clock enable is unchanged 602 #define CLKCTL_CLKENSET0_LRFD 0x00000002U 603 #define CLKCTL_CLKENSET0_LRFD_M 0x00000002U 604 #define CLKCTL_CLKENSET0_LRFD_S 1U 605 #define CLKCTL_CLKENSET0_LRFD_CLK_SET 0x00000002U 606 #define CLKCTL_CLKENSET0_LRFD_CLK_UNCHGD 0x00000000U 607 608 // Field: [0] GPIO 609 // 610 // Configure IP clock enable 611 // ENUMs: 612 // CLK_SET Set IP clock enable 613 // CLK_UNCHGD IP clock enable is unchanged 614 #define CLKCTL_CLKENSET0_GPIO 0x00000001U 615 #define CLKCTL_CLKENSET0_GPIO_M 0x00000001U 616 #define CLKCTL_CLKENSET0_GPIO_S 0U 617 #define CLKCTL_CLKENSET0_GPIO_CLK_SET 0x00000001U 618 #define CLKCTL_CLKENSET0_GPIO_CLK_UNCHGD 0x00000000U 619 620 //***************************************************************************** 621 // 622 // Register: CLKCTL_O_CLKENSET1 623 // 624 //***************************************************************************** 625 //***************************************************************************** 626 // 627 // Register: CLKCTL_O_CLKENCLR0 628 // 629 //***************************************************************************** 630 // Field: [30] LGPT3 631 // 632 // Configure IP clock enable 633 // ENUMs: 634 // CLK_CLR Clear IP clock enable 635 // CLK_UNCHGD IP clock enable is unchanged 636 #define CLKCTL_CLKENCLR0_LGPT3 0x40000000U 637 #define CLKCTL_CLKENCLR0_LGPT3_M 0x40000000U 638 #define CLKCTL_CLKENCLR0_LGPT3_S 30U 639 #define CLKCTL_CLKENCLR0_LGPT3_CLK_CLR 0x40000000U 640 #define CLKCTL_CLKENCLR0_LGPT3_CLK_UNCHGD 0x00000000U 641 642 // Field: [29] LGPT2 643 // 644 // Configure IP clock enable 645 // ENUMs: 646 // CLK_CLR Clear IP clock enable 647 // CLK_UNCHGD IP clock enable is unchanged 648 #define CLKCTL_CLKENCLR0_LGPT2 0x20000000U 649 #define CLKCTL_CLKENCLR0_LGPT2_M 0x20000000U 650 #define CLKCTL_CLKENCLR0_LGPT2_S 29U 651 #define CLKCTL_CLKENCLR0_LGPT2_CLK_CLR 0x20000000U 652 #define CLKCTL_CLKENCLR0_LGPT2_CLK_UNCHGD 0x00000000U 653 654 // Field: [28] LGPT1 655 // 656 // Configure IP clock enable 657 // ENUMs: 658 // CLK_CLR Clear IP clock enable 659 // CLK_UNCHGD IP clock enable is unchanged 660 #define CLKCTL_CLKENCLR0_LGPT1 0x10000000U 661 #define CLKCTL_CLKENCLR0_LGPT1_M 0x10000000U 662 #define CLKCTL_CLKENCLR0_LGPT1_S 28U 663 #define CLKCTL_CLKENCLR0_LGPT1_CLK_CLR 0x10000000U 664 #define CLKCTL_CLKENCLR0_LGPT1_CLK_UNCHGD 0x00000000U 665 666 // Field: [27] LGPT0 667 // 668 // Configure IP clock enable 669 // ENUMs: 670 // CLK_CLR Clear IP clock enable 671 // CLK_UNCHGD IP clock enable is unchanged 672 #define CLKCTL_CLKENCLR0_LGPT0 0x08000000U 673 #define CLKCTL_CLKENCLR0_LGPT0_M 0x08000000U 674 #define CLKCTL_CLKENCLR0_LGPT0_S 27U 675 #define CLKCTL_CLKENCLR0_LGPT0_CLK_CLR 0x08000000U 676 #define CLKCTL_CLKENCLR0_LGPT0_CLK_UNCHGD 0x00000000U 677 678 // Field: [17] DMA 679 // 680 // Configure IP clock enable 681 // ENUMs: 682 // CLK_CLR Clear IP clock enable 683 // CLK_UNCHGD IP clock enable is unchanged 684 #define CLKCTL_CLKENCLR0_DMA 0x00020000U 685 #define CLKCTL_CLKENCLR0_DMA_M 0x00020000U 686 #define CLKCTL_CLKENCLR0_DMA_S 17U 687 #define CLKCTL_CLKENCLR0_DMA_CLK_CLR 0x00020000U 688 #define CLKCTL_CLKENCLR0_DMA_CLK_UNCHGD 0x00000000U 689 690 // Field: [16] LAES 691 // 692 // Configure IP clock enable 693 // ENUMs: 694 // CLK_CLR Clear IP clock enable 695 // CLK_UNCHGD IP clock enable is unchanged 696 #define CLKCTL_CLKENCLR0_LAES 0x00010000U 697 #define CLKCTL_CLKENCLR0_LAES_M 0x00010000U 698 #define CLKCTL_CLKENCLR0_LAES_S 16U 699 #define CLKCTL_CLKENCLR0_LAES_CLK_CLR 0x00010000U 700 #define CLKCTL_CLKENCLR0_LAES_CLK_UNCHGD 0x00000000U 701 702 // Field: [14] ADC0 703 // 704 // Configure IP clock enable 705 // ENUMs: 706 // CLK_CLR Clear IP clock enable 707 // CLK_UNCHGD IP clock enable is unchanged 708 #define CLKCTL_CLKENCLR0_ADC0 0x00004000U 709 #define CLKCTL_CLKENCLR0_ADC0_M 0x00004000U 710 #define CLKCTL_CLKENCLR0_ADC0_S 14U 711 #define CLKCTL_CLKENCLR0_ADC0_CLK_CLR 0x00004000U 712 #define CLKCTL_CLKENCLR0_ADC0_CLK_UNCHGD 0x00000000U 713 714 // Field: [10] SPI0 715 // 716 // Configure IP clock enable 717 // ENUMs: 718 // CLK_CLR Clear IP clock enable 719 // CLK_UNCHGD IP clock enable is unchanged 720 #define CLKCTL_CLKENCLR0_SPI0 0x00000400U 721 #define CLKCTL_CLKENCLR0_SPI0_M 0x00000400U 722 #define CLKCTL_CLKENCLR0_SPI0_S 10U 723 #define CLKCTL_CLKENCLR0_SPI0_CLK_CLR 0x00000400U 724 #define CLKCTL_CLKENCLR0_SPI0_CLK_UNCHGD 0x00000000U 725 726 // Field: [6] I2C0 727 // 728 // Configure IP clock enable 729 // ENUMs: 730 // CLK_CLR Clear IP clock enable 731 // CLK_UNCHGD IP clock enable is unchanged 732 #define CLKCTL_CLKENCLR0_I2C0 0x00000040U 733 #define CLKCTL_CLKENCLR0_I2C0_M 0x00000040U 734 #define CLKCTL_CLKENCLR0_I2C0_S 6U 735 #define CLKCTL_CLKENCLR0_I2C0_CLK_CLR 0x00000040U 736 #define CLKCTL_CLKENCLR0_I2C0_CLK_UNCHGD 0x00000000U 737 738 // Field: [2] UART0 739 // 740 // Configure IP clock enable 741 // ENUMs: 742 // CLK_CLR Clear IP clock enable 743 // CLK_UNCHGD IP clock enable is unchanged 744 #define CLKCTL_CLKENCLR0_UART0 0x00000004U 745 #define CLKCTL_CLKENCLR0_UART0_M 0x00000004U 746 #define CLKCTL_CLKENCLR0_UART0_S 2U 747 #define CLKCTL_CLKENCLR0_UART0_CLK_CLR 0x00000004U 748 #define CLKCTL_CLKENCLR0_UART0_CLK_UNCHGD 0x00000000U 749 750 // Field: [1] LRFD 751 // 752 // Configure IP clock enable 753 // ENUMs: 754 // CLK_CLR Clear IP clock enable 755 // CLK_UNCHGD IP clock enable is unchanged 756 #define CLKCTL_CLKENCLR0_LRFD 0x00000002U 757 #define CLKCTL_CLKENCLR0_LRFD_M 0x00000002U 758 #define CLKCTL_CLKENCLR0_LRFD_S 1U 759 #define CLKCTL_CLKENCLR0_LRFD_CLK_CLR 0x00000002U 760 #define CLKCTL_CLKENCLR0_LRFD_CLK_UNCHGD 0x00000000U 761 762 // Field: [0] GPIO 763 // 764 // Configure IP clock enable 765 // ENUMs: 766 // CLK_CLR Clear IP clock enable 767 // CLK_UNCHGD IP clock enable is unchanged 768 #define CLKCTL_CLKENCLR0_GPIO 0x00000001U 769 #define CLKCTL_CLKENCLR0_GPIO_M 0x00000001U 770 #define CLKCTL_CLKENCLR0_GPIO_S 0U 771 #define CLKCTL_CLKENCLR0_GPIO_CLK_CLR 0x00000001U 772 #define CLKCTL_CLKENCLR0_GPIO_CLK_UNCHGD 0x00000000U 773 774 //***************************************************************************** 775 // 776 // Register: CLKCTL_O_CLKENCLR1 777 // 778 //***************************************************************************** 779 //***************************************************************************** 780 // 781 // Register: CLKCTL_O_STBYPTR 782 // 783 //***************************************************************************** 784 // Field: [31:0] VAL 785 // 786 // Internal. Only to be used through TI provided API. 787 // ENUMs: 788 // MIN Internal. Only to be used through TI provided API. 789 #define CLKCTL_STBYPTR_VAL_W 32U 790 #define CLKCTL_STBYPTR_VAL_M 0xFFFFFFFFU 791 #define CLKCTL_STBYPTR_VAL_S 0U 792 #define CLKCTL_STBYPTR_VAL_MIN 0x00000000U 793 794 //***************************************************************************** 795 // 796 // Register: CLKCTL_O_IDLECFG 797 // 798 //***************************************************************************** 799 // Field: [0] MODE 800 // 801 // Flash LDO configuration in SLEEP/IDLE mode. 802 // ENUMs: 803 // LDO_OFF Flash LDO is off in SLEEP/IDLE mode. 804 // Decreases power 805 // consumption in SLEEP/IDLE mode, but gives 806 // longer wake up time. 807 // 808 // Note: NVM clock is turned 809 // off independent of DMA status. Therefore SW 810 // must ensure that DMA never access NVM in this 811 // mode. 812 // LDO_ON Flash LDO is on in SLEEP/IDLE mode. 813 // Gives fast wake up time 814 // from SLEEP/IDLE mode, but increased power 815 // consumption. 816 #define CLKCTL_IDLECFG_MODE 0x00000001U 817 #define CLKCTL_IDLECFG_MODE_M 0x00000001U 818 #define CLKCTL_IDLECFG_MODE_S 0U 819 #define CLKCTL_IDLECFG_MODE_LDO_OFF 0x00000001U 820 #define CLKCTL_IDLECFG_MODE_LDO_ON 0x00000000U 821 822 823 #endif // __CLKCTL__ 824
