1 /*
2  * Copyright (c) 2023 Antmicro <www.antmicro.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _SOC__H_
8 #define _SOC__H_
9 
10 /* Do not let CMSIS to handle GIC and Timer */
11 #include <stdint.h>
12 #define __GIC_PRESENT 0
13 #define __TIM_PRESENT 0
14 
15 /* Global system counter */
16 #define CNTCR_EN   BIT(0)
17 #define CNTCR_HDBG BIT(1)
18 
19 /* Safety area protect register */
20 #define PRCRS_CLK       BIT(0)
21 #define PRCRS_LPC_RESET BIT(1)
22 #define PRCRS_GPIO      BIT(2)
23 #define PRCRS_SYS_CTRL  BIT(3)
24 
25 /* Non-safety area protect register */
26 #define PRCRN_PRC0 BIT(0)
27 #define PRCRN_PRC1 BIT(1)
28 #define PRCRN_PRC2 BIT(2)
29 
30 #define SCI4ASYNCSEL BIT(31)
31 #define SCI3ASYNCSEL BIT(30)
32 #define SCI2ASYNCSEL BIT(29)
33 #define SCI1ASYNCSEL BIT(28)
34 #define SCI0ASYNCSEL BIT(27)
35 #define SPI2ASYNCSEL BIT(26)
36 #define SPI1ASYNCSEL BIT(25)
37 #define SPI0ASYNCSEL BIT(24)
38 #define CLMASEL      BIT(22)
39 #define PHYSEL       BIT(21)
40 #define FSELCANFD    BIT(20)
41 #define DIVSELXSPI1  BIT(14)
42 #define DIVSELXSPI0  BIT(6)
43 
44 #define CKIO_DEFAULT      BIT(17)
45 #define FSELXSPI1_DEFAULT GENMASK(10, 9)
46 #define FSELXSPI0_DEFAULT GENMASK(2, 1)
47 
48 #define SCI5ASYNCSEL     BIT(25)
49 #define SPI3ASYNCSEL     BIT(24)
50 #define DIVSELSUB        BIT(5)
51 #define FSELCPU1_DEFAULT 0b10 << 2
52 #define FSELCPU0_DEFAULT 0b10 << 0
53 
54 /* PRC Key Code - this value is required to allow any write operation
55  * to the PRCRS / PRCRN registers.
56  * See section 10.2 of the RZ/T2M User's Manual: Hardware.
57  */
58 #define PRC_KEY_CODE 0xa500
59 
60 void rzt2m_unlock_prcrn(uint32_t mask);
61 void rzt2m_lock_prcrn(uint32_t mask);
62 void rzt2m_unlock_prcrs(uint32_t mask);
63 void rzt2m_lock_prcrs(uint32_t mask);
64 
65 void rzt2m_set_sckcr2(uint32_t mask);
66 uint32_t rzt2m_get_sckcr2(void);
67 void rzt2m_set_sckcr(uint32_t mask);
68 uint32_t rzt2m_get_sckcr(void);
69 
70 #endif /* _SOC__H_ */
71