Searched defs:CIMR (Results 1 – 13 of 13) sorted by relevance
| /hal_nxp-3.5.0/s32/drivers/s32k3/Adc/include/ |
| D | Adc_Sar_Ip_HeaderWrapper_S32K3.h | 170 #define CIMR(base, regIndex) REG_ACCESS((base)->CIMR0, (regIndex)) macro
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 3145 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 3725 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 4836 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 4820 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 6452 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 5087 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 5090 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 6530 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 6454 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 6534 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 6608 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ member
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| /hal_nxp-3.5.0/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 4501 …__IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0… member
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