1 /* SPDX-License-Identifier: Apache-2.0 */ 2 /* 3 * Copyright (c) 2023 Intel Corporation 4 * 5 * Author: Adrian Warecki <adrian.warecki@intel.com> 6 */ 7 8 #ifndef __INTEL_DAI_DRIVER_DMIC_REGS_H__ 9 #define __INTEL_DAI_DRIVER_DMIC_REGS_H__ 10 11 /* DMIC timestamping registers */ 12 #define TS_DMIC_LOCAL_TSCTRL_OFFSET 0x000 13 #define TS_DMIC_LOCAL_OFFS_OFFSET 0x004 14 #define TS_DMIC_LOCAL_SAMPLE_OFFSET 0x008 15 #define TS_DMIC_LOCAL_WALCLK_OFFSET 0x010 16 #define TS_DMIC_TSCC_OFFSET 0x018 17 18 /* Timestamping */ 19 #define TIMESTAMP_BASE 0x00071800 20 21 /* Time Stamp Control Register */ 22 #define TS_DMIC_LOCAL_TSCTRL (TIMESTAMP_BASE + TS_DMIC_LOCAL_TSCTRL_OFFSET) 23 24 /* Intersample offset Register */ 25 #define TS_DMIC_LOCAL_OFFS (TIMESTAMP_BASE + TS_DMIC_LOCAL_OFFS_OFFSET) 26 27 #define TS_DMIC_LOCAL_SAMPLE (TIMESTAMP_BASE + TS_DMIC_LOCAL_SAMPLE_OFFSET) 28 #define TS_DMIC_LOCAL_WALCLK (TIMESTAMP_BASE + TS_DMIC_LOCAL_WALCLK_OFFSET) 29 30 /* Time Stamp Counter Captured 64 bits */ 31 #define TS_DMIC_TSCC (TIMESTAMP_BASE + TS_DMIC_TSCC_OFFSET) 32 33 /* New Timestamp Taken */ 34 #define TS_LOCAL_TSCTRL_NTK BIT(31) 35 36 /* Interrupt on New Timestamp Enable */ 37 #define TS_LOCAL_TSCTRL_IONTE BIT(30) 38 39 /* Automatically capture the local timestamp when the stream is started. */ 40 #define TS_LOCAL_TSCTRL_SIP BIT(8) 41 42 /* Hammock Harbor Time Stamp Enable */ 43 #define TS_LOCAL_TSCTRL_HHTSE BIT(7) 44 45 /* Link Wall Clock Select */ 46 #define TS_LOCAL_TSCTRL_LWCS BIT(6) 47 48 /* On Demand Time Stamp */ 49 #define TS_LOCAL_TSCTRL_ODTS BIT(5) 50 51 /* Capture DMA Select */ 52 #define TS_LOCAL_TSCTRL_CDMAS GENMASK(4, 0) 53 54 /* Snapshot of Audio Wall Clock Offset counter (frame offset). */ 55 #define TS_LOCAL_OFFS_FRM GENMASK(15, 12) 56 57 /* Snapshot of Audio Wall Clock Offset counter (clock offset). */ 58 #define TS_LOCAL_OFFS_CLK GENMASK(11, 0) 59 60 61 /* DMIC register offsets */ 62 63 /* Global registers */ 64 65 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF) 66 * PDM Primary Channel 67 */ 68 69 /* Control registers for packers */ 70 #define OUTCONTROL 0x0000 71 72 /* Status Register for FIFO interface */ 73 #define OUTSTAT 0x0004 74 75 /* Data read/Write port for FIFO */ 76 #define OUTDATA 0x0008 77 78 /* (crossed out) 000Ch LOCAL_OFFS Offset Counter 79 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp 80 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count 81 * 001Ch - 00FFh Reserved space for extensions 82 */ 83 84 /* Offset to PDM Secondary Channel */ 85 #define PDM_CHANNEL_REGS_SIZE 0x100 86 87 88 #define GLOBAL_CAPABILITIES 0x200 89 90 #define PDM_COEFFICIENT_A 0x400 91 #define PDM_COEF_RAM_A_LENGTH 0x400 92 93 #define PDM_COEFFICIENT_B 0x800 94 #define PDM_COEF_RAM_B_LENGTH 0x400 95 96 #define PDM0 0x1000 97 #define PDM1 0x2000 98 #define PDM2 0x3000 99 #define PDM3 0x4000 100 101 102 /* Local registers in each PDMx */ 103 104 /* Control register for CIC configuration and decimator setting */ 105 #define CIC_CONTROL 0x000 106 107 /* Control of the CIC filter plus voice channel (B) FIR decimation factor */ 108 #define CIC_CONFIG 0x004 109 110 /* Microphone interface control register */ 111 #define MIC_CONTROL 0x00c 112 113 /* FIR config */ 114 115 /* Control for the FIR decimator */ 116 #define FIR_CONTROL 0x020 117 118 /* Configuration of FIR decimator parameters */ 119 #define FIR_CONFIG 0x024 120 121 /* DC offset for left channel */ 122 #define DC_OFFSET_LEFT 0x028 123 124 /* DC offset for right channel */ 125 #define DC_OFFSET_RIGHT 0x02c 126 127 /* Gain for left channel */ 128 #define OUT_GAIN_LEFT 0x030 129 130 /* Gain for right channel */ 131 #define OUT_GAIN_RIGHT 0x034 132 133 /* Offset to secondary FIR */ 134 #define FIR_CHANNEL_REGS_SIZE 0x20 135 136 137 /* Digital Mic Shim Registers */ 138 139 /* Digital Microphone Link Control */ 140 #define DMICLCTL 0x04 141 142 /* Digital Microphone IP Pointer */ 143 #define DMICIPPTR 0x08 144 145 146 /* OUTCONTROL0 and OUTCONTROL1 */ 147 148 /* OUTCONTROLx IPM bit fields style */ 149 #define OUTCONTROL_BFTH_MAX 4 /* Max depth 16 */ 150 151 /* Threshold Interrupt Enable */ 152 #define OUTCONTROL_TIE BIT(27) 153 154 /* Start Input Packer */ 155 #define OUTCONTROL_SIP BIT(26) 156 157 /* FIFO Initialize (FINIT): The software will set this bit to immediately clear FIFO pointers. */ 158 #define OUTCONTROL_FINIT BIT(25) 159 160 /* Input Format Change Indicator */ 161 #define OUTCONTROL_FCI BIT(24) 162 163 /* Burst FIFO Threshold */ 164 #define OUTCONTROL_BFTH GENMASK(23, 20) 165 166 /* Output Format */ 167 #define OUTCONTROL_OF GENMASK(19, 18) 168 169 170 /* This field decides the packer mode */ 171 #define OUTCONTROL_IPM GENMASK(17, 16) 172 173 /* Source decimator for 1st stereo/mono data placeholder. */ 174 #define OUTCONTROL_IPM_SOURCE_1 GENMASK(14, 13) 175 176 /* Source decimator for 2nd stereo/mono data placeholder. */ 177 #define OUTCONTROL_IPM_SOURCE_2 GENMASK(12, 11) 178 179 /* Source decimator for 3rd stereo/mono data placeholder. */ 180 #define OUTCONTROL_IPM_SOURCE_3 GENMASK(10, 9) 181 182 /* Source decimator for 4th stereo/mono data placeholder. */ 183 #define OUTCONTROL_IPM_SOURCE_4 GENMASK(8, 7) 184 185 /* Defines the mode of operation for all source decimator. */ 186 #define OUTCONTROL_IPM_SOURCE_MODE BIT(6) 187 188 /* FIFO Trigger Threshold */ 189 #define OUTCONTROL_TH GENMASK(5, 0) 190 191 192 /* OUTSTAT0 and OUTSTAT1 bits */ 193 194 /* Asynchronous FIFO is empty */ 195 #define OUTSTAT_AFE BIT(31) 196 197 /* Asynchronous FIFO Not Empty */ 198 #define OUTSTAT_ASNE BIT(29) 199 200 /* FIFO Service Request */ 201 #define OUTSTAT_RFS BIT(28) 202 203 /* Overrun */ 204 #define OUTSTAT_ROR BIT(27) 205 206 /* FIFO Level (FL): Current FIFO Level in the Asynchronous FIFO. */ 207 #define OUTSTAT_FL_MASK GENMASK(6, 0) 208 209 /* CIC_CONTROL bits */ 210 211 /* Microphone interface reset. */ 212 #define CIC_CONTROL_SOFT_RESET BIT(16) 213 214 /* When set to 1, the CIC channel B (right) is started, otherwise it is muted and idle. */ 215 #define CIC_CONTROL_CIC_START_B BIT(15) 216 217 /* When set to 1, the CIC channel A (left) is started, otherwise it is muted and idle. */ 218 #define CIC_CONTROL_CIC_START_A BIT(14) 219 220 /* Polarity of the microphone output. */ 221 #define CIC_CONTROL_MIC_B_POLARITY BIT(3) 222 223 /* Polarity of the microphone output. */ 224 #define CIC_CONTROL_MIC_A_POLARITY BIT(2) 225 226 /* Mute currently active microphones */ 227 #define CIC_CONTROL_MIC_MUTE BIT(1) 228 229 /* When set, the microphone input operates in the stereo mode */ 230 #define CIC_CONTROL_STEREO_MODE BIT(0) 231 232 233 /* CIC_CONFIG masks */ 234 235 /* Number of bits for shift right in the output stage of the CIC filter to compensate the gain 236 * accumulated due to decimation. 237 */ 238 #define CIC_CONFIG_CIC_SHIFT GENMASK(27, 24) 239 240 /* Period of activation of comb section in the microphone clocks minus 1 */ 241 #define CIC_CONFIG_COMB_COUNT GENMASK(15, 8) 242 243 244 /* MIC_CONTROL */ 245 246 /* Clock divider used for producing the microphone clock from audio IO clock with approximately 50% 247 * duty cycle. 248 */ 249 #define MIC_CONTROL_PDM_CLKDIV GENMASK(15, 8) 250 251 #define MIC_CONTROL_PDM_SKEW GENMASK(7, 4) 252 253 /* Inverts the clock edge that will be used to sample microphone data stream. */ 254 #define MIC_CONTROL_CLK_EDGE BIT(3) 255 256 /* Enable clock on microphone B (Right) */ 257 #define MIC_CONTROL_PDM_EN_B BIT(1) 258 259 /* Enable clock on microphone A (left) */ 260 #define MIC_CONTROL_PDM_EN_A BIT(0) 261 262 /* FIR decimation filter is started. */ 263 #define FIR_CONTROL_START BIT(7) 264 265 /* Array microphone control bit for synchronous start of multiple interfaces. */ 266 #define FIR_CONTROL_ARRAY_START_EN BIT(6) 267 268 /* Automatic DC compensation enable */ 269 #define FIR_CONTROL_DCCOMP BIT(4) 270 271 /* Write in the coefficient memory will mute the output for the N audio clocks */ 272 #define FIR_CONTROL_AUTO_MUTE BIT(2) 273 274 /* Mute outputs of this filter and set it to zero. */ 275 #define FIR_CONTROL_MUTE BIT(1) 276 277 /* Filter operates in stereo mode */ 278 #define FIR_CONTROL_STEREO BIT(0) 279 280 281 /* FIR_CONFIG bits */ 282 283 /* Decimation factor of the FIR filter minus 1. */ 284 #define FIR_CONFIG_FIR_DECIMATION GENMASK(20, 16) 285 286 /* Number of bits for shift right in the output stage of the CIC filter to compensate the gain 287 * accumulated due to decimation. 288 */ 289 #define FIR_CONFIG_FIR_SHIFT GENMASK(11, 8) 290 291 /* The number of active taps of the FIR filter minus 1. */ 292 #define FIR_CONFIG_FIR_LENGTH GENMASK(7, 0) 293 294 295 /* DC_OFFSET_LEFT and DC_OFFSET_RIGHT */ 296 297 /* Value added to the output of the FIR filter. */ 298 #define DC_OFFSET_DC_OFFS GENMASK(21, 0) 299 300 301 /* OUT_GAIN_LEFT and OUT_GAIN_RIGHT */ 302 303 /* Value added to the output of the FIR filter. */ 304 #define OUT_GAIN GENMASK(19, 0) 305 306 /* FIR coefficients */ 307 #define FIR_COEF GENMASK(19, 0) 308 309 310 /* GLOBAL_CAPABILITIES */ 311 312 /* Nnumber of data entries supported in the PCM XCLK FIFO per FIR output. */ 313 #define GLOBAL_CAP_PCM_XCLK_FIFO_DEPTH GENMASK(5, 0) 314 315 /* Port Count */ 316 #define GLOBAL_CAP_PORT_COUNT GENMASK(7, 6) 317 318 /* FIR Count */ 319 #define GLOBAL_CAP_FIR_COUNT BIT(8) 320 321 /* FIR max gain configuration. */ 322 #define GLOBAL_CAP_FIR_MAX_GAIN BIT(9) 323 324 /* FIR A RF Depth */ 325 #define GLOBAL_CAP_FIR_A_RF_DEPTH GENMASK(23, 16) 326 327 /* FIR B RF Depth */ 328 #define GLOBAL_CAP_FIR_B_RF_DEPTH GENMASK(31, 24) 329 330 331 /* DMIC Link Control 332 * 333 * This register controls the specific link. 334 */ 335 #define DMICLCTL_OFFSET 0x04 336 337 /* Set Power Active */ 338 #define DMICLCTL_SPA BIT(0) 339 340 /* Current Power Active */ 341 #define DMICLCTL_CPA BIT(8) 342 343 /* Dynamic Clock Gating Disable */ 344 #define DMICLCTL_DCGD BIT(30) 345 346 /* Idle Clock Gating Disable */ 347 #define DMICLCTL_ICGD BIT(31) 348 349 #endif /* !__INTEL_DAI_DRIVER_DMIC_REGS_H__ */ 350
