1 /* 2 * Copyright 2023, Cypress Semiconductor Corporation (an Infineon company) 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef INCLUDED_CHIP_CONSTANTS_H_ 19 #define INCLUDED_CHIP_CONSTANTS_H_ 20 21 #include "whd.h" 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #define WRAPPER_REGISTER_OFFSET (0x100000) 28 typedef enum chip_var 29 { 30 ARM_CORE_BASE_ADDRESS = 1, 31 SOCSRAM_BASE_ADDRESS, 32 SOCSRAM_WRAPPER_BASE_ADDRESS, 33 SDIOD_CORE_BASE_ADDRESS, 34 PMU_BASE_ADDRESS, 35 CHIP_RAM_SIZE, 36 ATCM_RAM_BASE_ADDRESS, 37 SOCRAM_SRMEM_SIZE, 38 CHANSPEC_BAND_MASK, 39 CHANSPEC_BAND_2G, 40 CHANSPEC_BAND_5G, 41 CHANSPEC_BAND_SHIFT, 42 CHANSPEC_BW_10, 43 CHANSPEC_BW_20, 44 CHANSPEC_BW_40, 45 CHANSPEC_BW_MASK, 46 CHANSPEC_BW_SHIFT, 47 CHANSPEC_CTL_SB_LOWER, 48 CHANSPEC_CTL_SB_UPPER, 49 CHANSPEC_CTL_SB_NONE, 50 CHANSPEC_CTL_SB_MASK 51 } chip_var_t; 52 53 #define VERIFY_RESULT(x) { whd_result_t verify_result = WHD_SUCCESS; verify_result = (x); \ 54 if (verify_result != WHD_SUCCESS){ \ 55 WPRINT_WHD_ERROR( ("Function %s failed at line %d \n", __func__, __LINE__) ); \ 56 return verify_result; } } 57 #define GET_C_VAR(whd_driver, var) get_whd_var(whd_driver, var) 58 59 uint32_t get_whd_var(whd_driver_t whd_driver, chip_var_t var); 60 61 whd_result_t get_arm_core_base_address(uint16_t, uint32_t *); 62 whd_result_t get_socsram_base_address(uint16_t, uint32_t *, whd_bool_t); 63 whd_result_t get_sdiod_core_base_address(uint16_t, uint32_t *); 64 whd_result_t get_pmu_base_address(uint16_t, uint32_t *); 65 whd_result_t get_chip_ram_size(uint16_t, uint32_t *); 66 whd_result_t get_atcm_ram_base_address(uint16_t, uint32_t *); 67 whd_result_t get_socsram_srmem_size(uint16_t, uint32_t *); 68 whd_result_t get_wl_chanspec_band_mask(uint16_t, uint32_t *); 69 whd_result_t get_wl_chanspec_band_2G(uint16_t, uint32_t *); 70 whd_result_t get_wl_chanspec_band_5G(uint16_t, uint32_t *); 71 whd_result_t get_wl_chanspec_band_shift(uint16_t, uint32_t *); 72 whd_result_t get_wl_chanspec_bw_10(uint16_t, uint32_t *); 73 whd_result_t get_wl_chanspec_bw_20(uint16_t, uint32_t *); 74 whd_result_t get_wl_chanspec_bw_40(uint16_t, uint32_t *); 75 whd_result_t get_wl_chanspec_bw_mask(uint16_t, uint32_t *); 76 whd_result_t get_wl_chanspec_bw_shift(uint16_t, uint32_t *); 77 whd_result_t get_wl_chanspec_ctl_sb_lower(uint16_t, uint32_t *); 78 whd_result_t get_wl_chanspec_ctl_sb_upper(uint16_t, uint32_t *); 79 whd_result_t get_wl_chanspec_ctl_sb_none(uint16_t, uint32_t *); 80 whd_result_t get_wl_chanspec_ctl_sb_mask(uint16_t, uint32_t *); 81 82 uint32_t whd_chip_set_chip_id(whd_driver_t whd_driver, uint16_t id); 83 uint16_t whd_chip_get_chip_id(whd_driver_t whd_driver); 84 85 #undef CHIP_FIRMWARE_SUPPORTS_PM_LIMIT_IOVAR 86 87 #ifdef __cplusplus 88 } /* extern "C" */ 89 #endif 90 91 #endif /* ifndef INCLUDED_CHIP_CONSTANTS_H_ */ 92 93
