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Searched defs:CH1STAT_CLR (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h8292 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h9006 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h10546 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h10566 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h11588 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h12659 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h12373 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h12661 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h13027 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h13891 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h13813 …__IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168… member