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Searched defs:CH0STAT_CLR (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h8280 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h8994 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h10534 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h10554 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h11576 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h12647 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h12361 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h12649 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h13015 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h13879 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h13801 …__IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128… member