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Searched defs:CFG_NUM_LANES (Results 1 – 25 of 47) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h30119 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
57388 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
DMIMXRT1175_cm7.h30121 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
56573 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h29809 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
56049 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
DMIMXRT1165_cm4.h29807 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
56864 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h30121 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
56573 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h31812 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
60772 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
DMIMXRT1166_cm7.h31814 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
59957 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h32121 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
61293 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
DMIMXRT1173_cm7.h32123 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
60478 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h32126 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
60481 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h26339 __IO uint32_t CFG_NUM_LANES; /**< Configure number of lanes, offset: 0x0 */ member
DMIMXRT595S_cm33.h33390 __IO uint32_t CFG_NUM_LANES; /**< Configure number of lanes, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h32128 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
71148 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
DMIMXRT1176_cm4.h32126 __IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */ member
71963 …__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h33389 __IO uint32_t CFG_NUM_LANES; /**< Configure number of lanes, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h33735 __IO uint32_t CFG_NUM_LANES; /**< Configure Number of Lanes, offset: 0x0 */ member
DMIMXRT758S_hifi1.h33689 __IO uint32_t CFG_NUM_LANES; /**< Configure Number of Lanes, offset: 0x0 */ member
DMIMXRT758S_cm33_core0.h48225 __IO uint32_t CFG_NUM_LANES; /**< Configure Number of Lanes, offset: 0x0 */ member
DMIMXRT758S_ezhv.h47349 __IO uint32_t CFG_NUM_LANES; /**< Configure Number of Lanes, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h33689 __IO uint32_t CFG_NUM_LANES; /**< Configure Number of Lanes, offset: 0x0 */ member
DMIMXRT798S_cm33_core1.h33735 __IO uint32_t CFG_NUM_LANES; /**< Configure Number of Lanes, offset: 0x0 */ member
DMIMXRT798S_hifi4.h48158 __IO uint32_t CFG_NUM_LANES; /**< Configure Number of Lanes, offset: 0x0 */ member
DMIMXRT798S_cm33_core0.h48225 __IO uint32_t CFG_NUM_LANES; /**< Configure Number of Lanes, offset: 0x0 */ member
DMIMXRT798S_ezhv.h47349 __IO uint32_t CFG_NUM_LANES; /**< Configure Number of Lanes, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_cm4_core1.h83034 __IO uint32_t CFG_NUM_LANES; /**< offset: 0x0 */ member

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