1 /********************************************************************** 2 * Copyright (C) 2014-2015 Cadence Design Systems, Inc.- http://www.cadence.com 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 *********************************************************************** 17 * edd_int.h 18 * Private declarations for Ethernet DMA-MAC Driver 19 * 20 ***********************************************************************/ 21 22 /**************************************************************************** 23 * Modification by Infineon: To make this file compile with ModusToolbox 24 * toolchain 25 *****************************************************************************/ 26 27 #ifndef _EDD_INT_H_ 28 #define _EDD_INT_H_ 29 30 #include "cy_device_headers.h" 31 #include "cedi.h" 32 33 #ifndef ETH_AXI_MASTER_PRESENT 34 // Assumed that if "ETH_AXI_MASTER_PRESENT" did not exist in Cypress header file, AXI is present. 35 #define ETH_AXI_MASTER_PRESENT 1 36 #endif 37 38 /****************************************************************************** 39 * Private Constants 40 *****************************************************************************/ 41 42 #define GEM_GXL_MODULE_ID_V0 (0x0007) 43 #define GEM_GXL_MODULE_ID_V1 (0x0107) 44 #define GEM_XL_MODULE_ID (0x0008) 45 46 #define XGM_GXL_MODULE_ID (0x000B) 47 48 #define OFFLOADS_GEM_GXL_REV (0x0107) 49 50 #define CEDI_MIN_TXBD 1 51 #define CEDI_MIN_RXBD 1 52 53 #define MAX_JUMBO_FRAME_LENGTH (16383) 54 55 /* Tx Descriptor flags/status - word 1 only */ 56 #define CEDI_TXD_LAST_BUF (1 << 15) 57 #define CEDI_TXD_NO_AUTO_CRC (1 << 16) 58 #define CEDI_TXD_UFO_ENABLE (1 << 17) 59 #define CEDI_TXD_TSO_ENABLE (1 << 18) 60 #define CEDI_TXD_AUTOSEQ_SEL (1 << 19) 61 #define CEDI_TXD_CHKOFF_SHIFT (20) 62 #define CEDI_TXD_CHKOFF_MASK (7 << CEDI_TXD_CHKOFF_SHIFT) 63 #define CEDI_TXD_TS_VALID (1 << 23) 64 #define CEDI_TXD_STREAM_SHIFT (24) 65 #define CEDI_TXD_STREAM_MASK (3 << CEDI_TXD_STREAM_SHIFT) 66 #define CEDI_TXD_LATE_COLL (1 << 26) 67 #define CEDI_TXD_FR_CORR (1 << 27) 68 #define CEDI_TXD_UNDERRUN (1 << 28) 69 #define CEDI_TXD_RETRY_EXC (1 << 29) 70 #define CEDI_TXD_WRAP (1 << 30) 71 #define CEDI_TXD_USED (1 << 31) 72 /* MSS/MFS only used on word 1 of 2nd descriptor */ 73 #define CEDI_TXD_MSSMFS_SHIFT (16) 74 #define CEDI_TXD_MSSMFS_MASK (0x3FFF << CEDI_TXD_MSSMFS_SHIFT) 75 #define CEDI_TXD_LEN_MASK ((1 << 14) - 1) 76 77 /* Rx Descriptor flags - word 0 */ 78 #define CEDI_RXD_USED (1 << 0) 79 #define CEDI_RXD_WRAP (1 << 1) 80 #define CEDI_RXD_TS_VALID (1 << 2) 81 #define CEDI_RXD_ADDR_MASK (0xFFFFFFFC) 82 #define CEDI_RXD_ADDR_SHIFT (2) 83 84 /* Rx Descriptor flags/status - word 1 */ 85 #define CEDI_RXD_LEN_MASK ((1 << 13) - 1) 86 /*** need to include bit 13 if jumbo frames enabled ***/ 87 #define CEDI_RXD_LEN13_FCS_STAT (1 << 13) 88 #define CEDI_RXD_SOF (1 << 14) 89 #define CEDI_RXD_EOF (1 << 15) 90 #define CEDI_RXD_CFI (1 << 16) 91 #define CEDI_RXD_VLAN_PRI_SHIFT (17) 92 #define CEDI_RXD_VLAN_PRI_MASK (7 << CEDI_RXD_VLAN_PRI_SHIFT) 93 /* if header-data splitting, these definitions are valid when not EOF: */ 94 #define CEDI_RXD_HDR (1 << 16) /* header buffer */ 95 #define CEDI_RXD_EOH (1 << 17) /* end of header */ 96 97 #define CEDI_RXD_PRI_TAG (1 << 20) 98 #define CEDI_RXD_VLAN_TAG (1 << 21) 99 // either Type ID match register or 100 // (if Rx chksum offload enabled) checksum status 101 #define CEDI_RXD_TYP_IDR_CHK_STA_SHIFT (22) 102 #define CEDI_RXD_TYP_IDR_CHK_STA_MASK (3 << CEDI_RXD_TYP_IDR_CHK_STA_SHIFT) 103 // either Type ID matched or 104 // (if Rx chksum offload enabled) SNAP encoded and no CFI 105 #define CEDI_RXD_TYP_MAT_SNP_NCFI (1 << 24) 106 #define CEDI_RXD_SPEC_REG_SHIFT (25) 107 #define CEDI_RXD_SPEC_REG_MASK (3 << CEDI_RXD_SPEC_REG_SHIFT) 108 #define CEDI_RXD_SPEC_ADD_MAT (1 << 27) 109 #define CEDI_RXD_EXT_ADD_MAT (1 << 28) 110 #define CEDI_RXD_UNI_HASH_MAT (1 << 29) 111 #define CEDI_RXD_MULTI_HASH_MAT (1 << 30) 112 #define CEDI_RXD_BROADCAST_DET (1 << 31) 113 114 /* For Tx/Rx time stamp extraction from descriptor words */ 115 #define CEDI_TS_NANO_SEC_MASK (0x3FFFFFFF) 116 #define CEDI_TS_SEC0_SHIFT (30) 117 #define CEDI_TS_SEC1_MASK (0x0F) 118 #define CEDI_TS_SEC1_POS_SHIFT (2) 119 #define CEDI_TS_SEC_WIDTH (6U) 120 #define CEDI_TS_SEC_TOP (1U << CEDI_TS_SEC_WIDTH) 121 #define CEDI_TS_SEC_MASK (CEDI_TS_SEC_TOP - 1U) 122 123 124 125 #define CEDI_RXD_EMPTY (0xFFAA0000) 126 127 #define CEDI_PHY_ADDR_OP (0) 128 #define CEDI_PHY_WRITE_OP (1) 129 #define CEDI_PHY_CL22_READ_OP (2) 130 #define CEDI_PHY_CL45_READ_INC_OP (2) 131 #define CEDI_PHY_CL45_READ_OP (3) 132 133 134 #define CEDI_TWO_BD_WORD_SIZE (8) // Size required for two buffer descriptor word (in bytes). 135 #define CEDI_BYTES_PER_WORD_SHIFT (2) // Shift variable for number of bytes in a word 136 #define CEDI_DESC_WORD_NUM_MAX (6) // Maximum number of words allowed in a descriptor. 137 138 #define CEDI_AMBD_BURST_LEN_1 (0x01) // for CEDI_DMA_DBUR_LEN_1 139 #define CEDI_AMBD_BURST_LEN_4 (0x04) // for CEDI_DMA_DBUR_LEN_4 140 #define CEDI_AMBD_BURST_LEN_8 (0x08) // for CEDI_DMA_DBUR_LEN_8 141 #define CEDI_AMBD_BURST_LEN_16 (0x10) // for CEDI_DMA_DBUR_LEN_16 142 143 /****************************************************************************** 144 * Local macros - assume pD is privateData parameter in function scope, and 145 * cfg has been initialised with register base address 146 *****************************************************************************/ 147 148 /* access a privateData field, via the local void *pD parameter */ 149 #define CEDI_PdVar(var) (((CEDI_PrivateData *)pD)->var) 150 /* get register address via the privateDat->cfg.regBase field */ 151 #define CEDI_RegAddr(reg) (&(((struct emac_regs *)(CEDI_PdVar(cfg).regBase))->reg)) 152 153 /****************************************************************************** 154 * Types 155 *****************************************************************************/ 156 157 /* Tx Descriptor defs */ 158 typedef struct { 159 uint32_t word[CEDI_DESC_WORD_NUM_MAX]; 160 } txDesc; 161 162 typedef struct { 163 txDesc *bdBase; // base address of descriptor ring 164 txDesc *bdHead; // first available descriptor 165 txDesc *bdTail; // first descriptor waiting to be freed 166 txDesc *bd1stBuf; // first buffer of current frame 167 uint16_t descMax; // total number of descriptors 168 uint16_t descFree; // number of descriptors that can accept buffers 169 uintptr_t *vHead; // virt address corresponding to head BD 170 uintptr_t *vTail; // end of virt address circular array 171 uintptr_t *vAddrList; // pointer to virt addresses storage 172 uint8_t firstToFree; // flag indicating stage of frame clean-up: set 173 // when about to clear first buffer of frame 174 uint8_t descNum; // descriptor counter used by qTxBuf: stays at 0 until 175 // start 2nd desc of frame, then inc to 1, etc. 176 } txQueue_t; 177 178 /* Rx Descriptor defs */ 179 typedef struct { 180 uint32_t word[CEDI_DESC_WORD_NUM_MAX]; 181 } rxDesc; 182 183 typedef struct { 184 rxDesc *rxDescStart; // start of Rx descriptor list 185 rxDesc *rxDescStop; // end-stop Rx descriptor, trails behind "Tail"; 186 // always kept "used" but with no buffer 187 rxDesc *rxDescTail; // next Rx descriptor to process (one after end-stop) 188 rxDesc *rxDescEnd; // last descriptor in Rx list 189 uint16_t numRxDesc; // total number of descriptors in the list, 190 // including unused end-stop 191 uint16_t numRxBufs; // number of useable buffers/descriptors in list 192 uintptr_t *rxTailVA; // tail Rx virtual addr 193 uintptr_t *rxStopVA; // end-stop Rx virtual addr, corr. to rxDescStop 194 uintptr_t *rxEndVA; // end Rx virtual addr 195 uintptr_t *rxBufVAddr; // list of buffer virtual addresses in sync 196 // with physical addresses held in descriptor lists 197 } rxQueue_t; 198 199 /* Driver private data - place the tx & rx virtual address lists after this 200 * (with these included in privateData memory requirement) */ 201 typedef struct { 202 CEDI_Config cfg; // copy of CEDI_Config info supplied to init 203 CEDI_Callbacks cb; // pointers to callback functions 204 CEDI_DesignCfg hwCfg; // copy of DesignCfg Debug registers 205 uint8_t numQs; // number of Qs in this h/w config. 206 txQueue_t txQueue[CEDI_MAX_TX_QUEUES]; // tx queue info 207 rxQueue_t rxQueue[CEDI_MAX_RX_QUEUES]; // rx queue info 208 // CPS_LockHandle isrLock; // lock used during isr calls 209 uint8_t anLinkStat; // retain link status (low) until read 210 uint8_t anRemFault; // retain link partner remote fault status 211 // (high) until read 212 uint8_t autoNegActive; // auto-negotiation in progress flag 213 uint8_t basePageExp; // data expected from link partner: set 214 // initially to indicate base page, clear 215 // after first received to denote next page 216 // expected. Set on start auto-negotiation. 217 218 CEDI_LpPageRx lpPageRx; // reserved for passing page Rx in callback 219 CEDI_NetAnStatus anStatus; // reserved for a-n status in callback 220 CEDI_1588TimerVal ptpTime; // reserved for passing ptp event times 221 // CPS_LockHandle autoNegLock; // lock to protect auto-neg flags and next 222 // page register when isr writes null 223 // message page 224 uint16_t txDescriptorSize; // bytes per Tx descriptor 225 uint16_t rxDescriptorSize; // bytes per Rx descriptor 226 } CEDI_PrivateData; 227 228 229 /*********************** Internal Driver functions ***************************/ 230 231 uint32_t initRxDescLists(void *pD); 232 uint32_t subNsTsuInc24bSupport(void *pD); 233 234 /* Driver API function prototypes (only required if called within API) */ 235 236 uint32_t emacSetEventEnable(void *pD, uint32_t events, uint8_t enable, 237 uint8_t queueNum); 238 uint32_t emacResetPcs(void *pD); 239 uint32_t emacWriteUserOutputs(void *pD, uint16_t outVal); 240 uint32_t emacGetJumboFramesRx(void *pD, uint8_t *enable); 241 uint32_t emacGetJumboFrameRxMaxLen(void *pD, uint16_t *length); 242 uint32_t emacGet1536ByteFramesRx(void *pD, uint8_t *enable); 243 uint32_t emacGetPtpFrameTxTime(void *pD, CEDI_1588TimerVal *time); 244 uint32_t emacGetPtpFrameRxTime(void *pD, CEDI_1588TimerVal *time); 245 uint32_t emacGetPtpPeerFrameTxTime(void *pD, CEDI_1588TimerVal *time); 246 uint32_t emacGetPtpPeerFrameRxTime(void *pD, CEDI_1588TimerVal *time); 247 uint32_t emacClearStats(void *pD); 248 249 uint32_t emacSetAutoNegEnable(void *pD, uint8_t enable); 250 uint32_t emacGetPcsReady(void *pD, uint8_t *ready); 251 uint32_t emacGetLinkStatus(void *pD, uint8_t *status); 252 uint32_t emacSetAnAdvPage(void *pD, CEDI_AnAdvPage *advDat); 253 uint32_t emacGetLpAbilityPage(void *pD, CEDI_LpAbilityPage *lpAbl); 254 uint32_t emacGetLpNextPage(void *pD, CEDI_LpNextPage *npDat); 255 uint32_t emacSetNextPageTx(void *pD, CEDI_AnNextPage *npDat); 256 257 /****************** API Prototypes for other source modules ******************/ 258 259 /****************************** edd_tx.c *************************************/ 260 261 uint32_t emacCalcMaxTxFrameSize(void *pD, CEDI_FrameSize *maxTxSize); 262 263 uint32_t emacQueueTxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *bufAdd, 264 uint32_t length, uint8_t flags); 265 266 uint32_t emacQTxBuf(void *pD, CEDI_qTxBufParams *prm); 267 268 uint32_t emacDeQTxBuf(void *pD, CEDI_qTxBufParams *prm); 269 270 uint32_t emacTxDescFree(void *pD, uint8_t queueNum, uint16_t *numFree); 271 272 uint32_t emacFreeTxDesc(void *pD, uint8_t queueNum, CEDI_TxDescData *descData); 273 274 void emacGetTxDescStat(void *pD, uint32_t txDStatWord, CEDI_TxDescStat *txDStat); 275 276 void emacGetTxDescSize(void *pD, uint32_t *txDescSize); 277 278 uint32_t emacResetTxQ(void *pD, uint8_t queueNum); 279 280 uint32_t emacStartTx(void *pD); 281 282 void emacStopTx(void *pD); 283 284 void emacAbortTx(void *pD); 285 286 uint32_t emacTransmitting(void *pD); 287 288 void emacEnableTx(void *pD); 289 290 uint32_t emacGetTxEnabled(void *pD); 291 292 uint32_t emacGetTxStatus(void *pD, CEDI_TxStatus *status); 293 294 void emacClearTxStatus(void *pD, uint32_t resetStatus); 295 296 uint32_t emacSetTxPartialStFwd(void *pD, uint32_t watermark, uint8_t enable); 297 298 uint32_t emacGetTxPartialStFwd(void *pD, uint32_t *watermark, uint8_t *enable); 299 300 301 uint32_t emacEnableCbs(void *pD, uint8_t qSel, uint32_t idleSlope); 302 303 void emacDisableCbs(void *pD, uint8_t qSel); 304 305 uint32_t emacGetCbsQSetting(void *pD, uint8_t qSel, 306 uint8_t *enable, uint32_t *idleSlope); 307 308 309 uint32_t emacSetIpgStretch(void *pD, uint8_t enable, uint8_t multiplier, 310 uint8_t divisor); 311 312 uint32_t emacGetIpgStretch(void *pD, uint8_t *enabled, uint8_t *multiplier, 313 uint8_t *divisor); 314 315 316 317 /****************************** edd_rx.c *************************************/ 318 319 uint32_t emacCalcMaxRxFrameSize(void *pD, uint32_t *maxSize); 320 321 uint32_t emacAddRxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *buf, 322 uint8_t init); 323 324 uint32_t emacNumRxBufs(void *pD, uint8_t queueNum, uint16_t *numBufs); 325 326 uint32_t emacNumRxUsed(void *pD, uint8_t queueNum); 327 328 uint32_t emacReadRxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *buf, 329 uint8_t init, CEDI_RxDescData *descData); 330 331 void emacGetRxDescStat(void *pD, uint32_t rxDStatWord, CEDI_RxDescStat *rxDStat); 332 333 void emacGetRxDescSize(void *pD, uint32_t *rxDescSize); 334 335 uint32_t emacRxEnabled(void *pD); 336 337 void emacEnableRx(void *pD); 338 339 void emacDisableRx(void *pD); 340 341 uint32_t emacRemoveRxBuf(void *pD, uint8_t queueNum, CEDI_BuffAddr *buf); 342 343 void emacFindQBaseAddr(void *pD, uint8_t queueNum, rxQueue_t *rxQ, 344 uint32_t *pAddr, uintptr_t *vAddr); 345 346 uint32_t emacResetRxQ(void *pD, uint8_t queueNum, uint8_t ptrsOnly); 347 348 uint32_t emacGetRxStatus(void *pD, CEDI_RxStatus *status); 349 350 void emacClearRxStatus(void *pD, uint32_t resetStatus); 351 352 353 uint32_t emacSetHdrDataSplit(void *pD, uint8_t enable); 354 355 uint32_t emacGetHdrDataSplit(void *pD, uint8_t *enable); 356 357 uint32_t emacSetRscEnable(void *pD, uint8_t queue, uint8_t enable); 358 359 uint32_t emacGetRscEnable(void *pD, uint8_t queue, uint8_t *enable); 360 361 uint32_t emacSetRscClearMask(void *pD, uint8_t setMask); 362 363 364 uint32_t emacSetRxPartialStFwd(void *pD, uint32_t watermark, uint8_t enable); 365 366 uint32_t emacGetRxPartialStFwd(void *pD, uint32_t *watermark, uint8_t *enable); 367 368 uint32_t emacSetSpecificAddr(void *pD, uint8_t addrNum, CEDI_MacAddress *addr, 369 uint8_t specFilterType,uint8_t byteMask); 370 371 uint32_t emacGetSpecificAddr(void *pD, uint8_t addrNum, CEDI_MacAddress *addr, 372 uint8_t *specFilterType, uint8_t *byteMask); 373 374 uint32_t emacSetSpecificAddr1Mask(void *pD, CEDI_MacAddress *mask); 375 376 uint32_t emacGetSpecificAddr1Mask(void *pD, CEDI_MacAddress *mask); 377 378 uint32_t emacDisableSpecAddr(void *pD, uint8_t addrNum); 379 380 uint32_t emacSetTypeIdMatch(void *pD, uint8_t matchSel, uint16_t typeId, 381 uint8_t enable); 382 383 uint32_t emacGetTypeIdMatch(void *pD, uint8_t matchSel, uint16_t *typeId, 384 uint8_t *enabled); 385 386 void emacSetUnicastEnable(void *pD, uint8_t enable); 387 388 uint32_t emacGetUnicastEnable(void *pD, uint8_t *enable); 389 390 void emacSetMulticastEnable(void *pD, uint8_t enable); 391 392 uint32_t emacGetMulticastEnable(void *pD, uint8_t *enable); 393 394 void emacSetNoBroadcast(void *pD, uint8_t reject); 395 396 uint32_t emacGetNoBroadcast(void *pD, uint8_t *reject); 397 398 void emacSetVlanOnly(void *pD, uint8_t enable); 399 400 uint32_t emacGetVlanOnly(void *pD, uint8_t *enable); 401 402 void emacSetStackedVlanReg(void *pD, uint8_t enable, uint16_t vlanType); 403 404 void emacGetStackedVlanReg(void *pD, uint8_t *enable, uint16_t *vlanType); 405 406 void emacSetCopyAllFrames(void *pD, uint8_t enable); 407 408 uint32_t emacGetCopyAllFrames(void *pD, uint8_t *enable); 409 410 uint32_t emacSetHashAddr(void *pD, uint32_t hAddrTop, uint32_t hAddrBot); 411 412 uint32_t emacGetHashAddr(void *pD, uint32_t *hAddrTop, uint32_t *hAddrBot); 413 414 void emacSetLenErrDiscard(void *pD, uint8_t enable); 415 416 uint32_t emacGetLenErrDiscard(void *pD, uint8_t *enable); 417 418 419 uint32_t emacGetNumScreenRegs(void *pD, CEDI_NumScreeners *regNums); 420 421 uint32_t emacSetType1ScreenReg(void *pD, uint8_t regNum, CEDI_T1Screen *regVals); 422 423 uint32_t emacGetType1ScreenReg(void *pD, uint8_t regNum, CEDI_T1Screen *regVals); 424 425 uint32_t emacSetType2ScreenReg(void *pD, uint8_t regNum, CEDI_T2Screen *regVals); 426 427 uint32_t emacGetType2ScreenReg(void *pD, uint8_t regNum, CEDI_T2Screen *regVals); 428 429 uint32_t emacSetType2EthertypeReg(void *pD, uint8_t index, uint16_t eTypeVal); 430 431 uint32_t emacGetType2EthertypeReg(void *pD, uint8_t index, uint16_t *eTypeVal); 432 433 uint32_t emacSetType2CompareReg(void *pD, uint8_t index, 434 CEDI_T2Compare *regVals); 435 436 uint32_t emacGetType2CompareReg(void *pD, uint8_t index, 437 CEDI_T2Compare *regVals); 438 439 440 #endif /* multiple inclusion protection */ 441
