1 /********************************************************************** 2 * Copyright (C) 2013-2015 Cadence Design Systems, Inc.- http://www.cadence.com 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 ********************************************************************** 17 * WARNING: This file is auto-generated using api-generator utility. 18 * Do not edit it manually. 19 ********************************************************************** 20 * Cadence Core Driver for the Cadence Ethernet MAC (EMAC) core. This 21 * header file lists the API providing a HAL (hardware abstraction 22 * layer) interface for the EMAC core, GEM_GXL part no. IP7014 23 **********************************************************************/ 24 25 #ifndef _CEDI_H_ 26 #define _CEDI_H_ 27 28 #include "cdn_stdint.h" 29 30 /** @defgroup ConfigInfo Configuration and Hardware Operation Information 31 * The following definitions specify the driver operation environment that 32 * is defined by hardware configuration or client code. These defines are 33 * located in the header file of the core driver. 34 * @{ 35 */ 36 37 /********************************************************************** 38 * Defines 39 **********************************************************************/ 40 /** 41 * General config. 42 * @xmlonly <defstofollow>4</defstofollow> REMOVE_ME @endxmlonly 43 * Max number of Rx priority queues supported by driver 44 */ 45 #define CEDI_MAX_RX_QUEUES (16) 46 47 /** Max number of Tx priority queues supported by driver */ 48 #define CEDI_MAX_TX_QUEUES (16) 49 50 /** Allows en/disabling of events on all priority queues */ 51 #define CEDI_ALL_QUEUES (255) 52 53 /** Max size of each Rx buffer descriptor list */ 54 #define CEDI_MAX_RBQ_LENGTH (1000) 55 56 /** max size of each Tx buffer descriptor list */ 57 #define CEDI_MAX_TBQ_LENGTH (1000) 58 59 /** Bit-flags to specify DMA endianism. @xmlonly <defstofollow>1</defstofollow> REMOVE_ME @endxmlonly */ 60 #define CEDI_END_SWAP_DESC (0x01) 61 62 #define CEDI_END_SWAP_DATA (0x02) 63 64 /** Bit-flags to specify DMA config register bits 24-27; see EMAC User Guide for details. @xmlonly <defstofollow>3</defstofollow> REMOVE_ME @endxmlonly */ 65 #define CEDI_CFG_DMA_DISC_RXP (0x01) 66 67 #define CEDI_CFG_DMA_FRCE_RX_BRST (0x02) 68 69 #define CEDI_CFG_DMA_FRCE_TX_BRST (0x04) 70 71 /** 72 * Bit-flags to specify checksum offload operation. 73 * @xmlonly <defstofollow>1</defstofollow> REMOVE_ME @endxmlonly 74 */ 75 #define CEDI_CFG_CHK_OFF_TX (0x01) 76 77 #define CEDI_CFG_CHK_OFF_RX (0x02) 78 79 /** 80 * Bit-flags for selecting interrupts to enable/disable/read. 81 * @xmlonly <defstofollow>28</defstofollow> REMOVE_ME @endxmlonly 82 * Frame has been transmitted successfully 83 */ 84 #define CEDI_EV_TX_COMPLETE (0x00000001) 85 86 /** Used bit set has been read in Tx descriptor list */ 87 #define CEDI_EV_TX_USED_READ (0x00000002) 88 89 /** Tx underrun */ 90 #define CEDI_EV_TX_UNDERRUN (0x00000004) 91 92 /** Retry limit exceeded or late collision */ 93 #define CEDI_EV_TX_RETRY_EX_LATE_COLL (0x00000008) 94 95 /** Tx frame corruption */ 96 #define CEDI_EV_TX_FR_CORRUPT (0x00000010) 97 98 /** Frame received successfully and stored */ 99 #define CEDI_EV_RX_COMPLETE (0x00000020) 100 101 /** Used bit set has been read in Rx descriptor list */ 102 #define CEDI_EV_RX_USED_READ (0x00000040) 103 104 /** Rx overrun error */ 105 #define CEDI_EV_RX_OVERRUN (0x00000080) 106 107 /** DMA hresp not OK */ 108 #define CEDI_EV_HRESP_NOT_OK (0x00000100) 109 110 /** PCS auto-negotiation link partner page received */ 111 #define CEDI_EV_PCS_LP_PAGE_RX (0x00000200) 112 113 /** PCS auto-negotiation has completed */ 114 #define CEDI_EV_PCS_AN_COMPLETE (0x00000400) 115 116 /** Link status change detected by PCS */ 117 #define CEDI_EV_PCS_LINK_CHANGE_DET (0x00000800) 118 119 /** Pause frame transmitted */ 120 #define CEDI_EV_PAUSE_FRAME_TX (0x00001000) 121 122 /** Pause time reaches zero or zeroq pause frame received */ 123 #define CEDI_EV_PAUSE_TIME_ZERO (0x00002000) 124 125 /** Pause frame with non-zero quantum received */ 126 #define CEDI_EV_PAUSE_NZ_QU_RX (0x00004000) 127 128 /** PTP delay_req frame transmitted */ 129 #define CEDI_EV_PTP_TX_DLY_REQ (0x00008000) 130 131 /** PTP sync frame transmitted */ 132 #define CEDI_EV_PTP_TX_SYNC (0x00010000) 133 134 /** PTP pdelay_req frame transmitted */ 135 #define CEDI_EV_PTP_TX_PDLY_REQ (0x00020000) 136 137 /** PTP pdelay_resp frame transmitted */ 138 #define CEDI_EV_PTP_TX_PDLY_RSP (0x00040000) 139 140 /** PTP delay_req frame received */ 141 #define CEDI_EV_PTP_RX_DLY_REQ (0x00080000) 142 143 /** PTP sync frame received */ 144 #define CEDI_EV_PTP_RX_SYNC (0x00100000) 145 146 /** PTP pdelay_req frame received */ 147 #define CEDI_EV_PTP_RX_PDLY_REQ (0x00200000) 148 149 /** PTP pdelay_resp frame received */ 150 #define CEDI_EV_PTP_RX_PDLY_RSP (0x00400000) 151 152 /** TSU seconds register increment */ 153 #define CEDI_EV_TSU_SEC_INC (0x00800000) 154 155 /** TSU timer count match */ 156 #define CEDI_EV_TSU_TIME_MATCH (0x01000000) 157 158 /** Management Frame Sent */ 159 #define CEDI_EV_MAN_FRAME (0x02000000) 160 161 /** LPI indication status bit change received */ 162 #define CEDI_EV_LPI_CH_RX (0x04000000) 163 164 /** Wake on LAN event received */ 165 #define CEDI_EV_WOL_RX (0x08000000) 166 167 /** External input interrupt detected */ 168 #define CEDI_EV_EXT_INTR (0x10000000) 169 170 /** Bit-flags for indicating functionality supported by the driver/EMAC @xmlonly <defstofollow>3</defstofollow> REMOVE_ME @endxmlonly Large Segmentation Offload */ 171 #define CEDI_CAP_LSO (0x00000001) 172 173 /** Receive Side Coalescing offload */ 174 #define CEDI_CAP_RSC (0x00000002) 175 176 /** Receive Side Scaling offload */ 177 #define CEDI_CAP_RSS (0x00000004) 178 179 /** Bit-flags for selecting Tx Status fields to reset. @xmlonly <defstofollow>7</defstofollow> REMOVE_ME @endxmlonly */ 180 #define CEDI_TXS_USED_READ (0x0001) 181 182 #define CEDI_TXS_COLLISION (0x0002) 183 184 #define CEDI_TXS_RETRY_EXC (0x0004) 185 186 #define CEDI_TXS_FRAME_ERR (0x0010) 187 188 #define CEDI_TXS_TX_COMPLETE (0x0020) 189 190 #define CEDI_TXS_UNDERRUN (0x0040) 191 192 #define CEDI_TXS_LATE_COLL (0x0080) 193 194 #define CEDI_TXS_HRESP_ERR (0x0100) 195 196 /** 197 * Bit-flags for selecting Rx Status fields to reset. 198 * @xmlonly <defstofollow>3</defstofollow> REMOVE_ME @endxmlonly 199 */ 200 #define CEDI_RXS_NO_BUFF (0x0001) 201 202 #define CEDI_RXS_FRAME_RX (0x0002) 203 204 #define CEDI_RXS_OVERRUN (0x0004) 205 206 #define CEDI_RXS_HRESP_ERR (0x0008) 207 208 /** 209 * Transmit IP/TCP/UDP checksum generation offload errors 210 * reported in Tx descriptor status. 211 * @xmlonly <defstofollow>7</defstofollow> REMOVE_ME @endxmlonly 212 */ 213 #define CEDI_TXD_CHKOFF_NO_ERROR (0) 214 215 #define CEDI_TXD_CHKOFF_VLAN_HDR_ERR (1) 216 217 #define CEDI_TXD_CHKOFF_SNAP_HDR_ERR (2) 218 219 #define CEDI_TXD_CHKOFF_INVALID_IP (3) 220 221 #define CEDI_TXD_CHKOFF_INVALID_PKT (4) 222 223 #define CEDI_TXD_CHKOFF_PKT_FRAGMENT (5) 224 225 #define CEDI_TXD_CHKOFF_NON_TCP_UDP (6) 226 227 #define CEDI_TXD_CHKOFF_PREM_END_PKT (7) 228 229 /** 230 * Bit-flags to control queueTxBuf/qTxBuf behaviour. 231 * @xmlonly <defstofollow>5</defstofollow> REMOVE_ME @endxmlonly 232 * Indicates last buffer in frame 233 */ 234 #define CEDI_TXB_LAST_BUFF (0x01) 235 236 /** EMAC will not calculate & insert frame CRC. */ 237 #define CEDI_TXB_NO_AUTO_CRC (0x02) 238 239 /** 240 * Prevents transmission being started automatically 241 * after queueing the last buffer in the frame; 242 * has no effect if CEDI_TXB_LAST_BUFF not also present. 243 */ 244 #define CEDI_TXB_NO_AUTO_START (0x04) 245 246 /** select TCP encapsulation for the current frame - must be set for first and second buffers in frame, ie header and first data buffers */ 247 #define CEDI_TXB_TCP_ENCAP (0x08) 248 249 /** select UFO fragmentation for the current frame - only relevant for first buffer in frame, which includes the header only; Ignored if CEDI_TXB_TCP_ENCAP is set. */ 250 #define CEDI_TXB_UDP_ENCAP (0x10) 251 252 /** 253 * select auto sequence-number generation, based on the current value of 254 * the EMAC sequence number counter for this stream 255 */ 256 #define CEDI_TXB_TSO_AUTO_SEQ (0x20) 257 258 /** Max length accepted by queueTxBuf */ 259 #define CEDI_TXD_LMASK ((1 << 14) - 1) 260 261 /** TCP flags (standard, some used to control RSC) @xmlonly <defstofollow>5</defstofollow> REMOVE_ME @endxmlonly */ 262 #define CEDI_TCP_FLG_FIN (0x0001) 263 264 #define CEDI_TCP_FLG_SYN (0x0002) 265 266 #define CEDI_TCP_FLG_RST (0x0004) 267 268 #define CEDI_TCP_FLG_PSH (0x0008) 269 270 #define CEDI_TCP_FLG_ACK (0x0010) 271 272 #define CEDI_TCP_FLG_URG (0x0020) 273 274 /** 275 * Bit-flags to control MDIO write/read operations. 276 * @xmlonly <defstofollow>2</defstofollow> REMOVE_ME @endxmlonly 277 */ 278 #define CEDI_MDIO_FLG_CLAUSE_45 (0x01) 279 280 #define CEDI_MDIO_FLG_SET_ADDR (0x02) 281 282 #define CEDI_MDIO_FLG_INC_ADDR (0x04) 283 284 /** 285 * PFC Priority based pause frame support: 286 * Maximum number of quantum priorities supported. 287 */ 288 #define CEDI_QUANTA_PRIORITY_MAX 8 289 290 /** 291 * @} 292 */ 293 294 #define CEDI_EVSET_ALL_Q0_EVENTS (CEDI_EV_TX_COMPLETE|CEDI_EV_TX_USED_READ| CEDI_EV_TX_UNDERRUN|CEDI_EV_TX_FR_CORRUPT| CEDI_EV_TX_RETRY_EX_LATE_COLL| CEDI_EV_RX_COMPLETE|CEDI_EV_RX_USED_READ|CEDI_EV_RX_OVERRUN|CEDI_EV_HRESP_NOT_OK| CEDI_EV_PCS_LP_PAGE_RX|CEDI_EV_PCS_AN_COMPLETE|CEDI_EV_PCS_LINK_CHANGE_DET| CEDI_EV_PAUSE_FRAME_TX|CEDI_EV_PAUSE_TIME_ZERO|CEDI_EV_PAUSE_NZ_QU_RX| CEDI_EV_PTP_TX_DLY_REQ|CEDI_EV_PTP_TX_SYNC|CEDI_EV_PTP_TX_PDLY_REQ| CEDI_EV_PTP_TX_PDLY_RSP|CEDI_EV_PTP_RX_DLY_REQ|CEDI_EV_PTP_RX_SYNC| CEDI_EV_PTP_RX_PDLY_REQ|CEDI_EV_PTP_RX_PDLY_RSP| CEDI_EV_TSU_SEC_INC|CEDI_EV_TSU_TIME_MATCH| CEDI_EV_MAN_FRAME|CEDI_EV_LPI_CH_RX|CEDI_EV_WOL_RX| CEDI_EV_EXT_INTR ) 295 296 #define CEDI_EVSET_ALL_QN_EVENTS (CEDI_EV_TX_COMPLETE| CEDI_EV_TX_RETRY_EX_LATE_COLL| CEDI_EV_TX_FR_CORRUPT|CEDI_EV_RX_COMPLETE| CEDI_EV_RX_USED_READ|CEDI_EV_HRESP_NOT_OK) 297 298 #define CEDI_EVSET_TX_RX_EVENTS (CEDI_EV_TX_COMPLETE|CEDI_EV_TX_USED_READ|CEDI_EV_TX_UNDERRUN| CEDI_EV_TX_RETRY_EX_LATE_COLL| CEDI_EV_TX_FR_CORRUPT|CEDI_EV_RX_COMPLETE| CEDI_EV_RX_USED_READ|CEDI_EV_RX_OVERRUN| CEDI_EV_HRESP_NOT_OK) 299 300 301 /** @defgroup DataStructure Dynamic Data Structures 302 * This section defines the data structures used by the driver to provide 303 * hardware information, modification and dynamic operation of the driver. 304 * These data structures are defined in the header file of the core driver 305 * and utilized by the API. 306 * @{ 307 */ 308 309 /********************************************************************** 310 * Forward declarations 311 **********************************************************************/ 312 struct CEDI_Config; 313 struct CEDI_SysReq; 314 struct CEDI_TxStatus; 315 struct CEDI_RxStatus; 316 struct CEDI_BuffAddr; 317 struct CEDI_TimeStampData; 318 struct CEDI_TxDescData; 319 struct CEDI_TxDescStat; 320 struct CEDI_RxDescData; 321 struct CEDI_RxDescStat; 322 struct CEDI_qTxBufParams; 323 struct CEDI_FrameSize; 324 struct CEDI_MacAddress; 325 struct CEDI_Statistics; 326 struct CEDI_NumScreeners; 327 struct CEDI_T1Screen; 328 struct CEDI_T2Screen; 329 struct CEDI_T2Compare; 330 struct CEDI_1588TimerVal; 331 struct CEDI_TsuTimerVal; 332 struct CEDI_TimerIncrement; 333 struct CEDI_AnAdvPage; 334 struct CEDI_defLpAbility; 335 struct CEDI_sgmLpAbility; 336 union CEDI_LpAbility; 337 struct CEDI_LpAbilityPage; 338 struct CEDI_AnNextPage; 339 struct CEDI_LpNextPage; 340 union CEDI_LpPage; 341 struct CEDI_LpPageRx; 342 struct CEDI_NetAnStatus; 343 struct CEDI_WakeOnLanReg; 344 struct CEDI_LpiStats; 345 struct CEDI_DesignCfg; 346 struct CEDI_Callbacks; 347 348 /********************************************************************** 349 * Enumerations 350 **********************************************************************/ 351 /** @defgroup DataStructure Dynamic Data Structures This section defines the data structures used by the driver to provide hardware information, modification, and dynamic operation of the driver. These data structures are defined in the header file of the core driver and utilized by the API. @{ */ 352 typedef enum 353 { 354 CEDI_DMA_BUS_WIDTH_32 = 0, 355 CEDI_DMA_BUS_WIDTH_64 = 1, 356 CEDI_DMA_BUS_WIDTH_128 = 2, 357 } CEDI_BusWidth; 358 359 typedef enum 360 { 361 CEDI_DMA_DBUR_LEN_1 = 0, 362 CEDI_DMA_DBUR_LEN_4 = 1, 363 CEDI_DMA_DBUR_LEN_8 = 2, 364 CEDI_DMA_DBUR_LEN_16 = 3, 365 } CEDI_DmaDatBLen; 366 367 typedef enum 368 { 369 CEDI_MDC_DIV_BY_8 = 0, 370 CEDI_MDC_DIV_BY_16 = 1, 371 CEDI_MDC_DIV_BY_32 = 2, 372 CEDI_MDC_DIV_BY_48 = 3, 373 CEDI_MDC_DIV_BY_64 = 4, 374 CEDI_MDC_DIV_BY_96 = 5, 375 CEDI_MDC_DIV_BY_128 = 6, 376 CEDI_MDC_DIV_BY_224 = 7, 377 } CEDI_MdcClkDiv; 378 379 typedef enum 380 { 381 CEDI_MDIO_DEV_PMD_PMA = 1, 382 CEDI_MDIO_DEV_WIS = 2, 383 CEDI_MDIO_DEV_PCS = 3, 384 CEDI_MDIO_DEV_PHY_XS = 4, 385 CEDI_MDIO_DEV_DTE_XS = 5, 386 } CEDI_MdioDevType; 387 388 typedef enum 389 { 390 CEDI_IFSP_10M_MII = 0, 391 CEDI_IFSP_100M_MII = 1, 392 CEDI_IFSP_1000M_GMII = 2, 393 CEDI_IFSP_10M_SGMII = 3, 394 CEDI_IFSP_100M_SGMII = 4, 395 CEDI_IFSP_1000M_SGMII = 5, 396 CEDI_IFSP_1000BASE_X = 6, 397 } CEDI_Interface; 398 399 typedef enum 400 { 401 CEDI_TX_TS_DISABLED = 0, 402 CEDI_TX_TS_PTP_EVENT_ONLY = 1, 403 CEDI_TX_TS_PTP_ALL = 2, 404 CEDI_TX_TS_ALL = 3, 405 } CEDI_TxTsMode; 406 407 typedef enum 408 { 409 CEDI_RX_TS_DISABLED = 0, 410 CEDI_RX_TS_PTP_EVENT_ONLY = 1, 411 CEDI_RX_TS_PTP_ALL = 2, 412 CEDI_RX_TS_ALL = 3, 413 } CEDI_RxTsMode; 414 415 /** Enum defining speed selection or indication */ 416 typedef enum 417 { 418 CEDI_SPEED_10M = 0, 419 CEDI_SPEED_100M = 1, 420 CEDI_SPEED_1000M = 2, 421 } CEDI_IfSpeed; 422 423 /** Enum defining Tx free descriptor call status */ 424 typedef enum 425 { 426 CEDI_TXDATA_1ST_NOT_LAST = 0, 427 CEDI_TXDATA_1ST_AND_LAST = 1, 428 CEDI_TXDATA_MID_BUFFER = 2, 429 CEDI_TXDATA_LAST_BUFFER = 3, 430 CEDI_TXDATA_NONE_FREED = 4, 431 } CEDI_TxFreeDStat; 432 433 /** Enum defining Rx data buffer read status */ 434 typedef enum 435 { 436 CEDI_RXDATA_SOF_EOF = 0, 437 CEDI_RXDATA_SOF_ONLY = 1, 438 CEDI_RXDATA_NO_FLAG = 2, 439 CEDI_RXDATA_EOF_ONLY = 3, 440 CEDI_RXDATA_NODATA = 4, 441 } CEDI_RxRdStat; 442 443 /** enum defining offset for screener type 2 compare values. Note the offset is applied after the specified point, e.g. T2COMP_OFF_ETYPE denotes the ethertype field, so an offset of 12 bytes from this would be the source IP address in an IP header. */ 444 typedef enum 445 { 446 CEDI_T2COMP_OFF_SOF = 0, 447 CEDI_T2COMP_OFF_ETYPE = 1, 448 CEDI_T2COMP_OFF_IPHDR = 2, 449 CEDI_T2COMP_OFF_TCPUDP = 3, 450 } CEDI_T2Offset; 451 452 /** enum defining pause capability in auto-negotiation */ 453 typedef enum 454 { 455 CEDI_AN_PAUSE_CAP_NONE = 0, 456 CEDI_AN_PAUSE_CAP_SYM = 1, 457 CEDI_AN_PAUSE_CAP_ASYM = 2, 458 CEDI_AN_PAUSE_CAP_BOTH = 3, 459 } CEDI_PauseCap; 460 461 /** enum defining loopback mode selection */ 462 typedef enum 463 { 464 CEDI_NO_LOOPBACK = 0, 465 CEDI_LOCAL_LOOPBACK = 1, 466 CEDI_SERDES_LOOPBACK = 2, 467 } CEDI_LoopbackMode; 468 469 /** enum defining remote fault indication by link partner in auto-negotiation */ 470 typedef enum 471 { 472 CEDI_AN_REM_FLT_NONE = 0, 473 CEDI_AN_REM_FLT_LNK_FAIL = 1, 474 CEDI_AN_REM_FLT_OFFLINE = 2, 475 CEDI_AN_REM_FLT_AN_ERR = 3, 476 } CEDI_RemoteFault; 477 478 /********************************************************************** 479 * Callbacks 480 **********************************************************************/ 481 /** 482 * Reports PHY Management frame tx complete. 483 * Params: read = 1 if a read operation, = 0 if a write operation, and 484 * readData - data from the PHY, if read operation. 485 */ 486 typedef void (*CEDI_CbPhyManComplete)(void* pD, uint8_t read, uint16_t readData); 487 488 /** 489 * Reports Tx completed / Tx used bit read events. 490 * Params: event - indicates two types of event, which are OR'd together if both 491 * occurred (CEDI_EV_TX_COMPLETE: frame has been transmitted successfully, 492 * and CEDI_EV_TX_USED_READ: used bit set has been read in Tx descriptor list), 493 * and queueNum- the priority queue number (only relevant to TX_COMPLETE) 494 * range 0 to txQs-1. 495 */ 496 typedef void (*CEDI_CbTxEvent)(void* pD, uint32_t event, uint8_t queueNum); 497 498 /** 499 * Reports Tx errors. Params: error - indicates one or more of three 500 * possible events, OR'd together (CEDI_EV_TX_UNDERRUN: Tx underrun, 501 * CEDI_EV_TX_RETRY_EX_LATE_COLL: retry limit exceeded or late collision, 502 * CEDI_EV_TX_FR_CORRUPT: Tx frame corruption), and queueNum - the priority 503 * queue number, range 0 to txQs-1 (not relevant to TX_UNDERRUN). 504 */ 505 typedef void (*CEDI_CbTxError)(void* pD, uint32_t error, uint8_t queueNum); 506 507 /** 508 * Reports Frame Rx completed successfully. Param: queueNum - the priority 509 * queue number, range 0 to rxQs-1. 510 */ 511 typedef void (*CEDI_CbRxFrame)(void* pD, uint8_t queueNum); 512 513 /** 514 * Reports Rx errors. Params: error - one or more of two possible errors, 515 * together (CEDI_EV_RX_USED_READ: used bit set has been read in Rx descriptor 516 * list; CEDI_EV_RX_OVERRUN: Rx overrun error), 517 * and queueNum - the priority queue number, range 0 to rxQs-1. 518 */ 519 typedef void (*CEDI_CbRxError)(void* pD, uint32_t error, uint8_t queueNum); 520 521 /** 522 * Reports Hresp not OK error. Param: queueNum - number of the Tx or Rx 523 * queue being accessed (range 0 to rxQs-1). 524 */ 525 typedef void (*CEDI_CbHrespError)(void* pD, uint8_t queueNum); 526 527 /** 528 * Reports PCS auto-negotiation page received. Param: pageRx - pointer to a 529 * struct containing the link partner base or next page data. 530 */ 531 typedef void (*CEDI_CbLpPageRx)(void* pD, struct CEDI_LpPageRx* pageRx); 532 533 /** 534 * Reports PCS auto-negotiation completed. Param: netStat - pointer to a 535 * struct with the network resolution status. 536 */ 537 typedef void (*CEDI_CbAnComplete)(void* pD, struct CEDI_NetAnStatus* netStat); 538 539 /** 540 * Reports Link Status Changed. Param: linkState - link status: if 541 * auto-negotiation enabled, when =1 link is up, else link is down; 542 * if auto-negotiation not enabled, this will indicate the synchronisation 543 * status. If link status has gone down, the value will not return to 1 544 * until after it has been read, therefore to see current state must 545 * re-read with a getLinkStatus call. 546 */ 547 typedef void (*CEDI_CbLinkChange)(void* pD, uint8_t linkState); 548 549 /** 550 * Reports TSU Event occurred. Param: event - indicates one of two events, 551 * OR'd together (CEDI_EV_TSU_SEC_INC: TSU seconds register increment; 552 * CEDI_EV_TSU_TIME_MATCH: TSU timer count match). 553 */ 554 typedef void (*CEDI_CbTsuEvent)(void* pD, uint32_t event); 555 556 /** 557 * Reports Pause Event occurred. Param: event - indicates one or more of 558 * three event types, OR'd together (CEDI_EV_PAUSE_FRAME_TX: Pause frame 559 * transmitted; CEDI_EV_PAUSE_TIME_ZERO: Pause time zero; 560 * CEDI_EV_PAUSE_NZ_QU_RX: Pause frame with non-zero quantum received). 561 */ 562 typedef void (*CEDI_CbPauseEvent)(void* pD, uint32_t event); 563 564 /** 565 * Reports PTP Primary Frame transmitted. Params: type - indicates 566 * one of two frame types, OR'd together (CEDI_EV_PTP_TX_DLY_REQ: 567 * delay_req; CEDI_EV_PTP_TX_SYNC: sync) 568 * , and time: pointer to 569 * a struct containing the time latched when the frame was 570 * transmitted. This is not set if IP config param tsu=0. 571 */ 572 typedef void (*CEDI_CbPtpPriFrameTx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time); 573 574 /** 575 * Reports PTP Peer Frame transmitted. Params: type - indicates 576 * one of two frame types, OR'd together (CEDI_EV_PTP_TX_PDLY_REQ: 577 * pdelay_req; CEDI_EV_PTP_TX_PDLY_RSP: pdelay_rsp) 578 * , and time: pointer to 579 * a struct containing the time latched when the frame was 580 * transmitted. This is not set if IP config param tsu=0. 581 */ 582 typedef void (*CEDI_CbPtpPeerFrameTx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time); 583 584 /** 585 * Reports PTP Primary Frame received. Params: type - indicates 586 * one of two frame types, OR'd together (CEDI_EV_PTP_RX_DLY_REQ: 587 * delay_req; CEDI_EV_PTP_RX_SYNC: sync) 588 * , and time: pointer to 589 * a struct containing the time latched when the frame was 590 * received. This is not set if IP config param tsu=0. 591 */ 592 typedef void (*CEDI_CbPtpPriFrameRx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time); 593 594 /** 595 * Reports PTP Peer Frame received. Params: type - indicates 596 * one of two frame types, OR'd together (CEDI_EV_PTP_RX_PDLY_REQ: 597 * pdelay_req; CEDI_EV_PTP_RX_PDLY_RSP: pdelay_rsp) 598 * , and time: pointer to 599 * a struct containing the time latched when the frame was 600 * received. This is not set if IP config param tsu=0. 601 */ 602 typedef void (*CEDI_CbPtpPeerFrameRx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time); 603 604 /** Reports LPI Status changed. */ 605 typedef void (*CEDI_CbLpiStatus)(void* pD); 606 607 /** Reports Wake On LAN event received. */ 608 typedef void (*CEDI_CbWolEvent)(void* pD); 609 610 /** Reports External input interrupt occurred. */ 611 typedef void (*CEDI_CbExtInpIntr)(void* pD); 612 613 /********************************************************************** 614 * Structures and unions 615 **********************************************************************/ 616 /** 617 * Configuration parameters passed to probe & init. 618 * Note that only the first eight fields are required for the probe call; 619 * all are required by init 620 */ 621 typedef struct CEDI_Config 622 { 623 /** base address of EMAC registers */ 624 uintptr_t regBase; 625 /** 626 * number of Rx priority queues, up to 1 more than 627 * highest defined dma_priority_queueN value 628 * (for example, =4 if highest is dma_priority_queue3) 629 */ 630 uint8_t rxQs; 631 /** number of Tx priority queues, same limit as for rxQs */ 632 uint8_t txQs; 633 /** 634 * number of descriptors in each Tx 635 * descriptor queue 636 */ 637 uint16_t txQLen[16]; 638 /** 639 * number of descriptors in each Rx 640 * descriptor queue 641 */ 642 uint16_t rxQLen[16]; 643 /** DMA address bus width. 0=32b , 1=64b */ 644 uint8_t dmaAddrBusWidth; 645 /** enable Tx extended BD mode */ 646 uint8_t enTxExtBD; 647 /** enable Rx extended BD mode */ 648 uint8_t enRxExtBD; 649 /** 650 * sets endian swap for data buffers and descriptors 651 * accesses: OR'd combination of CEDI_END_SWAP_DESC 652 * and CEDI_END_SWAP_DATA 653 */ 654 uint8_t dmaEndianism; 655 /** DMA bus width: 32, 64 or 128 bits */ 656 CEDI_BusWidth dmaBusWidth; 657 /** 658 * events to enable on start, OR together bit-flags 659 * defined in Interrupt control 660 */ 661 uint32_t intrEnable; 662 /** 663 * Upper 32 bits of physical address of Tx descriptor queues. 664 * Used only if DMA configured for 64-bit addressing. 665 * This is the single upper address used for Tx & Rx descriptors by older 666 * MAC h/w, in GEM_GXL before r1p06f2, and XGM_GXL up to r1p01 667 */ 668 uint32_t upper32BuffTxQAddr; 669 /** 670 * Upper 32 bits of physical address of Rx descriptor queues. 671 * Used only if DMA configured for 64-bit addressing 672 */ 673 uint32_t upper32BuffRxQAddr; 674 /** 675 * start address of Tx descriptor queues (contiguous 676 * block for all queues) 677 */ 678 uintptr_t txQAddr; 679 /** physical address of Tx descriptor queues */ 680 uint32_t txQPhyAddr; 681 /** 682 * start address of Rx descriptor queues (contiguous 683 * block for all queues) 684 */ 685 uintptr_t rxQAddr; 686 /** physical address of Rx descriptor queues */ 687 uint32_t rxQPhyAddr; 688 /** 689 * length of rx buffers, as a multiple of 64 bytes, 690 * e.g. 2 = 128 bytes 691 */ 692 uint8_t rxBufLength[16]; 693 /** transmit packet buffer size select */ 694 uint8_t txPktBufSize; 695 /** receive packet buffer size select */ 696 uint8_t rxPktBufSize; 697 /** fixed burst length for DMA data transfers */ 698 CEDI_DmaDatBLen dmaDataBurstLen; 699 /** 700 * DMA config register bits 24, 25 & 26. 701 * OR the following bit-flags to set corresponding bits - 702 * CEDI_CFG_DMA_DISC_RXP, 703 * CEDI_CFG_DMA_FRCE_RX_BRST, 704 * CEDI_CFG_DMA_FRCE_TX_BRST 705 */ 706 uint8_t dmaCfgFlags; 707 /** 708 * set to 1 to initialise with MDIO enabled, or 0 to 709 * disable 710 */ 711 uint8_t enableMdio; 712 /** divisor to generate MDC from pclk */ 713 CEDI_MdcClkDiv mdcPclkDiv; 714 /** MII/GMII/SGMII and speed selection */ 715 CEDI_Interface ifTypeSel; 716 /** 717 * enable alternative SGMII mode (auto-negotiation 718 * ACK driven differently) 719 */ 720 uint8_t altSgmiiEn; 721 /** full/half duplex operation */ 722 uint8_t fullDuplex; 723 /** enable Rx in half-duplex while Tx */ 724 uint8_t enRxHalfDupTx; 725 /** enable external address match interface */ 726 uint8_t extAddrMatch; 727 /** start-of-frame offset for writing Rx data (0 to 3 bytes) */ 728 uint8_t rxBufOffset; 729 /** enable discard of frames with length field error */ 730 uint8_t rxLenErrDisc; 731 /** disable copying Rx pause frames to memory */ 732 uint8_t disCopyPause; 733 /** enable uni-direction Tx operation */ 734 uint8_t uniDirEnable; 735 /** 736 * enable checksum offload operation - OR bit-flags 737 * to enable in Tx and/or Rx: 738 * CEDI_CFG_CHK_OFF_TX, CEDI_CFG_CHK_OFF_RX 739 */ 740 uint8_t chkSumOffEn; 741 /** enable Rx of frames up to 1536 bytes */ 742 uint8_t rx1536ByteEn; 743 /** enable Rx of jumbo frames */ 744 uint8_t rxJumboFrEn; 745 /** enable Rx frames with non-standard preamble */ 746 uint8_t enRxBadPreamble; 747 /** ignore IPG rx_er (NetCfg b30) */ 748 uint8_t ignoreIpgRxEr; 749 /** 750 * replace CRC upper 16 bits with offset to UDP/TCP 751 * header for Rx frames 752 */ 753 uint8_t storeUdpTcpOffset; 754 /** enable external TSU timer port */ 755 uint8_t enExtTsuPort; 756 /** 757 * Maximum number of outstanding AXI write requests, 758 * that can be issued by DMA via the AW channel. 759 * Must not be = 0 if using AXI as this would disable writes 760 */ 761 uint8_t aw2wMaxPipeline; 762 /** 763 * Maximum number of outstanding AXI read requests, 764 * that can be issued by DMA via the AR channel. 765 * Must not be = 0 if using AXI as this would disable reads 766 */ 767 uint8_t ar2rMaxPipeline; 768 /** enable pfc multiple quantum (8 different priorities) */ 769 uint8_t pfcMultiQuantum; 770 /** 771 * address of CEDI_Statistics struct for driver to fill out: ignored if 772 * no_stats = 1 773 */ 774 uintptr_t statsRegs; 775 } CEDI_Config; 776 777 /** System requirements returned by probe */ 778 typedef struct CEDI_SysReq 779 { 780 /** size of memory required for driver's private data */ 781 uint32_t privDataSize; 782 /** size of contiguous block of Tx descriptor lists */ 783 uint32_t txDescListSize; 784 /** size of contiguous block of Rx descriptor lists */ 785 uint32_t rxDescListSize; 786 /** 787 * size of memory for storing statistics register contents: 788 * returned as 0 if no_stats was set to 1 789 */ 790 uint32_t statsSize; 791 } CEDI_SysReq; 792 793 /** struct for returning contents of the Tx Status register */ 794 typedef struct CEDI_TxStatus 795 { 796 uint8_t usedBitRead; 797 uint8_t collisionOcc; 798 uint8_t retryLimExc; 799 uint8_t txActive; 800 uint8_t txFrameErr; 801 uint8_t txComplete; 802 uint8_t txUnderRun; 803 uint8_t lateCollision; 804 uint8_t hRespNotOk; 805 } CEDI_TxStatus; 806 807 /** Bit-field struct for returning contents of the Rx Status register */ 808 typedef struct CEDI_RxStatus 809 { 810 uint8_t buffNotAvail; 811 uint8_t frameRx; 812 uint8_t rxOverrun; 813 uint8_t hRespNotOk; 814 } CEDI_RxStatus; 815 816 /** Struct for virtual & physical addresses of DMA-addressable data buffer */ 817 typedef struct CEDI_BuffAddr 818 { 819 uintptr_t vAddr; 820 uintptr_t pAddr; 821 } CEDI_BuffAddr; 822 823 /** Struct describing time stamp data allocated in descriptor */ 824 typedef struct CEDI_TimeStampData 825 { 826 /** TS valid - set to 1 if valid data stored */ 827 uint8_t tsValid; 828 /** Timestamp nanoseconds[29:0] - word2/4[29:0] */ 829 uint32_t tsNanoSec; 830 /** Timestamp seconds[1:0] from word2/4[31:30], seconds[5:2]from word3/5[5:2] */ 831 uint32_t tsSecs; 832 } CEDI_TimeStampData; 833 834 /** struct for returning tx descriptor data */ 835 typedef struct CEDI_TxDescData 836 { 837 /** physical & virtual addresses of buffer freed up */ 838 struct CEDI_BuffAddr bufAdd; 839 /** Tx descriptor status word - only valid if first buffer of frame */ 840 uint32_t txDescStat; 841 /** descriptor queue status, see freeTxDesc for description */ 842 uint8_t status; 843 /** Tx descriptor timestamp when valid (txTsData.tsValid will be set to 1) */ 844 struct CEDI_TimeStampData txTsData; 845 } CEDI_TxDescData; 846 847 /** struct for returning tx descriptor status fields */ 848 typedef struct CEDI_TxDescStat 849 { 850 /** IP/TCP/UDP checksum offload errors - see CEDI_TXD_CHKOFF_ constants */ 851 uint8_t chkOffErr; 852 /** late collision Tx error detected */ 853 uint8_t lateColl; 854 /** DMA frame corruption */ 855 uint8_t frameCorr; 856 /** Tx Underrun error detected */ 857 uint8_t txUnderrun; 858 /** Tx error, retries limit exceeded */ 859 uint8_t retryExc; 860 } CEDI_TxDescStat; 861 862 /** struct for returning rx descriptor data */ 863 typedef struct CEDI_RxDescData 864 { 865 /** Rx descriptor status word */ 866 uint32_t rxDescStat; 867 /** Rx data status, see readRxBuf for description */ 868 uint8_t status; 869 /** Rx descriptor timestamp when valid (rxTsData.tsValid will be set to 1) */ 870 struct CEDI_TimeStampData rxTsData; 871 } CEDI_RxDescData; 872 873 /** struct for rx descriptor status fields */ 874 typedef struct CEDI_RxDescStat 875 { 876 /** valid when eoh (length of header) or eof (total frame length) - includes b13 if not ignore fcs enabled */ 877 uint16_t bufLen; 878 /** ignore if jumbo frames enabled */ 879 uint8_t fcsStatus; 880 /** Start Of Frame in this buffer */ 881 uint8_t sof; 882 /** End Of Frame in this buffer */ 883 uint8_t eof; 884 /** Header-data split: header buffer */ 885 uint8_t header; 886 /** Header-data split: End Of Header in this buffer */ 887 uint8_t eoh; 888 /** Canonical Format Indicator */ 889 uint8_t cfi; 890 /** VLAN Priority */ 891 uint8_t vlanPri; 892 /** Priority tag detected */ 893 uint8_t priTagDet; 894 /** VLAN tag detected */ 895 uint8_t vlanTagDet; 896 /** only set if rx chksum offload disabled */ 897 uint8_t typeIdMatch; 898 /** Type ID match register if typeIdMatch set (RegNumber-1, i.e. 0 => reg. 1 ) */ 899 uint8_t typeMatchReg; 900 /** ignore if rx chksum offload disabled */ 901 uint8_t snapNoVlanCfi; 902 /** chksum offload checking status */ 903 uint8_t chkOffStat; 904 /** 905 * specific address register match (b27 OR b28) 906 * If packet buffer mode and extra specific address 907 * registers are used, this indicates match in 908 * one of the first eight registers 909 */ 910 uint8_t specAddMatch; 911 /** 912 * specific addr match register if specAddMatch set 913 * (RegNumber-1, i.e. 0 => reg. 1 ) 914 */ 915 uint8_t specAddReg; 916 /** external address match */ 917 uint8_t extAddrMatch; 918 /** unicast hash match */ 919 uint8_t uniHashMatch; 920 /** multicast hash match */ 921 uint8_t multiHashMatch; 922 /** all-1's broadcast address detected */ 923 uint8_t broadcast; 924 } CEDI_RxDescStat; 925 926 /** parameters for qTxBuf function */ 927 typedef struct CEDI_qTxBufParams 928 { 929 /** number of Tx queue */ 930 uint8_t queueNum; 931 /** pointer to struct containing physical & virtual addresses of buffer - virtual field is for upper layer use only, can contain other reference/status if required */ 932 struct CEDI_BuffAddr* bufAdd; 933 /** length of data in buffer */ 934 uint32_t length; 935 /** bit-flags (CEDI_TXB_xx) specifying last buffer/auto CRC and LSO controls */ 936 uint8_t flags; 937 /** Segment/fragment size (MSS for TCP or MFS for UDP) - used for all data descriptors */ 938 uint16_t mssMfs; 939 /** TCP Stream number, determines which auto-sequence counter to use - only for first (header) descriptor used when flags includes CEDI_TXB_TSO_AUTO_SEQ and CEDI_TXB_TCP_ENCAP */ 940 uint8_t tcpStream; 941 } CEDI_qTxBufParams; 942 943 /** Q buffer sizes */ 944 typedef struct CEDI_FrameSize 945 { 946 /** array of sizes per queue */ 947 uint32_t FrameSize[16]; 948 } CEDI_FrameSize; 949 950 /** struct for MAC address */ 951 typedef struct CEDI_MacAddress 952 { 953 uint8_t byte[6]; 954 } CEDI_MacAddress; 955 956 /** struct containing all statistics register values (144 bytes long) */ 957 typedef struct CEDI_Statistics 958 { 959 /** b31:0 of octets transmitted */ 960 uint32_t octetsTxLo; 961 /** b47:32 of octets transmitted */ 962 uint16_t octetsTxHi; 963 uint32_t framesTx; 964 uint32_t broadcastTx; 965 uint32_t multicastTx; 966 uint16_t pauseFrTx; 967 uint32_t fr64byteTx; 968 uint32_t fr65_127byteTx; 969 uint32_t fr128_255byteTx; 970 uint32_t fr256_511byteTx; 971 uint32_t fr512_1023byteTx; 972 uint32_t fr1024_1518byteTx; 973 uint32_t fr1519_byteTx; 974 uint16_t underrunFrTx; 975 uint32_t singleCollFrTx; 976 uint32_t multiCollFrTx; 977 uint16_t excessCollFrTx; 978 uint16_t lateCollFrTx; 979 uint32_t deferredFrTx; 980 uint16_t carrSensErrsTx; 981 /** b31:0 of octets received */ 982 uint32_t octetsRxLo; 983 /** b47:32 of octets received */ 984 uint16_t octetsRxHi; 985 uint32_t framesRx; 986 uint32_t broadcastRx; 987 uint32_t multicastRx; 988 uint16_t pauseFrRx; 989 uint32_t fr64byteRx; 990 uint32_t fr65_127byteRx; 991 uint32_t fr128_255byteRx; 992 uint32_t fr256_511byteRx; 993 uint32_t fr512_1023byteRx; 994 uint32_t fr1024_1518byteRx; 995 uint32_t fr1519_byteRx; 996 uint16_t undersizeFrRx; 997 uint16_t oversizeFrRx; 998 uint16_t jabbersRx; 999 uint16_t fcsErrorsRx; 1000 uint16_t lenChkErrRx; 1001 uint16_t rxSymbolErrs; 1002 uint16_t alignErrsRx; 1003 uint32_t rxResourcErrs; 1004 uint16_t overrunFrRx; 1005 uint16_t ipChksumErrs; 1006 uint16_t tcpChksumErrs; 1007 uint16_t udpChksumErrs; 1008 uint16_t dmaRxPBufFlush; 1009 } CEDI_Statistics; 1010 1011 /** struct for returning number of screening registers */ 1012 typedef struct CEDI_NumScreeners 1013 { 1014 /** number of Type1 screener registers */ 1015 uint8_t type1ScrRegs; 1016 /** number of Type2 screener registers */ 1017 uint8_t type2ScrRegs; 1018 /** number of ethtype registers */ 1019 uint8_t ethtypeRegs; 1020 /** number of compare registers */ 1021 uint8_t compareRegs; 1022 } CEDI_NumScreeners; 1023 1024 /** struct for writing/reading Type1 screening registers */ 1025 typedef struct CEDI_T1Screen 1026 { 1027 /** the priority queue allocated if match found, */ 1028 uint8_t qNum; 1029 /** if =1, enable UDP port matching */ 1030 uint8_t udpEnable; 1031 /** UDP port number to match if udpEnable=1 (ignored otherwise) */ 1032 uint16_t udpPort; 1033 /** if =1, enable DS/TC field matching */ 1034 uint8_t dstcEnable; 1035 /** DS field (IPv4) or TC field (IPv6) value to match against */ 1036 uint8_t dstcMatch; 1037 } CEDI_T1Screen; 1038 1039 /** struct for writing/reading Type2 screening registers */ 1040 typedef struct CEDI_T2Screen 1041 { 1042 /** the priority queue allocated if match found, */ 1043 uint8_t qNum; 1044 /** if =1, enable VLAN priority matching */ 1045 uint8_t vlanEnable; 1046 /** VLAN priority to match if vlanEnable=1 (ignored otherwise) */ 1047 uint8_t vlanPriority; 1048 /** if =1, enable EtherType field matching */ 1049 uint8_t eTypeEnable; 1050 /** Index of EtherType match register: when supported up to: CEDI_DesignCfg.num_scr2_ethtype_regs */ 1051 uint8_t ethTypeIndex; 1052 /** if =1, enable compare A matching */ 1053 uint8_t compAEnable; 1054 /** Index of compare register for compare A match. When supported up to: CEDI_DesignCfg.num_scr2_compare_regs */ 1055 uint8_t compAIndex; 1056 /** if =1, enable compare B matching */ 1057 uint8_t compBEnable; 1058 /** Index of compare register for compare B match. When supported up to: CEDI_DesignCfg.num_scr2_compare_regs */ 1059 uint8_t compBIndex; 1060 /** if =1, enable compare C matching */ 1061 uint8_t compCEnable; 1062 /** Index of compare register for compare C match. When supported up to: CEDI_DesignCfg.num_scr2_compare_regs */ 1063 uint8_t compCIndex; 1064 } CEDI_T2Screen; 1065 1066 /** struct for writing/reading screener Type 2 compare registers */ 1067 typedef struct CEDI_T2Compare 1068 { 1069 /** Mask Value field (or 1st 16 bits of compare when disableMask set) */ 1070 uint16_t compMask; 1071 /** Compare Value field (or 2nd 16 bits of compare when disableMask set) */ 1072 uint16_t compValue; 1073 /** Offset value */ 1074 uint8_t offsetVal; 1075 /** Position in frame to apply offset */ 1076 CEDI_T2Offset offsetPosition; 1077 /** Disable mask value function, to extend compare value to 4 bytes. Set to 1 to disable mask. */ 1078 uint8_t disableMask; 1079 } CEDI_T2Compare; 1080 1081 /** struct for writing/reading 1588 timer */ 1082 typedef struct CEDI_1588TimerVal 1083 { 1084 /** Upper 16 bits of seconds value */ 1085 uint16_t secsUpper; 1086 /** Lower 32 bits of seconds value */ 1087 uint32_t secsLower; 1088 /** Nanoseconds value (30 bits) */ 1089 uint32_t nanosecs; 1090 } CEDI_1588TimerVal; 1091 1092 /** struct for writing/reading TSU timer */ 1093 typedef struct CEDI_TsuTimerVal 1094 { 1095 /** Upper 16 bits of seconds value */ 1096 uint16_t secsUpper; 1097 /** Lower 32 bits of seconds value */ 1098 uint32_t secsLower; 1099 /** Upper 22 bits of nanoseconds value */ 1100 uint32_t nanosecs; 1101 } CEDI_TsuTimerVal; 1102 1103 /** struct for writing/reading the 1588 timer increment registers */ 1104 typedef struct CEDI_TimerIncrement 1105 { 1106 /** Whole nanoseconds to increment timer each clock cycle */ 1107 uint8_t nanoSecsInc; 1108 /** Sub-nanoseconds to increment the timer (16 bits) */ 1109 uint16_t subNsInc; 1110 /** Lower 8 bits of sub-nanoseconds to increment the timer */ 1111 uint8_t lsbSubNsInc; 1112 /** Number of increments before changing to alternative increment. If = 0 then never use alternative increment. */ 1113 uint8_t altIncCount; 1114 /** Alternative nanoseconds increment to apply */ 1115 uint8_t altNanoSInc; 1116 } CEDI_TimerIncrement; 1117 1118 /** 1119 * struct for returning contents of the auto-negotiation advertisement 1120 * register 1121 */ 1122 typedef struct CEDI_AnAdvPage 1123 { 1124 /** full duplex capability */ 1125 uint8_t fullDuplex; 1126 /** half duplex capability */ 1127 uint8_t halfDuplex; 1128 /** pause capability */ 1129 CEDI_PauseCap pauseCap; 1130 /** remote fault condition */ 1131 CEDI_RemoteFault remFlt; 1132 /** next page exchange required */ 1133 uint8_t nextPage; 1134 } CEDI_AnAdvPage; 1135 1136 /** struct for default (non-SGMII) auto-negotiation link partner abilities */ 1137 typedef struct CEDI_defLpAbility 1138 { 1139 /** full duplex capability */ 1140 uint8_t fullDuplex; 1141 /** half duplex capability */ 1142 uint8_t halfDuplex; 1143 /** pause capability */ 1144 CEDI_PauseCap pauseCap; 1145 /** remote fault condition */ 1146 CEDI_RemoteFault remFlt; 1147 /** link partner acknowledge indication */ 1148 uint8_t lpAck; 1149 /** next page exchange required */ 1150 uint8_t lpNextPage; 1151 } CEDI_defLpAbility; 1152 1153 /** struct for SGMII mode auto-negotiation link partner abilities */ 1154 typedef struct CEDI_sgmLpAbility 1155 { 1156 /** speed, = 10/100/1000Mbps */ 1157 CEDI_IfSpeed speed; 1158 /** 1159 * duplex capability, = 0 for half duplex, 1160 * =1 for full duplex 1161 */ 1162 uint8_t duplex; 1163 /** link partner acknowledge indication */ 1164 uint8_t lpAck; 1165 /** =0 if link down, =1 if link up */ 1166 uint8_t linkStatus; 1167 } CEDI_sgmLpAbility; 1168 1169 /** 1170 * union of two possible link partner ability structs, 1171 * one for default configuration and one for SGMII configuration 1172 */ 1173 typedef union CEDI_LpAbility 1174 { 1175 struct CEDI_defLpAbility defLpAbl; 1176 struct CEDI_sgmLpAbility sgmLpAbl; 1177 } CEDI_LpAbility; 1178 1179 /** Struct for link partner ability page info. If sgmii =0 then read default ability page struct from ablInfo. If sgmii =1 then read SGMII mode ability page struct from ablInfo. */ 1180 typedef struct CEDI_LpAbilityPage 1181 { 1182 union CEDI_LpAbility ablInfo; 1183 uint8_t sgmii; 1184 } CEDI_LpAbilityPage; 1185 1186 /** Struct for auto-negotiation next page register data */ 1187 typedef struct CEDI_AnNextPage 1188 { 1189 /** message data as defined by message page indicator (11 bits) */ 1190 uint16_t message; 1191 /** acknowledge 2 */ 1192 uint8_t ack2; 1193 /** message page indicator */ 1194 uint8_t msgPage; 1195 /** set if another next page to transmit */ 1196 uint8_t np; 1197 } CEDI_AnNextPage; 1198 1199 /** struct for auto-negotiation link partner next page data */ 1200 typedef struct CEDI_LpNextPage 1201 { 1202 /** message data as defined by message page indicator (11 bits) */ 1203 uint16_t message; 1204 /** toggles for each received page */ 1205 uint8_t toggle; 1206 /** acknowledge 2 */ 1207 uint8_t ack2; 1208 /** message page indicator */ 1209 uint8_t msgPage; 1210 /** 1211 * indicates if link partner successfully 1212 * received last message 1213 */ 1214 uint8_t ack; 1215 /** set if another next page to transmit */ 1216 uint8_t np; 1217 } CEDI_LpNextPage; 1218 1219 /** union for link partner page data - ability page or next page */ 1220 typedef union CEDI_LpPage 1221 { 1222 struct CEDI_LpAbilityPage lpBasePage; 1223 struct CEDI_LpNextPage lpNextPage; 1224 } CEDI_LpPage; 1225 1226 /** Struct for returning page data from link partner. If nextPage = 0 then read link partner base page from lpPage.lpBasePage, else read next page from lpPage.lpNextPage */ 1227 typedef struct CEDI_LpPageRx 1228 { 1229 union CEDI_LpPage lpPageDat; 1230 uint8_t nextPage; 1231 } CEDI_LpPageRx; 1232 1233 /** Struct for returning network status related to auto-negotiation */ 1234 typedef struct CEDI_NetAnStatus 1235 { 1236 /** 1237 * if auto-negotiation enabled: = 1 if LINK up, 1238 * = 0 if LINK down 1239 * else synchronisation status 1240 */ 1241 uint8_t linkState; 1242 /** if = 1 then both devices full duplex */ 1243 uint8_t duplexRes; 1244 /** enable pause Tx */ 1245 uint8_t pauseTxRes; 1246 /** enable pause Rx */ 1247 uint8_t pauseRxRes; 1248 } CEDI_NetAnStatus; 1249 1250 /** Struct for writing/reading the Wake On LAN register */ 1251 typedef struct CEDI_WakeOnLanReg 1252 { 1253 /** Least significant 16 bits of target IP address to match */ 1254 uint16_t wolReqAddr; 1255 /** Magic packet events cause WOL assert (equal 1 means enabled) */ 1256 uint8_t magPktEn; 1257 /** ARP request events cause WOL assert (equal 1 means enabled) */ 1258 uint8_t arpEn; 1259 /** Specific address 1 events cause WOL assert (equal 1 means enabled) */ 1260 uint8_t specAd1En; 1261 /** Multicast hash events cause WOL assert (equal 1 means enabled) */ 1262 uint8_t multiHashEn; 1263 } CEDI_WakeOnLanReg; 1264 1265 /** Struct for returning the LPI Tx and Rx statistics */ 1266 typedef struct CEDI_LpiStats 1267 { 1268 /** Number of transitions to Rx low power idle */ 1269 uint16_t rxLpiTrans; 1270 /** Counts time in Rx LPI indication */ 1271 uint32_t rxLpiTime; 1272 /** Number of transitions to LPI Tx enable */ 1273 uint16_t txLpiTrans; 1274 /** Counts time in LPI Tx enable */ 1275 uint32_t txLpiTime; 1276 } CEDI_LpiStats; 1277 1278 /** Struct containing all design configuration fields, plus some other features which are revision-dependent, e.g. intrp_mod */ 1279 typedef struct CEDI_DesignCfg 1280 { 1281 uint16_t moduleId; 1282 uint16_t moduleRev; 1283 uint8_t fixNumber; 1284 uint8_t numQueues; 1285 uint8_t no_pcs; 1286 uint8_t serdes; 1287 uint8_t RDC_50; 1288 uint8_t TDC_50; 1289 uint8_t int_loopback; 1290 uint8_t no_int_loopback; 1291 uint8_t ext_fifo_interface; 1292 uint8_t apb_rev1; 1293 uint8_t apb_rev2; 1294 uint8_t user_io; 1295 uint8_t user_out_width; 1296 uint8_t user_in_width; 1297 uint8_t no_scan_pins; 1298 uint8_t no_stats; 1299 uint8_t no_snapshot; 1300 uint8_t irq_read_clear; 1301 uint8_t exclude_cbs; 1302 uint8_t num_spec_add_filters; 1303 uint8_t dma_bus_width; 1304 uint8_t axi_cache_value; 1305 uint16_t jumbo_max_length; 1306 uint8_t hprot_value; 1307 uint8_t rx_pkt_buffer; 1308 uint8_t tx_pkt_buffer; 1309 uint8_t rx_pbuf_addr; 1310 uint8_t tx_pbuf_addr; 1311 uint8_t axi; 1312 uint8_t rx_fifo_cnt_width; 1313 uint8_t tx_fifo_cnt_width; 1314 uint8_t tsu; 1315 uint8_t phy_ident; 1316 uint8_t dma_bus_width_def; 1317 uint8_t mdc_clock_div; 1318 uint8_t endian_swap_def; 1319 uint8_t rx_pbuf_size_def; 1320 uint8_t tx_pbuf_size_def; 1321 uint8_t rx_buffer_length_def; 1322 uint8_t tsu_clk; 1323 uint8_t axi_prot_value; 1324 uint8_t tx_pbuf_queue_segment_size; 1325 uint8_t ext_tsu_timer; 1326 uint8_t tx_add_fifo_if; 1327 uint8_t host_if_soft_select; 1328 uint8_t tx_pbuf_num_segments_q0; 1329 uint8_t tx_pbuf_num_segments_q1; 1330 uint8_t tx_pbuf_num_segments_q2; 1331 uint8_t tx_pbuf_num_segments_q3; 1332 uint8_t tx_pbuf_num_segments_q4; 1333 uint8_t tx_pbuf_num_segments_q5; 1334 uint8_t tx_pbuf_num_segments_q6; 1335 uint8_t tx_pbuf_num_segments_q7; 1336 uint8_t dma_addr_width; 1337 uint8_t tx_pbuf_num_segments_q8; 1338 uint8_t tx_pbuf_num_segments_q9; 1339 uint8_t tx_pbuf_num_segments_q10; 1340 uint8_t tx_pbuf_num_segments_q11; 1341 uint8_t tx_pbuf_num_segments_q12; 1342 uint8_t tx_pbuf_num_segments_q13; 1343 uint8_t tx_pbuf_num_segments_q14; 1344 uint8_t tx_pbuf_num_segments_q15; 1345 uint8_t num_type1_screeners; 1346 uint8_t num_type2_screeners; 1347 uint8_t num_scr2_ethtype_regs; 1348 uint8_t num_scr2_compare_regs; 1349 uint8_t axi_access_pipeline_bits; 1350 uint8_t pfc_multi_quantum; 1351 uint8_t pbuf_rsc; 1352 uint8_t pbuf_lso; 1353 uint8_t intrpt_mod; 1354 uint8_t hdr_split; 1355 uint8_t rx_pbuf_data; 1356 uint8_t tx_pbuf_data; 1357 } CEDI_DesignCfg; 1358 1359 /** 1360 * struct containing function pointers for event notification callbacks issued 1361 * by isr(). 1362 * <para>Each call passes the driver's privateData (pD) pointer for instance 1363 * identification if necessary, and may also pass data related to the event.</para> 1364 */ 1365 typedef struct CEDI_Callbacks 1366 { 1367 CEDI_CbPhyManComplete phyManComplete; 1368 CEDI_CbTxEvent txEvent; 1369 CEDI_CbTxError txError; 1370 CEDI_CbRxFrame rxFrame; 1371 CEDI_CbRxError rxError; 1372 CEDI_CbHrespError hrespError; 1373 CEDI_CbLpPageRx lpPageRx; 1374 CEDI_CbAnComplete anComplete; 1375 CEDI_CbLinkChange linkChange; 1376 CEDI_CbTsuEvent tsuEvent; 1377 CEDI_CbPauseEvent pauseEvent; 1378 CEDI_CbPtpPriFrameTx ptpPriFrameTx; 1379 CEDI_CbPtpPeerFrameTx ptpPeerFrameTx; 1380 CEDI_CbPtpPriFrameRx ptpPriFrameRx; 1381 CEDI_CbPtpPeerFrameRx ptpPeerFrameRx; 1382 CEDI_CbLpiStatus lpiStatus; 1383 CEDI_CbWolEvent wolEvent; 1384 CEDI_CbExtInpIntr extInpIntr; 1385 } CEDI_Callbacks; 1386 1387 /** 1388 * @} 1389 */ 1390 1391 /** @defgroup DriverObject Driver API Object 1392 * API listing for the driver. The API is contained in the object as 1393 * function pointers in the object structure. As the actual functions 1394 * resides in the Driver Object, the client software must first use the 1395 * global GetInstance function to obtain the Driver Object Pointer. 1396 * The actual APIs then can be invoked using obj->(api_name)() syntax. 1397 * These functions are defined in the header file of the core driver 1398 * and utilized by the API. 1399 * @{ 1400 */ 1401 1402 /********************************************************************** 1403 * API methods 1404 **********************************************************************/ 1405 typedef struct CEDI_OBJ 1406 { 1407 /** 1408 * Get the driver's memory requirements to support the given 1409 * configuration. If config->txQs or config->rxQs specify more than 1410 * the number of queues available in the h/w configuration, they will 1411 * be reduced to match the latter value, and the memReq values will 1412 * be based on this. 1413 * @param[out] memReq returns the size of memory allocations required 1414 * @param[in] config driver/hardware configuration required 1415 * @return EOK on success (requirements struct filled) 1416 * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints 1417 * @return EINVAL if config is NULL, or hardware not present 1418 */ 1419 uint32_t (*probe)(CEDI_Config* config, CEDI_SysReq* memReq); 1420 1421 /** 1422 * Initialise the driver instance and state, configure the EMAC as 1423 * specified in the 'config' settings, set up Tx & Rx descriptor 1424 * lists. 1425 * @param[in] callbacks client-supplied callback functions 1426 * @param[in,out] config specifies driver/hardware configuration 1427 * @param[in] pD driver state info specific to this instance 1428 * @return EOK on success 1429 * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters 1430 * @return EIO if driver encountered an error accessing hardware 1431 * @return EINVAL if illegal/inconsistent values in 'config' 1432 */ 1433 uint32_t (*init)(void* pD, const CEDI_Config* config, CEDI_Callbacks* callbacks); 1434 1435 /** 1436 * Destroy the driver (automatically performs a stop) 1437 * @param[in] pD driver state info specific to this instance 1438 */ 1439 void (*destroy)(void* pD); 1440 1441 /** 1442 * Start the EMAC driver, enabling interrupts and PCS auto- 1443 * negotiation. 1444 * @param[in] pD driver state info specific to this instance 1445 */ 1446 void (*start)(void* pD); 1447 1448 /** 1449 * Stop the driver. This should disable the hardware, including its 1450 * interrupt at the source, and make a best-effort to cancel any 1451 * pending transactions. 1452 * @param[in] pD driver state info specific to this instance 1453 */ 1454 void (*stop)(void* pD); 1455 1456 /** 1457 * Driver ISR. Platform-specific code is responsible for ensuring 1458 * this gets called when the corresponding hardware's interrupt is 1459 * asserted. Registering the ISR should be done after calling init, 1460 * and before calling start. The driver's ISR will not attempt to 1461 * lock any locks, but will perform client callbacks. If the client 1462 * wishes to defer processing to non-interrupt time, it is 1463 * responsible for doing so. 1464 * @param[in] pD driver state info specific to this instance 1465 * @return EOK if any interrupt detected (and callback) 1466 * @return ECANCELED if no interrupt bit detected 1467 * @return EINVAL for invalid pD pointer 1468 */ 1469 uint32_t (*isr)(void* pD); 1470 1471 /** 1472 * Enable or disable the specified interrupts. mechanical test will 1473 * always fail as no callback pointers are given 1474 * @param[in] enable if =1 enable the events, if =0 then disable 1475 * @param[in] events OR'd combination of bit-flags selecting the events to be enabled or disabled 1476 * @param[in] pD driver private state info specific to this instance 1477 * @param[in] queueNum between 0 and config->rxQs-1, or = CEDI_ALL_QUEUES 1478 * - number of Tx or Rx priority queue, 1479 * relevant to some of Tx and Rx events: CEDI_EV_TX_COMPLETE, CEDI_EV_TX_RETRY_EX_LATE_COLL, CEDI_EV_TX_FR_CORRUPT, CEDI_EV_RX_COMPLETE, 1480 * CEDI_EV_RX_USED_READ, CEDI_EV_RX_OVERRUN, CEDI_EV_HRESP_NOT_OK. 1481 * Must be = 0 or CEDI_ALL_QUEUES for other events. 1482 * To dis/enable on all available Qs, set queueNum to CEDI_ALL_QUEUES 1483 * and set events to CEDI_EVSET_ALL_Q0_EVENTS. 1484 * @return EOK for success 1485 * @return EINVAL for invalid queueNum 1486 */ 1487 uint32_t (*setEventEnable)(void* pD, uint32_t events, uint8_t enable, uint8_t queueNum); 1488 1489 /** 1490 * Read the enabled state of the specifed interrupts. OR the returned 1491 * event value with the CEDI_EV_ event bit-flags to determine if 1492 * event(s) are enabled. 1493 * @param[out] event returned enabled events 1494 * @param[in] pD driver private state info specific to this instance 1495 * @param[in] queueNum Tx or Rx priority queue to report events for 1496 * @return EOK for success 1497 * @return EINVAL for invalid pointer or queueNum 1498 */ 1499 uint32_t (*getEventEnable)(void* pD, uint8_t queueNum, uint32_t* event); 1500 1501 /** 1502 * Set the value of the Tx & Rx interrupt moderation register fields. 1503 * A non-zero value in either field introduces an interrupt stand-off 1504 * delay of the 8-bit value in units of 800ns before the 1505 * corresponding frame complete event causes an interrupt, limiting 1506 * the interrupt rate. 1507 * @param[in] txIntDelay Interrupt delay to apply to Tx frame complete 1508 * @param[in] rxIntDelay Interrupt delay to apply to Rx frame complete 1509 * @param[in] pD driver private state info specific to this instance 1510 * @return EOK for success 1511 * @return EINVAL for invalid pointer 1512 */ 1513 uint32_t (*setIntrptModerate)(void* pD, uint8_t txIntDelay, uint8_t rxIntDelay); 1514 1515 /** 1516 * Read the values of the interrupt moderation register fields 1517 * @param[out] txIntDelay Interrupt delay to apply to Tx frame complete 1518 * @param[out] rxIntDelay Interrupt delay to apply to Rx frame complete 1519 * @param[in] pD driver private state info specific to this instance 1520 * @return EOK for success 1521 * @return EINVAL for invalid pointers 1522 */ 1523 uint32_t (*getIntrptModerate)(void* pD, uint8_t* txIntDelay, uint8_t* rxIntDelay); 1524 1525 /** 1526 * Select 10/100/1000Mbps operation speed. 1527 * @param[in] speedSel a CEDI_IfSpeed enum indicating Tx/Rx speed 1528 * @param[in] pD driver private state info specific to this instance 1529 * @return EOK if successful 1530 * @return EINVAL if invalid parameter 1531 */ 1532 uint32_t (*setIfSpeed)(void* pD, CEDI_IfSpeed speedSel); 1533 1534 /** 1535 * Read selected operation speed 1536 * @param[out] speedSel returns CEDI_IfSpeed enum indicating Tx/Rx speed " 1537 * @param[in] pD driver private state info specific to this instance 1538 * @return EOK for success 1539 * @return EINVAL if invalid parameter 1540 */ 1541 uint32_t (*getIfSpeed)(void* pD, CEDI_IfSpeed* speedSel); 1542 1543 /** 1544 * Enable/disable reception of jumbo frames 1545 * @param[in] enable if =1 then enable jumbo frames accept, if =0 disable. 1546 * @param[in] pD driver private state info specific to this instance 1547 */ 1548 void (*setJumboFramesRx)(void* pD, uint8_t enable); 1549 1550 /** 1551 * Read jumbo frames enable status 1552 * @param[out] enable equal 1 if jumbo frames accept enabled; equal 0 if disabled. 1553 * @param[in] pD driver private state info specific to this instance 1554 * @return EOK for success 1555 * @return EINVAL for invalid pointer 1556 */ 1557 uint32_t (*getJumboFramesRx)(void* pD, uint8_t* enable); 1558 1559 /** 1560 * Set maximum length of jumbo frames to be received. (This is 1561 * initialised to gem_jumbo_max_length bytes.) Disables jumbo frame 1562 * reception temporarily while changing max length. 1563 * @param[in] length max. length to receive, in bytes. Maximum is 16383 1564 * @param[in] pD driver private state info specific to this instance 1565 * @return EOK if successful 1566 * @return EINVAL if length greater than 16383 1567 */ 1568 uint32_t (*setJumboFrameRxMaxLen)(void* pD, uint16_t length); 1569 1570 /** 1571 * Read maximum length of jumbo frames to be received 1572 * @param[out] length returns max. length to receive, in bytes 1573 * @param[in] pD driver private state info specific to this instance 1574 * @return EOK for success 1575 * @return EINVAL for invalid pointer 1576 */ 1577 uint32_t (*getJumboFrameRxMaxLen)(void* pD, uint16_t* length); 1578 1579 /** 1580 * Enable/disable uni-direction transmit operation. 1581 * @param[in] enable if =1 enable, if =0 then disable 1582 * @param[in] pD driver private state info specific to this instance 1583 */ 1584 void (*setUniDirEnable)(void* pD, uint8_t enable); 1585 1586 /** 1587 * Read enable status for uni-direction transmit operation 1588 * @param[out] enable equal 1 if enabled, equal 0 if disabled 1589 * @param[in] pD driver private state info specific to this instance 1590 * @return EOK for success 1591 * @return EINVAL for invalid pointer 1592 */ 1593 uint32_t (*getUniDirEnable)(void* pD, uint8_t* enable); 1594 1595 /** 1596 * Enable/disable Tx IP, TCP and UDP checksum generation offload. 1597 * Only valid if using DMA packet buffering mode. 1598 * @param[in] enable if =1 then enable, if =0 then disable 1599 * @param[in] pD driver private state info specific to this instance 1600 * @return EOK for success 1601 * @return EINVAL if packet buffering not enabled or null pointer 1602 */ 1603 uint32_t (*setTxChecksumOffload)(void* pD, uint8_t enable); 1604 1605 /** 1606 * Read enable/disable of Tx IP, TCP and UDP checksum generation 1607 * offload 1608 * @param[out] enable equal 1 if enabled, equal 0 if disabled 1609 * @param[in] pD driver private state info specific to this instance 1610 * @return EOK for success 1611 * @return EINVAL for invalid pointer 1612 */ 1613 uint32_t (*getTxChecksumOffload)(void* pD, uint8_t* enable); 1614 1615 /** 1616 * Set Rx buffer offset for writing start of frame. 1617 * @param[in] pD driver private state info specific to this instance 1618 * @param[in] offset offset to use, range 0 to 3 bytes 1619 * @return EOK for success 1620 * @return EINVAL if offset invalid or null pointer 1621 */ 1622 uint32_t (*setRxBufOffset)(void* pD, uint8_t offset); 1623 1624 /** 1625 * Read Rx buffer offset for writing start of frame 1626 * @param[in] pD driver private state info specific to this instance 1627 * @param[out] offset offset in use, range 0 to 3 bytes 1628 * @return EOK for success 1629 * @return EINVAL for invalid pointer 1630 */ 1631 uint32_t (*getRxBufOffset)(void* pD, uint8_t* offset); 1632 1633 /** 1634 * Enable/disable reception of frames up to 1536 bytes, instead of 1635 * normal 1518 bytes limit 1636 * @param[in] enable if =1 then enable 1536-byte frames accept, if =0 disable 1637 * @param[in] pD driver private state info specific to this instance 1638 */ 1639 void (*set1536ByteFramesRx)(void* pD, uint8_t enable); 1640 1641 /** 1642 * Read 1536-byte frames Rx enable status 1643 * @param[out] enable equal 1 if 1536-byte frames accept enabled equal 0 if disabled. 1644 * @param[in] pD driver private state info specific to this instance 1645 * @return EOK for success 1646 * @return EINVAL for invalid pointer 1647 */ 1648 uint32_t (*get1536ByteFramesRx)(void* pD, uint8_t* enable); 1649 1650 /** 1651 * Enable/disable Rx IP, TCP and UDP checksum offload. When enabled, 1652 * frames with bad IP, TCP or UDP checksums will be discarded. 1653 * @param[in] enable if =1 then enable, if =0 then disable 1654 * @param[in] pD driver private state info specific to this instance 1655 */ 1656 void (*setRxChecksumOffload)(void* pD, uint8_t enable); 1657 1658 /** 1659 * Read enable/disable of Rx IP, TCP and UDP checksum offload 1660 * @param[out] enable equal 1 if enabled, equal 0 if disabled 1661 * @param[in] pD driver private state info specific to this instance 1662 * @return EOK for success 1663 * @return EINVAL for invalid pointer 1664 */ 1665 uint32_t (*getRxChecksumOffload)(void* pD, uint8_t* enable); 1666 1667 /** 1668 * Enable/disable FCS remove feature. When enabled, received frames 1669 * will be written without frame check sequence (last four bytes). 1670 * @param[in] enable if =1 then enable, if =0 then disable 1671 * @param[in] pD driver private state info specific to this instance 1672 */ 1673 void (*setFcsRemove)(void* pD, uint8_t enable); 1674 1675 /** 1676 * Read enable/disable status for FCS remove feature 1677 * @param[out] enable equal 1 if enabled, equal 0 if disabled 1678 * @param[in] pD driver private state info specific to this instance 1679 * @return EOK for success 1680 * @return EINVAL for invalid pointer 1681 */ 1682 uint32_t (*getFcsRemove)(void* pD, uint8_t* enable); 1683 1684 /** 1685 * Enable/disable partial store and forward Tx mode if possible 1686 * @param[in] enable if =1 then enables partial store and forward Tx mode, if =0 then disables 1687 * @param[in] pD driver private state info specific to this instance 1688 * @param[in] watermark value to control data forwarding - ignored if enable==0 1689 * @return EOK if successful 1690 * @return ENOTSUP if not in tx packet buffer mode 1691 * @return EINVAL if parameter invalid 1692 */ 1693 uint32_t (*setTxPartialStFwd)(void* pD, uint32_t watermark, uint8_t enable); 1694 1695 /** 1696 * Get watermark value for partial store and forward Tx mode 1697 * @param[out] enable =1 if partial store and forward Tx mode enabled 1698 * @param[in] pD driver private state info specific to this instance 1699 * @param[out] watermark returns value to control data forwarding if partial store and forward Tx mode enabled 1700 * @return EOK for success 1701 * @return ENOTSUP if not in tx packet buffer mode 1702 * @return EINVAL if invalid parameter 1703 */ 1704 uint32_t (*getTxPartialStFwd)(void* pD, uint32_t* watermark, uint8_t* enable); 1705 1706 /** 1707 * Enable/disable partial store and forward Rx mode if possible 1708 * @param[in] enable if =1 then enables partial store and forward Rx mode, if =0 then disables 1709 * @param[in] pD driver private state info specific to this instance 1710 * @param[in] watermark value to control data forwarding 1711 * @return EOK if successful 1712 * @return ENOTSUP if not in rx packet buffer mode 1713 * @return EINVAL if invalid parameter 1714 */ 1715 uint32_t (*setRxPartialStFwd)(void* pD, uint32_t watermark, uint8_t enable); 1716 1717 /** 1718 * Get watermark value for partial store and forward Rx mode 1719 * @param[out] enable =1 if partial store and forward Rx mode enabled 1720 * @param[in] pD driver private state info specific to this instance 1721 * @param[out] watermark pointer for returning watermark value set (undefined if partial store & forward not enabled) 1722 * @return EOK for success 1723 * @return ENOTSUP if not in rx packet buffer mode 1724 * @return EINVAL if invalid parameter 1725 */ 1726 uint32_t (*getRxPartialStFwd)(void* pD, uint32_t* watermark, uint8_t* enable); 1727 1728 /** 1729 * Set the fields of the Rx DMA Data Buffer Address Mask register, 1730 * which allows any/all of bits 31:28 of rx data buffer address to be 1731 * forced to a particular value 1732 * @param[in] bitValues 4-bit field specifying values to force address bits 31:28 to, if corresponding bit in enableBit is set to 1 1733 * @param[in] pD driver private state info specific to this instance 1734 * @param[in] enableBit 4-bit field selecting bits to force value on 1735 * @return EOK if successful 1736 * @return EINVAL if parameter value invalid 1737 */ 1738 uint32_t (*setRxDmaDataAddrMask)(void* pD, uint8_t enableBit, uint8_t bitValues); 1739 1740 /** 1741 * Read the fields of the Rx DMA Data Buffer Address Mask register, 1742 * which allows any/all of bits 31:28 of rx data buffer address to be 1743 * forced to a particular value 1744 * @param[out] bitValues pointer for returning 4-bit field specifying values to force address bits to, if corresponding bit in enableBit is set to 1 1745 * @param[in] pD driver private state info specific to this instance 1746 * @param[out] enableBit pointer for returning 4-bit field selecting bits to force value on 1747 * @return EOK if successful 1748 * @return EINVAL if any parameter equal NULL 1749 */ 1750 uint32_t (*getRxDmaDataAddrMask)(void* pD, uint8_t* enableBit, uint8_t* bitValues); 1751 1752 /** 1753 * Enable/disable receive bad preamble feature. When enabled, frames 1754 * with non-standard preamble will not be rejected. 1755 * @param[in] enable if =1 then enable, if =0 then disable 1756 * @param[in] pD driver private state info specific to this instance 1757 */ 1758 void (*setRxBadPreamble)(void* pD, uint8_t enable); 1759 1760 /** 1761 * Read enable/disable status for receive bad preamble feature 1762 * @param[out] enable equal 1 if enabled, equal 0 if disabled 1763 * @param[in] pD driver private state info specific to this instance 1764 * @return EOK for success 1765 * @return EINVAL for invalid pointer 1766 */ 1767 uint32_t (*getRxBadPreamble)(void* pD, uint8_t* enable); 1768 1769 /** 1770 * Select full/half duplex operation. 1771 * @param[in] enable if =1 select full duplex operation if =0 select half duplex. 1772 * @param[in] pD driver private state info specific to this instance 1773 */ 1774 void (*setFullDuplex)(void* pD, uint8_t enable); 1775 1776 /** 1777 * Read full/half duplex operation 1778 * @param[out] enable equal 1 if full duplex operation enabled equal 0 if half duplex. 1779 * @param[in] pD driver private state info specific to this instance 1780 * @return EOK for success 1781 * @return EINVAL for invalid pointer 1782 */ 1783 uint32_t (*getFullDuplex)(void* pD, uint8_t* enable); 1784 1785 /** 1786 * Enable/disable ignore FCS feature. When enabled, frames with 1787 * FCS/CRC errors will not be rejected. 1788 * @param[in] enable if =1 then enable, if =0 then disable 1789 * @param[in] pD driver private state info specific to this instance 1790 */ 1791 void (*setIgnoreFcsRx)(void* pD, uint8_t enable); 1792 1793 /** 1794 * Read enable/disable status for FCS ignore feature 1795 * @param[out] enable equal 1 if enabled, equal 0 if disabled 1796 * @param[in] pD driver private state info specific to this instance 1797 * @return EOK for success 1798 * @return EINVAL for invalid pointer 1799 */ 1800 uint32_t (*getIgnoreFcsRx)(void* pD, uint8_t* enable); 1801 1802 /** 1803 * Enable/disable frame Rx in half-duplex mode while transmitting. 1804 * @param[in] enable if =1 then enable, if =0 then disable 1805 * @param[in] pD driver private state info specific to this instance 1806 */ 1807 void (*setRxHalfDuplexInTx)(void* pD, uint8_t enable); 1808 1809 /** 1810 * Read enable status for frame Rx in half-duplex mode while 1811 * transmitting 1812 * @param[out] enable equal 1 if enabled, equal 0 if disabled 1813 * @param[in] pD driver private state info specific to this instance 1814 * @return EOK for success 1815 * @return EINVAL for invalid pointer 1816 */ 1817 uint32_t (*getRxHalfDuplexInTx)(void* pD, uint8_t* enable); 1818 1819 /** 1820 * Return capabilities supported by the driver/EMAC hardware 1821 * @param[out] cap pointer for returning supported capabilities, OR combination of CEDI_CAP_XXX flags 1822 * @param[in] pD driver private state info specific to this instance 1823 * @return EOK for success 1824 * @return EINVAL for invalid pointer 1825 */ 1826 uint32_t (*getIfCapabilities)(void* pD, uint32_t* cap); 1827 1828 /** 1829 * Enable or disable loop back mode in the EMAC. 1830 * @param[in] mode enum selecting mode enable/disable. =CEDI_SERDES_LOOPBACK: select loopback mode in PHY transceiver, if available; =CEDI_LOCAL_LOOPBACK: select internal loopback mode. Tx and Rx should be disabled when enabling or disabling this mode. Only available if int_loopback defined; =CEDI_NO_LOOPBACK: disable loopback mode 1831 * @param[in] pD driver private state info specific to this instance 1832 * @return EOK for success 1833 * @return ENOTSUP if CEDI_SERDES_LOOPBACK selected and no_pcs defined, or if CEDI_LOCAL_LOOPBACK selected and either (no_int_loopback defined or PCS mode is selected) 1834 */ 1835 uint32_t (*setLoopback)(void* pD, uint8_t mode); 1836 1837 /** 1838 * Return loopback mode, same values as for setLoopbackMode. 1839 * @param[out] mode returns enum for mode enable/disable. =CEDI_SERDES_LOOPBACK: selected loopback mode in PHY transceiver, if available; =CEDI_LOCAL_LOOPBACK: selected internal loopback mode. Only available if int_loopback defined; =CEDI_NO_LOOPBACK: disabled loopback mode 1840 * @param[in] pD driver private state info specific to this instance 1841 */ 1842 uint32_t (*getLoopback)(void* pD, uint8_t* mode); 1843 1844 /** 1845 * Identify max Tx pkt size for queues. When using full store & 1846 * forward packet buffering, this is based on the sram size for each 1847 * queue, otherwise it is limited by an internal counter to 16kB. 1848 * @param[out] maxTxSize pointer for returning array of sizes for queues 1849 * @param[in] pD driver private state info specific to this instance 1850 * @return EOK if successful 1851 * @return EINVAL if any parameter equal NULL 1852 */ 1853 uint32_t (*calcMaxTxFrameSize)(void* pD, CEDI_FrameSize* maxTxSize); 1854 1855 /** 1856 * Add a buffer containing Tx data to the end of the transmit queue. 1857 * Use repeated calls for multi-buffer frames, setting lastBuffer on 1858 * the last call, to indicate the end of the frame. 1859 * @param[in] bufAdd pointer to address of buffer 1860 * @param[in] flags bit-flags (CEDI_TXB_xx) specifying last buffer/auto CRC 1861 * @param[in] length length of data in buffer 1862 * @param[in] pD driver private state info specific to this instance 1863 * @param[in] queueNum number of Tx queue 1864 * @return EOK if successful 1865 * @return ENOENT if no available descriptors 1866 * @return EINVAL if invalid queueNum, length or buffer alignment, NULL pointers or buffer address 1867 */ 1868 uint32_t (*queueTxBuf)(void* pD, uint8_t queueNum, CEDI_BuffAddr* bufAdd, uint32_t length, uint8_t flags); 1869 1870 /** 1871 * Add a buffer containing Tx data to the end of the transmit queue. 1872 * Use repeated calls for multi-buffer frames, setting 1873 * CEDI_TXB_LAST_BUFF in the flags on the last call, to indicate the 1874 * end of the frame. This function is required for utilising TSO/UFO. 1875 * @param[in] params pointer to struct for all parameters required by the function 1876 * @param[in] pD driver private state info specific to this instance 1877 * @return EOK if successful 1878 * @return ENOENT if no available descriptors 1879 * @return EINVAL if invalid queueNum, length or buffer alignment, NULL pointers or buffer address or prm->flags specifies CEDI_TXB_LAST_BUFF at same time as CEDI_TXB_TCP_ENCAP or CEDI_TXB_UDP_ENCAP 1880 */ 1881 uint32_t (*qTxBuf)(void* pD, CEDI_qTxBufParams* params); 1882 1883 /** 1884 * Remove buffer from head of transmit queue in case of error during 1885 * queueing and free the corresponding descriptor. Caller must have 1886 * knowledge of queueing status, i.e. latest frame has not been 1887 * completed for transmission (first used bit still set) and how many 1888 * descriptors have been queued for untransmitted frame. 1889 * @param[in, out] params pointer to struct for parameters to be returned. Not all fields are used - queueNum must be specified, and bufAdd and length are returned 1890 * @param[in] pD driver private state info specific to this instance 1891 * @return EOK if successful 1892 * @return ENOENT if no unfree descriptors 1893 * @return EINVAL if invalid queueNum or NULL parameters 1894 */ 1895 uint32_t (*deQTxBuf)(void* pD, CEDI_qTxBufParams* params); 1896 1897 /** 1898 * Get number of free descriptors in specified Tx queue 1899 * @param[out] numFree pointer for returning number of free descriptors 1900 * @param[in] pD driver private state info specific to this instance 1901 * @param[in] queueNum number of Tx queue 1902 * @return EOK if successful 1903 * @return EINVAL if invalid parameter 1904 */ 1905 uint32_t (*txDescFree)(void* pD, uint8_t queueNum, uint16_t* numFree); 1906 1907 /** 1908 * Read Tx descriptor queue and free used descriptor.\n Struct 1909 * fields:\n CEDI_BuffAddr bufAdd - addresses of buffer freed up 1910 * uint32_t txDescStat - descriptor status word. Only valid if first 1911 * buffer of frame. uint8_t status - descriptor queue status, one of 1912 * the following values: CEDI_TXDATA_1ST_NOT_LAST :a first descriptor 1913 * was freed, frame not finished: 1914 * bufAdd & txDescStat are valid CEDI_TXDATA_1ST_AND_LAST :a first 1915 * descriptor was freed, frame is finished: 1916 * bufAdd & txDescStat are valid CEDI_TXDATA_MID_BUFFER :a 1917 * descriptor was freed, (not first in 1918 * frame), frame not finished: bufAdd valid, 1919 * txDescStat not valid CEDI_TXDATA_LAST_BUFFER :a descriptor was 1920 * freed, frame is finished: bufAdd valid, 1921 * txDescStat not valid CEDI_TXDATA_NONE_FREED :no used descriptor 1922 * to free: bufAdd & txDescStat not valid 1923 * CEDI_TimeStampData txTsData - Tx descriptor timestamp when valid 1924 * (txTsData->tsValid will be set to 1). 1925 * @param[out] descData pointer for returning status & descriptor data 1926 * @param[in] pD driver private state info specific to this instance 1927 * @param[in] queueNum number of Tx queue 1928 * @return EOK if successful (and status is set) 1929 * @return ENOENT if the queue is empty (status equal CEDI_TXDATA_NONE_FREED) 1930 * @return EIO if an incomplete frame was detected (no lastBuffer flag in queue) 1931 * @return EINVAL if any parameter invalid 1932 */ 1933 uint32_t (*freeTxDesc)(void* pD, uint8_t queueNum, CEDI_TxDescData* descData); 1934 1935 /** 1936 * Decode the Tx descriptor status into a bit-field struct 1937 * @param[in] txDStatWord - Tx descriptor status word 1938 * @param[in] pD driver private state info specific to this instance 1939 * @param[out] txDStat - pointer to bit-field struct for decoded status fields 1940 */ 1941 void (*getTxDescStat)(void* pD, uint32_t txDStatWord, CEDI_TxDescStat* txDStat); 1942 1943 /** 1944 * Provides the size of Tx descriptor calculated for current 1945 * configuration. 1946 * @param[out] txDescSize - pointer to Tx descriptor size 1947 * @param[in] pD driver private state info specific to this instance 1948 */ 1949 void (*getTxDescSize)(void* pD, uint32_t* txDescSize); 1950 1951 /** 1952 * Reset transmit buffer queue. Any untransmitted buffer data will be 1953 * discarded and must be re-queued. Transmission must be disabled 1954 * before calling this function. 1955 * @param[in] pD driver private state info specific to this instance 1956 * @param[in] queueNum number of Tx queue 1957 * @return EOK if successful 1958 * @return EINVAL if invalid parameter 1959 */ 1960 uint32_t (*resetTxQ)(void* pD, uint8_t queueNum); 1961 1962 /** 1963 * Enable & start the transmit circuit. Not required during normal 1964 * operation, as queueTxBuf will automatically start Tx when complete 1965 * frame has been queued, but may be used to restart after a Tx 1966 * error. 1967 * @param[in] pD driver private state info specific to this instance 1968 * @return EOK for success 1969 * @return ECANCELED if no entries in buffer 1970 */ 1971 uint32_t (*startTx)(void* pD); 1972 1973 /** 1974 * Halt transmission as soon as current frame Tx has finished 1975 * @param[in] pD driver private state info specific to this instance 1976 */ 1977 void (*stopTx)(void* pD); 1978 1979 /** 1980 * Immediately disable transmission without waiting for completion. 1981 * Since the EMAC will reset to point to the start of transmit 1982 * descriptor list, the buffer queues may have to be reset after this 1983 * call. 1984 * @param[in] pD driver private state info specific to this instance 1985 */ 1986 void (*abortTx)(void* pD); 1987 1988 /** 1989 * Get state of transmitter 1990 * @param[in] pD driver private state info specific to this instance 1991 * @return 1 if active 1992 * @return 0 if idle or pD equal NULL 1993 */ 1994 uint32_t (*transmitting)(void* pD); 1995 1996 /** 1997 * Enable the transmit circuit. This will be done automatically when 1998 * call startTx, but it may be desirable to call this earlier, since 1999 * some functionality depends on transmit being enabled. 2000 * @param[in] pD driver private state info specific to this instance 2001 */ 2002 void (*enableTx)(void* pD); 2003 2004 /** 2005 * Get state of transmision enabled 2006 * @param[in] pD driver private state info specific to this instance 2007 * @return 1 if transmission enabled 2008 * @return 0 if transmission disabled or pD equal NULL 2009 */ 2010 uint32_t (*getTxEnabled)(void* pD); 2011 2012 /** 2013 * Get the content of EMAC transmit status register 2014 * @param[out] status pointer to struct with fields for each flag 2015 * @param[in] pD driver private state info specific to this instance 2016 * @return 0 if no status bits set or status equal NULL 2017 * @return number raw Tx status value read 2018 */ 2019 uint32_t (*getTxStatus)(void* pD, CEDI_TxStatus* status); 2020 2021 /** 2022 * Reset the bits of EMAC transmit status register as selected in 2023 * resetStatus 2024 * @param[in] resetStatus OR'd combination of CEDI_TXS_ bit-flags 2025 * @param[in] pD driver private state info specific to this instance 2026 */ 2027 void (*clearTxStatus)(void* pD, uint32_t resetStatus); 2028 2029 /** 2030 * Enable credit-based shaping (CBS) on the specified queue. If 2031 * already enabled then first disables, sets a new idle slope value 2032 * for the queue, and re-enables CBS 2033 * @param[in] idleSlope new idle slope value (in bytes/sec) 2034 * @param[in] pD driver private state info specific to this instance 2035 * @param[in] qSel if =0 selects highest priority queue (queue A), if =1 selects next-highest priority queue (queue B) 2036 * @return EOK if successful 2037 * @return ENOTSUP if CBS not present in h/w config 2038 * @return EINVAL if priority queueing not enabled (i.e. only one Tx queue) or invalid parameter 2039 */ 2040 uint32_t (*enableCbs)(void* pD, uint8_t qSel, uint32_t idleSlope); 2041 2042 /** 2043 * Disable CBS on the specified queue 2044 * @param[in] pD driver private state info specific to this instance 2045 * @param[in] qSel if =0 selects highest priority queue (queue A), if =1 selectsnext-highest priority queue (queue B) 2046 */ 2047 void (*disableCbs)(void* pD, uint8_t qSel); 2048 2049 /** 2050 * Read CBS setting for the specified queue. 2051 * @param[out] enable returns: 1 if CBS enabled for the specified queue 0 if not enabled 2052 * @param[out] idleSlope pointer for returning the idleSlope value for selected queue. 2053 * @param[in] pD driver private state info specific to this instance 2054 * @param[in] qSel if =0 selects highest priority queue (queue A), if =1 selects next-highest priority queue (queue B) 2055 * @return EOK for success 2056 * @return ENOTSUP if CBS not present in h/w config 2057 * @return EINVAL for invalid pointer 2058 */ 2059 uint32_t (*getCbsQSetting)(void* pD, uint8_t qSel, uint8_t* enable, uint32_t* idleSlope); 2060 2061 /** 2062 * Enable/disable the inter-packet gap (IPG) stretch function. 2063 * @param[in] enable if =1 then enable IPG stretch, if =0 then disable 2064 * @param[in] divisor after multiplying previous frame length, divide by (divisor+1) - if result>96 bits, 2065 * this is used for the Tx IPG. Ignored if enable equal 0. 2066 * @param[in] pD driver private state info specific to this instance 2067 * @param[in] multiplier multiplying factor applied to previous Tx frame length. Ignored if enable equal 0. 2068 * @return EOK if successful 2069 * @return EINVAL if pD equal NULL 2070 */ 2071 uint32_t (*setIpgStretch)(void* pD, uint8_t enable, uint8_t multiplier, uint8_t divisor); 2072 2073 /** 2074 * Read the inter-packet gap (IPG) stretch settings. 2075 * @param[out] enable pointer for returning enabled state: returns 1 if IPG stretch enabled, 0 if disabled. 2076 * @param[out] divisor pointer for returning IPG divisor 2077 * @param[in] pD driver private state info specific to this instance 2078 * @param[out] multiplier pointer for returning IPG multiplying factor 2079 * @return EOK if successful 2080 * @return EINVAL if any parameter equal NULL 2081 */ 2082 uint32_t (*getIpgStretch)(void* pD, uint8_t* enable, uint8_t* multiplier, uint8_t* divisor); 2083 2084 /** 2085 * Identify max Rx pkt size for queues - determined by size of Rx 2086 * packet buffer (if using full store & forward mode), and the 2087 * current maximum frame size, e.g. 1518, 1536 or jumbo frame. 2088 * @param[out] maxSize pointer for returning max frame size same for each Rx queue 2089 * @param[in] pD driver private state info specific to this instance 2090 * @return EOK if successful 2091 * @return EINVAL if NULL parameters 2092 */ 2093 uint32_t (*calcMaxRxFrameSize)(void* pD, uint32_t* maxSize); 2094 2095 /** 2096 * Add a buffer (size determined by rxBufLength in CEDI_Config) to 2097 * the end of the receive buffer queue. This function is intended to 2098 * be used during setting up the receive buffers, and should not be 2099 * called while Rx is enabled or unread data remains in the queue. 2100 * Note that one extra descriptor is reserved, to provide wrap-around 2101 * protection (must always have one used bit set). 2102 * @param[in] init if >0 then initialise the buffer data to all zeros 2103 * @param[in] buf pointer to address of buffer. Checked for word-alignment in 64/128-bit width cases. 2104 * @param[in] pD driver private state info specific to this instance 2105 * @param[in] queueNum number of the Rx queue 2106 * @return EOK if successful 2107 * @return EINVAL if invalid queueNum, buffer alignment, or bufStart pointer/addresses 2108 */ 2109 uint32_t (*addRxBuf)(void* pD, uint8_t queueNum, CEDI_BuffAddr* buf, uint8_t init); 2110 2111 /** 2112 * Get the total number of buffers/descriptors present in the 2113 * specified Rx queue. 2114 * @param[out] numBufs pointer for returning number of descriptors 2115 * @param[in] pD driver private state info specific to this instance 2116 * @param[in] queueNum number of the Rx queue 2117 * @return EOK if successful 2118 * @return EINVAL if invalid parameter 2119 */ 2120 uint32_t (*numRxBufs)(void* pD, uint8_t queueNum, uint16_t* numBufs); 2121 2122 /** 2123 * Get the number of buffers/descriptors marked "used" in the 2124 * specified Rx queue, i.e. those holding unread data. 2125 * @param[in] pD driver private state info specific to this instance 2126 * @param[in] queueNum number of the Rx queue 2127 * @return 0 if invalid parameter or NULL pointer 2128 * @return number of used buffers 2129 */ 2130 uint32_t (*numRxUsed)(void* pD, uint8_t queueNum); 2131 2132 /** 2133 * Read first unread descriptor (at tail of queue): if new data is 2134 * available it swaps out the buffer and replaces it with a new one, 2135 * clears the descriptor for re-use, then updates the driver queue- 2136 * pointer. Checks for Start Of Frame (SOF) and End Of Frame (EOF) 2137 * flags in the descriptors, passing back in status parameter. If EOF 2138 * set, the descriptor status is returned via rxDescStat. Struct 2139 * fields: uint32_t rxDescStat - Rx descriptor status word 2140 * uint8_t status - Rx data status, one of the following values: 2141 * CEDI_RXDATA_SOF_EOF :data available, single-buffer frame (SOF & 2142 * EOF set) CEDI_RXDATA_SOF_ONLY 2143 * :data available, start of multi-buffer frame 2144 * CEDI_RXDATA_NO_FLAG :data available, intermediate buffer of 2145 * multi- buffer frame 2146 * CEDI_RXDATA_EOF_ONLY :data available, end of multi-buffer frame 2147 * CEDI_RXDATA_NODATA :no data available CEDI_TimeStampData 2148 * rxTsData - Rx descriptor timestamp when valid 2149 * (rxTsData->tsValid will be set to 1) 2150 * @param[in] init if >0 then initialise the (new) buffer data to all zeros. Ignored if no data available. 2151 * @param[out] descData pointer for returning status & descriptor data 2152 * @param[in,out] buf pointer to address of memory for new buffer to add to Rx descriptor queue; if data is available the buffer addresses for this are returned in buf, else if no data available then the new buffer can be re-used. Physical address of buffer is checked for word-alignment in 64/128-bit width cases. 2153 * @param[in] pD driver private state info specific to this instance 2154 * @param[in] queueNum number of the Rx queue 2155 * @return EOK if successful 2156 * @return EINVAL if invalid queueNum, buf, rxDescStat or status parameters 2157 */ 2158 uint32_t (*readRxBuf)(void* pD, uint8_t queueNum, CEDI_BuffAddr* buf, uint8_t init, CEDI_RxDescData* descData); 2159 2160 /** 2161 * Decode the Rx descriptor status into a bit-field struct. Note 2162 * that most of these fields are only valid when End Of Frame bit15 2163 * is set - see hardware user guide 2164 * @param[in] rxDStatWord - Rx descriptor status word 2165 * @param[in] pD driver private state info specific to this instance 2166 * @param[out] rxDStat pointer to bit-field struct for decoded status fields 2167 */ 2168 void (*getRxDescStat)(void* pD, uint32_t rxDStatWord, CEDI_RxDescStat* rxDStat); 2169 2170 /** 2171 * Provides the size of Rx descriptor calculated for current 2172 * configuration. 2173 * @param[out] rxDescSize - pointer to Rx descriptor size 2174 * @param[in] pD driver private state info specific to this instance 2175 */ 2176 void (*getRxDescSize)(void* pD, uint32_t* rxDescSize); 2177 2178 /** 2179 * Get state of receiver 2180 * @param[in] pD driver private state info specific to this instance 2181 * @return 1 if enabled 2182 * @return 0 if disabled or pD equal NULL 2183 */ 2184 uint32_t (*rxEnabled)(void* pD); 2185 2186 /** 2187 * Enable the receive circuit. 2188 * @param[in] pD driver private state info specific to this instance 2189 */ 2190 void (*enableRx)(void* pD); 2191 2192 /** 2193 * Disable the receive circuit. 2194 * @param[in] pD driver private state info specific to this instance 2195 */ 2196 void (*disableRx)(void* pD); 2197 2198 /** 2199 * Remove a buffer from the end of the receive buffer queue. This 2200 * function is intended to be used when shutting down the driver, 2201 * prior to deallocating the receive buffers, and should not be 2202 * called while Rx is enabled or unread data remains in the queue. 2203 * @param[out] buf pointer to struct for returning virtual and physical addresses of buffer. 2204 * @param[in] pD driver private state info specific to this instance 2205 * @param[in] queueNum number of the Rx queue 2206 * @return EOK if successful 2207 * @return ENOENT if no buffers left to free (mechanical success) 2208 * @return EINVAL if invalid queueNum 2209 */ 2210 uint32_t (*removeRxBuf)(void* pD, uint8_t queueNum, CEDI_BuffAddr* buf); 2211 2212 /** 2213 * Reset Rx buffer descriptor list to initial empty state (if 2214 * ptrsOnly=0), clearing all descriptors. For use after a fatal 2215 * error. Disables receive circuit. 2216 * @param[in] ptrsOnly "flag to allow full queue to be reset after link down/up (enableRx). 2217 * if =1 then only reset tail & stop pointers and clear used bits" 2218 * @param[in] pD driver private state info specific to this instance 2219 * @param[in] queueNum number of the Rx queue 2220 * @return EOK if successful 2221 * @return EINVAL if invalid parameter 2222 */ 2223 uint32_t (*resetRxQ)(void* pD, uint8_t queueNum, uint8_t ptrsOnly); 2224 2225 /** 2226 * Return the content of EMAC receive status register 2227 * @param[out] status pointer to struct with fields for each flag 2228 * @param[in] pD driver private state info specific to this instance 2229 * @return 1 if any flags set 2230 * @return 0 if not or status equal NULL 2231 */ 2232 uint32_t (*getRxStatus)(void* pD, CEDI_RxStatus* status); 2233 2234 /** 2235 * Reset the bits of EMAC receive status register as selected in 2236 * resetStatus 2237 * @param[in] resetStatus OR'd combination of CEDI_RXS_ bit-flags 2238 * @param[in] pD driver private state info specific to this instance 2239 */ 2240 void (*clearRxStatus)(void* pD, uint32_t resetStatus); 2241 2242 /** 2243 * Enable/disable header-data split feature. When enabled, frame 2244 * L2/L3/L4 headers will written to separate buffer, before data 2245 * starts in a second buffer (if not zero payload) 2246 * @param[in] enable if =1 then enable; if =0 then disable 2247 * @param[in] pD driver private state info specific to this instance 2248 * @return EOK if success 2249 * @return EINVAL if invalid parameter 2250 */ 2251 uint32_t (*setHdrDataSplit)(void* pD, uint8_t enable); 2252 2253 /** 2254 * Read enable/disable status for header-data split feature 2255 * @param[out] enable pointer for returning enabled status 2256 * @param[in] pD driver private state info specific to this instance 2257 * @return EOK successful 2258 * @return EINVAL if invalid parameter 2259 */ 2260 uint32_t (*getHdrDataSplit)(void* pD, uint8_t* enable); 2261 2262 /** 2263 * Enable/disable Receive Segment Coalescing function. When enabled, 2264 * consecutive TCP/IP frames on a priority queue will be combined to 2265 * form a single large frame 2266 * @param[in] queue priority queue to enable or disable RSC on 2267 * @param[in] enable if =1 enable RSC on selected priority queue(s); else disable it 2268 * @param[in] pD driver private state info specific to this instance 2269 * @return EOK for success 2270 * @return ENOTSUP if feature not available 2271 * @return EINVAL for invalid parameter 2272 */ 2273 uint32_t (*setRscEnable)(void* pD, uint8_t queue, uint8_t enable); 2274 2275 /** 2276 * Read enabled status of RSC on a specified priority queue 2277 * @param[in] queue priority queue to read RSC enabled status for 2278 * @param[out] enable pointer for returning enabled status 2279 * @param[in] pD driver private state info specific to this instance 2280 * @return EOK successful 2281 * @return ENOTSUP if feature not available 2282 * @return EINVAL if invalid parameter 2283 */ 2284 uint32_t (*getRscEnable)(void* pD, uint8_t queue, uint8_t* enable); 2285 2286 /** 2287 * "Set/Clear Mask of Receive Segment Coalescing disabling. When mask 2288 * is set and RSC is enabled, the RSC operation is not disabled by 2289 * receipt of frame with an end-coalesce flag set (SYN/FIN/RST/URG)" 2290 * @param[in] pD driver private state info specific to this instance 2291 * @param[in] setMask if =1 prevents RSC disabling by end-coalesce flags (SYN/FIN/RST/URG) - applies to all queues 2292 * @return EOK for success 2293 * @return ENOTSUP if feature not available 2294 * @return EINVAL for invalid pointer 2295 */ 2296 uint32_t (*setRscClearMask)(void* pD, uint8_t setMask); 2297 2298 /** 2299 * Set specific address register to the given address value 2300 * @param[in] specFilterType flag specifying whether to use MAC source or destination address to be compared for filtering. Source filter when =1. 2301 * @param[in] addrNum number of specific address filter, in range 1 - num_spec_add_filters 2302 * @param[in] addr pointer to the 6-byte MAC address value to write 2303 * @param[in] pD driver private state info specific to this instance 2304 * @param[in] byteMask Bits masking out bytes of specific address from comparison. 2305 * @return EOK if success 2306 * @return ENOTSUP if no specific address registers available 2307 * @return EINVAL if invalid parameter 2308 */ 2309 uint32_t (*setSpecificAddr)(void* pD, uint8_t addrNum, CEDI_MacAddress* addr, uint8_t specFilterType, uint8_t byteMask); 2310 2311 /** 2312 * Get the value of a specific address register destination address 2313 * for filtering. When set to 1 use source address. 2314 * @param[out] specFilterType flag specifying whether to use MAC source or destination address to be 2315 * compared for filtering. =1 for source address 2316 * @param[in] addrNum number of specific address filter, in range 1 - num_spec_add_filters 2317 * @param[out] addr pointer to a 6-byte MAC address struct for returning the address value 2318 * @param[in] pD driver private state info specific to this instance 2319 * @param[out] byteMask "Bits masking out bytes of specific address from comparison. When high, 2320 * the associated address byte will be ignored. e.g. LSB of byteMask=1 2321 * implies first byte received should not be compared." 2322 * @return EOK if success 2323 * @return ENOTSUP if no specific address registers available 2324 * @return EINVAL if invalid parameter 2325 */ 2326 uint32_t (*getSpecificAddr)(void* pD, uint8_t addrNum, CEDI_MacAddress* addr, uint8_t* specFilterType, uint8_t* byteMask); 2327 2328 /** 2329 * Set the specific address 1 mask register to the given value, 2330 * allowing address matching against a portion of the specific 2331 * address 1 register 2332 * @param[in] mask pointer to the address mask value to write 2333 * @param[in] pD driver private state info specific to this instance 2334 * @return EOK if successful 2335 * @return ENOTSUP if CEDI_DesignCfg.num_spec_add_filters==0 2336 * @return EINVAL if mask equal NULL 2337 */ 2338 uint32_t (*setSpecificAddr1Mask)(void* pD, CEDI_MacAddress* mask); 2339 2340 /** 2341 * Get the value of specific address 1 mask register 2342 * @param[out] mask pointer to a 6-byte MAC address struct for returning the mask value 2343 * @param[in] pD driver private state info specific to this instance 2344 * @return EOK if successful 2345 * @return ENOTSUP if CEDI_DesignCfg.num_spec_add_filters==0 2346 * @return EINVAL if mask equal NULL 2347 */ 2348 uint32_t (*getSpecificAddr1Mask)(void* pD, CEDI_MacAddress* mask); 2349 2350 /** 2351 * Disable the specific address match stored at given register, by 2352 * writing 0 to lower address register 2353 * @param[in] addrNum - number of specific address filters, in range 1 - num_spec_add_filters 2354 * @param[in] pD - driver private state info specific to this instance 2355 * @return EOK if successful 2356 * @return ENOTSUP if (CEDI_DesignCfg.num_spec_add_filters==0) 2357 * @return EINVAL if ((addrNum==0) || (addrNum>CEDI_DesignCfg.num_spec_add_filters)) 2358 */ 2359 uint32_t (*disableSpecAddr)(void* pD, uint8_t addrNum); 2360 2361 /** 2362 * En/Disable Type ID match field of the specified register, and set 2363 * type Id value if enabling 2364 * @param[in] typeId the Type ID match value to write ignored if enable equal 0 2365 * @param[in] enable if =1 enables the type matching for this ID, if =0 then disables type matching for this ID 2366 * @param[in] matchSel number of TypeID Match register, range 1 - 4 2367 * @param[in] pD driver private state info specific to this instance 2368 * @return EOK if successful 2369 * @return EINVAL if matchSel invalid 2370 */ 2371 uint32_t (*setTypeIdMatch)(void* pD, uint8_t matchSel, uint16_t typeId, uint8_t enable); 2372 2373 /** 2374 * Read the specified Type ID match register settings 2375 * @param[out] typeId pointer for returning the Type ID match value read ignored if disabled 2376 * @param[out] enable "pointer for returning enabled status: equal 1 if typeId matching is 2377 * enabled for this register, equal 0 if disabled" 2378 * @param[in] matchSel number of TypeID Match register, range 1 - 4 2379 * @param[in] pD driver private state info specific to this instance 2380 * @return EOK if successful 2381 * @return EINVAL if matchSel invalid 2382 */ 2383 uint32_t (*getTypeIdMatch)(void* pD, uint8_t matchSel, uint16_t* typeId, uint8_t* enable); 2384 2385 /** 2386 * En/disable reception of unicast frames when hash register matched 2387 * @param[in] enable if =1 enables reception, if =0 then disables 2388 * @param[in] pD driver private state info specific to this instance 2389 */ 2390 void (*setUnicastEnable)(void* pD, uint8_t enable); 2391 2392 /** 2393 * Return state of unicast frame matching 2394 * @param[out] enable equal 1 if reception enabled, equal 0 if disabled 2395 * @param[in] pD driver private state info specific to this instance 2396 * @return EOK for success 2397 * @return EINVAL for invalid pointer 2398 */ 2399 uint32_t (*getUnicastEnable)(void* pD, uint8_t* enable); 2400 2401 /** 2402 * En/disable reception of multicast frames when hash register 2403 * matched 2404 * @param[in] enable if =1 enables, if =0 then disables 2405 * @param[in] pD driver private state info specific to this instance 2406 */ 2407 void (*setMulticastEnable)(void* pD, uint8_t enable); 2408 2409 /** 2410 * Return state of multicast frame matching 2411 * @param[out] enable equal 1 if enabled, equal 0 if disabled 2412 * @param[in] pD driver private state info specific to this instance 2413 * @return EOK for success 2414 * @return EINVAL for invalid pointer 2415 */ 2416 uint32_t (*getMulticastEnable)(void* pD, uint8_t* enable); 2417 2418 /** 2419 * Dis/Enable receipt of broadcast frames 2420 * @param[in] pD driver private state info specific to this instance 2421 * @param[in] reject if =0 broadcasts are accepted, if =1 they are rejected. 2422 */ 2423 void (*setNoBroadcast)(void* pD, uint8_t reject); 2424 2425 /** 2426 * Return broadcast rejection setting 2427 * @param[in] pD driver private state info specific to this instance 2428 * @param[out] reject returns 0 if broadcasts are accepted, 1 if they are rejected 2429 * @return EOK for success 2430 * @return EINVAL for invalid pointer 2431 */ 2432 uint32_t (*getNoBroadcast)(void* pD, uint8_t* reject); 2433 2434 /** 2435 * En/Disable receipt of only frames which have been VLAN tagged 2436 * @param[in] enable if =1 reject non-VLAN-tagged frames, if =0 then accept 2437 * @param[in] pD driver private state info specific to this instance 2438 */ 2439 void (*setVlanOnly)(void* pD, uint8_t enable); 2440 2441 /** 2442 * Return VLAN-tagged filter setting 2443 * @param[out] enable returns 1 if non-VLAN-tagged frames rejected 2444 * @param[in] pD driver private state info specific to this instance 2445 * @return EOK for success 2446 * @return EINVAL for invalid pointer 2447 */ 2448 uint32_t (*getVlanOnly)(void* pD, uint8_t* enable); 2449 2450 /** 2451 * En/Disable stacked VLAN processing mode. 2452 * @param[in] enable if =1 enables stacked VLAN processing, if =0 disables it 2453 * @param[in] pD driver private state info specific to this instance 2454 * @param[in] vlanType sets user defined VLAN type for matching first VLAN tag. Ignored if enable equal 0. 2455 */ 2456 void (*setStackedVlanReg)(void* pD, uint8_t enable, uint16_t vlanType); 2457 2458 /** 2459 * Reads stacked VLAN register settings. 2460 * @param[out] enable pointer for returning Enabled field equal 1 if enabled equal 0 if disabled. 2461 * @param[in] pD driver private state info specific to this instance 2462 * @param[out] vlanType pointer for returning VLAN type field 2463 */ 2464 void (*getStackedVlanReg)(void* pD, uint8_t* enable, uint16_t* vlanType); 2465 2466 /** 2467 * En/Disable copy all frames mode 2468 * @param[in] enable if =1 enables copy all frames mode, if =0 then this is disabled 2469 * @param[in] pD driver private state info specific to this instance 2470 */ 2471 void (*setCopyAllFrames)(void* pD, uint8_t enable); 2472 2473 /** 2474 * Get "copy all" setting 2475 * @param[out] enable equal 1 if copy all frames mode enabled equal 0 if this is disabled 2476 * @param[in] pD driver private state info specific to this instance 2477 * @return EOK for success 2478 * @return EINVAL for invalid pointer 2479 */ 2480 uint32_t (*getCopyAllFrames)(void* pD, uint8_t* enable); 2481 2482 /** 2483 * Set the hash address register. 2484 * @param[in] hAddrBot least significant 32 bits of hash register 2485 * @param[in] hAddrTop most significant 32 bits of hash register 2486 * @param[in] pD driver private state info specific to this instance 2487 * @return EOK for success 2488 * @return EINVAL if pD equal NULL 2489 */ 2490 uint32_t (*setHashAddr)(void* pD, uint32_t hAddrTop, uint32_t hAddrBot); 2491 2492 /** 2493 * Read the hash address register. 2494 * @param[out] hAddrBot pointer for returning least significant 32 bits of hash register 2495 * @param[out] hAddrTop pointer for returning most significant 32 bits of hash register 2496 * @param[in] pD driver private state info specific to this instance 2497 * @return EOK for success 2498 * @return EINVAL if any parameter equal NULL 2499 */ 2500 uint32_t (*getHashAddr)(void* pD, uint32_t* hAddrTop, uint32_t* hAddrBot); 2501 2502 /** 2503 * Enable/disable discard of frames with length shorter than given in 2504 * length field 2505 * @param[in] enable if =1 then enable, if =0 then disable 2506 * @param[in] pD driver private state info specific to this instance 2507 */ 2508 void (*setLenErrDiscard)(void* pD, uint8_t enable); 2509 2510 /** 2511 * Read enable/disable status for discard of frames with length 2512 * shorter than given in length field. 2513 * @param[out] enable equal 1 if enabled, equal 0 if disabled 2514 * @param[in] pD driver private state info specific to this instance 2515 * @return EOK for success 2516 * @return EINVAL for invalid pointer 2517 */ 2518 uint32_t (*getLenErrDiscard)(void* pD, uint8_t* enable); 2519 2520 /** 2521 * Read numbers of screener, ethtype & compare registers 2522 * @param[out] regNums points to a CEDI_NumScreeners struct for returning the numbers of registers 2523 * @param[in] pD driver private state info specific to this instance 2524 * @return EOK if successful 2525 * @return EINVAL if parameter invalid 2526 */ 2527 uint32_t (*getNumScreenRegs)(void* pD, CEDI_NumScreeners* regNums); 2528 2529 /** 2530 * Write Rx frame matching values to a Type 1 screening register, for 2531 * allocating to a priority queue. 2532 * @param[in] regNum Type 1 register number, range 0 to CEDI_DesignCfg.num_type1_screeners-1 2533 * @param[in] regVals points to a CEDI_T1Screen struct with the match parameters to be written 2534 * @param[in] pD driver private state info specific to this instance 2535 * @return EOK if successful 2536 * @return EINVAL if parameter invalid 2537 */ 2538 uint32_t (*setType1ScreenReg)(void* pD, uint8_t regNum, CEDI_T1Screen* regVals); 2539 2540 /** 2541 * Read Rx frame matching values from a Type1 screening register 2542 * @param[in] regNum Type 1 register number, range 0 to CEDI_DesignCfg.num_type1_screeners-1 2543 * @param[out] regVals points to a CEDI_T1Screen struct for returning the match parameters 2544 * @param[in] pD driver private state info specific to this instance 2545 * @return EOK if successful 2546 * @return EINVAL if parameter invalid 2547 */ 2548 uint32_t (*getType1ScreenReg)(void* pD, uint8_t regNum, CEDI_T1Screen* regVals); 2549 2550 /** 2551 * Write Rx frame matching values to a Type 2 screening register, for 2552 * allocating to a priority queue. 2553 * @param[in] regNum Type 2 register number, range 0 to CEDI_DesignCfg.num_type2_screeners-1 2554 * @param[in] regVals points to a CEDI_T2Screen struct with the match parameters to be written 2555 * @param[in] pD driver private state info specific to this instance 2556 * @return EOK if successful 2557 * @return EINVAL if parameter invalid 2558 */ 2559 uint32_t (*setType2ScreenReg)(void* pD, uint8_t regNum, CEDI_T2Screen* regVals); 2560 2561 /** 2562 * Read Rx frame matching values from a Type 2 screening register 2563 * @param[in] regNum Type 2 register number, range 0 to CEDI_DesignCfg.num_type2_screeners-1 2564 * @param[out] regVals points to a CEDI_T2Screen struct for returning the match parameters 2565 * @param[in] pD driver private state info specific to this instance 2566 * @return EOK if successful 2567 * @return EINVAL if parameter invalid 2568 */ 2569 uint32_t (*getType2ScreenReg)(void* pD, uint8_t regNum, CEDI_T2Screen* regVals); 2570 2571 /** 2572 * Write the ethertype compare value at the given index in the 2573 * Ethertype registers 2574 * @param[in] index Type 2 ethertype register number, range 0 to CEDI_DesignCfg.num_scr2_ethtype_regs-1 2575 * @param[in] eTypeVal Ethertype compare value to write 2576 * @param[in] pD driver private state info specific to this instance 2577 * @return EOK if successful 2578 * @return EINVAL if parameter invalid 2579 */ 2580 uint32_t (*setType2EthertypeReg)(void* pD, uint8_t index, uint16_t eTypeVal); 2581 2582 /** 2583 * Read the ethertype compare value at the given index in the 2584 * Ethertype registers 2585 * @param[in] index Type 2 ethertype register number, range 0 to CEDI_DesignCfg.num_scr2_ethtype_regs-1 2586 * @param[out] eTypeVal pointer for returning the Ethertype compare value 2587 * @param[in] pD driver private state info specific to this instance 2588 * @return EOK if successful 2589 * @return EINVAL if parameter invalid 2590 */ 2591 uint32_t (*getType2EthertypeReg)(void* pD, uint8_t index, uint16_t* eTypeVal); 2592 2593 /** 2594 * Write the compare value at the given index in the Type 2 compare 2595 * register 2596 * @param[in] index Type 2 compare register number, range 0 to CEDI_DesignCfg.num_scr2_compare_regs-1 2597 * @param[in] regVals points to a CEDI_T2Compare struct with the compare parameters to be written 2598 * @param[in] pD driver private state info specific to this instance 2599 * @return EOK if successful 2600 * @return EINVAL if parameter invalid 2601 */ 2602 uint32_t (*setType2CompareReg)(void* pD, uint8_t index, CEDI_T2Compare* regVals); 2603 2604 /** 2605 * Read the compare value at the given index in the Type 2 compare 2606 * register 2607 * @param[in] index Type 2 compare register number, range 0 to CEDI_DesignCfg.num_scr2_compare_regs-1 2608 * @param[out] regVals points to a CEDI_T2Compare struct for returning the compare parameters 2609 * @param[in] pD driver private state info specific to this instance 2610 * @return EOK if successful 2611 * @return EINVAL if parameter invalid 2612 */ 2613 uint32_t (*getType2CompareReg)(void* pD, uint8_t index, CEDI_T2Compare* regVals); 2614 2615 /** 2616 * Enable/disable pausing after valid non-zero (non-PFC) pause frame 2617 * received 2618 * @param[in] enable if =1 then enable, if =0 then disable 2619 * @param[in] pD driver private state info specific to this instance 2620 */ 2621 void (*setPauseEnable)(void* pD, uint8_t enable); 2622 2623 /** 2624 * Read enable/disable of pausing after valid non-zero (non-PFC) 2625 * pause frame received. 2626 * @param[out] enable equal 1 if enabled, equal 0 if disabled 2627 * @param[in] pD driver private state info specific to this instance 2628 * @return EOK for success 2629 * @return EINVAL for invalid pointer 2630 */ 2631 uint32_t (*getPauseEnable)(void* pD, uint8_t* enable); 2632 2633 /** 2634 * Transmit a normal pause frame 2635 * @param[in] pD driver private state info specific to this instance 2636 */ 2637 void (*txPauseFrame)(void* pD); 2638 2639 /** 2640 * Transmit a pause frame with zero quantum value 2641 * @param[in] pD driver private state info specific to this instance 2642 */ 2643 void (*txZeroQPause)(void* pD); 2644 2645 /** 2646 * Return the current value of received pause quantum 2647 * @param[out] value returns transmit pause quantum value 2648 * @param[in] pD driver private state info specific to this instance 2649 * @return EOK for success 2650 * @return EINVAL for invalid pointer 2651 */ 2652 uint32_t (*getRxPauseQuantum)(void* pD, uint16_t* value); 2653 2654 /** 2655 * Set the pause quantum value to use when transmitting non-zero 2656 * quantum pause frame. 2657 * @param[in] qpriority quantum priority, the priority for the pause quantum 2658 * @param[in] value transmit pause quantum value 2659 * @param[in] pD driver private state info specific to this instance 2660 * @return EOK for success 2661 * @return EINVAL if invalid parameter 2662 */ 2663 uint32_t (*setTxPauseQuantum)(void* pD, uint16_t value, uint8_t qpriority); 2664 2665 /** 2666 * Read the non-zero transmit pause quantum value 2667 * @param[in] qpriority quantum priority,the priority for the pause quantum 2668 * @param[out] value returns transmit pause quantum value 2669 * @param[in] pD driver private state info specific to this instance 2670 * @return EOK for success 2671 * @return EINVAL if invalid parameter 2672 */ 2673 uint32_t (*getTxPauseQuantum)(void* pD, uint16_t* value, uint8_t qpriority); 2674 2675 /** 2676 * Disable/Enable copying of valid Rx pause frames to memory. 2677 * @param[in] disable if =1 disable, if =0 enable 2678 * @param[in] pD driver private state info specific to this instance 2679 */ 2680 void (*setCopyPauseDisable)(void* pD, uint8_t disable); 2681 2682 /** 2683 * Read disable/enable state for copying of valid Rx pause frames to 2684 * memory. 2685 * @param[out] disable if =1 disabled, if =0 enabled 2686 * @param[in] pD driver private state info specific to this instance 2687 * @return EOK for success 2688 * @return EINVAL for invalid pointer 2689 */ 2690 uint32_t (*getCopyPauseDisable)(void* pD, uint8_t* disable); 2691 2692 /** 2693 * Enable/disable PFC negotiation and reception of priority based 2694 * pause frames. 2695 * @param[in] enable if =1 enable, if =0 then disable 2696 * @param[in] pD driver private state info specific to this instance 2697 */ 2698 void (*setPfcPriorityBasedPauseRx)(void* pD, uint8_t enable); 2699 2700 /** 2701 * Read enable/disable state of reception for priority based pause 2702 * frames, and negotiation state. value can be decoded with two 2703 * constants: if (OR with CEDI_PFC_PBP_RX_EN) not equal 0 then 2704 * PFC priority based pause frame Rx enabled if (OR with 2705 * CEDI_PFC_PBP_NEG) not equal 0 then PFC priority based pause 2706 * has been negotiated 2707 * @param[out] enable returns combined enabled Rx state and negotiated state 2708 * @param[in] pD driver private state info specific to this instance 2709 * @return EOK for success 2710 * @return EINVAL for invalid pointer 2711 */ 2712 uint32_t (*getPfcPriorityBasedPauseRx)(void* pD, uint8_t* enable); 2713 2714 /** 2715 * Transmit PFC Priority Based Pause Frame, taking field values as 2716 * defined by setTxPfcPauseFrameFields. 2717 * @param[in] pD driver private state info specific to this instance 2718 * @return EOK for success 2719 * @return EINVAL if NULL pointer or not using full duplex mode or if transmission is disabled (mechanical success) 2720 */ 2721 uint32_t (*txPfcPriorityBasedPause)(void* pD); 2722 2723 /** 2724 * Set priority enable vector and zero quantum select vector fields 2725 * of the Tx PFC Pause Frame (see User Guide for description) 2726 * @param[in] priEnVector written to priority enable vector of PFC priority based pause frame 2727 * @param[in] zeroQSelVector selects pause quantum fields to set to zero 2728 * @param[in] pD driver private state info specific to this instance 2729 * @return EOK if successful 2730 * @return EINVAL if pD equal NULL 2731 */ 2732 uint32_t (*setTxPfcPauseFrameFields)(void* pD, uint8_t priEnVector, uint8_t zeroQSelVector); 2733 2734 /** 2735 * Read priority enable vector and zero quantum select vector fields 2736 * selected by setTxPfcPauseFrameFields. 2737 * @param[out] priEnVector pointer for returning priority enable vector to be written to PFC priority based pause frame 2738 * @param[out] zeroQSelVector pointer for returning vector selecting pause quantum fields to set to zero 2739 * @param[in] pD driver private state info specific to this instance 2740 * @return EOK if successful 2741 * @return EINVAL if any parameter equal NULL 2742 */ 2743 uint32_t (*getTxPfcPauseFrameFields)(void* pD, uint8_t* priEnVector, uint8_t* zeroQSelVector); 2744 2745 /** 2746 * Set Enable bit for multiple PFC pause quantums, one per pause 2747 * priority. 2748 * @param[in] enMultiPfcPause set this field to 1 to enable multiple PFC pause quantums. 2749 * @param[in] pD driver private state info specific to this instance 2750 * @return EOK if successful 2751 * @return EINVAL if pD equal NULL 2752 */ 2753 uint32_t (*setEnableMultiPfcPauseQuantum)(void* pD, uint8_t enMultiPfcPause); 2754 2755 /** 2756 * Get the Enable bit for multiple PFC pause quantums, one per pause 2757 * priority. 2758 * @param[out] enMultiPfcPause equal 1 if multiple PFC pause quantums enabled 2759 * @param[in] pD driver private state info specific to this instance 2760 * @return EOK if successful 2761 * @return EINVAL if any parameter equal NULL 2762 */ 2763 uint32_t (*getEnableMultiPfcPauseQuantum)(void* pD, uint8_t* enMultiPfcPause); 2764 2765 /** 2766 * Enable/disable detection of unicast PTP frames. 2767 * @param[in] enable if =1 enable, if =0 then disable 2768 * @param[in] pD driver private state info specific to this instance 2769 */ 2770 void (*setUnicastPtpDetect)(void* pD, uint8_t enable); 2771 2772 /** 2773 * Read enable/disable state for detection of unicast PTP frames. 2774 * @param[out] enable equal 1 if enabled, equal 0 if disabled 2775 * @param[in] pD driver private state info specific to this instance 2776 * @return EOK for success 2777 * @return EINVAL for invalid pointer 2778 */ 2779 uint32_t (*getUnicastPtpDetect)(void* pD, uint8_t* enable); 2780 2781 /** 2782 * Set Unicast IP destination address for detection of PTP Rx frames. 2783 * Unicast PTP frame recognition must be disabled. 2784 * @param[in] rxAddr IP destination address 2785 * @param[in] pD driver private state info specific to this instance 2786 * @return EOK if successful 2787 * @return ENOTSUP if unicast PTP frame recognition enabled 2788 * @return EINVAL if pD = NULL 2789 */ 2790 uint32_t (*setPtpRxUnicastIpAddr)(void* pD, uint32_t rxAddr); 2791 2792 /** 2793 * Read Unicast IP destination address for detection of PTP Rx 2794 * frames. 2795 * @param[out] rxAddr returns IP destination address 2796 * @param[in] pD driver private state info specific to this instance 2797 * @return EOK for success 2798 * @return EINVAL for invalid pointer 2799 */ 2800 uint32_t (*getPtpRxUnicastIpAddr)(void* pD, uint32_t* rxAddr); 2801 2802 /** 2803 * Set Unicast IP destination address for detection of PTP Tx frames. 2804 * Unicast PTP frame recognition must be disabled. 2805 * @param[in] txAddr IP destination address 2806 * @param[in] pD driver private state info specific to this instance 2807 * @return EOK if successful 2808 * @return ENOTSUP if unicast PTP frame recognition enabled 2809 * @return EINVAL if pD = NULL 2810 */ 2811 uint32_t (*setPtpTxUnicastIpAddr)(void* pD, uint32_t txAddr); 2812 2813 /** 2814 * Returns Unicast IP destination address for detection of PTP Tx 2815 * frames. 2816 * @param[out] txAddr returns IP destination address 2817 * @param[in] pD driver private state info specific to this instance 2818 * @return EOK for success 2819 * @return EINVAL for invalid pointer 2820 */ 2821 uint32_t (*getPtpTxUnicastIpAddr)(void* pD, uint32_t* txAddr); 2822 2823 /** 2824 * Write 1588 timer registers. 2825 * @param[in] pD driver private state info specific to this instance 2826 * @param[in] time pointer to CEDI_1588TimerVal struct with values to write to timer registers 2827 * @return EOK for success 2828 * @return ENOTSUP if tsu equal 0 2829 * @return EINVAL if either parameter equal NULL, or nanosecs >0x3FFFFFFF 2830 */ 2831 uint32_t (*set1588Timer)(void* pD, CEDI_1588TimerVal* time); 2832 2833 /** 2834 * Read 1588 timer registers. 2835 * @param[in] pD driver private state info specific to this instance 2836 * @param[out] time pointer to a CEDI_1588TimerVal struct for returning timer registers contents 2837 * @return EOK for success 2838 * @return ENOTSUP if tsu equal 0 2839 * @return EINVAL if either parameter NULL 2840 */ 2841 uint32_t (*get1588Timer)(void* pD, CEDI_1588TimerVal* time); 2842 2843 /** 2844 * Adjust the 1588 timer by adding or subtracting the specified 2845 * number of nanoseconds. 2846 * @param[in] nSecAdjust nanoseconds to adjust timer by: - if =1, enable time stamp storing, else disable (restore normal operation) 2847 * @param[in] pD driver private state info specific to this instance 2848 * @return EOK for success 2849 * @return ENOTSUP if tsu equal 0 2850 * @return EINVAL if invalid parameter 2851 */ 2852 uint32_t (*adjust1588Timer)(void* pD, int32_t nSecAdjust); 2853 2854 /** 2855 * Set 1588 timer initial and alternative increments, and when to 2856 * switch to alternative increment. The initial, or normal, increment 2857 * is how many nanoseconds are added to the timer value on each pclk 2858 * or tsu_clk cycle (if tsu_clk equal 1 in DesignCfgReg5). If 2859 * altIncCount>0, after altIncCount increments the altNanoSInc value 2860 * is used for one cycle, then the increment returns to the initial 2861 * value. See EMAC User Guide [01] for further description. 2862 * @param[in] incSettings pointer to CEDI_TimerIncrement struct for defining how much to increment the timer each clock cycle 2863 * @param[in] pD driver private state info specific to this instance 2864 * @return EOK for success 2865 * @return ENOTSUP if tsu equal 0 2866 * @return EINVAL if either parameter equal NULL 2867 */ 2868 uint32_t (*set1588TimerInc)(void* pD, CEDI_TimerIncrement* incSettings); 2869 2870 /** 2871 * Read 1588 timer increment settings. 2872 * @param[out] incSettings pointer to a CEDI_TimerIncrement struct for returning how the timer increment values 2873 * @param[in] pD driver private state info specific to this instance 2874 * @return EOK for success 2875 * @return ENOTSUP if tsu equal 0 2876 */ 2877 uint32_t (*get1588TimerInc)(void* pD, CEDI_TimerIncrement* incSettings); 2878 2879 /** 2880 * Write TSU timer comparison value. 2881 * @param[in] pD driver private state info specific to this instance 2882 * @param[in] time pointer to CEDI_TsuTimerVal struct with values to write to comparison registers 2883 * @return EOK for success 2884 * @return ENOTSUP if tsu equal 0, or nanosecs >0x003FFFFF 2885 */ 2886 uint32_t (*setTsuTimerCompVal)(void* pD, CEDI_TsuTimerVal* time); 2887 2888 /** 2889 * Read TSU timer comparison value. 2890 * @param[in] pD driver private state info specific to this instance 2891 * @param[out] time pointer to a CEDI_TsuTimerVal struct for returning comparison registers settings 2892 * @return EOK for success 2893 * @return ENOTSUP if tsu equal 0 2894 * @return EINVAL if either param equal NULL 2895 */ 2896 uint32_t (*getTsuTimerCompVal)(void* pD, CEDI_TsuTimerVal* time); 2897 2898 /** 2899 * Read 1588 timer value latched when SFD of PTP transmit primary 2900 * event crosses MII interface. 2901 * @param[in] pD driver private state info specific to this instance 2902 * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. 2903 * @return EOK for success 2904 * @return ENOTSUP if tsu equal 0 2905 */ 2906 uint32_t (*getPtpFrameTxTime)(void* pD, CEDI_1588TimerVal* time); 2907 2908 /** 2909 * Read 1588 timer value latched when SFD of PTP receive primary 2910 * event crosses MII interface. 2911 * @param[in] pD driver private state info specific to this instance 2912 * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. 2913 * @return EOK for success 2914 * @return ENOTSUP if tsu equal 0 2915 */ 2916 uint32_t (*getPtpFrameRxTime)(void* pD, CEDI_1588TimerVal* time); 2917 2918 /** 2919 * Read 1588 timer value latched when SFD of PTP transmit peer event 2920 * crosses MII interface. 2921 * @param[in] pD driver private state info specific to this instance 2922 * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. 2923 * @return EOK for success 2924 * @return ENOTSUP if tsu equal 0 2925 */ 2926 uint32_t (*getPtpPeerFrameTxTime)(void* pD, CEDI_1588TimerVal* time); 2927 2928 /** 2929 * Read 1588 timer value latched when SFD of PTP receive peer event 2930 * crosses MII interface. 2931 * @param[in] pD driver private state info specific to this instance 2932 * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. 2933 * @return EOK for success 2934 * @return ENOTSUP if tsu equal 0 2935 */ 2936 uint32_t (*getPtpPeerFrameRxTime)(void* pD, CEDI_1588TimerVal* time); 2937 2938 /** 2939 * Read nanoseconds and seconds (lo & hi words) from 1588 Timer Sync 2940 * Strobe registers 2941 * @param[in] pD driver private state info specific to this instance 2942 * @param[out] time pointer to a CEDI_1588TimerVal struct for returning latched timer registers contents. 2943 * @return EOK for success 2944 * @return ENOTSUP if tsu equal 0 2945 */ 2946 uint32_t (*get1588SyncStrobeTime)(void* pD, CEDI_1588TimerVal* time); 2947 2948 /** 2949 * Enable/disable use of external time stamp port. 2950 * @param[in] enable if =1 then enable, if =0 then disable 2951 * @param[in] pD driver private state info specific to this instance 2952 * @return EOK for success 2953 * @return ENOTSUP if ext_tsu_timer equal 0 2954 * @return EINVAL if invalid parameter 2955 */ 2956 uint32_t (*setExtTsuPortEnable)(void* pD, uint8_t enable); 2957 2958 /** 2959 * Read enable status for use of external time stamp port. 2960 * @param[out] enable equal 1 if enabled, equal 0 if disabled 2961 * @param[in] pD driver private state info specific to this instance 2962 * @return EOK for success 2963 * @return EINVAL for invalid pointer 2964 */ 2965 uint32_t (*getExtTsuPortEnable)(void* pD, uint8_t* enable); 2966 2967 /** 2968 * Enable/disable one-step Tx sync mode in which timestamp field of 2969 * every transmitted 1588 sync frame is replaced with the current TSU 2970 * timestamp. 2971 * @param[in] enable if =1 then enable, if =0 then disable 2972 * @param[in] pD driver private state info specific to this instance 2973 * @return EOK if successful 2974 * @return ENOTSUP if tsu equal 0 2975 * @return EINVAL if invalid parameter 2976 */ 2977 uint32_t (*set1588OneStepTxSyncEnable)(void* pD, uint8_t enable); 2978 2979 /** 2980 * Read enable/disable state of one-step 1588 Tx sync mode. 2981 * @param[out] enable pointer for returning state equal 1 if enabled equal 0 if disabled. 2982 * @param[in] pD driver private state info specific to this instance 2983 * @return EOK for success 2984 * @return EINVAL for invalid pointer 2985 */ 2986 uint32_t (*get1588OneStepTxSyncEnable)(void* pD, uint8_t* enable); 2987 2988 /** 2989 * Set the descriptor time stamp mode. 2990 * @param[in] txMode TX Descriptor timestamp insertion mode 2991 * @param[in] rxMode RX Descriptor timestamp insertion mode 2992 * @param[in] pD driver private state info specific to this instance 2993 * @return EOK for success 2994 * @return EINVAL if pD is NULL/parameters out of range 2995 */ 2996 uint32_t (*setDescTimeStampMode)(void* pD, CEDI_TxTsMode txMode, CEDI_RxTsMode rxMode); 2997 2998 /** 2999 * Get the descriptor time stamp mode. 3000 * @param[out] txMode TX Descriptor timestamp insertion mode 3001 * @param[out] rxMode RX Descriptor timestamp insertion mode 3002 * @param[in] pD driver private state info specific to this instance 3003 * @return EOK for success 3004 * @return EINVAL if pD is NULL 3005 */ 3006 uint32_t (*getDescTimeStampMode)(void* pD, CEDI_TxTsMode* txMode, CEDI_RxTsMode* rxMode); 3007 3008 /** 3009 * Enable/disable storing of nanoseconds field of Rx time stamp in 3010 * CRC field of received frame. 3011 * @param[in] enable if =1 then enable, if =0 then disable 3012 * @param[in] pD driver private state info specific to this instance 3013 * @return EOK for success 3014 * @return ENOTSUP if tsu equal 0 3015 */ 3016 uint32_t (*setStoreRxTimeStamp)(void* pD, uint8_t enable); 3017 3018 /** 3019 * Read Enable/disable state for storing nanoseconds Rx time stamp in 3020 * CRC field of received frame. 3021 * @param[out] enable equal 1 if time stamp storing enabled equal 0 if disabled 3022 * @param[in] pD driver private state info specific to this instance 3023 * @return EOK for success 3024 * @return EINVAL for invalid pointer 3025 */ 3026 uint32_t (*getStoreRxTimeStamp)(void* pD, uint8_t* enable); 3027 3028 /** 3029 * Does a PCS reset. After this, software can monitor getPcsReady to 3030 * determine when this has finished. 3031 * @param[in] pD driver private state info specific to this instance 3032 * @return EOK for success 3033 * @return ENOTSUP if no_pcs defined 3034 */ 3035 uint32_t (*resetPcs)(void* pD); 3036 3037 /** 3038 * Read PCS software reset bit, which goes high when resetPcs is 3039 * called, and returns low when the reset has completed, provided PCS 3040 * is enabled. 3041 * @param[out] ready pointer for returning 1 when PCS ready, i.e. reset has gone low or 0 if still in reset. 3042 * @param[in] pD driver private state info specific to this instance 3043 * @return EOK for success 3044 * @return ENOTSUP if PCS not enabled 3045 * @return EINVAL for invalid pointer 3046 */ 3047 uint32_t (*getPcsReady)(void* pD, uint8_t* ready); 3048 3049 /** 3050 * Enables and restarts auto-negotiation after writing the specified 3051 * abilities to the auto-negotiation advertisement register. After 3052 * this, normal progress of auto-negotiation will lead to a lpPageRx 3053 * callback, which includes the ability register data received from 3054 * the link partner. 3055 * @param[in] advDat pointer to CEDI_AnAdvPage struct for setting the advertised abilities register 3056 * @param[in] pD driver private state info specific to this instance 3057 * @return EOK for success 3058 * @return ENOTSUP if no_pcs defined or in SGMII mode 3059 * @return EBUSY if auto-negotiation already in progress 3060 * @return EINVAL if NULL parameter, invalid struct fields or completion event not enabled 3061 */ 3062 uint32_t (*startAutoNegotiation)(void* pD, CEDI_AnAdvPage* advDat); 3063 3064 /** 3065 * Enable/disable PCS auto-negotiation functionality. If auto- 3066 * negotiation is in progress, disabling will halt it. If enabling 3067 * while underway, an error is returned. 3068 * @param[in] enable if =1 then enable, if =0 then disable 3069 * @param[in] pD driver private state info specific to this instance 3070 * @return EBUSY if enable = 1 when auto-negotiation is under way 3071 * @return EOK for success 3072 * @return ENOTSUP if in SGMII mode 3073 * @return EINVAL if pD equal NULL 3074 */ 3075 uint32_t (*setAutoNegEnable)(void* pD, uint8_t enable); 3076 3077 /** 3078 * Read enable/disable of PCS auto-negotiation functionality. 3079 * @param[out] enable pointer for returning state, equal 1 if enabled equal 0 if disabled. 3080 * @param[in] pD driver private state info specific to this instance 3081 * @return EOK for success 3082 * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) 3083 * @return EINVAL if NULL parameter 3084 */ 3085 uint32_t (*getAutoNegEnable)(void* pD, uint8_t* enable); 3086 3087 /** 3088 * If auto-negotiation is enabled, this reads the status of 3089 * connection to link partner, else it reads the synchronisation 3090 * status. If link goes down, status remains low until this is read. 3091 * The driver will remember the low condition when read from register 3092 * (by this or other PCS functions), and this will only update to 3093 * current state when this function is called (i.e. after reading the 3094 * value to return), or when link status is reported via the 3095 * AnComplete callback. Therefore, if getLinkStatus reports link 3096 * down, the function should be called again if the current status is 3097 * required. 3098 * @param[out] status pointer returning 1 if link up (or sync) 0 if link down. 3099 * @param[in] pD driver private state info specific to this instance 3100 * @return EOK for success 3101 * @return EINVAL for invalid pointer 3102 */ 3103 uint32_t (*getLinkStatus)(void* pD, uint8_t* status); 3104 3105 /** 3106 * Read the remote fault status reported by link partner. Driver will 3107 * remember the high state when read from register, and only reset 3108 * when this function is called. 3109 * @param[out] status pointer returning 1 if remote fault indicated by link partner, 0 otherwise. 3110 * @param[in] pD driver private state info specific to this instance 3111 * @return EOK for success 3112 * @return EINVAL for invalid pointer 3113 */ 3114 uint32_t (*getAnRemoteFault)(void* pD, uint8_t* status); 3115 3116 /** 3117 * Read the auto-negotiation complete status. Completion will also be 3118 * reported by the anComplete callback, provided the 3119 * CEDI_EV_PCS_AN_COMPLETE interrupt is enabled. 3120 * @param[out] status pointer returning 1 if auto-negotiation complete 0 if incomplete. 3121 * @param[in] pD driver private state info specific to this instance 3122 * @return EOK for success 3123 * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) 3124 * @return EINVAL for invalid pointer 3125 */ 3126 uint32_t (*getAnComplete)(void* pD, uint8_t* status); 3127 3128 /** 3129 * Set advertisement base page fields. 3130 * @param[in] advDat - pointer to advertisement register data 3131 * @param[in] pD driver private state info specific to this instance 3132 * @return EOK for success 3133 * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) 3134 * @return EINVAL if NULL parameter 3135 */ 3136 uint32_t (*setAnAdvPage)(void* pD, CEDI_AnAdvPage* advDat); 3137 3138 /** 3139 * Get advertisement base page fields, extracted into a 3140 * CEDI_AnAdvPage struct 3141 * @param[out] advDat - pointer for returning the advertisement register data 3142 * @param[in] pD driver private state info specific to this instance 3143 * @return EOK for success 3144 * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) 3145 * @return EINVAL if NULL parameter 3146 */ 3147 uint32_t (*getAnAdvPage)(void* pD, CEDI_AnAdvPage* advDat); 3148 3149 /** 3150 * Get link partner ability page fields, extracted into a 3151 * CEDI_LpAbilityPage struct. This is a union of two different 3152 * structs, since the format depends on whether SGMII mode is in use 3153 * (network config bit 27) 3154 * @param[out] lpAbl pointer for returning the link partner ability data 3155 * @param[in] pD driver private state info specific to this instance 3156 * @return EOK for success 3157 * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) 3158 * @return EINVAL if NULL parameter 3159 */ 3160 uint32_t (*getLpAbilityPage)(void* pD, CEDI_LpAbilityPage* lpAbl); 3161 3162 /** 3163 * Read flag from auto-negotiation expansion register, indicating a 3164 * base or next page has been received from the link partner. 3165 * @param[in] pD driver private state info specific to this instance 3166 * @return 1 if page received and no_pcs not defined 3167 * @return 0 if page not received or invalid pointer 3168 */ 3169 uint32_t (*getPageRx)(void* pD); 3170 3171 /** 3172 * Set next page register fields for auto-negotiation with fields 3173 * specified in a CEDI_AnNextPage struct. 3174 * @param[in] npDat - pointer to struct containing next page data to transmit 3175 * @param[in] pD driver private state info specific to this instance 3176 * @return EOK for success 3177 * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) 3178 * @return EINVAL if NULL parameter or invalid struct fields 3179 */ 3180 uint32_t (*setNextPageTx)(void* pD, CEDI_AnNextPage* npDat); 3181 3182 /** 3183 * Read next page register field data. 3184 * @param[out] npDat - pointer to struct for returning next page register data. 3185 * @param[in] pD driver private state info specific to this instance 3186 * @return EOK for success 3187 * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) 3188 * @return EINVAL if NULL parameter 3189 */ 3190 uint32_t (*getNextPageTx)(void* pD, CEDI_AnNextPage* npDat); 3191 3192 /** 3193 * Read next page data received from link partner. 3194 * @param[out] npDat - pointer to CEDI_LpNextPage struct for returning link partner next page data. 3195 * @param[in] pD driver private state info specific to this instance 3196 * @return EOK for success 3197 * @return ENOTSUP if (CEDI_DesignCfg.no_pcs==1) 3198 * @return EINVAL if NULL parameter 3199 */ 3200 uint32_t (*getLpNextPage)(void* pD, CEDI_LpNextPage* npDat); 3201 3202 /** 3203 * Get PCS PHY upper ID (= EMAC Module ID) & PCS PHY lower ID (= EMAC 3204 * Rev) 3205 * @param[in] pD driver private state info specific to this instance 3206 * @param[out] phyId composed of PCS PHY upper ID (= EMAC Module ID) in the upper 16 bits, and PCS PHY 3207 * lower ID (= EMAC Rev) in the lower 16 bits. 3208 * @return EOK for success 3209 * @return EINVAL for invalid pointer 3210 */ 3211 uint32_t (*getPhyId)(void* pD, uint32_t* phyId); 3212 3213 /** 3214 * Enable/disable MDIO interface 3215 * @param[in] enable if =1 enable MDIO interface, if =0 then disable it 3216 * @param[in] pD driver private state info specific to this instance 3217 */ 3218 void (*setMdioEnable)(void* pD, uint8_t enable); 3219 3220 /** 3221 * Get en/disable state of MDIO interface 3222 * @param[in] pD driver private state info specific to this instance 3223 * @return 1 if MDIO interface enabled 3224 * @return 0 if MDIO interface disabled or pD equal NULL, or NULL parameter 3225 */ 3226 uint32_t (*getMdioEnable)(void* pD); 3227 3228 /** 3229 * Initiate a write or set address operation on the MDIO interface. 3230 * Clause 45 devices require a call to set the register address (if 3231 * this is changing since last access), and then a write or read 3232 * operation. The command writes to the shift register, which starts 3233 * output on the MDIO interface. Write completion is signalled by the 3234 * phyManComplete callback, or by polling getMdioIdle. 3235 * @param[in] addrData register address (if CEDI_MDIO_FLG_SET_ADDR) or data to write 3236 * @param[in] phyAddr PHY address 3237 * @param[in] flags Combination of 2 bit-flags: if CEDI_MDIO_FLG_CLAUSE_45 present, specifies 3238 * clause 45 PHY (else clause 22); 3239 * if CEDI_MDIO_FLG_SET_ADDR present, specifies a set address operation (else 3240 * do a write operation) - if not clause 45, this will be ignored. 3241 * @param[in] pD driver private state info specific to this instance 3242 * @param[in] devReg device type (clause 45) or register address (clause 22) - enum CEDI_MdioDevType 3243 * is available to specify the device type 3244 */ 3245 void (*phyStartMdioWrite)(void* pD, uint8_t flags, uint8_t phyAddr, uint8_t devReg, uint16_t addrData); 3246 3247 /** 3248 * Initiate a read operation on the MDIO interface. If clause 45, 3249 * the register address will need to be set by a preceding 3250 * phyStartMdioWrite call, unless same as for last operation. 3251 * Completion is signalled by the phyManComplete callback, which will 3252 * return the read data by a pointer parameter. Alternatively polling 3253 * getMdioIdle will indicate when the operation completes, then 3254 * getMdioReadDat will return the data. 3255 * @param[in] phyAddr PHY address 3256 * @param[in] flags Combination of 2 bit-flags: if CEDI_MDIO_FLG_CLAUSE_45 present, 3257 * specifies clause 45 PHY (else clause 22); 3258 * If CEDI_MDIO_FLG_INC_ADDR present, and clause 45, then address will be 3259 * incremented after the read operation. 3260 * @param[in] pD driver private state info specific to this instance 3261 * @param[in] devReg device type (clause 45) or register address (clause 22) - enum CEDI_MdioDevType 3262 * is available to specify the device type 3263 */ 3264 void (*phyStartMdioRead)(void* pD, uint8_t flags, uint8_t phyAddr, uint8_t devReg); 3265 3266 /** 3267 * Get data read from the PHY during a read operation. 3268 * @param[out] readData PHY read data, from in lower 16 bits of maintenance register 3269 * @param[in] pD driver private state info specific to this instance 3270 * @return EOK for success 3271 * @return EINVAL for invalid pointer 3272 */ 3273 uint32_t (*getMdioReadData)(void* pD, uint16_t* readData); 3274 3275 /** 3276 * Read status of PHY management logic 3277 * @param[in] pD driver private state info specific to this instance 3278 * @return 1 for idle (mechanical success) 3279 * @return 0 for busy, or pD equal NULL 3280 */ 3281 uint32_t (*getMdioIdle)(void* pD); 3282 3283 /** 3284 * Copy the statistics registers contents into the statsRegs struct 3285 * reserved by client 3286 * @param[in] pD driver private state info specific to this instance 3287 * @return EOK for success 3288 * @return ENOTSUP if no_stats defined 3289 */ 3290 uint32_t (*readStats)(void* pD); 3291 3292 /** 3293 * Clear the statistics registers. 3294 * @param[in] pD driver private state info specific to this instance 3295 * @return EOK for success 3296 * @return ENOTSUP if no_stats defined 3297 */ 3298 uint32_t (*clearStats)(void* pD); 3299 3300 /** 3301 * Record snapshot of current statistics counts into snapshot 3302 * registers. 3303 * @param[in] pD driver private state info specific to this instance 3304 * @return EOK for success 3305 * @return ENOTSUP if no_snapshot or no_stats defined 3306 */ 3307 uint32_t (*takeSnapshot)(void* pD); 3308 3309 /** 3310 * Define action taken when statistics registers are read 3311 * @param[in] enable if =1 then enable, if =0 then disable 3312 * @param[in] pD driver private state info specific to this instance 3313 * @return EOK for success 3314 * @return ENOTSUP if no_snapshot or no_stats defined 3315 */ 3316 uint32_t (*setReadSnapshot)(void* pD, uint8_t enable); 3317 3318 /** 3319 * Read state of ReadSnapshot flag 3320 * @param[out] enable pointer for returning ReadSnapshot flag: if =1 then read 3321 * snapshot is enabled; if =0 registers will show current statistics 3322 * @param[in] pD driver private state info specific to this instance 3323 * @return EOK for success 3324 * @return ENOTSUP if no_snapshot or no_stats defined 3325 */ 3326 uint32_t (*getReadSnapshot)(void* pD, uint8_t* enable); 3327 3328 /** 3329 * Set Wake On LAN (WOL) register using CEDI_WakeOnLanReg struct 3330 * @param[in] regVals pointer to CEDI_WakeOnLanReg struct for register values to set 3331 * @param[in] pD driver private state info specific to this instance 3332 * @return EOK if successful 3333 * @return EINVAL if invalid parameter 3334 */ 3335 uint32_t (*setWakeOnLanReg)(void* pD, CEDI_WakeOnLanReg* regVals); 3336 3337 /** 3338 * Read Wake On LAN register using CEDI_WakeOnLanReg struct 3339 * @param[out] regVals pointer to CEDI_WakeOnLanReg struct for returning WOL register contents 3340 * @param[in] pD driver private state info specific to this instance 3341 * @return EOK if successful 3342 * @return EINVAL if invalid parameter 3343 */ 3344 uint32_t (*getWakeOnLanReg)(void* pD, CEDI_WakeOnLanReg* regVals); 3345 3346 /** 3347 * Enable/disable low power indication (LPI) transmission. 3348 * @param[in] enable if =1 then enable, if =0 then disable 3349 * @param[in] pD driver private state info specific to this instance 3350 * @return EOK if successful 3351 * @return EINVAL if invalid parameter 3352 */ 3353 uint32_t (*setLpiTxEnable)(void* pD, uint8_t enable); 3354 3355 /** 3356 * Get LPI transmission status 3357 * @param[out] enable equal 1 if enabled, equal 0 if disabled 3358 * @param[in] pD driver private state info specific to this instance 3359 * @return EOK for success 3360 * @return EINVAL for invalid parameter 3361 */ 3362 uint32_t (*getLpiTxEnable)(void* pD, uint8_t* enable); 3363 3364 /** 3365 * Read LPI transitions & time in both Tx and Rx directions. The 3366 * registers are all cleared on read. 3367 * @param[out] lpiStats pointer to a CEDI_LpiStats struct for returning the LPI statistics. 3368 * @param[in] pD driver private state info specific to this instance 3369 * @return EOK if successful 3370 * @return EINVAL if invalid parameter 3371 */ 3372 uint32_t (*getLpiStats)(void* pD, CEDI_LpiStats* lpiStats); 3373 3374 /** 3375 * Copies all design configuration register fields into a 3376 * CEDI_DesignCfg struct declared by client software. 3377 * @param[out] hwCfg pointer to struct for receiving configuration data 3378 * @param[in] pD driver private state info specific to this instance 3379 * @return EOK for success 3380 * @return EINVAL if any parameters =NULL 3381 */ 3382 uint32_t (*getDesignConfig)(void* pD, CEDI_DesignCfg* hwCfg); 3383 3384 /** 3385 * Enable/disable writing to the statistics registers for debugging. 3386 * @param[in] enable if =1 enable writing, if =0 then disable 3387 * @param[in] pD driver private state info specific to this instance 3388 * @return EOK for success 3389 * @return EINVAL if no_stats defined 3390 */ 3391 uint32_t (*setWriteStatsEnable)(void* pD, uint8_t enable); 3392 3393 /** 3394 * Read enable/disable state of writing to the statistics registers 3395 * for debugging. 3396 * @param[out] enable pointer for returning state: equal 1 if writing enabled equal 0 if disabled. 3397 * @param[in] pD driver private state info specific to this instance 3398 * @return EOK for success 3399 * @return EINVAL if no_stats defined 3400 */ 3401 uint32_t (*getWriteStatsEnable)(void* pD, uint8_t* enable); 3402 3403 /** 3404 * Increments all statistics registers contents by 1 for debugging. 3405 * @param[in] pD driver private state info specific to this instance 3406 * @return EOK for success 3407 * @return EINVAL if no_stats defined 3408 */ 3409 uint32_t (*incStatsRegs)(void* pD); 3410 3411 /** 3412 * Enable/disable back pressure to force collisions an all received 3413 * frames in 10M or 100M half duplex mode. 3414 * @param[in] enable if =1 enable back pressure, if =0 then disable 3415 * @param[in] pD driver private state info specific to this instance 3416 */ 3417 void (*setRxBackPressure)(void* pD, uint8_t enable); 3418 3419 /** 3420 * Read Enable/disable state of back pressure to force collisions an 3421 * all received frames in 10M or 100M half duplex mode. 3422 * @param[out] enable equal 1 if enabled, equal 0 if disabled 3423 * @param[in] pD driver private state info specific to this instance 3424 * @return EOK for success 3425 * @return EINVAL for invalid pointer 3426 */ 3427 uint32_t (*getRxBackPressure)(void* pD, uint8_t* enable); 3428 3429 /** 3430 * Enable/disable forcing collisions by PCS on transmit. 3431 * @param[in] enable if =1 enable forcing collisions, if =0 then disable 3432 * @param[in] pD driver private state info specific to this instance 3433 * @return EOK for success 3434 * @return ENOTSUP if no_pcs defined 3435 */ 3436 uint32_t (*setCollisionTest)(void* pD, uint8_t enable); 3437 3438 /** 3439 * Read enable/disable state for forcing collisions by PCS on 3440 * transmit. 3441 * @param[out] enable pointer for returning state: equal 1 if forcing collisions enabled, equal 0 if disabled. 3442 * @param[in] pD driver private state info specific to this instance 3443 * @return EOK for success 3444 * @return ENOTSUP if no_pcs defined 3445 */ 3446 uint32_t (*getCollisionTest)(void* pD, uint8_t* enable); 3447 3448 /** 3449 * Enable/disable functionality to set backoff between collisions to 3450 * one slot time. This helps test for too many retries, and also 3451 * shortens pause countdown time in pause frame tests. 3452 * @param[in] enable if =1 enable retry test, if =0 then disable 3453 * @param[in] pD driver private state info specific to this instance 3454 */ 3455 void (*setRetryTest)(void* pD, uint8_t enable); 3456 3457 /** 3458 * Read enable/disable status of retry test functionality. 3459 * @param[out] enable =1 if retry test enabled, =0 if disabled 3460 * @param[in] pD driver private state info specific to this instance 3461 * @return EOK for success 3462 * @return EINVAL for invalid pointer 3463 */ 3464 uint32_t (*getRetryTest)(void* pD, uint8_t* enable); 3465 3466 /** 3467 * Write to the user_out_width user outputs. 3468 * @param[in] pD driver private state info specific to this instance 3469 * @param[in] outVal value to write to the user outputs 3470 * @return EOK for success 3471 * @return ENOTSUP if user_io not defined 3472 * @return EINVAL if pD equal NULL 3473 */ 3474 uint32_t (*writeUserOutputs)(void* pD, uint16_t outVal); 3475 3476 /** 3477 * Read from the user_out_width user outputs. 3478 * @param[in] pD driver private state info specific to this instance 3479 * @param[out] outVal pointer for returning value read from the user outputs 3480 * @return EOK for success 3481 * @return ENOTSUP if user_io not defined 3482 * @return EINVAL if NULL parameters 3483 */ 3484 uint32_t (*readUserOutputs)(void* pD, uint16_t* outVal); 3485 3486 /** 3487 * Set the state of the specified user output pin. 3488 * @param[in] state level to set on the pin 1 for high, 0 for low 3489 * @param[in] pin pin number to set, range 0 to user_out_width-1 3490 * @param[in] pD driver private state info specific to this instance 3491 * @return EOK for success 3492 * @return ENOTSUP if user_io not defined 3493 * @return EINVAL if pin out of range, or pD equal NULL 3494 */ 3495 uint32_t (*setUserOutPin)(void* pD, uint8_t pin, uint8_t state); 3496 3497 /** 3498 * Read from the user_in_width user inputs. 3499 * @param[in] pD driver private state info specific to this instance 3500 * @param[out] inVal pointer for returning value read from the user inputs 3501 * @return EOK for success 3502 * @return ENOTSUP if user_io not defined 3503 * @return EINVAL if NULL parameter 3504 */ 3505 uint32_t (*readUserInputs)(void* pD, uint16_t* inVal); 3506 3507 /** 3508 * Get the state of the specified user input pin. 3509 * @param[out] state pointer for returning level present on the pin, 1 for high, 0 for low 3510 * @param[in] pin pin number to read 3511 * @param[in] pD driver private state info specific to this instance 3512 * @return EOK for success 3513 * @return ENOTSUP if user_io not defined 3514 * @return EINVAL if pin out of range, or pD equal NULL 3515 */ 3516 uint32_t (*getUserInPin)(void* pD, uint8_t pin, uint8_t* state); 3517 3518 /** 3519 * Read the state of the MDIO pin 3520 * @param[out] state 1 for high, 0 for low 3521 * @param[in] pD driver private state info specific to this instance 3522 * @return EOK for success 3523 * @return EINVAL for invalid pointer 3524 */ 3525 uint32_t (*getMdioInState)(void* pD, uint8_t* state); 3526 3527 /** 3528 * Direct read of register contents 3529 * @param[in] offs address offset to register 3530 * @param[out] data pointer for returning data read 3531 * @param[in] pD driver private state info specific to this instance 3532 * @return EOK for success 3533 * @return EINVAL if offs out of range, or pD equal NULL 3534 */ 3535 uint32_t (*readReg)(void* pD, uint32_t offs, uint32_t* data); 3536 3537 /** 3538 * Direct write to register 3539 * @param[in] offs address offset to register 3540 * @param[in] data data to write 3541 * @param[in] pD driver private state info specific to this instance 3542 * @return EOK for success 3543 * @return EINVAL if offs out of range, or pD equal NULL 3544 */ 3545 uint32_t (*writeReg)(void* pD, uint32_t offs, uint32_t data); 3546 3547 } CEDI_OBJ; 3548 3549 /** 3550 * In order to access the CEDI APIs, the upper layer software must call 3551 * this global function to obtain the pointer to the driver object. 3552 * @return CEDI_OBJ* Driver Object Pointer 3553 */ 3554 extern CEDI_OBJ *CEDI_GetInstance(void); 3555 3556 /** 3557 * @} 3558 */ 3559 3560 3561 #endif /* _CEDI_H_ */ 3562