1 /*! 2 \file gd32f3x0.h 3 \brief general definitions for gd32f3x0 4 5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0 6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0 7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F3X0_H 38 #define GD32F3X0_H 39 40 #ifdef cplusplus 41 extern "C" { 42 #endif 43 44 /* define GD32F3x0 */ 45 #if !defined (GD32F3x0) 46 #define GD32F3x0 47 #endif /* define GD32F3x0 */ 48 #if !defined (GD32F3x0) 49 #error "Please select the target GD32F3x0 device used in your application (in gd32f3x0.h file)" 50 #endif /* undefine GD32F3x0 tip */ 51 52 /* define GD32F3x0 device category */ 53 #if (!defined (GD32F330))&&(!defined (GD32F350)) 54 #error "Please select GD32F3x0 device category( GD32F330 or GD32F350 )" 55 #endif /* undefine GD32F330 or GD32F350 tip */ 56 #if (defined (GD32F330))&&(defined (GD32F350)) 57 #error "Please select one GD32F3x0 device category( GD32F330 or GD32F350 )" 58 #endif /* define GD32F330 and GD32F350 tip */ 59 60 /* define value of high speed crystal oscillator (HXTAL) in Hz */ 61 #if !defined (HXTAL_VALUE) 62 #define HXTAL_VALUE ((uint32_t)8000000) 63 #endif /* high speed crystal oscillator value */ 64 65 /* define startup timeout value of high speed crystal oscillator (HXTAL) */ 66 #if !defined (HXTAL_STARTUP_TIMEOUT) 67 #define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) 68 #endif /* high speed crystal oscillator startup timeout */ 69 70 /* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ 71 #if !defined (IRC8M_VALUE) 72 #define IRC8M_VALUE ((uint32_t)8000000) 73 #endif /* internal 8MHz RC oscillator value */ 74 75 /* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ 76 #if !defined (IRC8M_STARTUP_TIMEOUT) 77 #define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) 78 #endif /* internal 8MHz RC oscillator startup timeout */ 79 80 /* define value of internal RC oscillator for ADC in Hz */ 81 #if !defined (IRC28M_VALUE) 82 #define IRC28M_VALUE ((uint32_t)28000000) 83 #endif /* IRC28M_VALUE */ 84 85 #if !defined (IRC48M_VALUE) 86 #define IRC48M_VALUE ((uint32_t)48000000) 87 #endif /* IRC48M_VALUE */ 88 89 /* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ 90 #if !defined (IRC40K_VALUE) 91 #define IRC40K_VALUE ((uint32_t)40000) 92 #endif /* internal 40KHz RC oscillator value */ 93 94 /* define value of low speed crystal oscillator (LXTAL)in Hz */ 95 #if !defined (LXTAL_VALUE) 96 #define LXTAL_VALUE ((uint32_t)32768) 97 #endif /* low speed crystal oscillator value */ 98 99 /* GD32F3x0 firmware library version number V1.0 */ 100 #define __GD32F3x0_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ 101 #define __GD32F3x0_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ 102 #define __GD32F3x0_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ 103 #define __GD32F3x0_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ 104 #define __GD32F3x0_STDPERIPH_VERSION ((__GD32F3x0_STDPERIPH_VERSION_MAIN << 24)\ 105 |(__GD32F3x0_STDPERIPH_VERSION_SUB1 << 16)\ 106 |(__GD32F3x0_STDPERIPH_VERSION_SUB2 << 8)\ 107 |(__GD32F3x0_STDPERIPH_VERSION_RC)) 108 109 /* configuration of the Cortex-M4 processor and core peripherals */ 110 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ 111 #define __MPU_PRESENT 0U /*!< GD32F3x0 do not provide MPU */ 112 #define __NVIC_PRIO_BITS 4U /*!< GD32F3x0 uses 4 bits for the priority levels */ 113 #define __Vendor_SysTickConfig 0U /*!< set to 1 if different sysTick config is used */ 114 #define __FPU_PRESENT 1U /*!< FPU present */ 115 116 /* define interrupt number */ 117 typedef enum IRQn 118 { 119 /* Cortex-M4 processor exceptions numbers */ 120 NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ 121 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ 122 BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ 123 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ 124 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ 125 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ 126 PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ 127 SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ 128 /* interruput numbers */ 129 WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ 130 LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ 131 RTC_IRQn = 2, /*!< RTC interrupt */ 132 FMC_IRQn = 3, /*!< FMC interrupt */ 133 RCU_CTC_IRQn = 4, /*!< RCU and CTC interrupt */ 134 EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */ 135 EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */ 136 EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */ 137 TSI_IRQn = 8, /*!< TSI Interrupt */ 138 DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */ 139 DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */ 140 DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */ 141 ADC_CMP_IRQn = 12, /*!< ADC, CMP0 and CMP1 interrupts */ 142 TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */ 143 TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */ 144 TIMER1_IRQn = 15, /*!< TIMER1 interrupt */ 145 TIMER2_IRQn = 16, /*!< TIMER2 interrupt */ 146 #ifdef GD32F350 147 TIMER5_DAC_IRQn = 17, /*!< TIMER5 and DAC interrupts */ 148 #endif /* GD32F350 */ 149 TIMER13_IRQn = 19, /*!< TIMER13 interrupt */ 150 TIMER14_IRQn = 20, /*!< TIMER14 interrupt */ 151 TIMER15_IRQn = 21, /*!< TIMER15 interrupt */ 152 TIMER16_IRQn = 22, /*!< TIMER16 interrupt */ 153 I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */ 154 I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */ 155 SPI0_IRQn = 25, /*!< SPI0 interrupt */ 156 SPI1_IRQn = 26, /*!< SPI1 interrupt */ 157 USART0_IRQn = 27, /*!< USART0 interrupt */ 158 USART1_IRQn = 28, /*!< USART1 interrupt */ 159 #ifdef GD32F350 160 CEC_IRQn = 30, /*!< CEC interrupt */ 161 #endif /* GD32F350 */ 162 I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ 163 I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ 164 DMA_Channel5_6_IRQn = 48, /*!< DMA channel 5 and channel 6 interrupts */ 165 #ifdef GD32F350 166 USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ 167 USBFS_IRQn = 67, /*!< USBFS global interrupt */ 168 #endif /* GD32F350 */ 169 } IRQn_Type; 170 171 /* includes */ 172 #include "core_cm4.h" 173 #include "system_gd32f3x0.h" 174 #include <stdint.h> 175 176 /* enum definitions */ 177 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; 178 typedef enum {RESET = 0, SET = !RESET} FlagStatus; 179 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; 180 181 /* bit operations */ 182 #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) 183 #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) 184 #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) 185 #ifndef BIT 186 #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) 187 #endif 188 #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 189 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) 190 191 /* main flash and SRAM memory map */ 192 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ 193 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ 194 /* SRAM and peripheral base bit-band region */ 195 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */ 196 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */ 197 /* peripheral memory map */ 198 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ 199 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ 200 #define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ 201 #define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */ 202 /* advanced peripheral bus 1 memory map */ 203 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ 204 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ 205 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ 206 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ 207 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ 208 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ 209 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ 210 #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ 211 #define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ 212 #define CEC_BASE (APB1_BUS_BASE + 0x00007800U) /*!< CEC base address */ 213 #define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */ 214 /* advanced peripheral bus 2 memory map */ 215 #define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ 216 #define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */ 217 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ 218 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ 219 /* advanced high performance bus 1 memory map */ 220 #define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ 221 #define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */ 222 #define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ 223 #define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ 224 #define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ 225 #define TSI_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< TSI base address */ 226 #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE0000U) /*!< USBFS base address */ 227 /* advanced high performance bus 2 memory map */ 228 #define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ 229 /* option byte and debug memory map */ 230 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ 231 #define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ 232 233 /* define marco USE_STDPERIPH_DRIVER */ 234 #if !defined USE_STDPERIPH_DRIVER 235 #define USE_STDPERIPH_DRIVER 236 #endif 237 #ifdef USE_STDPERIPH_DRIVER 238 #include "gd32f3x0_libopt.h" 239 #endif /* USE_STDPERIPH_DRIVER */ 240 241 #ifdef cplusplus 242 } 243 #endif 244 #endif 245
