1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 8 9 #ifndef _BSV_HW_DEFS_H 10 #define _BSV_HW_DEFS_H 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /* ********************** Macros ******************************* */ 19 20 /* poll NVM register to assure that the NVM boot is finished (and LCS and the keys are valid) */ 21 #define CC_BSV_WAIT_ON_NVM_IDLE_BIT(hwBaseAddress) \ 22 do { \ 23 uint32_t regVal; \ 24 do { \ 25 SB_HAL_READ_REGISTER( SB_REG_ADDR(hwBaseAddress, NVM_IS_IDLE), regVal); \ 26 regVal = CC_REG_FLD_GET(0, NVM_IS_IDLE, VALUE, regVal); \ 27 }while( !regVal ); \ 28 }while(0) 29 30 /* poll on the AIB acknowledge bit */ 31 #define CC_BSV_WAIT_ON_AIB_ACK_BIT(hwBaseAddress) \ 32 do { \ 33 uint32_t regVal; \ 34 do { \ 35 SB_HAL_READ_REGISTER( SB_REG_ADDR(hwBaseAddress, AIB_FUSE_PROG_COMPLETED), regVal); \ 36 }while( !(regVal & 0x1 )); \ 37 }while(0) 38 39 /* check HUK error bit in LCS register */ 40 #define CC_BSV_IS_OTP_HUK_ERROR(hwBaseAddress, regVal) \ 41 do { \ 42 SB_HAL_READ_REGISTER(SB_REG_ADDR(hwBaseAddress, LCS_REG), regVal); \ 43 regVal = CC_REG_FLD_GET(0, LCS_REG, ERROR_KDR_ZERO_CNT, regVal); \ 44 }while(0) 45 46 /* check KPICV error bit in LCS register */ 47 #define CC_BSV_IS_OTP_KPICV_ERROR(hwBaseAddress, regVal) \ 48 do { \ 49 SB_HAL_READ_REGISTER(SB_REG_ADDR(hwBaseAddress, LCS_REG), regVal); \ 50 regVal = CC_REG_FLD_GET(0, LCS_REG, ERROR_KPICV_ZERO_CNT, regVal); \ 51 }while(0) 52 53 /* check KCEICV error bit in LCS register */ 54 #define CC_BSV_IS_OTP_KCEICV_ERROR(hwBaseAddress, regVal) \ 55 do { \ 56 SB_HAL_READ_REGISTER(SB_REG_ADDR(hwBaseAddress, LCS_REG), regVal); \ 57 regVal = CC_REG_FLD_GET(0, LCS_REG, ERROR_KCEICV_ZERO_CNT, regVal); \ 58 }while(0) 59 60 /* check KCP error bit in LCS register */ 61 #define CC_BSV_IS_OTP_KCP_ERROR(hwBaseAddress, regVal) \ 62 do { \ 63 SB_HAL_READ_REGISTER(SB_REG_ADDR(hwBaseAddress, LCS_REG), regVal); \ 64 regVal = CC_REG_FLD_GET(0, LCS_REG, ERROR_PROV_ZERO_CNT, regVal); \ 65 }while(0) 66 67 /* check KCE error bit in LCS register */ 68 #define CC_BSV_IS_OTP_KCE_ERROR(hwBaseAddress, regVal) \ 69 do { \ 70 SB_HAL_READ_REGISTER(SB_REG_ADDR(hwBaseAddress, LCS_REG), regVal); \ 71 regVal = CC_REG_FLD_GET(0, LCS_REG, ERROR_KCE_ZERO_CNT, regVal); \ 72 }while(0) 73 74 /* read a word directly from OTP memory */ 75 #define CC_BSV_READ_OTP_WORD(hwBaseAddress, otpAddr, otpData) \ 76 do { \ 77 SB_HAL_READ_REGISTER((hwBaseAddress + CC_OTP_BASE_ADDR + otpAddr), otpData); \ 78 }while(0) 79 80 /* write a word directly from OTP memory */ 81 #define CC_BSV_WRITE_OTP_WORD(hwBaseAddress, otpAddr, otpData) \ 82 do { \ 83 SB_HAL_WRITE_REGISTER((hwBaseAddress + CC_OTP_BASE_ADDR + otpAddr), otpData); \ 84 CC_BSV_WAIT_ON_AIB_ACK_BIT(hwBaseAddress); \ 85 }while(0) 86 87 /* calc OTP memory length: 88 read RTL OTP address width. The supported sizes are 6 (for 2 Kbits),7,8,9,10,11 (for 64 Kbits). 89 convert value parameter to addresses of 32b words */ 90 #define CC_BSV_GET_OTP_LENGTH(hwBaseAddress, otpLength) \ 91 do { \ 92 SB_HAL_READ_REGISTER(SB_REG_ADDR(hwBaseAddress, OTP_ADDR_WIDTH_DEF), otpLength); \ 93 otpLength = CC_REG_FLD_GET(0, OTP_ADDR_WIDTH_DEF, VALUE, otpLength); \ 94 otpLength = (1 << otpLength); \ 95 }while(0) 96 97 /* check Hbk configuration in OTP memory */ 98 #define CC_BSV_IS_HBK_FULL(hwBaseAddress, isHbkFull, error) \ 99 do { \ 100 error = CC_BsvOTPWordRead(hwBaseAddress, CC_OTP_MANUFACTURE_FLAG_OFFSET, &isHbkFull); \ 101 isHbkFull = CC_REG_FLD_GET2(0, OTP_MANUFACTURE_FLAG, HBK0_NOT_IN_USE, isHbkFull); \ 102 }while(0) 103 104 /* check OEM RMA flag bit in OTP memory */ 105 #define CC_BSV_IS_OEM_RMA_FLAG_SET(hwBaseAddress, isOemRmaFlag, error) \ 106 do { \ 107 error = CC_BsvOTPWordRead(hwBaseAddress, CC_OTP_OEM_FLAG_OFFSET, &isOemRmaFlag); \ 108 isOemRmaFlag = CC_REG_FLD_GET2(0, OTP_OEM_FLAG, OEM_RMA_MODE, isOemRmaFlag); \ 109 }while(0) 110 111 /* check ICV RMA flag bit in OTP memory */ 112 #define CC_BSV_IS_ICV_RMA_FLAG_SET(hwBaseAddress, isIcvRmaFlag, error) \ 113 do { \ 114 error = CC_BsvOTPWordRead(hwBaseAddress, CC_OTP_OEM_FLAG_OFFSET, &isIcvRmaFlag); \ 115 isIcvRmaFlag = CC_REG_FLD_GET2(0, OTP_OEM_FLAG, ICV_RMA_MODE, isIcvRmaFlag); \ 116 }while(0) 117 118 /* poll on the crypto busy till it is = 0 */ 119 #define CC_BSV_WAIT_ON_CRYPTO_BUSY() \ 120 do { \ 121 uint32_t regVal=1; \ 122 do { \ 123 SB_HAL_READ_REGISTER(SB_REG_ADDR(hwBaseAddress, CRYPTO_BUSY), regVal); \ 124 }while( regVal ); \ 125 }while(0) 126 127 /* check KPICV "Not In Use" bit in OTP memory */ 128 #define CC_BSV_IS_KPICV_IN_USE(hwBaseAddress, isKpicvInUse, error) \ 129 do { \ 130 error = CC_BsvOTPWordRead(hwBaseAddress, CC_OTP_MANUFACTURE_FLAG_OFFSET, &isKpicvInUse); \ 131 isKpicvInUse = 0x1UL ^ (CC_REG_FLD_GET2(0, OTP_MANUFACTURE_FLAG, KPICV_NOT_IN_USE, isKpicvInUse)); \ 132 }while(0) 133 134 /* check KCEICV "Not In Use" bit in OTP memory */ 135 #define CC_BSV_IS_KCEICV_IN_USE(hwBaseAddress, isKceicvInUse, error) \ 136 do { \ 137 error = CC_BsvOTPWordRead(hwBaseAddress, CC_OTP_MANUFACTURE_FLAG_OFFSET, &isKceicvInUse); \ 138 isKceicvInUse = 0x1UL ^ (CC_REG_FLD_GET2(0, OTP_MANUFACTURE_FLAG, KCEICV_NOT_IN_USE, isKceicvInUse)); \ 139 }while(0) 140 141 /* check KCP "Not In Use" bit in OTP memory */ 142 #define CC_BSV_IS_KCP_IN_USE(hwBaseAddress, isKcpInUse, error) \ 143 do { \ 144 error = CC_BsvOTPWordRead(hwBaseAddress, CC_OTP_OEM_FLAG_OFFSET, &isKcpInUse); \ 145 isKcpInUse = 0x1UL ^ (CC_REG_FLD_GET2(0, OTP_OEM_FLAG, KCP_NOT_IN_USE, isKcpInUse)); \ 146 }while(0) 147 148 /* check KCE "Not In Use" bit in OTP memory */ 149 #define CC_BSV_IS_KCE_IN_USE(hwBaseAddress, isKceInUse, error) \ 150 do { \ 151 error = CC_BsvOTPWordRead(hwBaseAddress, CC_OTP_OEM_FLAG_OFFSET, &isKceInUse); \ 152 isKceInUse = 0x1UL ^ (CC_REG_FLD_GET2(0, OTP_OEM_FLAG, KCE_NOT_IN_USE, isKceInUse)); \ 153 }while(0) 154 155 156 157 /* ********************** Definitions ******************************* */ 158 159 /* HW clocks */ 160 #define CC_BSV_CLOCK_ENABLE 0x1UL 161 #define CC_BSV_CLOCK_DISABLE 0x0UL 162 163 /* Peripheral ID registers values */ 164 #define CC_BSV_PID_0_VAL 0x000000C0UL 165 #define CC_BSV_PID_1_VAL 0x000000B0UL 166 #define CC_BSV_PID_2_VAL 0x0000000BUL 167 #define CC_BSV_PID_3_VAL 0x00000000UL 168 #define CC_BSV_PID_4_VAL 0x00000004UL 169 #define CC_BSV_PID_SIZE_WORDS 5 170 171 /* Component ID registers values */ 172 #define CC_BSV_CID_0_VAL 0x0DUL 173 #define CC_BSV_CID_1_VAL 0xF0UL 174 #define CC_BSV_CID_2_VAL 0x05UL 175 #define CC_BSV_CID_3_VAL 0xB1UL 176 #define CC_BSV_CID_SIZE_WORDS 4 177 178 /* Secret Key */ 179 #define CC_BSV_SK_ERASER_VAL 0xFFFFFFFFUL 180 #define CC_BSV_256B_SK_INTEGRITY_ERASER_VAL 0xFFUL 181 #define CC_BSV_128B_SK_INTEGRITY_ERASER_VAL 0x7FUL 182 183 #ifdef __cplusplus 184 } 185 #endif 186 187 #endif 188 189 190 191
