1 /*
2  * Copyright (c) 2023 Antmicro <www.antmicro.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_DRIVERS_SERIAL_UART_RZT2M_H_
8 #define ZEPHYR_DRIVERS_SERIAL_UART_RZT2M_H_
9 
10 #include <stdint.h>
11 
12 #define MAX_FIFO_DEPTH      16
13 
14 #define RDR(base)   ((volatile uint32_t *)(base))
15 #define TDR(base)   ((volatile uint32_t *)(base + 0x04))
16 #define CCR0(base)  ((volatile uint32_t *)(base + 0x08))
17 #define CCR1(base)  ((volatile uint32_t *)(base + 0x0c))
18 #define CCR2(base)  ((volatile uint32_t *)(base + 0x10))
19 #define CCR3(base)  ((volatile uint32_t *)(base + 0x14))
20 #define CCR4(base)  ((volatile uint32_t *)(base + 0x18))
21 #define FCR(base)   ((volatile uint32_t *)(base + 0x24))
22 #define CSR(base)   ((volatile uint32_t *)(base + 0x48))
23 #define FRSR(base)  ((volatile uint32_t *)(base + 0x50))
24 #define FTSR(base)  ((volatile uint32_t *)(base + 0x54))
25 #define CFCLR(base) ((volatile uint32_t *)(base + 0x68))
26 #define FFCLR(base) ((volatile uint32_t *)(base + 0x70))
27 
28 #define CCR0_DEFAULT_VALUE 0x0
29 #define CCR1_DEFAULT_VALUE 0x00000010
30 #define CCR2_DEFAULT_VALUE 0xff00ff04
31 #define CCR3_DEFAULT_VALUE 0x00001203
32 #define CCR4_DEFAULT_VALUE 0x0
33 
34 #define RDR_MASK_RDAT GENMASK(8, 0)
35 
36 #define CCR0_MASK_RE    BIT(0)
37 #define CCR0_MASK_TE    BIT(4)
38 #define CCR0_MASK_DCME  BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE   BIT(16)
41 #define CCR0_MASK_TIE   BIT(20)
42 #define CCR0_MASK_TEIE  BIT(21)
43 #define CCR0_MASK_SSE   BIT(24)
44 
45 #define CCR1_MASK_CTSE   BIT(0)
46 #define CCR1_MASK_SPB2DT BIT(4)
47 #define CCR1_MASK_SPB2IO BIT(5)
48 #define CCR1_MASK_PE     BIT(8)
49 #define CCR1_MASK_PM     BIT(9)
50 #define CCR1_MASK_NFEN   BIT(28)
51 
52 #define CCR2_MASK_BGDM  BIT(4)
53 #define CCR2_MASK_ABCS  BIT(5)
54 #define CCR2_MASK_ABCSE BIT(6)
55 #define CCR2_MASK_BRR   GENMASK(15, 8)
56 #define CCR2_MASK_BRME  BIT(16)
57 #define CCR2_MASK_CKS   GENMASK(21, 20)
58 #define CCR2_MASK_MDDR  GENMASK(31, 24)
59 #define CCR2_MASK_BAUD_SETTING                                                                     \
60 	(CCR2_MASK_BRME | CCR2_MASK_ABCSE | CCR2_MASK_ABCS | CCR2_MASK_BGDM | CCR2_MASK_CKS |      \
61 	 CCR2_MASK_BRR | CCR2_MASK_MDDR)
62 
63 #define CCR3_MASK_STP   BIT(14)
64 #define CCR3_MASK_MP    BIT(19)
65 #define CCR3_MASK_FM    BIT(20)
66 #define CCR3_MASK_CKE   (BIT(24) | BIT(25))
67 #define CCR3_CKE_ENABLE BIT(24)
68 #define CCR3_CHR_7BIT   (BIT(8) | BIT(9))
69 #define CCR3_CHR_8BIT   BIT(9)
70 
71 #define CCR4_MASK_ASEN BIT(16)
72 #define CCR4_MASK_ATEN BIT(17)
73 
74 #define FCR_MASK_TFRST BIT(15)
75 #define FCR_MASK_RFRST BIT(23)
76 #define FCR_MASK_TTRG  GENMASK(12, 8)
77 #define FCR_MASK_RTRG  GENMASK(20, 16)
78 #define FCR_TTRG_15    (15 << 8)
79 #define FCR_RTRG_15    (15 << 16)
80 
81 #define CSR_MASK_ORER BIT(24)
82 #define CSR_MASK_PER  BIT(27)
83 #define CSR_MASK_FER  BIT(28)
84 #define CSR_MASK_TDRE BIT(29)
85 #define CSR_MASK_TEND BIT(30)
86 #define CSR_MASK_RDRF BIT(31)
87 
88 #define FRSR_MASK_DR BIT(0)
89 #define FRSR_R(val)  ((val >> 7) & 0x3f)
90 
91 #define FTSR_T(val) (val & 0x3f)
92 
93 #define CFCLR_MASK_ERSC  BIT(4)
94 #define CFCLR_MASK_DCMFC BIT(16)
95 #define CFCLR_MASK_DPERC BIT(17)
96 #define CFCLR_MASK_DFERC BIT(18)
97 #define CFCLR_MASK_ORERC BIT(24)
98 #define CFCLR_MASK_MFFC  BIT(26)
99 #define CFCLR_MASK_PERC  BIT(27)
100 #define CFCLR_MASK_FERC  BIT(28)
101 #define CFCLR_MASK_TDREC BIT(29)
102 #define CFCLR_MASK_RDRFC BIT(31)
103 #define CFCLR_ALL_FLAG_CLEAR                                                                       \
104 	(CFCLR_MASK_ERSC | CFCLR_MASK_DCMFC | CFCLR_MASK_DPERC | CFCLR_MASK_DFERC |                \
105 	 CFCLR_MASK_ORERC | CFCLR_MASK_MFFC | CFCLR_MASK_PERC | CFCLR_MASK_FERC |                  \
106 	 CFCLR_MASK_TDREC | CFCLR_MASK_RDRFC)
107 
108 #define FFCLR_MASK_DRC BIT(0)
109 
110 #define MSTPCRA                (volatile uint32_t *)(0x80280000 + 0x300)
111 #define MSTPCRA_MASK_SCIx(x)   BIT(x + 8)
112 #define BASE_TO_IFACE_ID(base) ((base & 0x1000000) ? 5 : ((base & 0xff00) >> 10) - 4)
113 
114 #define CCR2_MDDR_128	BIT(31)
115 #define CCR2_CKS_0	0
116 #define CCR2_BRME_0	0
117 #define CCR2_BRR_243	(0xf3 << 8)
118 #define CCR2_BRR_39	(0x27 << 8)
119 #define CCR2_BGDM_1	BIT(4)
120 
121 #define CCR2_BAUD_SETTING_9600   (CCR2_MDDR_128 | CCR2_BRR_243)
122 #define CCR2_BAUD_SETTING_115200 (CCR2_MDDR_128 | CCR2_BRR_39 | CCR2_BGDM_1)
123 
124 #endif /* ZEPHYR_DRIVERS_SERIAL_UART_RZT2M_H_ */
125