| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_STM.h | 80 …__IO uint32_t CCR; /**< Channel Control, array offset: 0x10, array s… member
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| D | S32K344_LPSPI.h | 90 __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/mcuxpresso/ |
| D | boot_multicore_slave.c | 42 __IO uint32_t CCR; /**< Core Control Register, offset: 0x68 */ member
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_STM.h | 80 …__IO uint32_t CCR; /**< Channel Control, array offset: 0x10, array s… member
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K118_SCB.h | 84 …__I uint32_t CCR; /**< Configuration and Control Register, offset: … member
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| D | S32K116_SCB.h | 84 …__I uint32_t CCR; /**< Configuration and Control Register, offset: … member
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| D | S32K148_LPSPI.h | 86 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member
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| D | S32K116_LPSPI.h | 86 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member
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| D | S32K118_LPSPI.h | 86 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member
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| D | S32K144_LPSPI.h | 86 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member
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| D | S32K146_LPSPI.h | 86 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member
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| D | S32K142W_LPSPI.h | 86 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member
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| D | S32K142_LPSPI.h | 86 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member
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| D | S32K144W_LPSPI.h | 86 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member
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| D | S32K142W_SCB.h | 84 …__IO uint32_t CCR; /**< Configuration and Control Register, offset: … member
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| D | S32K142_SCB.h | 84 …__IO uint32_t CCR; /**< Configuration and Control Register, offset: … member
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| D | S32K146_SCB.h | 84 …__IO uint32_t CCR; /**< Configuration and Control Register, offset: … member
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| D | S32K148_SCB.h | 84 …__IO uint32_t CCR; /**< Configuration and Control Register, offset: … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/ |
| D | fsl_power.c | 65 uint32_t CCR; member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/ |
| D | fsl_power.c | 65 uint32_t CCR; member
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/ |
| D | core_cm0.h | 348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm1.h | 348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_cm0plus.h | 366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| D | core_sc000.h | 354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/ |
| D | core_cm0plus.h | 366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
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