1 /****************************************************************************** 2 * Filename: hw_ccfg_h 3 * Revised: 2019-04-01 09:23:38 +0200 (Mon, 01 Apr 2019) 4 * Revision: 55513 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CCFG_H__ 38 #define __HW_CCFG_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CCFG component 44 // 45 //***************************************************************************** 46 // Extern LF clock configuration 47 #define CCFG_O_EXT_LF_CLK 0x00001FA8 48 49 // Mode Configuration 1 50 #define CCFG_O_MODE_CONF_1 0x00001FAC 51 52 // CCFG Size and Disable Flags 53 #define CCFG_O_SIZE_AND_DIS_FLAGS 0x00001FB0 54 55 // Mode Configuration 0 56 #define CCFG_O_MODE_CONF 0x00001FB4 57 58 // Voltage Load 0 59 #define CCFG_O_VOLT_LOAD_0 0x00001FB8 60 61 // Voltage Load 1 62 #define CCFG_O_VOLT_LOAD_1 0x00001FBC 63 64 // Real Time Clock Offset 65 #define CCFG_O_RTC_OFFSET 0x00001FC0 66 67 // Frequency Offset 68 #define CCFG_O_FREQ_OFFSET 0x00001FC4 69 70 // IEEE MAC Address 0 71 #define CCFG_O_IEEE_MAC_0 0x00001FC8 72 73 // IEEE MAC Address 1 74 #define CCFG_O_IEEE_MAC_1 0x00001FCC 75 76 // IEEE BLE Address 0 77 #define CCFG_O_IEEE_BLE_0 0x00001FD0 78 79 // IEEE BLE Address 1 80 #define CCFG_O_IEEE_BLE_1 0x00001FD4 81 82 // Bootloader Configuration 83 #define CCFG_O_BL_CONFIG 0x00001FD8 84 85 // Erase Configuration 86 #define CCFG_O_ERASE_CONF 0x00001FDC 87 88 // TI Options 89 #define CCFG_O_CCFG_TI_OPTIONS 0x00001FE0 90 91 // Test Access Points Enable 0 92 #define CCFG_O_CCFG_TAP_DAP_0 0x00001FE4 93 94 // Test Access Points Enable 1 95 #define CCFG_O_CCFG_TAP_DAP_1 0x00001FE8 96 97 // Image Valid 98 #define CCFG_O_IMAGE_VALID_CONF 0x00001FEC 99 100 // Protect Sectors 0-31 101 #define CCFG_O_CCFG_PROT_31_0 0x00001FF0 102 103 // Protect Sectors 32-63 104 #define CCFG_O_CCFG_PROT_63_32 0x00001FF4 105 106 // Protect Sectors 64-95 107 #define CCFG_O_CCFG_PROT_95_64 0x00001FF8 108 109 // Protect Sectors 96-127 110 #define CCFG_O_CCFG_PROT_127_96 0x00001FFC 111 112 //***************************************************************************** 113 // 114 // Register: CCFG_O_EXT_LF_CLK 115 // 116 //***************************************************************************** 117 // Field: [31:24] DIO 118 // 119 // Unsigned integer, selecting the DIO to supply external 32kHz clock as 120 // SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO 121 // will be marked as reserved by the pin driver (TI-RTOS environment) and hence 122 // not selectable for other usage. 123 #define CCFG_EXT_LF_CLK_DIO_W 8 124 #define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 125 #define CCFG_EXT_LF_CLK_DIO_S 24 126 127 // Field: [23:0] RTC_INCREMENT 128 // 129 // Unsigned integer, defining the input frequency of the external clock and is 130 // written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: 131 // EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: 132 // RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) 133 #define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 134 #define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF 135 #define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 136 137 //***************************************************************************** 138 // 139 // Register: CCFG_O_MODE_CONF_1 140 // 141 //***************************************************************************** 142 // Field: [31] TCXO_TYPE 143 // 144 // Selects the TCXO type. 145 // 146 // 0: CMOS type. Internal common-mode bias will not be enabled. 147 // 1: Clipped-sine type. Internal common-mode bias will be enabled when TCXO is 148 // used. 149 // 150 // Bit field value is only valid if MODE_CONF.XOSC_FREQ=0. 151 #define CCFG_MODE_CONF_1_TCXO_TYPE 0x80000000 152 #define CCFG_MODE_CONF_1_TCXO_TYPE_BITN 31 153 #define CCFG_MODE_CONF_1_TCXO_TYPE_M 0x80000000 154 #define CCFG_MODE_CONF_1_TCXO_TYPE_S 31 155 156 // Field: [30:24] TCXO_MAX_START 157 // 158 // Maximum TCXO startup time in units of 100us. 159 // Bit field value is only valid if MODE_CONF.XOSC_FREQ=0. 160 #define CCFG_MODE_CONF_1_TCXO_MAX_START_W 7 161 #define CCFG_MODE_CONF_1_TCXO_MAX_START_M 0x7F000000 162 #define CCFG_MODE_CONF_1_TCXO_MAX_START_S 24 163 164 // Field: [23:20] ALT_DCDC_VMIN 165 // 166 // Minimum voltage for when DC/DC should be used if alternate DC/DC setting is 167 // enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). 168 // Voltage = (28 + ALT_DCDC_VMIN) / 16. 169 // 0: 1.75V 170 // 1: 1.8125V 171 // ... 172 // 14: 2.625V 173 // 15: 2.6875V 174 // 175 // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must 176 // be called regularly to apply this field (handled automatically if using TI 177 // RTOS!). 178 #define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 179 #define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 180 #define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 181 182 // Field: [19] ALT_DCDC_DITHER_EN 183 // 184 // Enable DC/DC dithering if alternate DC/DC setting is enabled 185 // (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). 186 // 0: Dither disable 187 // 1: Dither enable 188 #define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 189 #define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 190 #define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 191 #define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 192 193 // Field: [18:16] ALT_DCDC_IPEAK 194 // 195 // Inductor peak current if alternate DC/DC setting is enabled 196 // (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external 197 // inductor! 198 // 199 // 0: 46mA (min) 200 // ... 201 // 4: 70mA 202 // ... 203 // 7: 87mA (max) 204 #define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 205 #define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 206 #define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 207 208 // Field: [15:12] DELTA_IBIAS_INIT 209 // 210 // Signed delta value for IBIAS_INIT. Delta value only applies if 211 // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. 212 // See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT 213 #define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 214 #define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 215 #define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 216 217 // Field: [11:8] DELTA_IBIAS_OFFSET 218 // 219 // Signed delta value for IBIAS_OFFSET. Delta value only applies if 220 // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. 221 // See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET 222 #define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 223 #define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 224 #define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 225 226 // Field: [7:0] XOSC_MAX_START 227 // 228 // Unsigned value of maximum XOSC startup time (worst case) in units of 100us. 229 // Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. 230 #define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 231 #define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF 232 #define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 233 234 //***************************************************************************** 235 // 236 // Register: CCFG_O_SIZE_AND_DIS_FLAGS 237 // 238 //***************************************************************************** 239 // Field: [31:16] SIZE_OF_CCFG 240 // 241 // Total size of CCFG in bytes. 242 #define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 243 #define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 244 #define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 245 246 // Field: [15:4] DISABLE_FLAGS 247 // 248 // Reserved for future use. Software should not rely on the value of a 249 // reserved. Writing any other value than the reset/default value may result in 250 // undefined behavior. 251 #define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 252 #define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 253 #define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 254 255 // Field: [3] DIS_TCXO 256 // 257 // Deprecated. Must be set to 1. 258 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 259 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 260 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 261 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 262 263 // Field: [2] DIS_GPRAM 264 // 265 // Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). 266 // 0: GPRAM is enabled and hence CACHE disabled. 267 // 1: GPRAM is disabled and instead CACHE is enabled (default). 268 // Notes: 269 // - Disabling CACHE will reduce CPU execution speed (up to 60%). 270 // - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if 271 // enabled. 272 // See: 273 // VIMS:CTL.MODE 274 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 275 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 276 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 277 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 278 279 // Field: [1] DIS_ALT_DCDC_SETTING 280 // 281 // Disable alternate DC/DC settings. 282 // 0: Enable alternate DC/DC settings. 283 // 1: Disable alternate DC/DC settings. 284 // See: 285 // MODE_CONF_1.ALT_DCDC_VMIN 286 // MODE_CONF_1.ALT_DCDC_DITHER_EN 287 // MODE_CONF_1.ALT_DCDC_IPEAK 288 // 289 // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must 290 // be called regularly to apply this field (handled automatically if using TI 291 // RTOS!). 292 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 293 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 294 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 295 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 296 297 // Field: [0] DIS_XOSC_OVR 298 // 299 // Disable XOSC override functionality. 300 // 0: Enable XOSC override functionality. 301 // 1: Disable XOSC override functionality. 302 // See: 303 // MODE_CONF_1.DELTA_IBIAS_INIT 304 // MODE_CONF_1.DELTA_IBIAS_OFFSET 305 // MODE_CONF_1.XOSC_MAX_START 306 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 307 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 308 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 309 #define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 310 311 //***************************************************************************** 312 // 313 // Register: CCFG_O_MODE_CONF 314 // 315 //***************************************************************************** 316 // Field: [31:28] VDDR_TRIM_SLEEP_DELTA 317 // 318 // Signed delta value to apply to the 319 // VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. 320 // 0x8 (-8) : Delta = -7 321 // ... 322 // 0xF (-1) : Delta = 0 323 // 0x0 (0) : Delta = +1 324 // ... 325 // 0x7 (7) : Delta = +8 326 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 327 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 328 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 329 330 // Field: [27] DCDC_RECHARGE 331 // 332 // DC/DC during recharge in powerdown. 333 // 0: Use the DC/DC during recharge in powerdown. 334 // 1: Do not use the DC/DC during recharge in powerdown (default). 335 // 336 // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must 337 // be called regularly to apply this field (handled automatically if using TI 338 // RTOS!). 339 #define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 340 #define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 341 #define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 342 #define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 343 344 // Field: [26] DCDC_ACTIVE 345 // 346 // DC/DC in active mode. 347 // 0: Use the DC/DC during active mode. 348 // 1: Do not use the DC/DC during active mode (default). 349 // 350 // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must 351 // be called regularly to apply this field (handled automatically if using TI 352 // RTOS!). 353 #define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 354 #define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 355 #define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 356 #define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 357 358 // Field: [25] VDDR_EXT_LOAD 359 // 360 // Reserved for future use. Software should not rely on the value of a 361 // reserved. Writing any other value than the reset/default value may result in 362 // undefined behavior. 363 #define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 364 #define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 365 #define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 366 #define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 367 368 // Field: [24] VDDS_BOD_LEVEL 369 // 370 // VDDS BOD level. 371 // 0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum 372 // PA output power on CC13xx). 373 // 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default). 374 #define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 375 #define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 376 #define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 377 #define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 378 379 // Field: [23:22] SCLK_LF_OPTION 380 // 381 // Select source for SCLK_LF. 382 // ENUMs: 383 // RCOSC_LF Low frequency RCOSC (default) 384 // XOSC_LF 32.768kHz low frequency XOSC 385 // EXTERNAL_LF External low frequency clock on DIO defined by 386 // EXT_LF_CLK.DIO. The RTC tick speed 387 // AON_RTC:SUBSECINC is updated to 388 // EXT_LF_CLK.RTC_INCREMENT (done in the 389 // SetupTrimDevice() driverlib boot function). 390 // External clock must always be running when the 391 // chip is in standby for VDDR recharge timing. 392 // XOSC_HF_DLF 31.25kHz clock derived from 48MHz XOSC or HPOSC. 393 // The RTC tick speed AON_RTC:SUBSECINC is updated 394 // to 0x8637BD, corresponding to a 31.25kHz clock 395 // (done in the SetupTrimDevice() driverlib boot 396 // function). The device must be blocked from 397 // entering Standby mode when using this clock 398 // source. 399 #define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 400 #define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 401 #define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 402 #define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 403 #define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 404 #define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 405 #define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 406 407 // Field: [21] VDDR_TRIM_SLEEP_TC 408 // 409 // 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated 410 // 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time 411 // standby mode is entered. This improves low-temperature RCOSC_LF frequency 412 // stability in standby mode. 413 // 414 // When temperature compensation is performed, the delta is calculates this 415 // way: 416 // Delta = max (delta, min(8, floor(62-temp)/8)) 417 // Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current 418 // temperature in degrees C. 419 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 420 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 421 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 422 #define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 423 424 // Field: [20] RTC_COMP 425 // 426 // Reserved for future use. Software should not rely on the value of a 427 // reserved. Writing any other value than the reset/default value may result in 428 // undefined behavior. 429 #define CCFG_MODE_CONF_RTC_COMP 0x00100000 430 #define CCFG_MODE_CONF_RTC_COMP_BITN 20 431 #define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 432 #define CCFG_MODE_CONF_RTC_COMP_S 20 433 434 // Field: [19:18] XOSC_FREQ 435 // 436 // Selects which high frequency oscillator is used (required for radio usage). 437 // ENUMs: 438 // 24M 24 MHz XOSC_HF. Not supported. 439 // 48M 48 MHz XOSC_HF 440 // HPOSC Internal high precision oscillator. 441 // TCXO External 48Mhz TCXO. 442 // Refer to 443 // MODE_CONF_1.TCXO_MAX_START and 444 // MODE_CONF_1.TCXO_TYPE bit fields for additional 445 // configuration of TCXO. 446 #define CCFG_MODE_CONF_XOSC_FREQ_W 2 447 #define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 448 #define CCFG_MODE_CONF_XOSC_FREQ_S 18 449 #define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 450 #define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 451 #define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 452 #define CCFG_MODE_CONF_XOSC_FREQ_TCXO 0x00000000 453 454 // Field: [17] XOSC_CAP_MOD 455 // 456 // Enable modification (delta) to XOSC cap-array. Value specified in 457 // XOSC_CAPARRAY_DELTA. 458 // 0: Apply cap-array delta 459 // 1: Do not apply cap-array delta (default) 460 #define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 461 #define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 462 #define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 463 #define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 464 465 // Field: [16] HF_COMP 466 // 467 // Reserved for future use. Software should not rely on the value of a 468 // reserved. Writing any other value than the reset/default value may result in 469 // undefined behavior. 470 #define CCFG_MODE_CONF_HF_COMP 0x00010000 471 #define CCFG_MODE_CONF_HF_COMP_BITN 16 472 #define CCFG_MODE_CONF_HF_COMP_M 0x00010000 473 #define CCFG_MODE_CONF_HF_COMP_S 16 474 475 // Field: [15:8] XOSC_CAPARRAY_DELTA 476 // 477 // Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. 478 // Enabled by XOSC_CAP_MOD. 479 #define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 480 #define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 481 #define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 482 483 // Field: [7:0] VDDR_CAP 484 // 485 // Unsigned 8-bit integer, representing the minimum decoupling capacitance 486 // (worst case) on VDDR, in units of 100nF. This should take into account 487 // capacitor tolerance and voltage dependent capacitance variation. This bit 488 // affects the recharge period calculation when going into powerdown or 489 // standby. 490 // 491 // NOTE! If using the following functions this field must be configured (used 492 // by TI RTOS): 493 // SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() 494 #define CCFG_MODE_CONF_VDDR_CAP_W 8 495 #define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF 496 #define CCFG_MODE_CONF_VDDR_CAP_S 0 497 498 //***************************************************************************** 499 // 500 // Register: CCFG_O_VOLT_LOAD_0 501 // 502 //***************************************************************************** 503 // Field: [31:24] VDDR_EXT_TP45 504 // 505 // Reserved for future use. Software should not rely on the value of a 506 // reserved. Writing any other value than the reset/default value may result in 507 // undefined behavior. 508 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 509 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 510 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 511 512 // Field: [23:16] VDDR_EXT_TP25 513 // 514 // Reserved for future use. Software should not rely on the value of a 515 // reserved. Writing any other value than the reset/default value may result in 516 // undefined behavior. 517 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 518 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 519 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 520 521 // Field: [15:8] VDDR_EXT_TP5 522 // 523 // Reserved for future use. Software should not rely on the value of a 524 // reserved. Writing any other value than the reset/default value may result in 525 // undefined behavior. 526 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 527 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 528 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 529 530 // Field: [7:0] VDDR_EXT_TM15 531 // 532 // Reserved for future use. Software should not rely on the value of a 533 // reserved. Writing any other value than the reset/default value may result in 534 // undefined behavior. 535 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 536 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF 537 #define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 538 539 //***************************************************************************** 540 // 541 // Register: CCFG_O_VOLT_LOAD_1 542 // 543 //***************************************************************************** 544 // Field: [31:24] VDDR_EXT_TP125 545 // 546 // Reserved for future use. Software should not rely on the value of a 547 // reserved. Writing any other value than the reset/default value may result in 548 // undefined behavior. 549 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 550 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 551 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 552 553 // Field: [23:16] VDDR_EXT_TP105 554 // 555 // Reserved for future use. Software should not rely on the value of a 556 // reserved. Writing any other value than the reset/default value may result in 557 // undefined behavior. 558 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 559 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 560 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 561 562 // Field: [15:8] VDDR_EXT_TP85 563 // 564 // Reserved for future use. Software should not rely on the value of a 565 // reserved. Writing any other value than the reset/default value may result in 566 // undefined behavior. 567 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 568 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 569 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 570 571 // Field: [7:0] VDDR_EXT_TP65 572 // 573 // Reserved for future use. Software should not rely on the value of a 574 // reserved. Writing any other value than the reset/default value may result in 575 // undefined behavior. 576 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 577 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF 578 #define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 579 580 //***************************************************************************** 581 // 582 // Register: CCFG_O_RTC_OFFSET 583 // 584 //***************************************************************************** 585 // Field: [31:16] RTC_COMP_P0 586 // 587 // Reserved for future use. Software should not rely on the value of a 588 // reserved. Writing any other value than the reset/default value may result in 589 // undefined behavior. 590 #define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 591 #define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 592 #define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 593 594 // Field: [15:8] RTC_COMP_P1 595 // 596 // Reserved for future use. Software should not rely on the value of a 597 // reserved. Writing any other value than the reset/default value may result in 598 // undefined behavior. 599 #define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 600 #define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 601 #define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 602 603 // Field: [7:0] RTC_COMP_P2 604 // 605 // Reserved for future use. Software should not rely on the value of a 606 // reserved. Writing any other value than the reset/default value may result in 607 // undefined behavior. 608 #define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 609 #define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF 610 #define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 611 612 //***************************************************************************** 613 // 614 // Register: CCFG_O_FREQ_OFFSET 615 // 616 //***************************************************************************** 617 // Field: [31:16] HF_COMP_P0 618 // 619 // Reserved for future use. Software should not rely on the value of a 620 // reserved. Writing any other value than the reset/default value may result in 621 // undefined behavior. 622 #define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 623 #define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 624 #define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 625 626 // Field: [15:8] HF_COMP_P1 627 // 628 // Reserved for future use. Software should not rely on the value of a 629 // reserved. Writing any other value than the reset/default value may result in 630 // undefined behavior. 631 #define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 632 #define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 633 #define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 634 635 // Field: [7:0] HF_COMP_P2 636 // 637 // Reserved for future use. Software should not rely on the value of a 638 // reserved. Writing any other value than the reset/default value may result in 639 // undefined behavior. 640 #define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 641 #define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF 642 #define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 643 644 //***************************************************************************** 645 // 646 // Register: CCFG_O_IEEE_MAC_0 647 // 648 //***************************************************************************** 649 // Field: [31:0] ADDR 650 // 651 // Bits[31:0] of the 64-bits custom IEEE MAC address. 652 // If different from 0xFFFFFFFF then the value of this field is applied; 653 // otherwise use value from FCFG. 654 #define CCFG_IEEE_MAC_0_ADDR_W 32 655 #define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF 656 #define CCFG_IEEE_MAC_0_ADDR_S 0 657 658 //***************************************************************************** 659 // 660 // Register: CCFG_O_IEEE_MAC_1 661 // 662 //***************************************************************************** 663 // Field: [31:0] ADDR 664 // 665 // Bits[63:32] of the 64-bits custom IEEE MAC address. 666 // If different from 0xFFFFFFFF then the value of this field is applied; 667 // otherwise use value from FCFG. 668 #define CCFG_IEEE_MAC_1_ADDR_W 32 669 #define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF 670 #define CCFG_IEEE_MAC_1_ADDR_S 0 671 672 //***************************************************************************** 673 // 674 // Register: CCFG_O_IEEE_BLE_0 675 // 676 //***************************************************************************** 677 // Field: [31:0] ADDR 678 // 679 // Bits[31:0] of the 64-bits custom IEEE BLE address. 680 // If different from 0xFFFFFFFF then the value of this field is applied; 681 // otherwise use value from FCFG. 682 #define CCFG_IEEE_BLE_0_ADDR_W 32 683 #define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF 684 #define CCFG_IEEE_BLE_0_ADDR_S 0 685 686 //***************************************************************************** 687 // 688 // Register: CCFG_O_IEEE_BLE_1 689 // 690 //***************************************************************************** 691 // Field: [31:0] ADDR 692 // 693 // Bits[63:32] of the 64-bits custom IEEE BLE address. 694 // If different from 0xFFFFFFFF then the value of this field is applied; 695 // otherwise use value from FCFG. 696 #define CCFG_IEEE_BLE_1_ADDR_W 32 697 #define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF 698 #define CCFG_IEEE_BLE_1_ADDR_S 0 699 700 //***************************************************************************** 701 // 702 // Register: CCFG_O_BL_CONFIG 703 // 704 //***************************************************************************** 705 // Field: [31:24] BOOTLOADER_ENABLE 706 // 707 // Bootloader enable. Boot loader can be accessed if 708 // IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and 709 // conditions for boot loader backdoor are met). 710 // 0xC5: Boot loader is enabled. 711 // Any other value: Boot loader is disabled. 712 #define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 713 #define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 714 #define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 715 716 // Field: [16] BL_LEVEL 717 // 718 // Sets the active level of the selected DIO number BL_PIN_NUMBER if boot 719 // loader backdoor is enabled by the BL_ENABLE field. 720 // 0: Active low. 721 // 1: Active high. 722 #define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 723 #define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 724 #define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 725 #define CCFG_BL_CONFIG_BL_LEVEL_S 16 726 727 // Field: [15:8] BL_PIN_NUMBER 728 // 729 // DIO number that is level checked if the boot loader backdoor is enabled by 730 // the BL_ENABLE field. 731 #define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 732 #define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 733 #define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 734 735 // Field: [7:0] BL_ENABLE 736 // 737 // Enables the boot loader backdoor. 738 // 0xC5: Boot loader backdoor is enabled. 739 // Any other value: Boot loader backdoor is disabled. 740 // 741 // NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader 742 // backdoor is enabled. 743 #define CCFG_BL_CONFIG_BL_ENABLE_W 8 744 #define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF 745 #define CCFG_BL_CONFIG_BL_ENABLE_S 0 746 747 //***************************************************************************** 748 // 749 // Register: CCFG_O_ERASE_CONF 750 // 751 //***************************************************************************** 752 // Field: [8] CHIP_ERASE_DIS_N 753 // 754 // Chip erase. 755 // This bit controls if a chip erase requested through the JTAG WUC TAP will be 756 // ignored in a following boot caused by a reset of the MCU VD. 757 // A successful chip erase operation will force the content of the flash main 758 // bank back to the state as it was when delivered by TI. 759 // 0: Disable. Any chip erase request detected during boot will be ignored. 760 // 1: Enable. Any chip erase request detected during boot will be performed by 761 // the boot FW. 762 #define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 763 #define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 764 #define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 765 #define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 766 767 // Field: [0] BANK_ERASE_DIS_N 768 // 769 // Bank erase. 770 // This bit controls if the ROM serial boot loader will accept a received Bank 771 // Erase command (COMMAND_BANK_ERASE). 772 // A successful Bank Erase operation will erase all main bank sectors not 773 // protected by write protect configuration bits in CCFG. 774 // 0: Disable the boot loader bank erase function. 775 // 1: Enable the boot loader bank erase function. 776 #define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 777 #define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 778 #define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 779 #define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 780 781 //***************************************************************************** 782 // 783 // Register: CCFG_O_CCFG_TI_OPTIONS 784 // 785 //***************************************************************************** 786 // Field: [7:0] TI_FA_ENABLE 787 // 788 // TI Failure Analysis. 789 // 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) 790 // option with the unlock code. 791 // All other values: Disable the functionality of unlocking the TI FA option 792 // with the unlock code. 793 #define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 794 #define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF 795 #define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 796 797 //***************************************************************************** 798 // 799 // Register: CCFG_O_CCFG_TAP_DAP_0 800 // 801 //***************************************************************************** 802 // Field: [23:16] CPU_DAP_ENABLE 803 // 804 // Enable CPU DAP. 805 // 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM 806 // boot FW. 807 // Any other value: Main CPU DAP access will remain disabled out of 808 // power-up/system-reset. 809 #define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 810 #define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 811 #define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 812 813 // Field: [15:8] PWRPROF_TAP_ENABLE 814 // 815 // Enable PWRPROF TAP. 816 // 0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot 817 // FW if enabled by corresponding configuration value in FCFG1 defined by TI. 818 // Any other value: PWRPROF TAP access will remain disabled out of 819 // power-up/system-reset. 820 #define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_W 8 821 #define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M 0x0000FF00 822 #define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S 8 823 824 // Field: [7:0] TEST_TAP_ENABLE 825 // 826 // Enable Test TAP. 827 // 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW 828 // if enabled by corresponding configuration value in FCFG1 defined by TI. 829 // Any other value: TEST TAP access will remain disabled out of 830 // power-up/system-reset. 831 #define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 832 #define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF 833 #define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 834 835 //***************************************************************************** 836 // 837 // Register: CCFG_O_CCFG_TAP_DAP_1 838 // 839 //***************************************************************************** 840 // Field: [23:16] PBIST2_TAP_ENABLE 841 // 842 // Enable PBIST2 TAP. 843 // 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot 844 // FW if enabled by corresponding configuration value in FCFG1 defined by TI. 845 // Any other value: PBIST2 TAP access will remain disabled out of 846 // power-up/system-reset. 847 #define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 848 #define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 849 #define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 850 851 // Field: [15:8] PBIST1_TAP_ENABLE 852 // 853 // Enable PBIST1 TAP. 854 // 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot 855 // FW if enabled by corresponding configuration value in FCFG1 defined by TI. 856 // Any other value: PBIST1 TAP access will remain disabled out of 857 // power-up/system-reset. 858 #define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 859 #define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 860 #define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 861 862 // Field: [7:0] AON_TAP_ENABLE 863 // 864 // Enable AON TAP 865 // 0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW 866 // if enabled by corresponding configuration value in FCFG1 defined by TI. 867 // Any other value: AON TAP access will remain disabled out of 868 // power-up/system-reset. 869 #define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_W 8 870 #define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M 0x000000FF 871 #define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S 0 872 873 //***************************************************************************** 874 // 875 // Register: CCFG_O_IMAGE_VALID_CONF 876 // 877 //***************************************************************************** 878 // Field: [31:0] IMAGE_VALID 879 // 880 // This field must have the address value of the start of the flash vector 881 // table in order to enable the boot FW in ROM to transfer control to a flash 882 // image. 883 // Any illegal vector table start address value will force the boot FW in ROM 884 // to transfer control to the serial boot loader in ROM. 885 #define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 886 #define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF 887 #define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 888 889 //***************************************************************************** 890 // 891 // Register: CCFG_O_CCFG_PROT_31_0 892 // 893 //***************************************************************************** 894 // Field: [31] WRT_PROT_SEC_31 895 // 896 // 0: Sector protected 897 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 898 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 899 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 900 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 901 902 // Field: [30] WRT_PROT_SEC_30 903 // 904 // 0: Sector protected 905 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 906 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 907 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 908 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 909 910 // Field: [29] WRT_PROT_SEC_29 911 // 912 // 0: Sector protected 913 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 914 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 915 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 916 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 917 918 // Field: [28] WRT_PROT_SEC_28 919 // 920 // 0: Sector protected 921 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 922 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 923 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 924 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 925 926 // Field: [27] WRT_PROT_SEC_27 927 // 928 // 0: Sector protected 929 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 930 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 931 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 932 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 933 934 // Field: [26] WRT_PROT_SEC_26 935 // 936 // 0: Sector protected 937 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 938 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 939 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 940 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 941 942 // Field: [25] WRT_PROT_SEC_25 943 // 944 // 0: Sector protected 945 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 946 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 947 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 948 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 949 950 // Field: [24] WRT_PROT_SEC_24 951 // 952 // 0: Sector protected 953 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 954 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 955 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 956 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 957 958 // Field: [23] WRT_PROT_SEC_23 959 // 960 // 0: Sector protected 961 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 962 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 963 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 964 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 965 966 // Field: [22] WRT_PROT_SEC_22 967 // 968 // 0: Sector protected 969 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 970 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 971 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 972 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 973 974 // Field: [21] WRT_PROT_SEC_21 975 // 976 // 0: Sector protected 977 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 978 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 979 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 980 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 981 982 // Field: [20] WRT_PROT_SEC_20 983 // 984 // 0: Sector protected 985 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 986 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 987 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 988 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 989 990 // Field: [19] WRT_PROT_SEC_19 991 // 992 // 0: Sector protected 993 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 994 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 995 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 996 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 997 998 // Field: [18] WRT_PROT_SEC_18 999 // 1000 // 0: Sector protected 1001 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 1002 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 1003 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 1004 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 1005 1006 // Field: [17] WRT_PROT_SEC_17 1007 // 1008 // 0: Sector protected 1009 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 1010 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 1011 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 1012 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 1013 1014 // Field: [16] WRT_PROT_SEC_16 1015 // 1016 // 0: Sector protected 1017 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 1018 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 1019 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 1020 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 1021 1022 // Field: [15] WRT_PROT_SEC_15 1023 // 1024 // 0: Sector protected 1025 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 1026 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 1027 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 1028 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 1029 1030 // Field: [14] WRT_PROT_SEC_14 1031 // 1032 // 0: Sector protected 1033 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 1034 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 1035 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 1036 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 1037 1038 // Field: [13] WRT_PROT_SEC_13 1039 // 1040 // 0: Sector protected 1041 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 1042 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 1043 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 1044 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 1045 1046 // Field: [12] WRT_PROT_SEC_12 1047 // 1048 // 0: Sector protected 1049 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 1050 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 1051 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 1052 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 1053 1054 // Field: [11] WRT_PROT_SEC_11 1055 // 1056 // 0: Sector protected 1057 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 1058 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 1059 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 1060 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 1061 1062 // Field: [10] WRT_PROT_SEC_10 1063 // 1064 // 0: Sector protected 1065 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 1066 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 1067 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 1068 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 1069 1070 // Field: [9] WRT_PROT_SEC_9 1071 // 1072 // 0: Sector protected 1073 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 1074 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 1075 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 1076 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 1077 1078 // Field: [8] WRT_PROT_SEC_8 1079 // 1080 // 0: Sector protected 1081 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 1082 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 1083 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 1084 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 1085 1086 // Field: [7] WRT_PROT_SEC_7 1087 // 1088 // 0: Sector protected 1089 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 1090 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 1091 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 1092 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 1093 1094 // Field: [6] WRT_PROT_SEC_6 1095 // 1096 // 0: Sector protected 1097 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 1098 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 1099 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 1100 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 1101 1102 // Field: [5] WRT_PROT_SEC_5 1103 // 1104 // 0: Sector protected 1105 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 1106 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 1107 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 1108 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 1109 1110 // Field: [4] WRT_PROT_SEC_4 1111 // 1112 // 0: Sector protected 1113 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 1114 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 1115 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 1116 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 1117 1118 // Field: [3] WRT_PROT_SEC_3 1119 // 1120 // 0: Sector protected 1121 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 1122 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 1123 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 1124 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 1125 1126 // Field: [2] WRT_PROT_SEC_2 1127 // 1128 // 0: Sector protected 1129 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 1130 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 1131 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 1132 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 1133 1134 // Field: [1] WRT_PROT_SEC_1 1135 // 1136 // 0: Sector protected 1137 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 1138 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 1139 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 1140 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 1141 1142 // Field: [0] WRT_PROT_SEC_0 1143 // 1144 // 0: Sector protected 1145 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 1146 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 1147 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 1148 #define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 1149 1150 //***************************************************************************** 1151 // 1152 // Register: CCFG_O_CCFG_PROT_63_32 1153 // 1154 //***************************************************************************** 1155 // Field: [31] WRT_PROT_SEC_63 1156 // 1157 // 0: Sector protected 1158 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 1159 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 1160 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 1161 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 1162 1163 // Field: [30] WRT_PROT_SEC_62 1164 // 1165 // 0: Sector protected 1166 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 1167 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 1168 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 1169 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 1170 1171 // Field: [29] WRT_PROT_SEC_61 1172 // 1173 // 0: Sector protected 1174 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 1175 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 1176 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 1177 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 1178 1179 // Field: [28] WRT_PROT_SEC_60 1180 // 1181 // 0: Sector protected 1182 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 1183 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 1184 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 1185 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 1186 1187 // Field: [27] WRT_PROT_SEC_59 1188 // 1189 // 0: Sector protected 1190 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 1191 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 1192 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 1193 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 1194 1195 // Field: [26] WRT_PROT_SEC_58 1196 // 1197 // 0: Sector protected 1198 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 1199 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 1200 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 1201 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 1202 1203 // Field: [25] WRT_PROT_SEC_57 1204 // 1205 // 0: Sector protected 1206 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 1207 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 1208 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 1209 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 1210 1211 // Field: [24] WRT_PROT_SEC_56 1212 // 1213 // 0: Sector protected 1214 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 1215 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 1216 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 1217 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 1218 1219 // Field: [23] WRT_PROT_SEC_55 1220 // 1221 // 0: Sector protected 1222 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 1223 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 1224 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 1225 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 1226 1227 // Field: [22] WRT_PROT_SEC_54 1228 // 1229 // 0: Sector protected 1230 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 1231 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 1232 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 1233 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 1234 1235 // Field: [21] WRT_PROT_SEC_53 1236 // 1237 // 0: Sector protected 1238 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 1239 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 1240 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 1241 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 1242 1243 // Field: [20] WRT_PROT_SEC_52 1244 // 1245 // 0: Sector protected 1246 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 1247 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 1248 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 1249 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 1250 1251 // Field: [19] WRT_PROT_SEC_51 1252 // 1253 // 0: Sector protected 1254 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 1255 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 1256 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 1257 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 1258 1259 // Field: [18] WRT_PROT_SEC_50 1260 // 1261 // 0: Sector protected 1262 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 1263 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 1264 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 1265 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 1266 1267 // Field: [17] WRT_PROT_SEC_49 1268 // 1269 // 0: Sector protected 1270 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 1271 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 1272 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 1273 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 1274 1275 // Field: [16] WRT_PROT_SEC_48 1276 // 1277 // 0: Sector protected 1278 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 1279 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 1280 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 1281 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 1282 1283 // Field: [15] WRT_PROT_SEC_47 1284 // 1285 // 0: Sector protected 1286 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 1287 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 1288 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 1289 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 1290 1291 // Field: [14] WRT_PROT_SEC_46 1292 // 1293 // 0: Sector protected 1294 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 1295 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 1296 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 1297 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 1298 1299 // Field: [13] WRT_PROT_SEC_45 1300 // 1301 // 0: Sector protected 1302 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 1303 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 1304 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 1305 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 1306 1307 // Field: [12] WRT_PROT_SEC_44 1308 // 1309 // 0: Sector protected 1310 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 1311 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 1312 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 1313 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 1314 1315 // Field: [11] WRT_PROT_SEC_43 1316 // 1317 // 0: Sector protected 1318 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 1319 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 1320 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 1321 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 1322 1323 // Field: [10] WRT_PROT_SEC_42 1324 // 1325 // 0: Sector protected 1326 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 1327 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 1328 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 1329 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 1330 1331 // Field: [9] WRT_PROT_SEC_41 1332 // 1333 // 0: Sector protected 1334 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 1335 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 1336 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 1337 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 1338 1339 // Field: [8] WRT_PROT_SEC_40 1340 // 1341 // 0: Sector protected 1342 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 1343 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 1344 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 1345 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 1346 1347 // Field: [7] WRT_PROT_SEC_39 1348 // 1349 // 0: Sector protected 1350 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 1351 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 1352 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 1353 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 1354 1355 // Field: [6] WRT_PROT_SEC_38 1356 // 1357 // 0: Sector protected 1358 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 1359 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 1360 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 1361 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 1362 1363 // Field: [5] WRT_PROT_SEC_37 1364 // 1365 // 0: Sector protected 1366 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 1367 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 1368 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 1369 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 1370 1371 // Field: [4] WRT_PROT_SEC_36 1372 // 1373 // 0: Sector protected 1374 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 1375 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 1376 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 1377 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 1378 1379 // Field: [3] WRT_PROT_SEC_35 1380 // 1381 // 0: Sector protected 1382 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 1383 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 1384 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 1385 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 1386 1387 // Field: [2] WRT_PROT_SEC_34 1388 // 1389 // 0: Sector protected 1390 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 1391 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 1392 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 1393 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 1394 1395 // Field: [1] WRT_PROT_SEC_33 1396 // 1397 // 0: Sector protected 1398 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 1399 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 1400 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 1401 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 1402 1403 // Field: [0] WRT_PROT_SEC_32 1404 // 1405 // 0: Sector protected 1406 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 1407 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 1408 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 1409 #define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 1410 1411 //***************************************************************************** 1412 // 1413 // Register: CCFG_O_CCFG_PROT_95_64 1414 // 1415 //***************************************************************************** 1416 // Field: [31] WRT_PROT_SEC_95 1417 // 1418 // 0: Sector protected 1419 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 1420 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 1421 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 1422 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 1423 1424 // Field: [30] WRT_PROT_SEC_94 1425 // 1426 // 0: Sector protected 1427 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 1428 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 1429 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 1430 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 1431 1432 // Field: [29] WRT_PROT_SEC_93 1433 // 1434 // 0: Sector protected 1435 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 1436 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 1437 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 1438 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 1439 1440 // Field: [28] WRT_PROT_SEC_92 1441 // 1442 // 0: Sector protected 1443 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 1444 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 1445 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 1446 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 1447 1448 // Field: [27] WRT_PROT_SEC_91 1449 // 1450 // 0: Sector protected 1451 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 1452 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 1453 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 1454 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 1455 1456 // Field: [26] WRT_PROT_SEC_90 1457 // 1458 // 0: Sector protected 1459 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 1460 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 1461 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 1462 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 1463 1464 // Field: [25] WRT_PROT_SEC_89 1465 // 1466 // 0: Sector protected 1467 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 1468 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 1469 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 1470 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 1471 1472 // Field: [24] WRT_PROT_SEC_88 1473 // 1474 // 0: Sector protected 1475 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 1476 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 1477 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 1478 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 1479 1480 // Field: [23] WRT_PROT_SEC_87 1481 // 1482 // 0: Sector protected 1483 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 1484 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 1485 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 1486 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 1487 1488 // Field: [22] WRT_PROT_SEC_86 1489 // 1490 // 0: Sector protected 1491 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 1492 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 1493 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 1494 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 1495 1496 // Field: [21] WRT_PROT_SEC_85 1497 // 1498 // 0: Sector protected 1499 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 1500 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 1501 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 1502 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 1503 1504 // Field: [20] WRT_PROT_SEC_84 1505 // 1506 // 0: Sector protected 1507 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 1508 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 1509 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 1510 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 1511 1512 // Field: [19] WRT_PROT_SEC_83 1513 // 1514 // 0: Sector protected 1515 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 1516 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 1517 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 1518 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 1519 1520 // Field: [18] WRT_PROT_SEC_82 1521 // 1522 // 0: Sector protected 1523 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 1524 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 1525 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 1526 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 1527 1528 // Field: [17] WRT_PROT_SEC_81 1529 // 1530 // 0: Sector protected 1531 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 1532 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 1533 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 1534 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 1535 1536 // Field: [16] WRT_PROT_SEC_80 1537 // 1538 // 0: Sector protected 1539 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 1540 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 1541 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 1542 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 1543 1544 // Field: [15] WRT_PROT_SEC_79 1545 // 1546 // 0: Sector protected 1547 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 1548 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 1549 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 1550 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 1551 1552 // Field: [14] WRT_PROT_SEC_78 1553 // 1554 // 0: Sector protected 1555 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 1556 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 1557 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 1558 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 1559 1560 // Field: [13] WRT_PROT_SEC_77 1561 // 1562 // 0: Sector protected 1563 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 1564 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 1565 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 1566 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 1567 1568 // Field: [12] WRT_PROT_SEC_76 1569 // 1570 // 0: Sector protected 1571 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 1572 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 1573 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 1574 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 1575 1576 // Field: [11] WRT_PROT_SEC_75 1577 // 1578 // 0: Sector protected 1579 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 1580 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 1581 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 1582 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 1583 1584 // Field: [10] WRT_PROT_SEC_74 1585 // 1586 // 0: Sector protected 1587 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 1588 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 1589 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 1590 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 1591 1592 // Field: [9] WRT_PROT_SEC_73 1593 // 1594 // 0: Sector protected 1595 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 1596 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 1597 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 1598 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 1599 1600 // Field: [8] WRT_PROT_SEC_72 1601 // 1602 // 0: Sector protected 1603 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 1604 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 1605 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 1606 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 1607 1608 // Field: [7] WRT_PROT_SEC_71 1609 // 1610 // 0: Sector protected 1611 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 1612 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 1613 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 1614 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 1615 1616 // Field: [6] WRT_PROT_SEC_70 1617 // 1618 // 0: Sector protected 1619 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 1620 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 1621 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 1622 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 1623 1624 // Field: [5] WRT_PROT_SEC_69 1625 // 1626 // 0: Sector protected 1627 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 1628 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 1629 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 1630 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 1631 1632 // Field: [4] WRT_PROT_SEC_68 1633 // 1634 // 0: Sector protected 1635 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 1636 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 1637 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 1638 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 1639 1640 // Field: [3] WRT_PROT_SEC_67 1641 // 1642 // 0: Sector protected 1643 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 1644 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 1645 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 1646 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 1647 1648 // Field: [2] WRT_PROT_SEC_66 1649 // 1650 // 0: Sector protected 1651 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 1652 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 1653 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 1654 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 1655 1656 // Field: [1] WRT_PROT_SEC_65 1657 // 1658 // 0: Sector protected 1659 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 1660 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 1661 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 1662 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 1663 1664 // Field: [0] WRT_PROT_SEC_64 1665 // 1666 // 0: Sector protected 1667 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 1668 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 1669 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 1670 #define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 1671 1672 //***************************************************************************** 1673 // 1674 // Register: CCFG_O_CCFG_PROT_127_96 1675 // 1676 //***************************************************************************** 1677 // Field: [31] WRT_PROT_SEC_127 1678 // 1679 // 0: Sector protected 1680 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 1681 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 1682 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 1683 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 1684 1685 // Field: [30] WRT_PROT_SEC_126 1686 // 1687 // 0: Sector protected 1688 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 1689 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 1690 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 1691 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 1692 1693 // Field: [29] WRT_PROT_SEC_125 1694 // 1695 // 0: Sector protected 1696 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 1697 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 1698 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 1699 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 1700 1701 // Field: [28] WRT_PROT_SEC_124 1702 // 1703 // 0: Sector protected 1704 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 1705 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 1706 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 1707 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 1708 1709 // Field: [27] WRT_PROT_SEC_123 1710 // 1711 // 0: Sector protected 1712 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 1713 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 1714 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 1715 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 1716 1717 // Field: [26] WRT_PROT_SEC_122 1718 // 1719 // 0: Sector protected 1720 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 1721 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 1722 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 1723 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 1724 1725 // Field: [25] WRT_PROT_SEC_121 1726 // 1727 // 0: Sector protected 1728 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 1729 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 1730 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 1731 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 1732 1733 // Field: [24] WRT_PROT_SEC_120 1734 // 1735 // 0: Sector protected 1736 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 1737 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 1738 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 1739 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 1740 1741 // Field: [23] WRT_PROT_SEC_119 1742 // 1743 // 0: Sector protected 1744 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 1745 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 1746 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 1747 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 1748 1749 // Field: [22] WRT_PROT_SEC_118 1750 // 1751 // 0: Sector protected 1752 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 1753 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 1754 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 1755 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 1756 1757 // Field: [21] WRT_PROT_SEC_117 1758 // 1759 // 0: Sector protected 1760 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 1761 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 1762 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 1763 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 1764 1765 // Field: [20] WRT_PROT_SEC_116 1766 // 1767 // 0: Sector protected 1768 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 1769 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 1770 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 1771 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 1772 1773 // Field: [19] WRT_PROT_SEC_115 1774 // 1775 // 0: Sector protected 1776 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 1777 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 1778 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 1779 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 1780 1781 // Field: [18] WRT_PROT_SEC_114 1782 // 1783 // 0: Sector protected 1784 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 1785 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 1786 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 1787 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 1788 1789 // Field: [17] WRT_PROT_SEC_113 1790 // 1791 // 0: Sector protected 1792 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 1793 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 1794 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 1795 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 1796 1797 // Field: [16] WRT_PROT_SEC_112 1798 // 1799 // 0: Sector protected 1800 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 1801 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 1802 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 1803 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 1804 1805 // Field: [15] WRT_PROT_SEC_111 1806 // 1807 // 0: Sector protected 1808 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 1809 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 1810 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 1811 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 1812 1813 // Field: [14] WRT_PROT_SEC_110 1814 // 1815 // 0: Sector protected 1816 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 1817 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 1818 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 1819 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 1820 1821 // Field: [13] WRT_PROT_SEC_109 1822 // 1823 // 0: Sector protected 1824 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 1825 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 1826 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 1827 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 1828 1829 // Field: [12] WRT_PROT_SEC_108 1830 // 1831 // 0: Sector protected 1832 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 1833 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 1834 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 1835 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 1836 1837 // Field: [11] WRT_PROT_SEC_107 1838 // 1839 // 0: Sector protected 1840 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 1841 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 1842 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 1843 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 1844 1845 // Field: [10] WRT_PROT_SEC_106 1846 // 1847 // 0: Sector protected 1848 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 1849 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 1850 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 1851 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 1852 1853 // Field: [9] WRT_PROT_SEC_105 1854 // 1855 // 0: Sector protected 1856 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 1857 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 1858 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 1859 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 1860 1861 // Field: [8] WRT_PROT_SEC_104 1862 // 1863 // 0: Sector protected 1864 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 1865 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 1866 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 1867 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 1868 1869 // Field: [7] WRT_PROT_SEC_103 1870 // 1871 // 0: Sector protected 1872 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 1873 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 1874 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 1875 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 1876 1877 // Field: [6] WRT_PROT_SEC_102 1878 // 1879 // 0: Sector protected 1880 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 1881 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 1882 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 1883 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 1884 1885 // Field: [5] WRT_PROT_SEC_101 1886 // 1887 // 0: Sector protected 1888 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 1889 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 1890 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 1891 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 1892 1893 // Field: [4] WRT_PROT_SEC_100 1894 // 1895 // 0: Sector protected 1896 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 1897 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 1898 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 1899 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 1900 1901 // Field: [3] WRT_PROT_SEC_99 1902 // 1903 // 0: Sector protected 1904 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 1905 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 1906 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 1907 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 1908 1909 // Field: [2] WRT_PROT_SEC_98 1910 // 1911 // 0: Sector protected 1912 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 1913 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 1914 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 1915 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 1916 1917 // Field: [1] WRT_PROT_SEC_97 1918 // 1919 // 0: Sector protected 1920 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 1921 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 1922 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 1923 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 1924 1925 // Field: [0] WRT_PROT_SEC_96 1926 // 1927 // 0: Sector protected 1928 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 1929 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 1930 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 1931 #define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 1932 1933 1934 #endif // __CCFG__ 1935
