1 /* 2 * Copyright (c) 2022 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_ 7 #define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_ 8 9 10 /* macros related to interrupt handling */ 11 #define XTENSA_IRQ_NUM_SHIFT 0 12 #define CAVS_IRQ_NUM_SHIFT 8 13 #define XTENSA_IRQ_NUM_MASK 0xff 14 #define CAVS_IRQ_NUM_MASK 0xff 15 16 /* 17 * IRQs are mapped on 2 levels. 3rd and 4th level are left as 0x00. 18 * 19 * 1. Peripheral Register bit offset. 20 * 2. CAVS logic bit offset. 21 */ 22 #define XTENSA_IRQ_NUMBER(_irq) \ 23 ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) 24 #define CAVS_IRQ_NUMBER(_irq) \ 25 (((_irq >> CAVS_IRQ_NUM_SHIFT) & CAVS_IRQ_NUM_MASK) - 1) 26 27 /* Macro that aggregates the bi-level interrupt into an IRQ number */ 28 #define SOC_AGGREGATE_IRQ(cavs_irq, core_irq) \ 29 ( \ 30 ((core_irq & XTENSA_IRQ_NUM_MASK) << XTENSA_IRQ_NUM_SHIFT) | \ 31 (((cavs_irq + 1) & CAVS_IRQ_NUM_MASK) << CAVS_IRQ_NUM_SHIFT) \ 32 ) 33 34 #define CAVS_L2_AGG_INT_LEVEL2 DT_IRQN(DT_INST(0, intel_cavs_intc)) 35 #define CAVS_L2_AGG_INT_LEVEL3 DT_IRQN(DT_INST(1, intel_cavs_intc)) 36 #define CAVS_L2_AGG_INT_LEVEL4 DT_IRQN(DT_INST(2, intel_cavs_intc)) 37 #define CAVS_L2_AGG_INT_LEVEL5 DT_IRQN(DT_INST(3, intel_cavs_intc)) 38 39 #define CAVS_ICTL_INT_CPU_OFFSET(x) (0x40 * x) 40 41 42 #endif 43
