1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CAN_TBS.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_CAN_TBS 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CAN_TBS_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CAN_TBS_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CAN_TBS Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CAN_TBS_Peripheral_Access_Layer CAN_TBS Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CAN_TBS - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t CAN_TB_VALUE; /**< CAN Time Base Output Value, offset: 0x0 */ 74 uint8_t RESERVED_0[2044]; 75 __IO uint32_t CAN_TS_SEL; /**< CAN Timestamp Mux Selector, offset: 0x800 */ 76 } CAN_TBS_Type, *CAN_TBS_MemMapPtr; 77 78 /** Number of instances of the CAN_TBS module. */ 79 #define CAN_TBS_INSTANCE_COUNT (26u) 80 81 /* CAN_TBS - Peripheral instance base addresses */ 82 /** Peripheral CANXL_0_TBS base address */ 83 #define IP_CANXL_0_TBS_BASE (0x419B0000u) 84 /** Peripheral CANXL_0_TBS base pointer */ 85 #define IP_CANXL_0_TBS ((CAN_TBS_Type *)IP_CANXL_0_TBS_BASE) 86 /** Peripheral CANXL_1_TBS base address */ 87 #define IP_CANXL_1_TBS_BASE (0x419C0000u) 88 /** Peripheral CANXL_1_TBS base pointer */ 89 #define IP_CANXL_1_TBS ((CAN_TBS_Type *)IP_CANXL_1_TBS_BASE) 90 /** Peripheral CE_CAN_TBS_0 base address */ 91 #define IP_CE_CAN_TBS_0_BASE (0x449A8000u) 92 /** Peripheral CE_CAN_TBS_0 base pointer */ 93 #define IP_CE_CAN_TBS_0 ((CAN_TBS_Type *)IP_CE_CAN_TBS_0_BASE) 94 /** Peripheral CE_CAN_TBS_1 base address */ 95 #define IP_CE_CAN_TBS_1_BASE (0x449B8000u) 96 /** Peripheral CE_CAN_TBS_1 base pointer */ 97 #define IP_CE_CAN_TBS_1 ((CAN_TBS_Type *)IP_CE_CAN_TBS_1_BASE) 98 /** Peripheral CE_CAN_TBS_2 base address */ 99 #define IP_CE_CAN_TBS_2_BASE (0x449C8000u) 100 /** Peripheral CE_CAN_TBS_2 base pointer */ 101 #define IP_CE_CAN_TBS_2 ((CAN_TBS_Type *)IP_CE_CAN_TBS_2_BASE) 102 /** Peripheral CE_CAN_TBS_3 base address */ 103 #define IP_CE_CAN_TBS_3_BASE (0x449D8000u) 104 /** Peripheral CE_CAN_TBS_3 base pointer */ 105 #define IP_CE_CAN_TBS_3 ((CAN_TBS_Type *)IP_CE_CAN_TBS_3_BASE) 106 /** Peripheral CE_CAN_TBS_4 base address */ 107 #define IP_CE_CAN_TBS_4_BASE (0x449E8000u) 108 /** Peripheral CE_CAN_TBS_4 base pointer */ 109 #define IP_CE_CAN_TBS_4 ((CAN_TBS_Type *)IP_CE_CAN_TBS_4_BASE) 110 /** Peripheral CE_CAN_TBS_5 base address */ 111 #define IP_CE_CAN_TBS_5_BASE (0x449F8000u) 112 /** Peripheral CE_CAN_TBS_5 base pointer */ 113 #define IP_CE_CAN_TBS_5 ((CAN_TBS_Type *)IP_CE_CAN_TBS_5_BASE) 114 /** Peripheral CE_CAN_TBS_6 base address */ 115 #define IP_CE_CAN_TBS_6_BASE (0x44BA8000u) 116 /** Peripheral CE_CAN_TBS_6 base pointer */ 117 #define IP_CE_CAN_TBS_6 ((CAN_TBS_Type *)IP_CE_CAN_TBS_6_BASE) 118 /** Peripheral CE_CAN_TBS_7 base address */ 119 #define IP_CE_CAN_TBS_7_BASE (0x44BB8000u) 120 /** Peripheral CE_CAN_TBS_7 base pointer */ 121 #define IP_CE_CAN_TBS_7 ((CAN_TBS_Type *)IP_CE_CAN_TBS_7_BASE) 122 /** Peripheral CE_CAN_TBS_8 base address */ 123 #define IP_CE_CAN_TBS_8_BASE (0x44BC8000u) 124 /** Peripheral CE_CAN_TBS_8 base pointer */ 125 #define IP_CE_CAN_TBS_8 ((CAN_TBS_Type *)IP_CE_CAN_TBS_8_BASE) 126 /** Peripheral CE_CAN_TBS_9 base address */ 127 #define IP_CE_CAN_TBS_9_BASE (0x44BD8000u) 128 /** Peripheral CE_CAN_TBS_9 base pointer */ 129 #define IP_CE_CAN_TBS_9 ((CAN_TBS_Type *)IP_CE_CAN_TBS_9_BASE) 130 /** Peripheral CE_CAN_TBS_10 base address */ 131 #define IP_CE_CAN_TBS_10_BASE (0x44BE8000u) 132 /** Peripheral CE_CAN_TBS_10 base pointer */ 133 #define IP_CE_CAN_TBS_10 ((CAN_TBS_Type *)IP_CE_CAN_TBS_10_BASE) 134 /** Peripheral CE_CAN_TBS_11 base address */ 135 #define IP_CE_CAN_TBS_11_BASE (0x44BF8000u) 136 /** Peripheral CE_CAN_TBS_11 base pointer */ 137 #define IP_CE_CAN_TBS_11 ((CAN_TBS_Type *)IP_CE_CAN_TBS_11_BASE) 138 /** Peripheral CE_CAN_TBS_12 base address */ 139 #define IP_CE_CAN_TBS_12_BASE (0x44DA8000u) 140 /** Peripheral CE_CAN_TBS_12 base pointer */ 141 #define IP_CE_CAN_TBS_12 ((CAN_TBS_Type *)IP_CE_CAN_TBS_12_BASE) 142 /** Peripheral CE_CAN_TBS_13 base address */ 143 #define IP_CE_CAN_TBS_13_BASE (0x44DB8000u) 144 /** Peripheral CE_CAN_TBS_13 base pointer */ 145 #define IP_CE_CAN_TBS_13 ((CAN_TBS_Type *)IP_CE_CAN_TBS_13_BASE) 146 /** Peripheral CE_CAN_TBS_14 base address */ 147 #define IP_CE_CAN_TBS_14_BASE (0x44DC8000u) 148 /** Peripheral CE_CAN_TBS_14 base pointer */ 149 #define IP_CE_CAN_TBS_14 ((CAN_TBS_Type *)IP_CE_CAN_TBS_14_BASE) 150 /** Peripheral CE_CAN_TBS_15 base address */ 151 #define IP_CE_CAN_TBS_15_BASE (0x44DD8000u) 152 /** Peripheral CE_CAN_TBS_15 base pointer */ 153 #define IP_CE_CAN_TBS_15 ((CAN_TBS_Type *)IP_CE_CAN_TBS_15_BASE) 154 /** Peripheral CE_CAN_TBS_16 base address */ 155 #define IP_CE_CAN_TBS_16_BASE (0x44DE8000u) 156 /** Peripheral CE_CAN_TBS_16 base pointer */ 157 #define IP_CE_CAN_TBS_16 ((CAN_TBS_Type *)IP_CE_CAN_TBS_16_BASE) 158 /** Peripheral CE_CAN_TBS_17 base address */ 159 #define IP_CE_CAN_TBS_17_BASE (0x44DF8000u) 160 /** Peripheral CE_CAN_TBS_17 base pointer */ 161 #define IP_CE_CAN_TBS_17 ((CAN_TBS_Type *)IP_CE_CAN_TBS_17_BASE) 162 /** Peripheral CE_CAN_TBS_18 base address */ 163 #define IP_CE_CAN_TBS_18_BASE (0x44FA8000u) 164 /** Peripheral CE_CAN_TBS_18 base pointer */ 165 #define IP_CE_CAN_TBS_18 ((CAN_TBS_Type *)IP_CE_CAN_TBS_18_BASE) 166 /** Peripheral CE_CAN_TBS_19 base address */ 167 #define IP_CE_CAN_TBS_19_BASE (0x44FB8000u) 168 /** Peripheral CE_CAN_TBS_19 base pointer */ 169 #define IP_CE_CAN_TBS_19 ((CAN_TBS_Type *)IP_CE_CAN_TBS_19_BASE) 170 /** Peripheral CE_CAN_TBS_20 base address */ 171 #define IP_CE_CAN_TBS_20_BASE (0x44FC8000u) 172 /** Peripheral CE_CAN_TBS_20 base pointer */ 173 #define IP_CE_CAN_TBS_20 ((CAN_TBS_Type *)IP_CE_CAN_TBS_20_BASE) 174 /** Peripheral CE_CAN_TBS_21 base address */ 175 #define IP_CE_CAN_TBS_21_BASE (0x44FD8000u) 176 /** Peripheral CE_CAN_TBS_21 base pointer */ 177 #define IP_CE_CAN_TBS_21 ((CAN_TBS_Type *)IP_CE_CAN_TBS_21_BASE) 178 /** Peripheral CE_CAN_TBS_22 base address */ 179 #define IP_CE_CAN_TBS_22_BASE (0x44FE8000u) 180 /** Peripheral CE_CAN_TBS_22 base pointer */ 181 #define IP_CE_CAN_TBS_22 ((CAN_TBS_Type *)IP_CE_CAN_TBS_22_BASE) 182 /** Peripheral CE_CAN_TBS_23 base address */ 183 #define IP_CE_CAN_TBS_23_BASE (0x44FF8000u) 184 /** Peripheral CE_CAN_TBS_23 base pointer */ 185 #define IP_CE_CAN_TBS_23 ((CAN_TBS_Type *)IP_CE_CAN_TBS_23_BASE) 186 /** Array initializer of CAN_TBS peripheral base addresses */ 187 #define IP_CAN_TBS_BASE_ADDRS { IP_CANXL_0_TBS_BASE, IP_CANXL_1_TBS_BASE, IP_CE_CAN_TBS_0_BASE, IP_CE_CAN_TBS_1_BASE, IP_CE_CAN_TBS_2_BASE, IP_CE_CAN_TBS_3_BASE, IP_CE_CAN_TBS_4_BASE, IP_CE_CAN_TBS_5_BASE, IP_CE_CAN_TBS_6_BASE, IP_CE_CAN_TBS_7_BASE, IP_CE_CAN_TBS_8_BASE, IP_CE_CAN_TBS_9_BASE, IP_CE_CAN_TBS_10_BASE, IP_CE_CAN_TBS_11_BASE, IP_CE_CAN_TBS_12_BASE, IP_CE_CAN_TBS_13_BASE, IP_CE_CAN_TBS_14_BASE, IP_CE_CAN_TBS_15_BASE, IP_CE_CAN_TBS_16_BASE, IP_CE_CAN_TBS_17_BASE, IP_CE_CAN_TBS_18_BASE, IP_CE_CAN_TBS_19_BASE, IP_CE_CAN_TBS_20_BASE, IP_CE_CAN_TBS_21_BASE, IP_CE_CAN_TBS_22_BASE, IP_CE_CAN_TBS_23_BASE } 188 /** Array initializer of CAN_TBS peripheral base pointers */ 189 #define IP_CAN_TBS_BASE_PTRS { IP_CANXL_0_TBS, IP_CANXL_1_TBS, IP_CE_CAN_TBS_0, IP_CE_CAN_TBS_1, IP_CE_CAN_TBS_2, IP_CE_CAN_TBS_3, IP_CE_CAN_TBS_4, IP_CE_CAN_TBS_5, IP_CE_CAN_TBS_6, IP_CE_CAN_TBS_7, IP_CE_CAN_TBS_8, IP_CE_CAN_TBS_9, IP_CE_CAN_TBS_10, IP_CE_CAN_TBS_11, IP_CE_CAN_TBS_12, IP_CE_CAN_TBS_13, IP_CE_CAN_TBS_14, IP_CE_CAN_TBS_15, IP_CE_CAN_TBS_16, IP_CE_CAN_TBS_17, IP_CE_CAN_TBS_18, IP_CE_CAN_TBS_19, IP_CE_CAN_TBS_20, IP_CE_CAN_TBS_21, IP_CE_CAN_TBS_22, IP_CE_CAN_TBS_23 } 190 191 /* ---------------------------------------------------------------------------- 192 -- CAN_TBS Register Masks 193 ---------------------------------------------------------------------------- */ 194 195 /*! 196 * @addtogroup CAN_TBS_Register_Masks CAN_TBS Register Masks 197 * @{ 198 */ 199 200 /*! @name CAN_TB_VALUE - CAN Time Base Output Value */ 201 /*! @{ */ 202 203 #define CAN_TBS_CAN_TB_VALUE_TB_VALUE_MASK (0xFFFFFFFFU) 204 #define CAN_TBS_CAN_TB_VALUE_TB_VALUE_SHIFT (0U) 205 #define CAN_TBS_CAN_TB_VALUE_TB_VALUE_WIDTH (32U) 206 #define CAN_TBS_CAN_TB_VALUE_TB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TBS_CAN_TB_VALUE_TB_VALUE_SHIFT)) & CAN_TBS_CAN_TB_VALUE_TB_VALUE_MASK) 207 /*! @} */ 208 209 /*! @name CAN_TS_SEL - CAN Timestamp Mux Selector */ 210 /*! @{ */ 211 212 #define CAN_TBS_CAN_TS_SEL_TS_SEL_MASK (0x3U) 213 #define CAN_TBS_CAN_TS_SEL_TS_SEL_SHIFT (0U) 214 #define CAN_TBS_CAN_TS_SEL_TS_SEL_WIDTH (2U) 215 #define CAN_TBS_CAN_TS_SEL_TS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TBS_CAN_TS_SEL_TS_SEL_SHIFT)) & CAN_TBS_CAN_TS_SEL_TS_SEL_MASK) 216 /*! @} */ 217 218 /*! 219 * @} 220 */ /* end of group CAN_TBS_Register_Masks */ 221 222 /*! 223 * @} 224 */ /* end of group CAN_TBS_Peripheral_Access_Layer */ 225 226 #endif /* #if !defined(S32Z2_CAN_TBS_H_) */ 227
