1 /**************************************************************************//** 2 * @file can_reg.h 3 * @version V1.00 4 * @brief CAN register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CAN_REG_H__ 10 #define __CAN_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup CAN Controller Area Network Controller(CAN) 23 Memory Mapped Structure for CAN Controller 24 @{ */ 25 26 27 typedef struct 28 { 29 30 /** 31 * @var CAN_IF_T::CREQ 32 * Offset: 0x20, 0x80 IFn Command Request Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[5:0] |MessageNumber|Message Number 37 * | | |0x01-0x20: Valid Message Number, the Message Object in the Message 38 * | | |RAM is selected for data transfer. 39 * | | |0x00: Not a valid Message Number, interpreted as 0x20. 40 * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. 41 * |[15] |Busy |Busy Flag 42 * | | |0 = Read/write action has finished. 43 * | | |1 = Writing to the IFn Command Request Register is in progress 44 * | | |This bit can only be read by the software. 45 * @var CAN_IF_T::CMASK 46 * Offset: 0x24, 0x84 IFn Command Mask Register 47 * --------------------------------------------------------------------------------------------------- 48 * |Bits |Field |Descriptions 49 * | :----: | :----: | :---- | 50 * |[0] |DAT_B |Access Data Bytes [7:4] 51 * | | |Write Operation: 52 * | | |0 = Data Bytes [7:4] unchanged. 53 * | | |1 = Transfer Data Bytes [7:4] to Message Object. 54 * | | |Read Operation: 55 * | | |0 = Data Bytes [7:4] unchanged. 56 * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register. 57 * |[1] |DAT_A |Access Data Bytes [3:0] 58 * | | |Write Operation: 59 * | | |0 = Data Bytes [3:0] unchanged. 60 * | | |1 = Transfer Data Bytes [3:0] to Message Object. 61 * | | |Read Operation: 62 * | | |0 = Data Bytes [3:0] unchanged. 63 * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register. 64 * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation 65 * | | |0 = TxRqst bit unchanged. 66 * | | |1 = Set TxRqst bit. 67 * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored. 68 * | | |Access New Data Bit when Read Operation. 69 * | | |0 = NewDat bit remains unchanged. 70 * | | |1 = Clear NewDat bit in the Message Object. 71 * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat 72 * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. 73 * |[3] |ClrIntPnd |Clear Interrupt Pending Bit 74 * | | |Write Operation: 75 * | | |When writing to a Message Object, this bit is ignored. 76 * | | |Read Operation: 77 * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged. 78 * | | |1 = Clear IntPnd bit in the Message Object. 79 * |[4] |Control |Control Access Control Bits 80 * | | |Write Operation: 81 * | | |0 = Control Bits unchanged. 82 * | | |1 = Transfer Control Bits to Message Object. 83 * | | |Read Operation: 84 * | | |0 = Control Bits unchanged. 85 * | | |1 = Transfer Control Bits to IFn Message Buffer Register. 86 * |[5] |Arb |Access Arbitration Bits 87 * | | |Write Operation: 88 * | | |0 = Arbitration bits unchanged. 89 * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object. 90 * | | |Read Operation: 91 * | | |0 = Arbitration bits unchanged. 92 * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register. 93 * |[6] |Mask |Access Mask Bits 94 * | | |Write Operation: 95 * | | |0 = Mask bits unchanged. 96 * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object. 97 * | | |Read Operation: 98 * | | |0 = Mask bits unchanged. 99 * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register. 100 * |[7] |WR_RD |Write / Read Mode 101 * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. 102 * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register. 103 * @var CAN_IF_T::MASK1 104 * Offset: 0x28, 0x88 IFn Mask 1 Register 105 * --------------------------------------------------------------------------------------------------- 106 * |Bits |Field |Descriptions 107 * | :----: | :----: | :---- | 108 * |[15:0] |Msk |Identifier Mask 15-0 109 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. 110 * | | |1 = The corresponding identifier bit is used for acceptance filtering. 111 * @var CAN_IF_T::MASK2 112 * Offset: 0x2C, 0x8C IFn Mask 2 Register 113 * --------------------------------------------------------------------------------------------------- 114 * |Bits |Field |Descriptions 115 * | :----: | :----: | :---- | 116 * |[12:0] |Msk |Identifier Mask 28-16 117 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. 118 * | | |1 = The corresponding identifier bit is used for acceptance filtering. 119 * |[14] |MDir |Mask Message Direction 120 * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering. 121 * | | |1 = The message direction bit (Dir) is used for acceptance filtering. 122 * |[15] |MXtd |Mask Extended Identifier 123 * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering. 124 * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering. 125 * | | |Note: When 11-bit (standard) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]) 126 * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. 127 * @var CAN_IF_T::ARB1 128 * Offset: 0x30, 0x90 IFn Arbitration 1 Register 129 * --------------------------------------------------------------------------------------------------- 130 * |Bits |Field |Descriptions 131 * | :----: | :----: | :---- | 132 * |[15:0] |ID |Message Identifier 15-0 133 * | | |ID28 - ID0, 29-bit Identifier (Extended Frame) 134 * | | |ID28 - ID18, 11-bit Identifier (Standard Frame) 135 * @var CAN_IF_T::ARB2 136 * Offset: 0x34, 0x94 IFn Arbitration 2 Register 137 * --------------------------------------------------------------------------------------------------- 138 * |Bits |Field |Descriptions 139 * | :----: | :----: | :---- | 140 * |[12:0] |ID |Message Identifier 28-16 141 * | | |ID28 - ID0, 29-bit Identifier (Extended Frame) 142 * | | |ID28 - ID18, 11-bit Identifier (Standard Frame) 143 * |[13] |Dir |Message Direction 144 * | | |0 = Direction is receive. 145 * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted 146 * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object. 147 * | | |1 = Direction is transmit. 148 * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame 149 * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one). 150 * |[14] |Xtd |Extended Identifier 151 * | | |0 = The 11-bit (standard) Identifier will be used for this Message Object. 152 * | | |1 = The 29-bit (extended) Identifier will be used for this Message Object. 153 * |[15] |MsgVal |Message Valid 154 * | | |0 = The Message Object is ignored by the Message Handler. 155 * | | |1 = The Message Object is configured and should be considered by the Message Handler. 156 * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]) 157 * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. 158 * @var CAN_IF_T::MCON 159 * Offset: 0x38, 0x98 IFn Message Control Register 160 * --------------------------------------------------------------------------------------------------- 161 * |Bits |Field |Descriptions 162 * | :----: | :----: | :---- | 163 * |[3:0] |DLC |Data Length Code 164 * | | |0-8: Data Frame has 0-8 data bytes. 165 * | | |9-15: Data Frame has 8 data bytes 166 * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes 167 * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 168 * | | |Data(0): 1st data byte of a CAN Data Frame 169 * | | |Data(1): 2nd data byte of a CAN Data Frame 170 * | | |Data(2): 3rd data byte of a CAN Data Frame 171 * | | |Data(3): 4th data byte of a CAN Data Frame 172 * | | |Data(4): 5th data byte of a CAN Data Frame 173 * | | |Data(5): 6th data byte of a CAN Data Frame 174 * | | |Data(6): 7th data byte of a CAN Data Frame 175 * | | |Data(7): 8th data byte of a CAN Data Frame 176 * | | |Note: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last 177 * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object 178 * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. 179 * |[7] |EoB |End of Buffer 180 * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer. 181 * | | |1 = Single Message Object or last Message Object of a FIFO Buffer. 182 * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer 183 * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one 184 * |[8] |TxRqst |Transmit Request 185 * | | |0 = This Message Object is not waiting for transmission. 186 * | | |1 = The transmission of this Message Object is requested and is not yet done. 187 * |[9] |RmtEn |Remote Enable Bit 188 * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. 189 * | | |1 = At the reception of a Remote Frame, TxRqst is set. 190 * |[10] |RxIE |Receive Interrupt Enable Bit 191 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame. 192 * | | |1 = IntPnd will be set after a successful reception of a frame. 193 * |[11] |TxIE |Transmit Interrupt Enable Bit 194 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame. 195 * | | |1 = IntPnd will be set after a successful transmission of a frame. 196 * |[12] |UMask |Use Acceptance Mask 197 * | | |0 = Mask ignored. 198 * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering. 199 * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one. 200 * |[13] |IntPnd |Interrupt Pending 201 * | | |0 = This message object is not the source of an interrupt. 202 * | | |1 = This message object is the source of an interrupt 203 * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. 204 * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive). 205 * | | |0 = No message lost since last time this bit was reset by the CPU. 206 * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message. 207 * |[15] |NewDat |New Data 208 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software. 209 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. 210 * @var CAN_IF_T::DAT_A1 211 * Offset: 0x3C, 0x9C IFn Data A1 Register 212 * --------------------------------------------------------------------------------------------------- 213 * |Bits |Field |Descriptions 214 * | :----: | :----: | :---- | 215 * |[7:0] |Data_0_ |Data Byte 0 216 * | | |1st data byte of a CAN Data Frame 217 * |[15:8] |Data_1_ |Data Byte 1 218 * | | |2nd data byte of a CAN Data Frame 219 * @var CAN_IF_T::DAT_A2 220 * Offset: 0x40, 0xA0 IFn Data A2 Register 221 * --------------------------------------------------------------------------------------------------- 222 * |Bits |Field |Descriptions 223 * | :----: | :----: | :---- | 224 * |[7:0] |Data_2_ |Data Byte 2 225 * | | |3rd data byte of CAN Data Frame 226 * |[15:8] |Data_3_ |Data Byte 3 227 * | | |4th data byte of CAN Data Frame 228 * @var CAN_IF_T::DAT_B1 229 * Offset: 0x44, 0xA4 IFn Data B1 Register 230 * --------------------------------------------------------------------------------------------------- 231 * |Bits |Field |Descriptions 232 * | :----: | :----: | :---- | 233 * |[7:0] |Data_4_ |Data Byte 4 234 * | | |5th data byte of CAN Data Frame 235 * |[15:8] |Data_5_ |Data Byte 5 236 * | | |6th data byte of CAN Data Frame 237 * @var CAN_IF_T::DAT_B2 238 * Offset: 0x48, 0xA8 IFn Data B2 Register 239 * --------------------------------------------------------------------------------------------------- 240 * |Bits |Field |Descriptions 241 * | :----: | :----: | :---- | 242 * |[7:0] |Data_6_ |Data Byte 6 243 * | | |7th data byte of CAN Data Frame. 244 * |[15:8] |Data_7_ |Data Byte 7 245 * | | |8th data byte of CAN Data Frame. 246 */ 247 __IO uint32_t CREQ; /*!< [0x0020] IFn Command Request Register */ 248 __IO uint32_t CMASK; /*!< [0x0024] IFn Command Mask Register */ 249 __IO uint32_t MASK1; /*!< [0x0028] IFn Mask 1 Register */ 250 __IO uint32_t MASK2; /*!< [0x002c] IFn Mask 2 Register */ 251 __IO uint32_t ARB1; /*!< [0x0030] IFn Arbitration 1 Register */ 252 __IO uint32_t ARB2; /*!< [0x0034] IFn Arbitration 2 Register */ 253 __IO uint32_t MCON; /*!< [0x0038] IFn Message Control Register */ 254 __IO uint32_t DAT_A1; /*!< [0x003c] IFn Data A1 Register */ 255 __IO uint32_t DAT_A2; /*!< [0x0040] IFn Data A2 Register */ 256 __IO uint32_t DAT_B1; /*!< [0x0044] IFn Data B1 Register */ 257 __IO uint32_t DAT_B2; /*!< [0x0048] IFn Data B2 Register */ 258 /// @cond HIDDEN_SYMBOLS 259 __I uint32_t RESERVE0[13]; 260 /// @endcond //HIDDEN_SYMBOLS 261 } CAN_IF_T; 262 263 264 typedef struct 265 { 266 267 268 /** 269 * @var CAN_T::CON 270 * Offset: 0x00 Control Register 271 * --------------------------------------------------------------------------------------------------- 272 * |Bits |Field |Descriptions 273 * | :----: | :----: | :---- | 274 * |[0] |Init |Init Initialization 275 * | | |0 = Normal Operation. 276 * | | |1 = Initialization is started. 277 * |[1] |IE |Module Interrupt Enable Bit 278 * | | |0 = Function interrupt is Disabled. 279 * | | |1 = Function interrupt is Enabled. 280 * |[2] |SIE |Status Change Interrupt Enable Bit 281 * | | |0 = Disabled - No Status Change Interrupt will be generated. 282 * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. 283 * |[3] |EIE |Error Interrupt Enable Bit 284 * | | |0 = Disabled - No Error Status Interrupt will be generated. 285 * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt. 286 * |[5] |DAR |Automatic Re-transmission Disable Bit 287 * | | |0 = Automatic Retransmission of disturbed messages Enabled. 288 * | | |1 = Automatic Retransmission Disabled. 289 * |[6] |CCE |Configuration Change Enable Bit 290 * | | |0 = No write access to the Bit Timing Register. 291 * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1). 292 * |[7] |Test |Test Mode Enable Bit 293 * | | |0 = Normal Operation. 294 * | | |1 = Test Mode. 295 * @var CAN_T::STATUS 296 * Offset: 0x04 Status Register 297 * --------------------------------------------------------------------------------------------------- 298 * |Bits |Field |Descriptions 299 * | :----: | :----: | :---- | 300 * |[2:0] |LEC |Last Error Code (Type of the Last Error to Occur on the CAN Bus) 301 * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus 302 * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error 303 * | | |The unused code '7' may be written by the CPU to check for updates 304 * | | |The Error! Reference source not found 305 * | | |describes the error code. 306 * |[3] |TxOK |Transmitted a Message Successfully 307 * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted 308 * | | |This bit is never reset by the CAN Core. 309 * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. 310 * |[4] |RxOK |Received a Message Successfully 311 * | | |0 = No message has been successfully received since this bit was last reset by the CPU 312 * | | |This bit is never reset by the CAN Core. 313 * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering). 314 * |[5] |EPass |Error Passive (Read Only) 315 * | | |0 = The CAN Core is error active. 316 * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification. 317 * |[6] |EWarn |Error Warning Status (Read Only) 318 * | | |0 = Both error counters are below the error warning limit of 96. 319 * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96. 320 * |[7] |BOff |Bus-off Status (Read Only) 321 * | | |0 = The CAN module is not in bus-off state. 322 * | | |1 = The CAN module is in bus-off state. 323 * @var CAN_T::ERR 324 * Offset: 0x08 Error Counter Register 325 * --------------------------------------------------------------------------------------------------- 326 * |Bits |Field |Descriptions 327 * | :----: | :----: | :---- | 328 * |[7:0] |TEC |Transmit Error Counter 329 * | | |Actual state of the Transmit Error Counter. Values between 0 and 255. 330 * |[14:8] |REC |Receive Error Counter 331 * | | |Actual state of the Receive Error Counter. Values between 0 and 127. 332 * |[15] |RP |Receive Error Passive 333 * | | |0 = The Receive Error Counter is below the error passive level. 334 * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification. 335 * @var CAN_T::BTIME 336 * Offset: 0x0C Bit Timing Register 337 * --------------------------------------------------------------------------------------------------- 338 * |Bits |Field |Descriptions 339 * | :----: | :----: | :---- | 340 * |[5:0] |BRP |Baud Rate Prescaler 341 * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta 342 * | | |The bit time is built up from a multiple of this quanta 343 * | | |Valid values for the Baud Rate Prescaler are [0...63] 344 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 345 * |[7:6] |SJW |(Re)Synchronization Jump Width 346 * | | |0x0-0x3: Valid programmed values are [0...3] 347 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 348 * |[11:8] |TSeg1 |Time Segment Before the Sample Point Minus Sync_Seg 349 * | | |0x01-0x0F: valid values for TSeg1 are [1...15] 350 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used. 351 * |[14:12] |TSeg2 |Time Segment After Sample Point 352 * | | |0x0-0x7: Valid values for TSeg2 are [0...7] 353 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 354 * @var CAN_T::IIDR 355 * Offset: 0x10 Interrupt Identifier Register 356 * --------------------------------------------------------------------------------------------------- 357 * |Bits |Field |Descriptions 358 * | :----: | :----: | :---- | 359 * |[15:0] |IntId |Interrupt Identifier (Indicates the Source of the Interrupt) 360 * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order 361 * | | |An interrupt remains pending until the application software has cleared it 362 * | | |If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active 363 * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. 364 * | | |The Status Interrupt has the highest priority 365 * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. 366 * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]) 367 * | | |The Status Interrupt is cleared by reading the Status Register. 368 * @var CAN_T::TEST 369 * Offset: 0x14 Test Register 370 * --------------------------------------------------------------------------------------------------- 371 * |Bits |Field |Descriptions 372 * | :----: | :----: | :---- | 373 * |[2] |Basic |Basic Mode 374 * | | |0 = Basic Mode Disabled. 375 * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. 376 * |[3] |Silent |Silent Mode 377 * | | |0 = Normal operation. 378 * | | |1 = The module is in Silent Mode. 379 * |[4] |LBack |Loop Back Mode Enable Bit 380 * | | |0 = Loop Back Mode is Disabled. 381 * | | |1 = Loop Back Mode is Enabled. 382 * |[6:5] |Tx |Tx[1:0]: Control of CAN_TX Pin 383 * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core. 384 * | | |01 = Sample Point can be monitored at CAN_TX pin. 385 * | | |10 = CAN_TX pin drives a dominant ('0') value. 386 * | | |11 = CAN_TX pin drives a recessive ('1') value. 387 * |[7] |Rx |Monitors the Actual Value of CAN_RX Pin (Read Only) *(1) 388 * | | |0 = The CAN bus is dominant (CAN_RX = '0'). 389 * | | |1 = The CAN bus is recessive (CAN_RX = '1'). 390 * @var CAN_T::BRPE 391 * Offset: 0x18 Baud Rate Prescaler Extension Register 392 * --------------------------------------------------------------------------------------------------- 393 * |Bits |Field |Descriptions 394 * | :----: | :----: | :---- | 395 * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension 396 * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023 397 * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. 398 * @var CAN_T::TXREQ1 399 * Offset: 0x100 Transmission Request Register 1 400 * --------------------------------------------------------------------------------------------------- 401 * |Bits |Field |Descriptions 402 * | :----: | :----: | :---- | 403 * |[15:0] |TxRqst16_1|Transmission Request Bits 16-1 (of All Message Objects) 404 * | | |0 = This Message Object is not waiting for transmission. 405 * | | |1 = The transmission of this Message Object is requested and is not yet done. 406 * | | |These bits are read only. 407 * @var CAN_T::TXREQ2 408 * Offset: 0x104 Transmission Request Register 2 409 * --------------------------------------------------------------------------------------------------- 410 * |Bits |Field |Descriptions 411 * | :----: | :----: | :---- | 412 * |[15:0] |TxRqst32_17|Transmission Request Bits 32-17 (of All Message Objects) 413 * | | |0 = This Message Object is not waiting for transmission. 414 * | | |1 = The transmission of this Message Object is requested and is not yet done. 415 * | | |These bits are read only. 416 * @var CAN_T::NDAT1 417 * Offset: 0x120 New Data Register 1 418 * --------------------------------------------------------------------------------------------------- 419 * |Bits |Field |Descriptions 420 * | :----: | :----: | :---- | 421 * |[15:0] |NewData16_1|New Data Bits 16-1 (of All Message Objects) 422 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. 423 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. 424 * @var CAN_T::NDAT2 425 * Offset: 0x124 New Data Register 2 426 * --------------------------------------------------------------------------------------------------- 427 * |Bits |Field |Descriptions 428 * | :----: | :----: | :---- | 429 * |[15:0] |NewData32_17|New Data Bits 32-17 (of All Message Objects) 430 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. 431 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. 432 * @var CAN_T::IPND1 433 * Offset: 0x140 Interrupt Pending Register 1 434 * --------------------------------------------------------------------------------------------------- 435 * |Bits |Field |Descriptions 436 * | :----: | :----: | :---- | 437 * |[15:0] |IntPnd16_1|Interrupt Pending Bits 16-1 (of All Message Objects) 438 * | | |0 = This message object is not the source of an interrupt. 439 * | | |1 = This message object is the source of an interrupt. 440 * @var CAN_T::IPND2 441 * Offset: 0x144 Interrupt Pending Register 2 442 * --------------------------------------------------------------------------------------------------- 443 * |Bits |Field |Descriptions 444 * | :----: | :----: | :---- | 445 * |[15:0] |IntPnd32_17|Interrupt Pending Bits 32-17 (of All Message Objects) 446 * | | |0 = This message object is not the source of an interrupt. 447 * | | |1 = This message object is the source of an interrupt. 448 * @var CAN_T::MVLD1 449 * Offset: 0x160 Message Valid Register 1 450 * --------------------------------------------------------------------------------------------------- 451 * |Bits |Field |Descriptions 452 * | :----: | :----: | :---- | 453 * |[15:0] |MsgVal16_1|Message Valid Bits 16-1 (of All Message Objects) (Read Only) 454 * | | |0 = This Message Object is ignored by the Message Handler. 455 * | | |1 = This Message Object is configured and should be considered by the Message Handler. 456 * | | |Ex 457 * | | |CAN_MVLD1[0] means Message object No.1 is valid or not 458 * | | |If CAN_MVLD1[0] is set, message object No.1 is configured. 459 * @var CAN_T::MVLD2 460 * Offset: 0x164 Message Valid Register 2 461 * --------------------------------------------------------------------------------------------------- 462 * |Bits |Field |Descriptions 463 * | :----: | :----: | :---- | 464 * |[15:0] |MsgVal32_17|Message Valid Bits 32-17 (of All Message Objects) (Read Only) 465 * | | |0 = This Message Object is ignored by the Message Handler. 466 * | | |1 = This Message Object is configured and should be considered by the Message Handler. 467 * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not 468 * | | |If CAN_MVLD2[15] is set, message object No.32 is configured. 469 * @var CAN_T::WU_EN 470 * Offset: 0x168 Wake-up Enable Control Register 471 * --------------------------------------------------------------------------------------------------- 472 * |Bits |Field |Descriptions 473 * | :----: | :----: | :---- | 474 * |[0] |WAKUP_EN |Wake-up Enable Bit 475 * | | |0 = The wake-up function Disabled. 476 * | | |1 = The wake-up function Enabled. 477 * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin. 478 * @var CAN_T::WU_STATUS 479 * Offset: 0x16C Wake-up Status Register 480 * --------------------------------------------------------------------------------------------------- 481 * |Bits |Field |Descriptions 482 * | :----: | :----: | :---- | 483 * |[0] |WAKUP_STS |Wake-up Status 484 * | | |0 = No wake-up event occurred. 485 * | | |1 = Wake-up event occurred. 486 * | | |Note: This bit can be cleared by writing '0'. 487 */ 488 __IO uint32_t CON; /*!< [0x0000] Control Register */ 489 __IO uint32_t STATUS; /*!< [0x0004] Status Register */ 490 __I uint32_t ERR; /*!< [0x0008] Error Counter Register */ 491 __IO uint32_t BTIME; /*!< [0x000c] Bit Timing Register */ 492 __I uint32_t IIDR; /*!< [0x0010] Interrupt Identifier Register */ 493 __IO uint32_t TEST; /*!< [0x0014] Test Register */ 494 __IO uint32_t BRPE; /*!< [0x0018] Baud Rate Prescaler Extension Register */ 495 /// @cond HIDDEN_SYMBOLS 496 __I uint32_t RESERVE0[1]; 497 /// @endcond //HIDDEN_SYMBOLS 498 __IO CAN_IF_T IF[2]; 499 /// @cond HIDDEN_SYMBOLS 500 __I uint32_t RESERVE2[8]; 501 /// @endcond //HIDDEN_SYMBOLS 502 __I uint32_t TXREQ1; /*!< [0x0100] Transmission Request Register 1 */ 503 __I uint32_t TXREQ2; /*!< [0x0104] Transmission Request Register 2 */ 504 /// @cond HIDDEN_SYMBOLS 505 __I uint32_t RESERVE3[6]; 506 /// @endcond //HIDDEN_SYMBOLS 507 __I uint32_t NDAT1; /*!< [0x0120] New Data Register 1 */ 508 __I uint32_t NDAT2; /*!< [0x0124] New Data Register 2 */ 509 /// @cond HIDDEN_SYMBOLS 510 __I uint32_t RESERVE4[6]; 511 /// @endcond //HIDDEN_SYMBOLS 512 __I uint32_t IPND1; /*!< [0x0140] Interrupt Pending Register 1 */ 513 __I uint32_t IPND2; /*!< [0x0144] Interrupt Pending Register 2 */ 514 /// @cond HIDDEN_SYMBOLS 515 __I uint32_t RESERVE5[6]; 516 /// @endcond //HIDDEN_SYMBOLS 517 __I uint32_t MVLD1; /*!< [0x0160] Message Valid Register 1 */ 518 __I uint32_t MVLD2; /*!< [0x0164] Message Valid Register 2 */ 519 __IO uint32_t WU_EN; /*!< [0x0168] Wake-up Enable Control Register */ 520 __IO uint32_t WU_STATUS; /*!< [0x016c] Wake-up Status Register */ 521 522 } CAN_T; 523 524 /** 525 @addtogroup CAN_CONST CAN Bit Field Definition 526 Constant Definitions for CAN Controller 527 @{ */ 528 529 #define CAN_CON_INIT_Pos (0) /*!< CAN_T::CON: Init Position */ 530 #define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: Init Mask */ 531 532 #define CAN_CON_IE_Pos (1) /*!< CAN_T::CON: IE Position */ 533 #define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */ 534 535 #define CAN_CON_SIE_Pos (2) /*!< CAN_T::CON: SIE Position */ 536 #define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */ 537 538 #define CAN_CON_EIE_Pos (3) /*!< CAN_T::CON: EIE Position */ 539 #define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */ 540 541 #define CAN_CON_DAR_Pos (5) /*!< CAN_T::CON: DAR Position */ 542 #define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */ 543 544 #define CAN_CON_CCE_Pos (6) /*!< CAN_T::CON: CCE Position */ 545 #define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */ 546 547 #define CAN_CON_TEST_Pos (7) /*!< CAN_T::CON: Test Position */ 548 #define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: Test Mask */ 549 550 #define CAN_STATUS_LEC_Pos (0) /*!< CAN_T::STATUS: LEC Position */ 551 #define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ 552 553 #define CAN_STATUS_TXOK_Pos (3) /*!< CAN_T::STATUS: TxOK Position */ 554 #define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TxOK Mask */ 555 556 #define CAN_STATUS_RXOK_Pos (4) /*!< CAN_T::STATUS: RxOK Position */ 557 #define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RxOK Mask */ 558 559 #define CAN_STATUS_EPASS_Pos (5) /*!< CAN_T::STATUS: EPass Position */ 560 #define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPass Mask */ 561 562 #define CAN_STATUS_EWARN_Pos (6) /*!< CAN_T::STATUS: EWarn Position */ 563 #define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWarn Mask */ 564 565 #define CAN_STATUS_BOFF_Pos (7) /*!< CAN_T::STATUS: BOff Position */ 566 #define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOff Mask */ 567 568 #define CAN_ERR_TEC_Pos (0) /*!< CAN_T::ERR: TEC Position */ 569 #define CAN_ERR_TEC_Msk (0xfful << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */ 570 571 #define CAN_ERR_REC_Pos (8) /*!< CAN_T::ERR: REC Position */ 572 #define CAN_ERR_REC_Msk (0x7ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */ 573 574 #define CAN_ERR_RP_Pos (15) /*!< CAN_T::ERR: RP Position */ 575 #define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */ 576 577 #define CAN_BTIME_BRP_Pos (0) /*!< CAN_T::BTIME: BRP Position */ 578 #define CAN_BTIME_BRP_Msk (0x3ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */ 579 580 #define CAN_BTIME_SJW_Pos (6) /*!< CAN_T::BTIME: SJW Position */ 581 #define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */ 582 583 #define CAN_BTIME_TSEG1_Pos (8) /*!< CAN_T::BTIME: TSeg1 Position */ 584 #define CAN_BTIME_TSEG1_Msk (0xful << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSeg1 Mask */ 585 586 #define CAN_BTIME_TSEG2_Pos (12) /*!< CAN_T::BTIME: TSeg2 Position */ 587 #define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSeg2 Mask */ 588 589 #define CAN_IIDR_IntId_Pos (0) /*!< CAN_T::IIDR: IntId Position */ 590 #define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) /*!< CAN_T::IIDR: IntId Mask */ 591 592 #define CAN_TEST_BASIC_Pos (2) /*!< CAN_T::TEST: Basic Position */ 593 #define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ 594 595 #define CAN_TEST_SILENT_Pos (3) /*!< CAN_T::TEST: Silent Position */ 596 #define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ 597 598 #define CAN_TEST_LBACK_Pos (4) /*!< CAN_T::TEST: LBack Position */ 599 #define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBack Mask */ 600 601 #define CAN_TEST_Tx_Pos (5) /*!< CAN_T::TEST: Tx Position */ 602 #define CAN_TEST_Tx_Msk (0x3ul << CAN_TEST_Tx_Pos) /*!< CAN_T::TEST: Tx Mask */ 603 604 #define CAN_TEST_Rx_Pos (7) /*!< CAN_T::TEST: Rx Position */ 605 #define CAN_TEST_Rx_Msk (0x1ul << CAN_TEST_Rx_Pos) /*!< CAN_T::TEST: Rx Mask */ 606 607 #define CAN_BRPE_BRPE_Pos (0) /*!< CAN_T::BRPE: BRPE Position */ 608 #define CAN_BRPE_BRPE_Msk (0xful << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ 609 610 #define CAN_IF_CREQ_MSGNUM_Pos (0) /*!< CAN_IF_T::CREQ: MessageNumber Position*/ 611 #define CAN_IF_CREQ_MSGNUM_Msk (0x3ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MessageNumber Mask */ 612 613 #define CAN_IF_CREQ_BUSY_Pos (15) /*!< CAN_IF_T::CREQ: Busy Position */ 614 #define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: Busy Mask */ 615 616 #define CAN_IF_CMASK_DATAB_Pos (0) /*!< CAN_IF_T::CMASK: DAT_B Position */ 617 #define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DAT_B Mask */ 618 619 #define CAN_IF_CMASK_DATAA_Pos (1) /*!< CAN_IF_T::CMASK: DAT_A Position */ 620 #define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DAT_A Mask */ 621 622 #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos (2) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/ 623 #define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask */ 624 625 #define CAN_IF_CMASK_CLRINTPND_Pos (3) /*!< CAN_IF_T::CMASK: ClrIntPnd Position */ 626 #define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: ClrIntPnd Mask */ 627 628 #define CAN_IF_CMASK_CONTROL_Pos (4) /*!< CAN_IF_T::CMASK: Control Position */ 629 #define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: Control Mask */ 630 631 #define CAN_IF_CMASK_ARB_Pos (5) /*!< CAN_IF_T::CMASK: Arb Position */ 632 #define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: Arb Mask */ 633 634 #define CAN_IF_CMASK_MASK_Pos (6) /*!< CAN_IF_T::CMASK: Mask Position */ 635 #define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: Mask Mask */ 636 637 #define CAN_IF_CMASK_WRRD_Pos (7) /*!< CAN_IF_T::CMASK: WR_RD Position */ 638 #define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WR_RD Mask */ 639 640 #define CAN_IF_MASK1_Msk_Pos (0) /*!< CAN_IF_T::MASK1: Msk Position */ 641 #define CAN_IF_MASK1_Msk_Msk (0xfffful << CAN_IF_MASK1_Msk_Pos) /*!< CAN_IF_T::MASK1: Msk Mask */ 642 643 #define CAN_IF_MASK2_Msk_Pos (0) /*!< CAN_IF_T::MASK2: Msk Position */ 644 #define CAN_IF_MASK2_Msk_Msk (0x1ffful << CAN_IF_MASK2_Msk_Pos) /*!< CAN_IF_T::MASK2: Msk Mask */ 645 646 #define CAN_IF_MASK2_MDIR_Pos (14) /*!< CAN_IF_T::MASK2: MDir Position */ 647 #define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDir Mask */ 648 649 #define CAN_IF_MASK2_MXTD_Pos (15) /*!< CAN_IF_T::MASK2: MXtd Position */ 650 #define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXtd Mask */ 651 652 #define CAN_IF_ARB1_ID_Pos (0) /*!< CAN_IF_T::ARB1: ID Position */ 653 #define CAN_IF_ARB1_ID_Msk (0xfffful << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */ 654 655 #define CAN_IF_ARB2_ID_Pos (0) /*!< CAN_IF_T::ARB2: ID Position */ 656 #define CAN_IF_ARB2_ID_Msk (0x1ffful << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */ 657 658 #define CAN_IF_ARB2_DIR_Pos (13) /*!< CAN_IF_T::ARB2: Dir Position */ 659 #define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: Dir Mask */ 660 661 #define CAN_IF_ARB2_XTD_Pos (14) /*!< CAN_IF_T::ARB2: Xtd Position */ 662 #define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: Xtd Mask */ 663 664 #define CAN_IF_ARB2_MSGVAL_Pos (15) /*!< CAN_IF_T::ARB2: MsgVal Position */ 665 #define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MsgVal Mask */ 666 667 #define CAN_IF_MCON_DLC_Pos (0) /*!< CAN_IF_T::MCON: DLC Position */ 668 #define CAN_IF_MCON_DLC_Msk (0xful << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */ 669 670 #define CAN_IF_MCON_EOB_Pos (7) /*!< CAN_IF_T::MCON: EoB Position */ 671 #define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EoB Mask */ 672 673 #define CAN_IF_MCON_TxRqst_Pos (8) /*!< CAN_IF_T::MCON: TxRqst Position */ 674 #define CAN_IF_MCON_TxRqst_Msk (0x1ul << CAN_IF_MCON_TxRqst_Pos) /*!< CAN_IF_T::MCON: TxRqst Mask */ 675 676 #define CAN_IF_MCON_RmtEn_Pos (9) /*!< CAN_IF_T::MCON: RmtEn Position */ 677 #define CAN_IF_MCON_RmtEn_Msk (0x1ul << CAN_IF_MCON_RmtEn_Pos) /*!< CAN_IF_T::MCON: RmtEn Mask */ 678 679 #define CAN_IF_MCON_RXIE_Pos (10) /*!< CAN_IF_T::MCON: RxIE Position */ 680 #define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RxIE Mask */ 681 682 #define CAN_IF_MCON_TXIE_Pos (11) /*!< CAN_IF_T::MCON: TxIE Position */ 683 #define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TxIE Mask */ 684 685 #define CAN_IF_MCON_UMASK_Pos (12) /*!< CAN_IF_T::MCON: UMask Position */ 686 #define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMask Mask */ 687 688 #define CAN_IF_MCON_IntPnd_Pos (13) /*!< CAN_IF_T::MCON: IntPnd Position */ 689 #define CAN_IF_MCON_IntPnd_Msk (0x1ul << CAN_IF_MCON_IntPnd_Pos) /*!< CAN_IF_T::MCON: IntPnd Mask */ 690 691 #define CAN_IF_MCON_MsgLst_Pos (14) /*!< CAN_IF_T::MCON: MsgLst Position */ 692 #define CAN_IF_MCON_MsgLst_Msk (0x1ul << CAN_IF_MCON_MsgLst_Pos) /*!< CAN_IF_T::MCON: MsgLst Mask */ 693 694 #define CAN_IF_MCON_NEWDAT_Pos (15) /*!< CAN_IF_T::MCON: NewDat Position */ 695 #define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NewDat Mask */ 696 697 #define CAN_IF_DAT_A1_DATA0_Pos (0) /*!< CAN_IF_T::DAT_A1: Data_0_ Position */ 698 #define CAN_IF_DAT_A1_DATA0_Msk (0xfful << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DAT_A1: Data_0_ Mask */ 699 700 #define CAN_IF_DAT_A1_DATA1_Pos (8) /*!< CAN_IF_T::DAT_A1: Data_1_ Position */ 701 #define CAN_IF_DAT_A1_DATA1_Msk (0xfful << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DAT_A1: Data_1_ Mask */ 702 703 #define CAN_IF_DAT_A2_DATA2_Pos (0) /*!< CAN_IF_T::DAT_A2: Data_2_ Position */ 704 #define CAN_IF_DAT_A2_DATA2_Msk (0xfful << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DAT_A2: Data_2_ Mask */ 705 706 #define CAN_IF_DAT_A2_DATA3_Pos (8) /*!< CAN_IF_T::DAT_A2: Data_3_ Position */ 707 #define CAN_IF_DAT_A2_DATA3_Msk (0xfful << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DAT_A2: Data_3_ Mask */ 708 709 #define CAN_IF_DAT_B1_DATA4_Pos (0) /*!< CAN_IF_T::DAT_B1: Data_4_ Position */ 710 #define CAN_IF_DAT_B1_DATA4_Msk (0xfful << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DAT_B1: Data_4_ Mask */ 711 712 #define CAN_IF_DAT_B1_DATA5_Pos (8) /*!< CAN_IF_T::DAT_B1: Data_5_ Position */ 713 #define CAN_IF_DAT_B1_DATA5_Msk (0xfful << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DAT_B1: Data_5_ Mask */ 714 715 #define CAN_IF_DAT_B2_DATA6_Pos (0) /*!< CAN_IF_T::DAT_B2: Data_6_ Position */ 716 #define CAN_IF_DAT_B2_DATA6_Msk (0xfful << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DAT_B2: Data_6_ Mask */ 717 718 #define CAN_IF_DAT_B2_DATA7_Pos (8) /*!< CAN_IF_T::DAT_B2: Data_7_ Position */ 719 #define CAN_IF_DAT_B2_DATA7_Msk (0xfful << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DAT_B2: Data_7_ Mask */ 720 721 #define CAN_TXREQ1_TXRQST16_1_Pos (0) /*!< CAN_T::TXREQ1: TxRqst16_1 Position */ 722 #define CAN_TXREQ1_TXRQST16_1_Msk (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos) /*!< CAN_T::TXREQ1: TxRqst16_1 Mask */ 723 724 #define CAN_TXREQ2_TXRQST32_17_Pos (0) /*!< CAN_T::TXREQ2: TxRqst32_17 Position */ 725 #define CAN_TXREQ2_TXRQST32_17_Msk (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos) /*!< CAN_T::TXREQ2: TxRqst32_17 Mask */ 726 727 #define CAN_NDAT1_NewData16_1_Pos (0) /*!< CAN_T::NDAT1: NewData16_1 Position */ 728 #define CAN_NDAT1_NewData16_1_Msk (0xfffful << CAN_NDAT1_NewData16_1_Pos) /*!< CAN_T::NDAT1: NewData16_1 Mask */ 729 730 #define CAN_NDAT2_NewData32_17_Pos (0) /*!< CAN_T::NDAT2: NewData32_17 Position */ 731 #define CAN_NDAT2_NewData32_17_Msk (0xfffful << CAN_NDAT2_NewData32_17_Pos) /*!< CAN_T::NDAT2: NewData32_17 Mask */ 732 733 #define CAN_IPND1_IntPnd16_1_Pos (0) /*!< CAN_T::IPND1: IntPnd16_1 Position */ 734 #define CAN_IPND1_IntPnd16_1_Msk (0xfffful << CAN_IPND1_IntPnd16_1_Pos) /*!< CAN_T::IPND1: IntPnd16_1 Mask */ 735 736 #define CAN_IPND2_IntPnd32_17_Pos (0) /*!< CAN_T::IPND2: IntPnd32_17 Position */ 737 #define CAN_IPND2_IntPnd32_17_Msk (0xfffful << CAN_IPND2_IntPnd32_17_Pos) /*!< CAN_T::IPND2: IntPnd32_17 Mask */ 738 739 #define CAN_MVLD1_MsgVal16_1_Pos (0) /*!< CAN_T::MVLD1: MsgVal16_1 Position */ 740 #define CAN_MVLD1_MsgVal16_1_Msk (0xfffful << CAN_MVLD1_MsgVal16_1_Pos) /*!< CAN_T::MVLD1: MsgVal16_1 Mask */ 741 742 #define CAN_MVLD2_MsgVal32_17_Pos (0) /*!< CAN_T::MVLD2: MsgVal32_17 Position */ 743 #define CAN_MVLD2_MsgVal32_17_Msk (0xfffful << CAN_MVLD2_MsgVal32_17_Pos) /*!< CAN_T::MVLD2: MsgVal32_17 Mask */ 744 745 #define CAN_WU_EN_WAKUP_EN_Pos (0) /*!< CAN_T::WU_EN: WAKUP_EN Position */ 746 #define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */ 747 748 #define CAN_WU_STATUS_WAKUP_STS_Pos (0) /*!< CAN_T::WU_STATUS: WAKUP_STS Position */ 749 #define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */ 750 751 /**@}*/ /* CAN_CONST */ 752 /**@}*/ /* end of CAN register group */ 753 /**@}*/ /* end of REGISTER group */ 754 755 #if defined ( __CC_ARM ) 756 #pragma no_anon_unions 757 #endif 758 759 #endif /* __CAN_REG_H__ */ 760
