1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CANXL_SIC.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_CANXL_SIC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CANXL_SIC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CANXL_SIC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CANXL_SIC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CANXL_SIC_Peripheral_Access_Layer CANXL_SIC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CANXL_SIC - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[64]; 74 __IO uint32_t SYSMC; /**< System Module Control, offset: 0x40 */ 75 __IO uint32_t SYSMCFG; /**< System Module Configuration, offset: 0x44 */ 76 __IO uint32_t SYSIE; /**< System Interrupt Enable, offset: 0x48 */ 77 __IO uint32_t SYSS; /**< System Status, offset: 0x4C */ 78 __I uint32_t SYSFRTL; /**< System Free Running Timer Low, offset: 0x50 */ 79 __I uint32_t SYSFRTH; /**< System Free Running Timer High, offset: 0x54 */ 80 __IO uint32_t SYSMDHICFG; /**< System Message Descriptor Host Interrupt Configuration, offset: 0x58 */ 81 uint8_t RESERVED_1[36]; 82 __IO uint32_t BCFG1; /**< BCANXL Configuration 1, offset: 0x80 */ 83 __IO uint32_t BCFG2; /**< BCANXL Configuration 2, offset: 0x84 */ 84 uint8_t RESERVED_2[4]; 85 __IO uint32_t BBPRS; /**< BCANXL Bit Time Quanta Prescaler, offset: 0x8C */ 86 __IO uint32_t BNCBT; /**< BCANXL Nominal Bit Timing, offset: 0x90 */ 87 __IO uint32_t BFDCBT; /**< BCANXL FD Data Phase Bit Timing, offset: 0x94 */ 88 __IO uint32_t BXDCBT; /**< BCANXL XL Data Phase Bit Timing, offset: 0x98 */ 89 __IO uint32_t BTDCC; /**< BCANXL Transceiver Delay Compensation Control, offset: 0x9C */ 90 __IO uint32_t BMICI; /**< BCANXL Medium Independent CAN interface, offset: 0xA0 */ 91 } CANXL_SIC_Type, *CANXL_SIC_MemMapPtr; 92 93 /** Number of instances of the CANXL_SIC module. */ 94 #define CANXL_SIC_INSTANCE_COUNT (2u) 95 96 /* CANXL_SIC - Peripheral instance base addresses */ 97 /** Peripheral CANXL_0__SIC base address */ 98 #define IP_CANXL_0__SIC_BASE (0x4741B000u) 99 /** Peripheral CANXL_0__SIC base pointer */ 100 #define IP_CANXL_0__SIC ((CANXL_SIC_Type *)IP_CANXL_0__SIC_BASE) 101 /** Peripheral CANXL_1__SIC base address */ 102 #define IP_CANXL_1__SIC_BASE (0x4751B000u) 103 /** Peripheral CANXL_1__SIC base pointer */ 104 #define IP_CANXL_1__SIC ((CANXL_SIC_Type *)IP_CANXL_1__SIC_BASE) 105 /** Array initializer of CANXL_SIC peripheral base addresses */ 106 #define IP_CANXL_SIC_BASE_ADDRS { IP_CANXL_0__SIC_BASE, IP_CANXL_1__SIC_BASE } 107 /** Array initializer of CANXL_SIC peripheral base pointers */ 108 #define IP_CANXL_SIC_BASE_PTRS { IP_CANXL_0__SIC, IP_CANXL_1__SIC } 109 110 /* ---------------------------------------------------------------------------- 111 -- CANXL_SIC Register Masks 112 ---------------------------------------------------------------------------- */ 113 114 /*! 115 * @addtogroup CANXL_SIC_Register_Masks CANXL_SIC Register Masks 116 * @{ 117 */ 118 119 /*! @name SYSMC - System Module Control */ 120 /*! @{ */ 121 122 #define CANXL_SIC_SYSMC_FRZREQ_MASK (0x1U) 123 #define CANXL_SIC_SYSMC_FRZREQ_SHIFT (0U) 124 #define CANXL_SIC_SYSMC_FRZREQ_WIDTH (1U) 125 #define CANXL_SIC_SYSMC_FRZREQ(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMC_FRZREQ_SHIFT)) & CANXL_SIC_SYSMC_FRZREQ_MASK) 126 127 #define CANXL_SIC_SYSMC_LPMREQ_MASK (0x2U) 128 #define CANXL_SIC_SYSMC_LPMREQ_SHIFT (1U) 129 #define CANXL_SIC_SYSMC_LPMREQ_WIDTH (1U) 130 #define CANXL_SIC_SYSMC_LPMREQ(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMC_LPMREQ_SHIFT)) & CANXL_SIC_SYSMC_LPMREQ_MASK) 131 132 #define CANXL_SIC_SYSMC_SOFRST_MASK (0x80000000U) 133 #define CANXL_SIC_SYSMC_SOFRST_SHIFT (31U) 134 #define CANXL_SIC_SYSMC_SOFRST_WIDTH (1U) 135 #define CANXL_SIC_SYSMC_SOFRST(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMC_SOFRST_SHIFT)) & CANXL_SIC_SYSMC_SOFRST_MASK) 136 /*! @} */ 137 138 /*! @name SYSMCFG - System Module Configuration */ 139 /*! @{ */ 140 141 #define CANXL_SIC_SYSMCFG_FB1EN_MASK (0x1U) 142 #define CANXL_SIC_SYSMCFG_FB1EN_SHIFT (0U) 143 #define CANXL_SIC_SYSMCFG_FB1EN_WIDTH (1U) 144 #define CANXL_SIC_SYSMCFG_FB1EN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMCFG_FB1EN_SHIFT)) & CANXL_SIC_SYSMCFG_FB1EN_MASK) 145 146 #define CANXL_SIC_SYSMCFG_DRWRDIS_MASK (0x2U) 147 #define CANXL_SIC_SYSMCFG_DRWRDIS_SHIFT (1U) 148 #define CANXL_SIC_SYSMCFG_DRWRDIS_WIDTH (1U) 149 #define CANXL_SIC_SYSMCFG_DRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMCFG_DRWRDIS_SHIFT)) & CANXL_SIC_SYSMCFG_DRWRDIS_MASK) 150 151 #define CANXL_SIC_SYSMCFG_MRP_MASK (0x8U) 152 #define CANXL_SIC_SYSMCFG_MRP_SHIFT (3U) 153 #define CANXL_SIC_SYSMCFG_MRP_WIDTH (1U) 154 #define CANXL_SIC_SYSMCFG_MRP(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMCFG_MRP_SHIFT)) & CANXL_SIC_SYSMCFG_MRP_MASK) 155 156 #define CANXL_SIC_SYSMCFG_MAXTXMB_MASK (0x7F0000U) 157 #define CANXL_SIC_SYSMCFG_MAXTXMB_SHIFT (16U) 158 #define CANXL_SIC_SYSMCFG_MAXTXMB_WIDTH (7U) 159 #define CANXL_SIC_SYSMCFG_MAXTXMB(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMCFG_MAXTXMB_SHIFT)) & CANXL_SIC_SYSMCFG_MAXTXMB_MASK) 160 161 #define CANXL_SIC_SYSMCFG_MAXRXMB_MASK (0x7F000000U) 162 #define CANXL_SIC_SYSMCFG_MAXRXMB_SHIFT (24U) 163 #define CANXL_SIC_SYSMCFG_MAXRXMB_WIDTH (7U) 164 #define CANXL_SIC_SYSMCFG_MAXRXMB(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMCFG_MAXRXMB_SHIFT)) & CANXL_SIC_SYSMCFG_MAXRXMB_MASK) 165 /*! @} */ 166 167 /*! @name SYSIE - System Interrupt Enable */ 168 /*! @{ */ 169 170 #define CANXL_SIC_SYSIE_FRZACKIE_MASK (0x1U) 171 #define CANXL_SIC_SYSIE_FRZACKIE_SHIFT (0U) 172 #define CANXL_SIC_SYSIE_FRZACKIE_WIDTH (1U) 173 #define CANXL_SIC_SYSIE_FRZACKIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_FRZACKIE_SHIFT)) & CANXL_SIC_SYSIE_FRZACKIE_MASK) 174 175 #define CANXL_SIC_SYSIE_LPMACKIE_MASK (0x2U) 176 #define CANXL_SIC_SYSIE_LPMACKIE_SHIFT (1U) 177 #define CANXL_SIC_SYSIE_LPMACKIE_WIDTH (1U) 178 #define CANXL_SIC_SYSIE_LPMACKIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_LPMACKIE_SHIFT)) & CANXL_SIC_SYSIE_LPMACKIE_MASK) 179 180 #define CANXL_SIC_SYSIE_IERRIE_MASK (0xF00U) 181 #define CANXL_SIC_SYSIE_IERRIE_SHIFT (8U) 182 #define CANXL_SIC_SYSIE_IERRIE_WIDTH (4U) 183 #define CANXL_SIC_SYSIE_IERRIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_IERRIE_SHIFT)) & CANXL_SIC_SYSIE_IERRIE_MASK) 184 185 #define CANXL_SIC_SYSIE_CERRIE_MASK (0x10000U) 186 #define CANXL_SIC_SYSIE_CERRIE_SHIFT (16U) 187 #define CANXL_SIC_SYSIE_CERRIE_WIDTH (1U) 188 #define CANXL_SIC_SYSIE_CERRIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CERRIE_SHIFT)) & CANXL_SIC_SYSIE_CERRIE_MASK) 189 190 #define CANXL_SIC_SYSIE_CPERRIE_MASK (0x20000U) 191 #define CANXL_SIC_SYSIE_CPERRIE_SHIFT (17U) 192 #define CANXL_SIC_SYSIE_CPERRIE_WIDTH (1U) 193 #define CANXL_SIC_SYSIE_CPERRIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CPERRIE_SHIFT)) & CANXL_SIC_SYSIE_CPERRIE_MASK) 194 195 #define CANXL_SIC_SYSIE_CBOFFIE_MASK (0x40000U) 196 #define CANXL_SIC_SYSIE_CBOFFIE_SHIFT (18U) 197 #define CANXL_SIC_SYSIE_CBOFFIE_WIDTH (1U) 198 #define CANXL_SIC_SYSIE_CBOFFIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CBOFFIE_SHIFT)) & CANXL_SIC_SYSIE_CBOFFIE_MASK) 199 200 #define CANXL_SIC_SYSIE_CBDONEIE_MASK (0x80000U) 201 #define CANXL_SIC_SYSIE_CBDONEIE_SHIFT (19U) 202 #define CANXL_SIC_SYSIE_CBDONEIE_WIDTH (1U) 203 #define CANXL_SIC_SYSIE_CBDONEIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CBDONEIE_SHIFT)) & CANXL_SIC_SYSIE_CBDONEIE_MASK) 204 205 #define CANXL_SIC_SYSIE_CRXWRNIE_MASK (0x100000U) 206 #define CANXL_SIC_SYSIE_CRXWRNIE_SHIFT (20U) 207 #define CANXL_SIC_SYSIE_CRXWRNIE_WIDTH (1U) 208 #define CANXL_SIC_SYSIE_CRXWRNIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CRXWRNIE_SHIFT)) & CANXL_SIC_SYSIE_CRXWRNIE_MASK) 209 210 #define CANXL_SIC_SYSIE_CTXWRNIE_MASK (0x200000U) 211 #define CANXL_SIC_SYSIE_CTXWRNIE_SHIFT (21U) 212 #define CANXL_SIC_SYSIE_CTXWRNIE_WIDTH (1U) 213 #define CANXL_SIC_SYSIE_CTXWRNIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CTXWRNIE_SHIFT)) & CANXL_SIC_SYSIE_CTXWRNIE_MASK) 214 215 #define CANXL_SIC_SYSIE_CFDPERRIE_MASK (0x400000U) 216 #define CANXL_SIC_SYSIE_CFDPERRIE_SHIFT (22U) 217 #define CANXL_SIC_SYSIE_CFDPERRIE_WIDTH (1U) 218 #define CANXL_SIC_SYSIE_CFDPERRIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CFDPERRIE_SHIFT)) & CANXL_SIC_SYSIE_CFDPERRIE_MASK) 219 220 #define CANXL_SIC_SYSIE_CPREXCIE_MASK (0x800000U) 221 #define CANXL_SIC_SYSIE_CPREXCIE_SHIFT (23U) 222 #define CANXL_SIC_SYSIE_CPREXCIE_WIDTH (1U) 223 #define CANXL_SIC_SYSIE_CPREXCIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CPREXCIE_SHIFT)) & CANXL_SIC_SYSIE_CPREXCIE_MASK) 224 225 #define CANXL_SIC_SYSIE_CDPERRIE_MASK (0x1000000U) 226 #define CANXL_SIC_SYSIE_CDPERRIE_SHIFT (24U) 227 #define CANXL_SIC_SYSIE_CDPERRIE_WIDTH (1U) 228 #define CANXL_SIC_SYSIE_CDPERRIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CDPERRIE_SHIFT)) & CANXL_SIC_SYSIE_CDPERRIE_MASK) 229 230 #define CANXL_SIC_SYSIE_CTFOERRIR_MASK (0x2000000U) 231 #define CANXL_SIC_SYSIE_CTFOERRIR_SHIFT (25U) 232 #define CANXL_SIC_SYSIE_CTFOERRIR_WIDTH (1U) 233 #define CANXL_SIC_SYSIE_CTFOERRIR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CTFOERRIR_SHIFT)) & CANXL_SIC_SYSIE_CTFOERRIR_MASK) 234 235 #define CANXL_SIC_SYSIE_CRFOERRIR_MASK (0x4000000U) 236 #define CANXL_SIC_SYSIE_CRFOERRIR_SHIFT (26U) 237 #define CANXL_SIC_SYSIE_CRFOERRIR_WIDTH (1U) 238 #define CANXL_SIC_SYSIE_CRFOERRIR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CRFOERRIR_SHIFT)) & CANXL_SIC_SYSIE_CRFOERRIR_MASK) 239 240 #define CANXL_SIC_SYSIE_CLSERRIE_MASK (0x8000000U) 241 #define CANXL_SIC_SYSIE_CLSERRIE_SHIFT (27U) 242 #define CANXL_SIC_SYSIE_CLSERRIE_WIDTH (1U) 243 #define CANXL_SIC_SYSIE_CLSERRIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CLSERRIE_SHIFT)) & CANXL_SIC_SYSIE_CLSERRIE_MASK) 244 245 #define CANXL_SIC_SYSIE_CMDOERRIE_MASK (0x10000000U) 246 #define CANXL_SIC_SYSIE_CMDOERRIE_SHIFT (28U) 247 #define CANXL_SIC_SYSIE_CMDOERRIE_WIDTH (1U) 248 #define CANXL_SIC_SYSIE_CMDOERRIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CMDOERRIE_SHIFT)) & CANXL_SIC_SYSIE_CMDOERRIE_MASK) 249 250 #define CANXL_SIC_SYSIE_CMDUERRIE_MASK (0x20000000U) 251 #define CANXL_SIC_SYSIE_CMDUERRIE_SHIFT (29U) 252 #define CANXL_SIC_SYSIE_CMDUERRIE_WIDTH (1U) 253 #define CANXL_SIC_SYSIE_CMDUERRIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CMDUERRIE_SHIFT)) & CANXL_SIC_SYSIE_CMDUERRIE_MASK) 254 255 #define CANXL_SIC_SYSIE_CRXSOERRIE_MASK (0x40000000U) 256 #define CANXL_SIC_SYSIE_CRXSOERRIE_SHIFT (30U) 257 #define CANXL_SIC_SYSIE_CRXSOERRIE_WIDTH (1U) 258 #define CANXL_SIC_SYSIE_CRXSOERRIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSIE_CRXSOERRIE_SHIFT)) & CANXL_SIC_SYSIE_CRXSOERRIE_MASK) 259 /*! @} */ 260 261 /*! @name SYSS - System Status */ 262 /*! @{ */ 263 264 #define CANXL_SIC_SYSS_FRZACKF_MASK (0x1U) 265 #define CANXL_SIC_SYSS_FRZACKF_SHIFT (0U) 266 #define CANXL_SIC_SYSS_FRZACKF_WIDTH (1U) 267 #define CANXL_SIC_SYSS_FRZACKF(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_FRZACKF_SHIFT)) & CANXL_SIC_SYSS_FRZACKF_MASK) 268 269 #define CANXL_SIC_SYSS_LPMACKF_MASK (0x2U) 270 #define CANXL_SIC_SYSS_LPMACKF_SHIFT (1U) 271 #define CANXL_SIC_SYSS_LPMACKF_WIDTH (1U) 272 #define CANXL_SIC_SYSS_LPMACKF(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_LPMACKF_SHIFT)) & CANXL_SIC_SYSS_LPMACKF_MASK) 273 274 #define CANXL_SIC_SYSS_NTRDY_MASK (0x4U) 275 #define CANXL_SIC_SYSS_NTRDY_SHIFT (2U) 276 #define CANXL_SIC_SYSS_NTRDY_WIDTH (1U) 277 #define CANXL_SIC_SYSS_NTRDY(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_NTRDY_SHIFT)) & CANXL_SIC_SYSS_NTRDY_MASK) 278 279 #define CANXL_SIC_SYSS_IERR_MASK (0xF00U) 280 #define CANXL_SIC_SYSS_IERR_SHIFT (8U) 281 #define CANXL_SIC_SYSS_IERR_WIDTH (4U) 282 #define CANXL_SIC_SYSS_IERR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_IERR_SHIFT)) & CANXL_SIC_SYSS_IERR_MASK) 283 284 #define CANXL_SIC_SYSS_CERR_MASK (0x10000U) 285 #define CANXL_SIC_SYSS_CERR_SHIFT (16U) 286 #define CANXL_SIC_SYSS_CERR_WIDTH (1U) 287 #define CANXL_SIC_SYSS_CERR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CERR_SHIFT)) & CANXL_SIC_SYSS_CERR_MASK) 288 289 #define CANXL_SIC_SYSS_CPASERR_MASK (0x20000U) 290 #define CANXL_SIC_SYSS_CPASERR_SHIFT (17U) 291 #define CANXL_SIC_SYSS_CPASERR_WIDTH (1U) 292 #define CANXL_SIC_SYSS_CPASERR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CPASERR_SHIFT)) & CANXL_SIC_SYSS_CPASERR_MASK) 293 294 #define CANXL_SIC_SYSS_CBOFF_MASK (0x40000U) 295 #define CANXL_SIC_SYSS_CBOFF_SHIFT (18U) 296 #define CANXL_SIC_SYSS_CBOFF_WIDTH (1U) 297 #define CANXL_SIC_SYSS_CBOFF(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CBOFF_SHIFT)) & CANXL_SIC_SYSS_CBOFF_MASK) 298 299 #define CANXL_SIC_SYSS_CBDONE_MASK (0x80000U) 300 #define CANXL_SIC_SYSS_CBDONE_SHIFT (19U) 301 #define CANXL_SIC_SYSS_CBDONE_WIDTH (1U) 302 #define CANXL_SIC_SYSS_CBDONE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CBDONE_SHIFT)) & CANXL_SIC_SYSS_CBDONE_MASK) 303 304 #define CANXL_SIC_SYSS_CRXWRN_MASK (0x100000U) 305 #define CANXL_SIC_SYSS_CRXWRN_SHIFT (20U) 306 #define CANXL_SIC_SYSS_CRXWRN_WIDTH (1U) 307 #define CANXL_SIC_SYSS_CRXWRN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CRXWRN_SHIFT)) & CANXL_SIC_SYSS_CRXWRN_MASK) 308 309 #define CANXL_SIC_SYSS_CTXWRN_MASK (0x200000U) 310 #define CANXL_SIC_SYSS_CTXWRN_SHIFT (21U) 311 #define CANXL_SIC_SYSS_CTXWRN_WIDTH (1U) 312 #define CANXL_SIC_SYSS_CTXWRN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CTXWRN_SHIFT)) & CANXL_SIC_SYSS_CTXWRN_MASK) 313 314 #define CANXL_SIC_SYSS_CFDPERR_MASK (0x400000U) 315 #define CANXL_SIC_SYSS_CFDPERR_SHIFT (22U) 316 #define CANXL_SIC_SYSS_CFDPERR_WIDTH (1U) 317 #define CANXL_SIC_SYSS_CFDPERR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CFDPERR_SHIFT)) & CANXL_SIC_SYSS_CFDPERR_MASK) 318 319 #define CANXL_SIC_SYSS_CPREXC_MASK (0x800000U) 320 #define CANXL_SIC_SYSS_CPREXC_SHIFT (23U) 321 #define CANXL_SIC_SYSS_CPREXC_WIDTH (1U) 322 #define CANXL_SIC_SYSS_CPREXC(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CPREXC_SHIFT)) & CANXL_SIC_SYSS_CPREXC_MASK) 323 324 #define CANXL_SIC_SYSS_CXDPERR_MASK (0x1000000U) 325 #define CANXL_SIC_SYSS_CXDPERR_SHIFT (24U) 326 #define CANXL_SIC_SYSS_CXDPERR_WIDTH (1U) 327 #define CANXL_SIC_SYSS_CXDPERR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CXDPERR_SHIFT)) & CANXL_SIC_SYSS_CXDPERR_MASK) 328 329 #define CANXL_SIC_SYSS_CTFUFLW_MASK (0x2000000U) 330 #define CANXL_SIC_SYSS_CTFUFLW_SHIFT (25U) 331 #define CANXL_SIC_SYSS_CTFUFLW_WIDTH (1U) 332 #define CANXL_SIC_SYSS_CTFUFLW(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CTFUFLW_SHIFT)) & CANXL_SIC_SYSS_CTFUFLW_MASK) 333 334 #define CANXL_SIC_SYSS_CRFOVR_MASK (0x4000000U) 335 #define CANXL_SIC_SYSS_CRFOVR_SHIFT (26U) 336 #define CANXL_SIC_SYSS_CRFOVR_WIDTH (1U) 337 #define CANXL_SIC_SYSS_CRFOVR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CRFOVR_SHIFT)) & CANXL_SIC_SYSS_CRFOVR_MASK) 338 339 #define CANXL_SIC_SYSS_CLOMSERR_MASK (0x8000000U) 340 #define CANXL_SIC_SYSS_CLOMSERR_SHIFT (27U) 341 #define CANXL_SIC_SYSS_CLOMSERR_WIDTH (1U) 342 #define CANXL_SIC_SYSS_CLOMSERR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CLOMSERR_SHIFT)) & CANXL_SIC_SYSS_CLOMSERR_MASK) 343 344 #define CANXL_SIC_SYSS_CMDOERR_MASK (0x10000000U) 345 #define CANXL_SIC_SYSS_CMDOERR_SHIFT (28U) 346 #define CANXL_SIC_SYSS_CMDOERR_WIDTH (1U) 347 #define CANXL_SIC_SYSS_CMDOERR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CMDOERR_SHIFT)) & CANXL_SIC_SYSS_CMDOERR_MASK) 348 349 #define CANXL_SIC_SYSS_CMDUERR_MASK (0x20000000U) 350 #define CANXL_SIC_SYSS_CMDUERR_SHIFT (29U) 351 #define CANXL_SIC_SYSS_CMDUERR_WIDTH (1U) 352 #define CANXL_SIC_SYSS_CMDUERR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CMDUERR_SHIFT)) & CANXL_SIC_SYSS_CMDUERR_MASK) 353 354 #define CANXL_SIC_SYSS_CRXOERR_MASK (0x40000000U) 355 #define CANXL_SIC_SYSS_CRXOERR_SHIFT (30U) 356 #define CANXL_SIC_SYSS_CRXOERR_WIDTH (1U) 357 #define CANXL_SIC_SYSS_CRXOERR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSS_CRXOERR_SHIFT)) & CANXL_SIC_SYSS_CRXOERR_MASK) 358 /*! @} */ 359 360 /*! @name SYSFRTL - System Free Running Timer Low */ 361 /*! @{ */ 362 363 #define CANXL_SIC_SYSFRTL_FRTL_MASK (0xFFFFFFFFU) 364 #define CANXL_SIC_SYSFRTL_FRTL_SHIFT (0U) 365 #define CANXL_SIC_SYSFRTL_FRTL_WIDTH (32U) 366 #define CANXL_SIC_SYSFRTL_FRTL(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSFRTL_FRTL_SHIFT)) & CANXL_SIC_SYSFRTL_FRTL_MASK) 367 /*! @} */ 368 369 /*! @name SYSFRTH - System Free Running Timer High */ 370 /*! @{ */ 371 372 #define CANXL_SIC_SYSFRTH_FRTH_MASK (0xFFFFFFFFU) 373 #define CANXL_SIC_SYSFRTH_FRTH_SHIFT (0U) 374 #define CANXL_SIC_SYSFRTH_FRTH_WIDTH (32U) 375 #define CANXL_SIC_SYSFRTH_FRTH(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSFRTH_FRTH_SHIFT)) & CANXL_SIC_SYSFRTH_FRTH_MASK) 376 /*! @} */ 377 378 /*! @name SYSMDHICFG - System Message Descriptor Host Interrupt Configuration */ 379 /*! @{ */ 380 381 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_0_MASK (0x1U) 382 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_0_SHIFT (0U) 383 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_0_WIDTH (1U) 384 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_0(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_TXDCFGHI0_0_SHIFT)) & CANXL_SIC_SYSMDHICFG_TXDCFGHI0_0_MASK) 385 386 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_1_MASK (0x2U) 387 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_1_SHIFT (1U) 388 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_1_WIDTH (1U) 389 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_TXDCFGHI0_1_SHIFT)) & CANXL_SIC_SYSMDHICFG_TXDCFGHI0_1_MASK) 390 391 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_2_MASK (0x4U) 392 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_2_SHIFT (2U) 393 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_2_WIDTH (1U) 394 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_TXDCFGHI0_2_SHIFT)) & CANXL_SIC_SYSMDHICFG_TXDCFGHI0_2_MASK) 395 396 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_3_MASK (0x8U) 397 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_3_SHIFT (3U) 398 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_3_WIDTH (1U) 399 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI0_3(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_TXDCFGHI0_3_SHIFT)) & CANXL_SIC_SYSMDHICFG_TXDCFGHI0_3_MASK) 400 401 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_0_MASK (0x100U) 402 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_0_SHIFT (8U) 403 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_0_WIDTH (1U) 404 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_0(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_TXDCFGHI1_0_SHIFT)) & CANXL_SIC_SYSMDHICFG_TXDCFGHI1_0_MASK) 405 406 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_1_MASK (0x200U) 407 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_1_SHIFT (9U) 408 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_1_WIDTH (1U) 409 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_TXDCFGHI1_1_SHIFT)) & CANXL_SIC_SYSMDHICFG_TXDCFGHI1_1_MASK) 410 411 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_2_MASK (0x400U) 412 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_2_SHIFT (10U) 413 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_2_WIDTH (1U) 414 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_TXDCFGHI1_2_SHIFT)) & CANXL_SIC_SYSMDHICFG_TXDCFGHI1_2_MASK) 415 416 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_3_MASK (0x800U) 417 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_3_SHIFT (11U) 418 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_3_WIDTH (1U) 419 #define CANXL_SIC_SYSMDHICFG_TXDCFGHI1_3(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_TXDCFGHI1_3_SHIFT)) & CANXL_SIC_SYSMDHICFG_TXDCFGHI1_3_MASK) 420 421 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_0_MASK (0x10000U) 422 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_0_SHIFT (16U) 423 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_0_WIDTH (1U) 424 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_0(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_RXDCFGHI0_0_SHIFT)) & CANXL_SIC_SYSMDHICFG_RXDCFGHI0_0_MASK) 425 426 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_1_MASK (0x20000U) 427 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_1_SHIFT (17U) 428 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_1_WIDTH (1U) 429 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_RXDCFGHI0_1_SHIFT)) & CANXL_SIC_SYSMDHICFG_RXDCFGHI0_1_MASK) 430 431 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_2_MASK (0x40000U) 432 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_2_SHIFT (18U) 433 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_2_WIDTH (1U) 434 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_RXDCFGHI0_2_SHIFT)) & CANXL_SIC_SYSMDHICFG_RXDCFGHI0_2_MASK) 435 436 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_3_MASK (0x80000U) 437 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_3_SHIFT (19U) 438 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_3_WIDTH (1U) 439 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI0_3(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_RXDCFGHI0_3_SHIFT)) & CANXL_SIC_SYSMDHICFG_RXDCFGHI0_3_MASK) 440 441 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_0_MASK (0x1000000U) 442 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_0_SHIFT (24U) 443 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_0_WIDTH (1U) 444 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_0(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_RXDCFGHI1_0_SHIFT)) & CANXL_SIC_SYSMDHICFG_RXDCFGHI1_0_MASK) 445 446 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_1_MASK (0x2000000U) 447 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_1_SHIFT (25U) 448 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_1_WIDTH (1U) 449 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_RXDCFGHI1_1_SHIFT)) & CANXL_SIC_SYSMDHICFG_RXDCFGHI1_1_MASK) 450 451 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_2_MASK (0x4000000U) 452 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_2_SHIFT (26U) 453 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_2_WIDTH (1U) 454 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_RXDCFGHI1_2_SHIFT)) & CANXL_SIC_SYSMDHICFG_RXDCFGHI1_2_MASK) 455 456 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_3_MASK (0x8000000U) 457 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_3_SHIFT (27U) 458 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_3_WIDTH (1U) 459 #define CANXL_SIC_SYSMDHICFG_RXDCFGHI1_3(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_SYSMDHICFG_RXDCFGHI1_3_SHIFT)) & CANXL_SIC_SYSMDHICFG_RXDCFGHI1_3_MASK) 460 /*! @} */ 461 462 /*! @name BCFG1 - BCANXL Configuration 1 */ 463 /*! @{ */ 464 465 #define CANXL_SIC_BCFG1_ABRDIS_MASK (0x1U) 466 #define CANXL_SIC_BCFG1_ABRDIS_SHIFT (0U) 467 #define CANXL_SIC_BCFG1_ABRDIS_WIDTH (1U) 468 #define CANXL_SIC_BCFG1_ABRDIS(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG1_ABRDIS_SHIFT)) & CANXL_SIC_BCFG1_ABRDIS_MASK) 469 470 #define CANXL_SIC_BCFG1_FDRSDIS_MASK (0x2U) 471 #define CANXL_SIC_BCFG1_FDRSDIS_SHIFT (1U) 472 #define CANXL_SIC_BCFG1_FDRSDIS_WIDTH (1U) 473 #define CANXL_SIC_BCFG1_FDRSDIS(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG1_FDRSDIS_SHIFT)) & CANXL_SIC_BCFG1_FDRSDIS_MASK) 474 /*! @} */ 475 476 /*! @name BCFG2 - BCANXL Configuration 2 */ 477 /*! @{ */ 478 479 #define CANXL_SIC_BCFG2_LPB_MASK (0x1U) 480 #define CANXL_SIC_BCFG2_LPB_SHIFT (0U) 481 #define CANXL_SIC_BCFG2_LPB_WIDTH (1U) 482 #define CANXL_SIC_BCFG2_LPB(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_LPB_SHIFT)) & CANXL_SIC_BCFG2_LPB_MASK) 483 484 #define CANXL_SIC_BCFG2_LOM_MASK (0x2U) 485 #define CANXL_SIC_BCFG2_LOM_SHIFT (1U) 486 #define CANXL_SIC_BCFG2_LOM_WIDTH (1U) 487 #define CANXL_SIC_BCFG2_LOM(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_LOM_SHIFT)) & CANXL_SIC_BCFG2_LOM_MASK) 488 489 #define CANXL_SIC_BCFG2_TSCAP_MASK (0xCU) 490 #define CANXL_SIC_BCFG2_TSCAP_SHIFT (2U) 491 #define CANXL_SIC_BCFG2_TSCAP_WIDTH (2U) 492 #define CANXL_SIC_BCFG2_TSCAP(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_TSCAP_SHIFT)) & CANXL_SIC_BCFG2_TSCAP_MASK) 493 494 #define CANXL_SIC_BCFG2_SRXEN_MASK (0x10U) 495 #define CANXL_SIC_BCFG2_SRXEN_SHIFT (4U) 496 #define CANXL_SIC_BCFG2_SRXEN_WIDTH (1U) 497 #define CANXL_SIC_BCFG2_SRXEN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_SRXEN_SHIFT)) & CANXL_SIC_BCFG2_SRXEN_MASK) 498 499 #define CANXL_SIC_BCFG2_FDEN_MASK (0x20U) 500 #define CANXL_SIC_BCFG2_FDEN_SHIFT (5U) 501 #define CANXL_SIC_BCFG2_FDEN_WIDTH (1U) 502 #define CANXL_SIC_BCFG2_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_FDEN_SHIFT)) & CANXL_SIC_BCFG2_FDEN_MASK) 503 504 #define CANXL_SIC_BCFG2_PEXCE_MASK (0x40U) 505 #define CANXL_SIC_BCFG2_PEXCE_SHIFT (6U) 506 #define CANXL_SIC_BCFG2_PEXCE_WIDTH (1U) 507 #define CANXL_SIC_BCFG2_PEXCE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_PEXCE_SHIFT)) & CANXL_SIC_BCFG2_PEXCE_MASK) 508 509 #define CANXL_SIC_BCFG2_EDFLTDIS_MASK (0x80U) 510 #define CANXL_SIC_BCFG2_EDFLTDIS_SHIFT (7U) 511 #define CANXL_SIC_BCFG2_EDFLTDIS_WIDTH (1U) 512 #define CANXL_SIC_BCFG2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_EDFLTDIS_SHIFT)) & CANXL_SIC_BCFG2_EDFLTDIS_MASK) 513 514 #define CANXL_SIC_BCFG2_ROM_MASK (0x100U) 515 #define CANXL_SIC_BCFG2_ROM_SHIFT (8U) 516 #define CANXL_SIC_BCFG2_ROM_WIDTH (1U) 517 #define CANXL_SIC_BCFG2_ROM(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_ROM_SHIFT)) & CANXL_SIC_BCFG2_ROM_MASK) 518 519 #define CANXL_SIC_BCFG2_XLEN_MASK (0x200U) 520 #define CANXL_SIC_BCFG2_XLEN_SHIFT (9U) 521 #define CANXL_SIC_BCFG2_XLEN_WIDTH (1U) 522 #define CANXL_SIC_BCFG2_XLEN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_XLEN_SHIFT)) & CANXL_SIC_BCFG2_XLEN_MASK) 523 524 #define CANXL_SIC_BCFG2_XLER_MASK (0x400U) 525 #define CANXL_SIC_BCFG2_XLER_SHIFT (10U) 526 #define CANXL_SIC_BCFG2_XLER_WIDTH (1U) 527 #define CANXL_SIC_BCFG2_XLER(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_XLER_SHIFT)) & CANXL_SIC_BCFG2_XLER_MASK) 528 529 #define CANXL_SIC_BCFG2_TMSE_MASK (0x800U) 530 #define CANXL_SIC_BCFG2_TMSE_SHIFT (11U) 531 #define CANXL_SIC_BCFG2_TMSE_WIDTH (1U) 532 #define CANXL_SIC_BCFG2_TMSE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_TMSE_SHIFT)) & CANXL_SIC_BCFG2_TMSE_MASK) 533 534 #define CANXL_SIC_BCFG2_TFER_MASK (0x1000U) 535 #define CANXL_SIC_BCFG2_TFER_SHIFT (12U) 536 #define CANXL_SIC_BCFG2_TFER_WIDTH (1U) 537 #define CANXL_SIC_BCFG2_TFER(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_TFER_SHIFT)) & CANXL_SIC_BCFG2_TFER_MASK) 538 539 #define CANXL_SIC_BCFG2_TSS_MASK (0x2000U) 540 #define CANXL_SIC_BCFG2_TSS_SHIFT (13U) 541 #define CANXL_SIC_BCFG2_TSS_WIDTH (1U) 542 #define CANXL_SIC_BCFG2_TSS(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_TSS_SHIFT)) & CANXL_SIC_BCFG2_TSS_MASK) 543 544 #define CANXL_SIC_BCFG2_FPES_MASK (0x20000000U) 545 #define CANXL_SIC_BCFG2_FPES_SHIFT (29U) 546 #define CANXL_SIC_BCFG2_FPES_WIDTH (1U) 547 #define CANXL_SIC_BCFG2_FPES(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BCFG2_FPES_SHIFT)) & CANXL_SIC_BCFG2_FPES_MASK) 548 /*! @} */ 549 550 /*! @name BBPRS - BCANXL Bit Time Quanta Prescaler */ 551 /*! @{ */ 552 553 #define CANXL_SIC_BBPRS_PRESDIV_MASK (0xFFU) 554 #define CANXL_SIC_BBPRS_PRESDIV_SHIFT (0U) 555 #define CANXL_SIC_BBPRS_PRESDIV_WIDTH (8U) 556 #define CANXL_SIC_BBPRS_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BBPRS_PRESDIV_SHIFT)) & CANXL_SIC_BBPRS_PRESDIV_MASK) 557 /*! @} */ 558 559 /*! @name BNCBT - BCANXL Nominal Bit Timing */ 560 /*! @{ */ 561 562 #define CANXL_SIC_BNCBT_NTSEG1_MASK (0x1FFU) 563 #define CANXL_SIC_BNCBT_NTSEG1_SHIFT (0U) 564 #define CANXL_SIC_BNCBT_NTSEG1_WIDTH (9U) 565 #define CANXL_SIC_BNCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BNCBT_NTSEG1_SHIFT)) & CANXL_SIC_BNCBT_NTSEG1_MASK) 566 567 #define CANXL_SIC_BNCBT_NTSEG2_MASK (0x7F000U) 568 #define CANXL_SIC_BNCBT_NTSEG2_SHIFT (12U) 569 #define CANXL_SIC_BNCBT_NTSEG2_WIDTH (7U) 570 #define CANXL_SIC_BNCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BNCBT_NTSEG2_SHIFT)) & CANXL_SIC_BNCBT_NTSEG2_MASK) 571 572 #define CANXL_SIC_BNCBT_NRJW_MASK (0x1FC00000U) 573 #define CANXL_SIC_BNCBT_NRJW_SHIFT (22U) 574 #define CANXL_SIC_BNCBT_NRJW_WIDTH (7U) 575 #define CANXL_SIC_BNCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BNCBT_NRJW_SHIFT)) & CANXL_SIC_BNCBT_NRJW_MASK) 576 /*! @} */ 577 578 /*! @name BFDCBT - BCANXL FD Data Phase Bit Timing */ 579 /*! @{ */ 580 581 #define CANXL_SIC_BFDCBT_FTSEG1_MASK (0xFFU) 582 #define CANXL_SIC_BFDCBT_FTSEG1_SHIFT (0U) 583 #define CANXL_SIC_BFDCBT_FTSEG1_WIDTH (8U) 584 #define CANXL_SIC_BFDCBT_FTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BFDCBT_FTSEG1_SHIFT)) & CANXL_SIC_BFDCBT_FTSEG1_MASK) 585 586 #define CANXL_SIC_BFDCBT_FTSEG2_MASK (0x7F000U) 587 #define CANXL_SIC_BFDCBT_FTSEG2_SHIFT (12U) 588 #define CANXL_SIC_BFDCBT_FTSEG2_WIDTH (7U) 589 #define CANXL_SIC_BFDCBT_FTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BFDCBT_FTSEG2_SHIFT)) & CANXL_SIC_BFDCBT_FTSEG2_MASK) 590 591 #define CANXL_SIC_BFDCBT_FRJW_MASK (0x1FC00000U) 592 #define CANXL_SIC_BFDCBT_FRJW_SHIFT (22U) 593 #define CANXL_SIC_BFDCBT_FRJW_WIDTH (7U) 594 #define CANXL_SIC_BFDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BFDCBT_FRJW_SHIFT)) & CANXL_SIC_BFDCBT_FRJW_MASK) 595 /*! @} */ 596 597 /*! @name BXDCBT - BCANXL XL Data Phase Bit Timing */ 598 /*! @{ */ 599 600 #define CANXL_SIC_BXDCBT_XTSEG1_MASK (0xFFU) 601 #define CANXL_SIC_BXDCBT_XTSEG1_SHIFT (0U) 602 #define CANXL_SIC_BXDCBT_XTSEG1_WIDTH (8U) 603 #define CANXL_SIC_BXDCBT_XTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BXDCBT_XTSEG1_SHIFT)) & CANXL_SIC_BXDCBT_XTSEG1_MASK) 604 605 #define CANXL_SIC_BXDCBT_XTSEG2_MASK (0x7F000U) 606 #define CANXL_SIC_BXDCBT_XTSEG2_SHIFT (12U) 607 #define CANXL_SIC_BXDCBT_XTSEG2_WIDTH (7U) 608 #define CANXL_SIC_BXDCBT_XTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BXDCBT_XTSEG2_SHIFT)) & CANXL_SIC_BXDCBT_XTSEG2_MASK) 609 610 #define CANXL_SIC_BXDCBT_XRJW_MASK (0x1FC00000U) 611 #define CANXL_SIC_BXDCBT_XRJW_SHIFT (22U) 612 #define CANXL_SIC_BXDCBT_XRJW_WIDTH (7U) 613 #define CANXL_SIC_BXDCBT_XRJW(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BXDCBT_XRJW_SHIFT)) & CANXL_SIC_BXDCBT_XRJW_MASK) 614 /*! @} */ 615 616 /*! @name BTDCC - BCANXL Transceiver Delay Compensation Control */ 617 /*! @{ */ 618 619 #define CANXL_SIC_BTDCC_FTDCOFF_MASK (0x7FU) 620 #define CANXL_SIC_BTDCC_FTDCOFF_SHIFT (0U) 621 #define CANXL_SIC_BTDCC_FTDCOFF_WIDTH (7U) 622 #define CANXL_SIC_BTDCC_FTDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BTDCC_FTDCOFF_SHIFT)) & CANXL_SIC_BTDCC_FTDCOFF_MASK) 623 624 #define CANXL_SIC_BTDCC_FTDMDIS_MASK (0x4000U) 625 #define CANXL_SIC_BTDCC_FTDMDIS_SHIFT (14U) 626 #define CANXL_SIC_BTDCC_FTDMDIS_WIDTH (1U) 627 #define CANXL_SIC_BTDCC_FTDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BTDCC_FTDMDIS_SHIFT)) & CANXL_SIC_BTDCC_FTDMDIS_MASK) 628 629 #define CANXL_SIC_BTDCC_FTDCEN_MASK (0x8000U) 630 #define CANXL_SIC_BTDCC_FTDCEN_SHIFT (15U) 631 #define CANXL_SIC_BTDCC_FTDCEN_WIDTH (1U) 632 #define CANXL_SIC_BTDCC_FTDCEN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BTDCC_FTDCEN_SHIFT)) & CANXL_SIC_BTDCC_FTDCEN_MASK) 633 634 #define CANXL_SIC_BTDCC_XTDCOFF_MASK (0xFF0000U) 635 #define CANXL_SIC_BTDCC_XTDCOFF_SHIFT (16U) 636 #define CANXL_SIC_BTDCC_XTDCOFF_WIDTH (8U) 637 #define CANXL_SIC_BTDCC_XTDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BTDCC_XTDCOFF_SHIFT)) & CANXL_SIC_BTDCC_XTDCOFF_MASK) 638 639 #define CANXL_SIC_BTDCC_XTDMDIS_MASK (0x40000000U) 640 #define CANXL_SIC_BTDCC_XTDMDIS_SHIFT (30U) 641 #define CANXL_SIC_BTDCC_XTDMDIS_WIDTH (1U) 642 #define CANXL_SIC_BTDCC_XTDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BTDCC_XTDMDIS_SHIFT)) & CANXL_SIC_BTDCC_XTDMDIS_MASK) 643 644 #define CANXL_SIC_BTDCC_XTDCEN_MASK (0x80000000U) 645 #define CANXL_SIC_BTDCC_XTDCEN_SHIFT (31U) 646 #define CANXL_SIC_BTDCC_XTDCEN_WIDTH (1U) 647 #define CANXL_SIC_BTDCC_XTDCEN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BTDCC_XTDCEN_SHIFT)) & CANXL_SIC_BTDCC_XTDCEN_MASK) 648 /*! @} */ 649 650 /*! @name BMICI - BCANXL Medium Independent CAN interface */ 651 /*! @{ */ 652 653 #define CANXL_SIC_BMICI_PWMO_MASK (0x3FU) 654 #define CANXL_SIC_BMICI_PWMO_SHIFT (0U) 655 #define CANXL_SIC_BMICI_PWMO_WIDTH (6U) 656 #define CANXL_SIC_BMICI_PWMO(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BMICI_PWMO_SHIFT)) & CANXL_SIC_BMICI_PWMO_MASK) 657 658 #define CANXL_SIC_BMICI_PWML_MASK (0x3F00U) 659 #define CANXL_SIC_BMICI_PWML_SHIFT (8U) 660 #define CANXL_SIC_BMICI_PWML_WIDTH (6U) 661 #define CANXL_SIC_BMICI_PWML(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BMICI_PWML_SHIFT)) & CANXL_SIC_BMICI_PWML_MASK) 662 663 #define CANXL_SIC_BMICI_PWMS_MASK (0x3F0000U) 664 #define CANXL_SIC_BMICI_PWMS_SHIFT (16U) 665 #define CANXL_SIC_BMICI_PWMS_WIDTH (6U) 666 #define CANXL_SIC_BMICI_PWMS(x) (((uint32_t)(((uint32_t)(x)) << CANXL_SIC_BMICI_PWMS_SHIFT)) & CANXL_SIC_BMICI_PWMS_MASK) 667 /*! @} */ 668 669 /*! 670 * @} 671 */ /* end of group CANXL_SIC_Register_Masks */ 672 673 /*! 674 * @} 675 */ /* end of group CANXL_SIC_Peripheral_Access_Layer */ 676 677 #endif /* #if !defined(S32Z2_CANXL_SIC_H_) */ 678
