1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CANXL_RXFIFO_CONTROL.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_CANXL_RXFIFO_CONTROL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CANXL_RXFIFO_CONTROL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CANXL_RXFIFO_CONTROL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CANXL_RXFIFO_CONTROL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CANXL_RXFIFO_CONTROL_Peripheral_Access_Layer CANXL_RXFIFO_CONTROL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CANXL_RXFIFO_CONTROL - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t RXFCSTA; /**< RxFIFO Control Status, offset: 0x0 */ 74 __IO uint32_t RXFSYSPOP; /**< RxFIFO POP Control, offset: 0x4 */ 75 __IO uint32_t RXFSYSLOCK; /**< RxFIFO System Lock Control, offset: 0x8 */ 76 uint8_t RESERVED_0[8]; 77 __IO uint32_t RXFSYSACT; /**< RxFIFO Activation, offset: 0x14 */ 78 uint8_t RESERVED_1[8]; 79 __IO uint32_t RXFIEN; /**< RxFIFO Interrupt Enable, offset: 0x20 */ 80 __IO uint32_t RXFS; /**< RxFIFO Status, offset: 0x24 */ 81 __IO uint32_t RXFC; /**< RxFIFO Configuration, offset: 0x28 */ 82 } CANXL_RXFIFO_CONTROL_Type, *CANXL_RXFIFO_CONTROL_MemMapPtr; 83 84 /** Number of instances of the CANXL_RXFIFO_CONTROL module. */ 85 #define CANXL_RXFIFO_CONTROL_INSTANCE_COUNT (2u) 86 87 /* CANXL_RXFIFO_CONTROL - Peripheral instance base addresses */ 88 /** Peripheral CANXL_0__RXFIFO_CONTROL base address */ 89 #define IP_CANXL_0__RXFIFO_CONTROL_BASE (0x47425000u) 90 /** Peripheral CANXL_0__RXFIFO_CONTROL base pointer */ 91 #define IP_CANXL_0__RXFIFO_CONTROL ((CANXL_RXFIFO_CONTROL_Type *)IP_CANXL_0__RXFIFO_CONTROL_BASE) 92 /** Peripheral CANXL_1__RXFIFO_CONTROL base address */ 93 #define IP_CANXL_1__RXFIFO_CONTROL_BASE (0x47525000u) 94 /** Peripheral CANXL_1__RXFIFO_CONTROL base pointer */ 95 #define IP_CANXL_1__RXFIFO_CONTROL ((CANXL_RXFIFO_CONTROL_Type *)IP_CANXL_1__RXFIFO_CONTROL_BASE) 96 /** Array initializer of CANXL_RXFIFO_CONTROL peripheral base addresses */ 97 #define IP_CANXL_RXFIFO_CONTROL_BASE_ADDRS { IP_CANXL_0__RXFIFO_CONTROL_BASE, IP_CANXL_1__RXFIFO_CONTROL_BASE } 98 /** Array initializer of CANXL_RXFIFO_CONTROL peripheral base pointers */ 99 #define IP_CANXL_RXFIFO_CONTROL_BASE_PTRS { IP_CANXL_0__RXFIFO_CONTROL, IP_CANXL_1__RXFIFO_CONTROL } 100 101 /* ---------------------------------------------------------------------------- 102 -- CANXL_RXFIFO_CONTROL Register Masks 103 ---------------------------------------------------------------------------- */ 104 105 /*! 106 * @addtogroup CANXL_RXFIFO_CONTROL_Register_Masks CANXL_RXFIFO_CONTROL Register Masks 107 * @{ 108 */ 109 110 /*! @name RXFCSTA - RxFIFO Control Status */ 111 /*! @{ */ 112 113 #define CANXL_RXFIFO_CONTROL_RXFCSTA_STATE_MASK (0x7U) 114 #define CANXL_RXFIFO_CONTROL_RXFCSTA_STATE_SHIFT (0U) 115 #define CANXL_RXFIFO_CONTROL_RXFCSTA_STATE_WIDTH (3U) 116 #define CANXL_RXFIFO_CONTROL_RXFCSTA_STATE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFCSTA_STATE_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFCSTA_STATE_MASK) 117 118 #define CANXL_RXFIFO_CONTROL_RXFCSTA_HWLOCK_MASK (0x40U) 119 #define CANXL_RXFIFO_CONTROL_RXFCSTA_HWLOCK_SHIFT (6U) 120 #define CANXL_RXFIFO_CONTROL_RXFCSTA_HWLOCK_WIDTH (1U) 121 #define CANXL_RXFIFO_CONTROL_RXFCSTA_HWLOCK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFCSTA_HWLOCK_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFCSTA_HWLOCK_MASK) 122 123 #define CANXL_RXFIFO_CONTROL_RXFCSTA_SYSLOCK_MASK (0x80U) 124 #define CANXL_RXFIFO_CONTROL_RXFCSTA_SYSLOCK_SHIFT (7U) 125 #define CANXL_RXFIFO_CONTROL_RXFCSTA_SYSLOCK_WIDTH (1U) 126 #define CANXL_RXFIFO_CONTROL_RXFCSTA_SYSLOCK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFCSTA_SYSLOCK_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFCSTA_SYSLOCK_MASK) 127 128 #define CANXL_RXFIFO_CONTROL_RXFCSTA_HWPOINTER_MASK (0x3F00U) 129 #define CANXL_RXFIFO_CONTROL_RXFCSTA_HWPOINTER_SHIFT (8U) 130 #define CANXL_RXFIFO_CONTROL_RXFCSTA_HWPOINTER_WIDTH (6U) 131 #define CANXL_RXFIFO_CONTROL_RXFCSTA_HWPOINTER(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFCSTA_HWPOINTER_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFCSTA_HWPOINTER_MASK) 132 133 #define CANXL_RXFIFO_CONTROL_RXFCSTA_SYSPOINTER_MASK (0x3F0000U) 134 #define CANXL_RXFIFO_CONTROL_RXFCSTA_SYSPOINTER_SHIFT (16U) 135 #define CANXL_RXFIFO_CONTROL_RXFCSTA_SYSPOINTER_WIDTH (6U) 136 #define CANXL_RXFIFO_CONTROL_RXFCSTA_SYSPOINTER(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFCSTA_SYSPOINTER_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFCSTA_SYSPOINTER_MASK) 137 /*! @} */ 138 139 /*! @name RXFSYSPOP - RxFIFO POP Control */ 140 /*! @{ */ 141 142 #define CANXL_RXFIFO_CONTROL_RXFSYSPOP_RXPOP_MASK (0x1FU) 143 #define CANXL_RXFIFO_CONTROL_RXFSYSPOP_RXPOP_SHIFT (0U) 144 #define CANXL_RXFIFO_CONTROL_RXFSYSPOP_RXPOP_WIDTH (5U) 145 #define CANXL_RXFIFO_CONTROL_RXFSYSPOP_RXPOP(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFSYSPOP_RXPOP_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFSYSPOP_RXPOP_MASK) 146 /*! @} */ 147 148 /*! @name RXFSYSLOCK - RxFIFO System Lock Control */ 149 /*! @{ */ 150 151 #define CANXL_RXFIFO_CONTROL_RXFSYSLOCK_SYSLOCK_MASK (0x1U) 152 #define CANXL_RXFIFO_CONTROL_RXFSYSLOCK_SYSLOCK_SHIFT (0U) 153 #define CANXL_RXFIFO_CONTROL_RXFSYSLOCK_SYSLOCK_WIDTH (1U) 154 #define CANXL_RXFIFO_CONTROL_RXFSYSLOCK_SYSLOCK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFSYSLOCK_SYSLOCK_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFSYSLOCK_SYSLOCK_MASK) 155 /*! @} */ 156 157 /*! @name RXFSYSACT - RxFIFO Activation */ 158 /*! @{ */ 159 160 #define CANXL_RXFIFO_CONTROL_RXFSYSACT_ACT_MASK (0x1U) 161 #define CANXL_RXFIFO_CONTROL_RXFSYSACT_ACT_SHIFT (0U) 162 #define CANXL_RXFIFO_CONTROL_RXFSYSACT_ACT_WIDTH (1U) 163 #define CANXL_RXFIFO_CONTROL_RXFSYSACT_ACT(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFSYSACT_ACT_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFSYSACT_ACT_MASK) 164 /*! @} */ 165 166 /*! @name RXFIEN - RxFIFO Interrupt Enable */ 167 /*! @{ */ 168 169 #define CANXL_RXFIFO_CONTROL_RXFIEN_RXFIE_MASK (0x1U) 170 #define CANXL_RXFIFO_CONTROL_RXFIEN_RXFIE_SHIFT (0U) 171 #define CANXL_RXFIFO_CONTROL_RXFIEN_RXFIE_WIDTH (1U) 172 #define CANXL_RXFIFO_CONTROL_RXFIEN_RXFIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFIEN_RXFIE_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFIEN_RXFIE_MASK) 173 174 #define CANXL_RXFIFO_CONTROL_RXFIEN_RXFEIE_MASK (0x2U) 175 #define CANXL_RXFIFO_CONTROL_RXFIEN_RXFEIE_SHIFT (1U) 176 #define CANXL_RXFIFO_CONTROL_RXFIEN_RXFEIE_WIDTH (1U) 177 #define CANXL_RXFIFO_CONTROL_RXFIEN_RXFEIE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFIEN_RXFEIE_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFIEN_RXFEIE_MASK) 178 /*! @} */ 179 180 /*! @name RXFS - RxFIFO Status */ 181 /*! @{ */ 182 183 #define CANXL_RXFIFO_CONTROL_RXFS_RXFF_MASK (0x1U) 184 #define CANXL_RXFIFO_CONTROL_RXFS_RXFF_SHIFT (0U) 185 #define CANXL_RXFIFO_CONTROL_RXFS_RXFF_WIDTH (1U) 186 #define CANXL_RXFIFO_CONTROL_RXFS_RXFF(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFS_RXFF_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFS_RXFF_MASK) 187 188 #define CANXL_RXFIFO_CONTROL_RXFS_RXFEF_MASK (0x2U) 189 #define CANXL_RXFIFO_CONTROL_RXFS_RXFEF_SHIFT (1U) 190 #define CANXL_RXFIFO_CONTROL_RXFS_RXFEF_WIDTH (1U) 191 #define CANXL_RXFIFO_CONTROL_RXFS_RXFEF(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFS_RXFEF_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFS_RXFEF_MASK) 192 /*! @} */ 193 194 /*! @name RXFC - RxFIFO Configuration */ 195 /*! @{ */ 196 197 #define CANXL_RXFIFO_CONTROL_RXFC_RXFD_MASK (0x1FU) 198 #define CANXL_RXFIFO_CONTROL_RXFC_RXFD_SHIFT (0U) 199 #define CANXL_RXFIFO_CONTROL_RXFC_RXFD_WIDTH (5U) 200 #define CANXL_RXFIFO_CONTROL_RXFC_RXFD(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFC_RXFD_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFC_RXFD_MASK) 201 202 #define CANXL_RXFIFO_CONTROL_RXFC_RXFWTM_MASK (0x1F00U) 203 #define CANXL_RXFIFO_CONTROL_RXFC_RXFWTM_SHIFT (8U) 204 #define CANXL_RXFIFO_CONTROL_RXFC_RXFWTM_WIDTH (5U) 205 #define CANXL_RXFIFO_CONTROL_RXFC_RXFWTM(x) (((uint32_t)(((uint32_t)(x)) << CANXL_RXFIFO_CONTROL_RXFC_RXFWTM_SHIFT)) & CANXL_RXFIFO_CONTROL_RXFC_RXFWTM_MASK) 206 /*! @} */ 207 208 /*! 209 * @} 210 */ /* end of group CANXL_RXFIFO_CONTROL_Register_Masks */ 211 212 /*! 213 * @} 214 */ /* end of group CANXL_RXFIFO_CONTROL_Peripheral_Access_Layer */ 215 216 #endif /* #if !defined(S32Z2_CANXL_RXFIFO_CONTROL_H_) */ 217
